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dc85447b BD |
1 | /* sound/soc/s3c24xx/s3c-i2c-v2.c |
2 | * | |
3 | * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs. | |
4 | * | |
5 | * Copyright (c) 2006 Wolfson Microelectronics PLC. | |
6 | * Graeme Gregory graeme.gregory@wolfsonmicro.com | |
7 | * linux@wolfsonmicro.com | |
8 | * | |
9 | * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics | |
10 | * http://armlinux.simtec.co.uk/ | |
11 | * Ben Dooks <ben@simtec.co.uk> | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/clk.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/io.h> | |
26 | ||
27 | #include <sound/core.h> | |
28 | #include <sound/pcm.h> | |
29 | #include <sound/pcm_params.h> | |
30 | #include <sound/initval.h> | |
31 | #include <sound/soc.h> | |
32 | ||
33 | #include <plat/regs-s3c2412-iis.h> | |
34 | ||
35 | #include <plat/audio.h> | |
36 | #include <mach/dma.h> | |
37 | ||
38 | #include "s3c-i2s-v2.h" | |
39 | ||
8a0f62b8 MB |
40 | #undef S3C_IIS_V2_SUPPORTED |
41 | ||
42 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) | |
43 | #define S3C_IIS_V2_SUPPORTED | |
44 | #endif | |
45 | ||
46 | #ifdef CONFIG_PLAT_S3C64XX | |
47 | #define S3C_IIS_V2_SUPPORTED | |
48 | #endif | |
49 | ||
50 | #ifndef S3C_IIS_V2_SUPPORTED | |
51 | #error Unsupported CPU model | |
52 | #endif | |
53 | ||
dc85447b | 54 | #define S3C2412_I2S_DEBUG_CON 0 |
dc85447b BD |
55 | |
56 | static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai) | |
57 | { | |
58 | return cpu_dai->private_data; | |
59 | } | |
60 | ||
61 | #define bit_set(v, b) (((v) & (b)) ? 1 : 0) | |
62 | ||
63 | #if S3C2412_I2S_DEBUG_CON | |
64 | static void dbg_showcon(const char *fn, u32 con) | |
65 | { | |
66 | printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn, | |
67 | bit_set(con, S3C2412_IISCON_LRINDEX), | |
68 | bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY), | |
69 | bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY), | |
70 | bit_set(con, S3C2412_IISCON_TXFIFO_FULL), | |
71 | bit_set(con, S3C2412_IISCON_RXFIFO_FULL)); | |
72 | ||
73 | printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n", | |
74 | fn, | |
75 | bit_set(con, S3C2412_IISCON_TXDMA_PAUSE), | |
76 | bit_set(con, S3C2412_IISCON_RXDMA_PAUSE), | |
77 | bit_set(con, S3C2412_IISCON_TXCH_PAUSE), | |
78 | bit_set(con, S3C2412_IISCON_RXCH_PAUSE)); | |
79 | printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn, | |
80 | bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE), | |
81 | bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE), | |
82 | bit_set(con, S3C2412_IISCON_IIS_ACTIVE)); | |
83 | } | |
84 | #else | |
85 | static inline void dbg_showcon(const char *fn, u32 con) | |
86 | { | |
87 | } | |
88 | #endif | |
89 | ||
90 | ||
91 | /* Turn on or off the transmission path. */ | |
92 | void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on) | |
93 | { | |
94 | void __iomem *regs = i2s->regs; | |
95 | u32 fic, con, mod; | |
96 | ||
ee7d4767 | 97 | pr_debug("%s(%d)\n", __func__, on); |
dc85447b BD |
98 | |
99 | fic = readl(regs + S3C2412_IISFIC); | |
100 | con = readl(regs + S3C2412_IISCON); | |
101 | mod = readl(regs + S3C2412_IISMOD); | |
102 | ||
ee7d4767 | 103 | pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic); |
dc85447b BD |
104 | |
105 | if (on) { | |
106 | con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE; | |
107 | con &= ~S3C2412_IISCON_TXDMA_PAUSE; | |
108 | con &= ~S3C2412_IISCON_TXCH_PAUSE; | |
109 | ||
110 | switch (mod & S3C2412_IISMOD_MODE_MASK) { | |
111 | case S3C2412_IISMOD_MODE_TXONLY: | |
112 | case S3C2412_IISMOD_MODE_TXRX: | |
113 | /* do nothing, we are in the right mode */ | |
114 | break; | |
115 | ||
116 | case S3C2412_IISMOD_MODE_RXONLY: | |
117 | mod &= ~S3C2412_IISMOD_MODE_MASK; | |
118 | mod |= S3C2412_IISMOD_MODE_TXRX; | |
119 | break; | |
120 | ||
121 | default: | |
a7be4d92 | 122 | dev_err(i2s->dev, "TXEN: Invalid MODE in IISMOD\n"); |
dc85447b BD |
123 | } |
124 | ||
125 | writel(con, regs + S3C2412_IISCON); | |
126 | writel(mod, regs + S3C2412_IISMOD); | |
127 | } else { | |
128 | /* Note, we do not have any indication that the FIFO problems | |
129 | * tha the S3C2410/2440 had apply here, so we should be able | |
130 | * to disable the DMA and TX without resetting the FIFOS. | |
131 | */ | |
132 | ||
133 | con |= S3C2412_IISCON_TXDMA_PAUSE; | |
134 | con |= S3C2412_IISCON_TXCH_PAUSE; | |
135 | con &= ~S3C2412_IISCON_TXDMA_ACTIVE; | |
136 | ||
137 | switch (mod & S3C2412_IISMOD_MODE_MASK) { | |
138 | case S3C2412_IISMOD_MODE_TXRX: | |
139 | mod &= ~S3C2412_IISMOD_MODE_MASK; | |
140 | mod |= S3C2412_IISMOD_MODE_RXONLY; | |
141 | break; | |
142 | ||
143 | case S3C2412_IISMOD_MODE_TXONLY: | |
144 | mod &= ~S3C2412_IISMOD_MODE_MASK; | |
145 | con &= ~S3C2412_IISCON_IIS_ACTIVE; | |
146 | break; | |
147 | ||
148 | default: | |
a7be4d92 | 149 | dev_err(i2s->dev, "TXDIS: Invalid MODE in IISMOD\n"); |
dc85447b BD |
150 | } |
151 | ||
152 | writel(mod, regs + S3C2412_IISMOD); | |
153 | writel(con, regs + S3C2412_IISCON); | |
154 | } | |
155 | ||
156 | fic = readl(regs + S3C2412_IISFIC); | |
157 | dbg_showcon(__func__, con); | |
ee7d4767 | 158 | pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic); |
dc85447b BD |
159 | } |
160 | EXPORT_SYMBOL_GPL(s3c2412_snd_txctrl); | |
161 | ||
162 | void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on) | |
163 | { | |
164 | void __iomem *regs = i2s->regs; | |
165 | u32 fic, con, mod; | |
166 | ||
ee7d4767 | 167 | pr_debug("%s(%d)\n", __func__, on); |
dc85447b BD |
168 | |
169 | fic = readl(regs + S3C2412_IISFIC); | |
170 | con = readl(regs + S3C2412_IISCON); | |
171 | mod = readl(regs + S3C2412_IISMOD); | |
172 | ||
ee7d4767 | 173 | pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic); |
dc85447b BD |
174 | |
175 | if (on) { | |
176 | con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE; | |
177 | con &= ~S3C2412_IISCON_RXDMA_PAUSE; | |
178 | con &= ~S3C2412_IISCON_RXCH_PAUSE; | |
179 | ||
180 | switch (mod & S3C2412_IISMOD_MODE_MASK) { | |
181 | case S3C2412_IISMOD_MODE_TXRX: | |
182 | case S3C2412_IISMOD_MODE_RXONLY: | |
183 | /* do nothing, we are in the right mode */ | |
184 | break; | |
185 | ||
186 | case S3C2412_IISMOD_MODE_TXONLY: | |
187 | mod &= ~S3C2412_IISMOD_MODE_MASK; | |
188 | mod |= S3C2412_IISMOD_MODE_TXRX; | |
189 | break; | |
190 | ||
191 | default: | |
a7be4d92 | 192 | dev_err(i2s->dev, "RXEN: Invalid MODE in IISMOD\n"); |
dc85447b BD |
193 | } |
194 | ||
195 | writel(mod, regs + S3C2412_IISMOD); | |
196 | writel(con, regs + S3C2412_IISCON); | |
197 | } else { | |
198 | /* See txctrl notes on FIFOs. */ | |
199 | ||
200 | con &= ~S3C2412_IISCON_RXDMA_ACTIVE; | |
201 | con |= S3C2412_IISCON_RXDMA_PAUSE; | |
202 | con |= S3C2412_IISCON_RXCH_PAUSE; | |
203 | ||
204 | switch (mod & S3C2412_IISMOD_MODE_MASK) { | |
205 | case S3C2412_IISMOD_MODE_RXONLY: | |
206 | con &= ~S3C2412_IISCON_IIS_ACTIVE; | |
207 | mod &= ~S3C2412_IISMOD_MODE_MASK; | |
208 | break; | |
209 | ||
210 | case S3C2412_IISMOD_MODE_TXRX: | |
211 | mod &= ~S3C2412_IISMOD_MODE_MASK; | |
212 | mod |= S3C2412_IISMOD_MODE_TXONLY; | |
213 | break; | |
214 | ||
215 | default: | |
a7be4d92 | 216 | dev_err(i2s->dev, "RXEN: Invalid MODE in IISMOD\n"); |
dc85447b BD |
217 | } |
218 | ||
219 | writel(con, regs + S3C2412_IISCON); | |
220 | writel(mod, regs + S3C2412_IISMOD); | |
221 | } | |
222 | ||
223 | fic = readl(regs + S3C2412_IISFIC); | |
ee7d4767 | 224 | pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic); |
dc85447b BD |
225 | } |
226 | EXPORT_SYMBOL_GPL(s3c2412_snd_rxctrl); | |
227 | ||
228 | /* | |
229 | * Wait for the LR signal to allow synchronisation to the L/R clock | |
230 | * from the codec. May only be needed for slave mode. | |
231 | */ | |
232 | static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s) | |
233 | { | |
234 | u32 iiscon; | |
235 | unsigned long timeout = jiffies + msecs_to_jiffies(5); | |
236 | ||
ee7d4767 | 237 | pr_debug("Entered %s\n", __func__); |
dc85447b BD |
238 | |
239 | while (1) { | |
240 | iiscon = readl(i2s->regs + S3C2412_IISCON); | |
241 | if (iiscon & S3C2412_IISCON_LRINDEX) | |
242 | break; | |
243 | ||
244 | if (timeout < jiffies) { | |
245 | printk(KERN_ERR "%s: timeout\n", __func__); | |
246 | return -ETIMEDOUT; | |
247 | } | |
248 | } | |
249 | ||
250 | return 0; | |
251 | } | |
252 | ||
253 | /* | |
254 | * Set S3C2412 I2S DAI format | |
255 | */ | |
256 | static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai, | |
257 | unsigned int fmt) | |
258 | { | |
259 | struct s3c_i2sv2_info *i2s = to_info(cpu_dai); | |
260 | u32 iismod; | |
261 | ||
ee7d4767 | 262 | pr_debug("Entered %s\n", __func__); |
dc85447b BD |
263 | |
264 | iismod = readl(i2s->regs + S3C2412_IISMOD); | |
ee7d4767 | 265 | pr_debug("hw_params r: IISMOD: %x \n", iismod); |
dc85447b BD |
266 | |
267 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) | |
268 | #define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK | |
269 | #define IISMOD_SLAVE S3C2412_IISMOD_SLAVE | |
270 | #define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL | |
271 | #endif | |
272 | ||
273 | #if defined(CONFIG_PLAT_S3C64XX) | |
274 | /* From Rev1.1 datasheet, we have two master and two slave modes: | |
275 | * IMS[11:10]: | |
276 | * 00 = master mode, fed from PCLK | |
277 | * 01 = master mode, fed from CLKAUDIO | |
278 | * 10 = slave mode, using PCLK | |
279 | * 11 = slave mode, using I2SCLK | |
280 | */ | |
281 | #define IISMOD_MASTER_MASK (1 << 11) | |
282 | #define IISMOD_SLAVE (1 << 11) | |
553b1dd5 | 283 | #define IISMOD_MASTER (0 << 11) |
dc85447b BD |
284 | #endif |
285 | ||
286 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
287 | case SND_SOC_DAIFMT_CBM_CFM: | |
288 | i2s->master = 0; | |
289 | iismod &= ~IISMOD_MASTER_MASK; | |
290 | iismod |= IISMOD_SLAVE; | |
291 | break; | |
292 | case SND_SOC_DAIFMT_CBS_CFS: | |
293 | i2s->master = 1; | |
294 | iismod &= ~IISMOD_MASTER_MASK; | |
295 | iismod |= IISMOD_MASTER; | |
296 | break; | |
297 | default: | |
38e43c81 | 298 | pr_err("unknwon master/slave format\n"); |
dc85447b BD |
299 | return -EINVAL; |
300 | } | |
301 | ||
302 | iismod &= ~S3C2412_IISMOD_SDF_MASK; | |
303 | ||
304 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
305 | case SND_SOC_DAIFMT_RIGHT_J: | |
306 | iismod |= S3C2412_IISMOD_SDF_MSB; | |
307 | break; | |
308 | case SND_SOC_DAIFMT_LEFT_J: | |
309 | iismod |= S3C2412_IISMOD_SDF_LSB; | |
310 | break; | |
311 | case SND_SOC_DAIFMT_I2S: | |
312 | iismod |= S3C2412_IISMOD_SDF_IIS; | |
313 | break; | |
314 | default: | |
38e43c81 | 315 | pr_err("Unknown data format\n"); |
dc85447b BD |
316 | return -EINVAL; |
317 | } | |
318 | ||
319 | writel(iismod, i2s->regs + S3C2412_IISMOD); | |
ee7d4767 | 320 | pr_debug("hw_params w: IISMOD: %x \n", iismod); |
dc85447b BD |
321 | return 0; |
322 | } | |
323 | ||
324 | static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream, | |
325 | struct snd_pcm_hw_params *params, | |
326 | struct snd_soc_dai *socdai) | |
327 | { | |
328 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
329 | struct snd_soc_dai_link *dai = rtd->dai; | |
330 | struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai); | |
331 | u32 iismod; | |
332 | ||
ee7d4767 | 333 | pr_debug("Entered %s\n", __func__); |
dc85447b BD |
334 | |
335 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
336 | dai->cpu_dai->dma_data = i2s->dma_playback; | |
337 | else | |
338 | dai->cpu_dai->dma_data = i2s->dma_capture; | |
339 | ||
340 | /* Working copies of register */ | |
341 | iismod = readl(i2s->regs + S3C2412_IISMOD); | |
ee7d4767 | 342 | pr_debug("%s: r: IISMOD: %x\n", __func__, iismod); |
dc85447b | 343 | |
553b1dd5 | 344 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) |
dc85447b BD |
345 | switch (params_format(params)) { |
346 | case SNDRV_PCM_FORMAT_S8: | |
347 | iismod |= S3C2412_IISMOD_8BIT; | |
348 | break; | |
349 | case SNDRV_PCM_FORMAT_S16_LE: | |
350 | iismod &= ~S3C2412_IISMOD_8BIT; | |
351 | break; | |
352 | } | |
553b1dd5 MB |
353 | #endif |
354 | ||
355 | #ifdef CONFIG_PLAT_S3C64XX | |
356 | iismod &= ~0x606; | |
357 | /* Sample size */ | |
358 | switch (params_format(params)) { | |
359 | case SNDRV_PCM_FORMAT_S8: | |
360 | /* 8 bit sample, 16fs BCLK */ | |
361 | iismod |= 0x2004; | |
362 | break; | |
363 | case SNDRV_PCM_FORMAT_S16_LE: | |
364 | /* 16 bit sample, 32fs BCLK */ | |
365 | break; | |
366 | case SNDRV_PCM_FORMAT_S24_LE: | |
367 | /* 24 bit sample, 48fs BCLK */ | |
368 | iismod |= 0x4002; | |
369 | break; | |
370 | } | |
371 | #endif | |
dc85447b BD |
372 | |
373 | writel(iismod, i2s->regs + S3C2412_IISMOD); | |
ee7d4767 | 374 | pr_debug("%s: w: IISMOD: %x\n", __func__, iismod); |
dc85447b BD |
375 | return 0; |
376 | } | |
377 | ||
378 | static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd, | |
379 | struct snd_soc_dai *dai) | |
380 | { | |
381 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
382 | struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai); | |
383 | int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE); | |
384 | unsigned long irqs; | |
385 | int ret = 0; | |
386 | ||
ee7d4767 | 387 | pr_debug("Entered %s\n", __func__); |
dc85447b BD |
388 | |
389 | switch (cmd) { | |
390 | case SNDRV_PCM_TRIGGER_START: | |
391 | /* On start, ensure that the FIFOs are cleared and reset. */ | |
392 | ||
393 | writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH, | |
394 | i2s->regs + S3C2412_IISFIC); | |
395 | ||
396 | /* clear again, just in case */ | |
397 | writel(0x0, i2s->regs + S3C2412_IISFIC); | |
398 | ||
399 | case SNDRV_PCM_TRIGGER_RESUME: | |
400 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
401 | if (!i2s->master) { | |
402 | ret = s3c2412_snd_lrsync(i2s); | |
403 | if (ret) | |
404 | goto exit_err; | |
405 | } | |
406 | ||
407 | local_irq_save(irqs); | |
408 | ||
409 | if (capture) | |
410 | s3c2412_snd_rxctrl(i2s, 1); | |
411 | else | |
412 | s3c2412_snd_txctrl(i2s, 1); | |
413 | ||
414 | local_irq_restore(irqs); | |
415 | break; | |
416 | ||
417 | case SNDRV_PCM_TRIGGER_STOP: | |
418 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
419 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
420 | local_irq_save(irqs); | |
421 | ||
422 | if (capture) | |
423 | s3c2412_snd_rxctrl(i2s, 0); | |
424 | else | |
425 | s3c2412_snd_txctrl(i2s, 0); | |
426 | ||
427 | local_irq_restore(irqs); | |
428 | break; | |
429 | default: | |
430 | ret = -EINVAL; | |
431 | break; | |
432 | } | |
433 | ||
434 | exit_err: | |
435 | return ret; | |
436 | } | |
437 | ||
438 | /* | |
439 | * Set S3C2412 Clock dividers | |
440 | */ | |
441 | static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai, | |
442 | int div_id, int div) | |
443 | { | |
444 | struct s3c_i2sv2_info *i2s = to_info(cpu_dai); | |
445 | u32 reg; | |
446 | ||
ee7d4767 | 447 | pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div); |
dc85447b BD |
448 | |
449 | switch (div_id) { | |
450 | case S3C_I2SV2_DIV_BCLK: | |
451 | reg = readl(i2s->regs + S3C2412_IISMOD); | |
452 | reg &= ~S3C2412_IISMOD_BCLK_MASK; | |
453 | writel(reg | div, i2s->regs + S3C2412_IISMOD); | |
454 | ||
ee7d4767 | 455 | pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD)); |
dc85447b BD |
456 | break; |
457 | ||
458 | case S3C_I2SV2_DIV_RCLK: | |
459 | if (div > 3) { | |
460 | /* convert value to bit field */ | |
461 | ||
462 | switch (div) { | |
463 | case 256: | |
464 | div = S3C2412_IISMOD_RCLK_256FS; | |
465 | break; | |
466 | ||
467 | case 384: | |
468 | div = S3C2412_IISMOD_RCLK_384FS; | |
469 | break; | |
470 | ||
471 | case 512: | |
472 | div = S3C2412_IISMOD_RCLK_512FS; | |
473 | break; | |
474 | ||
475 | case 768: | |
476 | div = S3C2412_IISMOD_RCLK_768FS; | |
477 | break; | |
478 | ||
479 | default: | |
480 | return -EINVAL; | |
481 | } | |
482 | } | |
483 | ||
484 | reg = readl(i2s->regs + S3C2412_IISMOD); | |
485 | reg &= ~S3C2412_IISMOD_RCLK_MASK; | |
486 | writel(reg | div, i2s->regs + S3C2412_IISMOD); | |
ee7d4767 | 487 | pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD)); |
dc85447b BD |
488 | break; |
489 | ||
490 | case S3C_I2SV2_DIV_PRESCALER: | |
491 | if (div >= 0) { | |
492 | writel((div << 8) | S3C2412_IISPSR_PSREN, | |
493 | i2s->regs + S3C2412_IISPSR); | |
494 | } else { | |
495 | writel(0x0, i2s->regs + S3C2412_IISPSR); | |
496 | } | |
ee7d4767 | 497 | pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR)); |
dc85447b BD |
498 | break; |
499 | ||
500 | default: | |
501 | return -EINVAL; | |
502 | } | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
507 | /* default table of all avaialable root fs divisors */ | |
508 | static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 }; | |
509 | ||
1d2b7ae9 BD |
510 | int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info, |
511 | unsigned int *fstab, | |
512 | unsigned int rate, struct clk *clk) | |
dc85447b BD |
513 | { |
514 | unsigned long clkrate = clk_get_rate(clk); | |
515 | unsigned int div; | |
516 | unsigned int fsclk; | |
517 | unsigned int actual; | |
518 | unsigned int fs; | |
519 | unsigned int fsdiv; | |
520 | signed int deviation = 0; | |
521 | unsigned int best_fs = 0; | |
522 | unsigned int best_div = 0; | |
523 | unsigned int best_rate = 0; | |
524 | unsigned int best_deviation = INT_MAX; | |
525 | ||
af3ea7bd MB |
526 | pr_debug("Input clock rate %ldHz\n", clkrate); |
527 | ||
dc85447b BD |
528 | if (fstab == NULL) |
529 | fstab = iis_fs_tab; | |
530 | ||
531 | for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) { | |
532 | fsdiv = iis_fs_tab[fs]; | |
533 | ||
534 | fsclk = clkrate / fsdiv; | |
535 | div = fsclk / rate; | |
536 | ||
537 | if ((fsclk % rate) > (rate / 2)) | |
538 | div++; | |
539 | ||
540 | if (div <= 1) | |
541 | continue; | |
542 | ||
543 | actual = clkrate / (fsdiv * div); | |
544 | deviation = actual - rate; | |
545 | ||
546 | printk(KERN_DEBUG "%dfs: div %d => result %d, deviation %d\n", | |
547 | fsdiv, div, actual, deviation); | |
548 | ||
549 | deviation = abs(deviation); | |
550 | ||
551 | if (deviation < best_deviation) { | |
552 | best_fs = fsdiv; | |
553 | best_div = div; | |
554 | best_rate = actual; | |
555 | best_deviation = deviation; | |
556 | } | |
557 | ||
558 | if (deviation == 0) | |
559 | break; | |
560 | } | |
561 | ||
562 | printk(KERN_DEBUG "best: fs=%d, div=%d, rate=%d\n", | |
563 | best_fs, best_div, best_rate); | |
564 | ||
565 | info->fs_div = best_fs; | |
566 | info->clk_div = best_div; | |
567 | ||
568 | return 0; | |
569 | } | |
1d2b7ae9 | 570 | EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate); |
dc85447b BD |
571 | |
572 | int s3c_i2sv2_probe(struct platform_device *pdev, | |
573 | struct snd_soc_dai *dai, | |
574 | struct s3c_i2sv2_info *i2s, | |
575 | unsigned long base) | |
576 | { | |
577 | struct device *dev = &pdev->dev; | |
07736d48 | 578 | unsigned int iismod; |
dc85447b BD |
579 | |
580 | i2s->dev = dev; | |
581 | ||
582 | /* record our i2s structure for later use in the callbacks */ | |
583 | dai->private_data = i2s; | |
584 | ||
c86bde54 MB |
585 | if (!base) { |
586 | struct resource *res = platform_get_resource(pdev, | |
587 | IORESOURCE_MEM, | |
588 | 0); | |
589 | if (!res) { | |
590 | dev_err(dev, "Unable to get register resource\n"); | |
591 | return -ENXIO; | |
592 | } | |
593 | ||
594 | if (!request_mem_region(res->start, resource_size(res), | |
595 | "s3c64xx-i2s-v4")) { | |
596 | dev_err(dev, "Unable to request register region\n"); | |
597 | return -EBUSY; | |
598 | } | |
599 | ||
600 | base = res->start; | |
601 | } | |
602 | ||
dc85447b BD |
603 | i2s->regs = ioremap(base, 0x100); |
604 | if (i2s->regs == NULL) { | |
605 | dev_err(dev, "cannot ioremap registers\n"); | |
606 | return -ENXIO; | |
607 | } | |
608 | ||
609 | i2s->iis_pclk = clk_get(dev, "iis"); | |
610 | if (i2s->iis_pclk == NULL) { | |
b52a5195 | 611 | dev_err(dev, "failed to get iis_clock\n"); |
dc85447b BD |
612 | iounmap(i2s->regs); |
613 | return -ENOENT; | |
614 | } | |
615 | ||
616 | clk_enable(i2s->iis_pclk); | |
617 | ||
07736d48 MB |
618 | /* Mark ourselves as in TXRX mode so we can run through our cleanup |
619 | * process without warnings. */ | |
620 | iismod = readl(i2s->regs + S3C2412_IISMOD); | |
621 | iismod |= S3C2412_IISMOD_MODE_TXRX; | |
622 | writel(iismod, i2s->regs + S3C2412_IISMOD); | |
dc85447b BD |
623 | s3c2412_snd_txctrl(i2s, 0); |
624 | s3c2412_snd_rxctrl(i2s, 0); | |
625 | ||
626 | return 0; | |
627 | } | |
dc85447b BD |
628 | EXPORT_SYMBOL_GPL(s3c_i2sv2_probe); |
629 | ||
630 | #ifdef CONFIG_PM | |
631 | static int s3c2412_i2s_suspend(struct snd_soc_dai *dai) | |
632 | { | |
633 | struct s3c_i2sv2_info *i2s = to_info(dai); | |
634 | u32 iismod; | |
635 | ||
636 | if (dai->active) { | |
637 | i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD); | |
638 | i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON); | |
639 | i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR); | |
640 | ||
641 | /* some basic suspend checks */ | |
642 | ||
643 | iismod = readl(i2s->regs + S3C2412_IISMOD); | |
644 | ||
645 | if (iismod & S3C2412_IISCON_RXDMA_ACTIVE) | |
646 | pr_warning("%s: RXDMA active?\n", __func__); | |
647 | ||
648 | if (iismod & S3C2412_IISCON_TXDMA_ACTIVE) | |
649 | pr_warning("%s: TXDMA active?\n", __func__); | |
650 | ||
651 | if (iismod & S3C2412_IISCON_IIS_ACTIVE) | |
652 | pr_warning("%s: IIS active\n", __func__); | |
653 | } | |
654 | ||
655 | return 0; | |
656 | } | |
657 | ||
658 | static int s3c2412_i2s_resume(struct snd_soc_dai *dai) | |
659 | { | |
660 | struct s3c_i2sv2_info *i2s = to_info(dai); | |
661 | ||
662 | pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n", | |
663 | dai->active, i2s->suspend_iismod, i2s->suspend_iiscon); | |
664 | ||
665 | if (dai->active) { | |
666 | writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON); | |
667 | writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD); | |
668 | writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR); | |
669 | ||
670 | writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH, | |
671 | i2s->regs + S3C2412_IISFIC); | |
672 | ||
673 | ndelay(250); | |
674 | writel(0x0, i2s->regs + S3C2412_IISFIC); | |
675 | } | |
676 | ||
677 | return 0; | |
678 | } | |
679 | #else | |
680 | #define s3c2412_i2s_suspend NULL | |
681 | #define s3c2412_i2s_resume NULL | |
682 | #endif | |
683 | ||
684 | int s3c_i2sv2_register_dai(struct snd_soc_dai *dai) | |
685 | { | |
3715c6aa BD |
686 | struct snd_soc_dai_ops *ops = dai->ops; |
687 | ||
688 | ops->trigger = s3c2412_i2s_trigger; | |
689 | ops->hw_params = s3c2412_i2s_hw_params; | |
690 | ops->set_fmt = s3c2412_i2s_set_fmt; | |
691 | ops->set_clkdiv = s3c2412_i2s_set_clkdiv; | |
dc85447b BD |
692 | |
693 | dai->suspend = s3c2412_i2s_suspend; | |
694 | dai->resume = s3c2412_i2s_resume; | |
695 | ||
696 | return snd_soc_register_dai(dai); | |
697 | } | |
dc85447b | 698 | EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai); |
a396e32e MB |
699 | |
700 | MODULE_LICENSE("GPL"); |