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Merge branch 'for-2.6.35' into for-2.6.36
[deliverable/linux.git] / sound / soc / s3c24xx / s3c-i2s-v2.c
CommitLineData
dc85447b
BD		 1/* sound/soc/s3c24xx/s3c-i2c-v2.c
2 *
3 * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
4 *
5 * Copyright (c) 2006 Wolfson Microelectronics PLC.
6 * Graeme Gregory graeme.gregory@wolfsonmicro.com
7 * linux@wolfsonmicro.com
8 *
9 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 * Ben Dooks <ben@simtec.co.uk>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
dc85447b
BD		 19#include <linux/delay.h>
20#include <linux/clk.h>
dc85447b
BD		 21#include <linux/io.h>
22
dc85447b
BD		 23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
dc85447b
BD		 25#include <sound/soc.h>
26
dc85447b
BD		 27#include <mach/dma.h>
28
d07e7ce9 29#include "regs-i2s-v2.h"
dc85447b 30#include "s3c-i2s-v2.h"
d3ff5a3e 31#include "s3c-dma.h"
dc85447b 32
8a0f62b8
MB		 33#undef S3C_IIS_V2_SUPPORTED
34
35#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
36#define S3C_IIS_V2_SUPPORTED
37#endif
38
39#ifdef CONFIG_PLAT_S3C64XX
40#define S3C_IIS_V2_SUPPORTED
41#endif
42
43#ifndef S3C_IIS_V2_SUPPORTED
44#error Unsupported CPU model
45#endif
46
dc85447b 47#define S3C2412_I2S_DEBUG_CON 0
dc85447b
BD		 48
49static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
50{
51 return cpu_dai->private_data;
52}
53
54#define bit_set(v, b) (((v) & (b)) ? 1 : 0)
55
56#if S3C2412_I2S_DEBUG_CON
57static void dbg_showcon(const char *fn, u32 con)
58{
59 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
60 bit_set(con, S3C2412_IISCON_LRINDEX),
61 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
62 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
63 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
64 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
65
66 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
67 fn,
68 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
69 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
70 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
71 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
72 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
73 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
74 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
75 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
76}
77#else
78static inline void dbg_showcon(const char *fn, u32 con)
79{
80}
81#endif
82
83
84/* Turn on or off the transmission path. */
abbc8246 85static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 86{
87 void __iomem *regs = i2s->regs;
88 u32 fic, con, mod;
89
ee7d4767 90 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 91
92 fic = readl(regs + S3C2412_IISFIC);
93 con = readl(regs + S3C2412_IISCON);
94 mod = readl(regs + S3C2412_IISMOD);
95
ee7d4767 96 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 97
98 if (on) {
99 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
100 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
101 con &= ~S3C2412_IISCON_TXCH_PAUSE;
102
103 switch (mod & S3C2412_IISMOD_MODE_MASK) {
104 case S3C2412_IISMOD_MODE_TXONLY:
105 case S3C2412_IISMOD_MODE_TXRX:
106 /* do nothing, we are in the right mode */
107 break;
108
109 case S3C2412_IISMOD_MODE_RXONLY:
110 mod &= ~S3C2412_IISMOD_MODE_MASK;
111 mod |= S3C2412_IISMOD_MODE_TXRX;
112 break;
113
114 default:
abbc8246
MB		 115 dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
116 mod & S3C2412_IISMOD_MODE_MASK);
117 break;
dc85447b
BD		 118 }
119
120 writel(con, regs + S3C2412_IISCON);
121 writel(mod, regs + S3C2412_IISMOD);
122 } else {
123 /* Note, we do not have any indication that the FIFO problems
124 * tha the S3C2410/2440 had apply here, so we should be able
125 * to disable the DMA and TX without resetting the FIFOS.
126 */
127
128 con |= S3C2412_IISCON_TXDMA_PAUSE;
129 con |= S3C2412_IISCON_TXCH_PAUSE;
130 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
131
132 switch (mod & S3C2412_IISMOD_MODE_MASK) {
133 case S3C2412_IISMOD_MODE_TXRX:
134 mod &= ~S3C2412_IISMOD_MODE_MASK;
135 mod |= S3C2412_IISMOD_MODE_RXONLY;
136 break;
137
138 case S3C2412_IISMOD_MODE_TXONLY:
139 mod &= ~S3C2412_IISMOD_MODE_MASK;
140 con &= ~S3C2412_IISCON_IIS_ACTIVE;
141 break;
142
143 default:
abbc8246
MB		 144 dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
145 mod & S3C2412_IISMOD_MODE_MASK);
146 break;
dc85447b
BD		 147 }
148
149 writel(mod, regs + S3C2412_IISMOD);
150 writel(con, regs + S3C2412_IISCON);
151 }
152
153 fic = readl(regs + S3C2412_IISFIC);
154 dbg_showcon(__func__, con);
ee7d4767 155 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 156}
dc85447b 157
abbc8246 158static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 159{
160 void __iomem *regs = i2s->regs;
161 u32 fic, con, mod;
162
ee7d4767 163 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 164
165 fic = readl(regs + S3C2412_IISFIC);
166 con = readl(regs + S3C2412_IISCON);
167 mod = readl(regs + S3C2412_IISMOD);
168
ee7d4767 169 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 170
171 if (on) {
172 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
173 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
174 con &= ~S3C2412_IISCON_RXCH_PAUSE;
175
176 switch (mod & S3C2412_IISMOD_MODE_MASK) {
177 case S3C2412_IISMOD_MODE_TXRX:
178 case S3C2412_IISMOD_MODE_RXONLY:
179 /* do nothing, we are in the right mode */
180 break;
181
182 case S3C2412_IISMOD_MODE_TXONLY:
183 mod &= ~S3C2412_IISMOD_MODE_MASK;
184 mod |= S3C2412_IISMOD_MODE_TXRX;
185 break;
186
187 default:
abbc8246
MB		 188 dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
189 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 190 }
191
192 writel(mod, regs + S3C2412_IISMOD);
193 writel(con, regs + S3C2412_IISCON);
194 } else {
195 /* See txctrl notes on FIFOs. */
196
197 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
198 con |= S3C2412_IISCON_RXDMA_PAUSE;
199 con |= S3C2412_IISCON_RXCH_PAUSE;
200
201 switch (mod & S3C2412_IISMOD_MODE_MASK) {
202 case S3C2412_IISMOD_MODE_RXONLY:
203 con &= ~S3C2412_IISCON_IIS_ACTIVE;
204 mod &= ~S3C2412_IISMOD_MODE_MASK;
205 break;
206
207 case S3C2412_IISMOD_MODE_TXRX:
208 mod &= ~S3C2412_IISMOD_MODE_MASK;
209 mod |= S3C2412_IISMOD_MODE_TXONLY;
210 break;
211
212 default:
abbc8246
MB		 213 dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
214 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 215 }
216
217 writel(con, regs + S3C2412_IISCON);
218 writel(mod, regs + S3C2412_IISMOD);
219 }
220
221 fic = readl(regs + S3C2412_IISFIC);
ee7d4767 222 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 223}
dc85447b 224
fa68e002
J		 225#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
226
dc85447b
BD		 227/*
228 * Wait for the LR signal to allow synchronisation to the L/R clock
229 * from the codec. May only be needed for slave mode.
230 */
231static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
232{
233 u32 iiscon;
fa68e002 234 unsigned long loops = msecs_to_loops(5);
dc85447b 235
ee7d4767 236 pr_debug("Entered %s\n", __func__);
dc85447b 237
fa68e002 238 while (--loops) {
dc85447b
BD		 239 iiscon = readl(i2s->regs + S3C2412_IISCON);
240 if (iiscon & S3C2412_IISCON_LRINDEX)
241 break;
242
fa68e002
J		 243 cpu_relax();
244 }
245
246 if (!loops) {
247 printk(KERN_ERR "%s: timeout\n", __func__);
248 return -ETIMEDOUT;
dc85447b
BD		 249 }
250
251 return 0;
252}
253
254/*
255 * Set S3C2412 I2S DAI format
256 */
257static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
258 unsigned int fmt)
259{
260 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
261 u32 iismod;
262
ee7d4767 263 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 264
265 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 266 pr_debug("hw_params r: IISMOD: %x \n", iismod);
dc85447b 267
dc85447b
BD		 268 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
269 case SND_SOC_DAIFMT_CBM_CFM:
270 i2s->master = 0;
ce76f9fd 271 iismod |= S3C2412_IISMOD_SLAVE;
dc85447b
BD		 272 break;
273 case SND_SOC_DAIFMT_CBS_CFS:
274 i2s->master = 1;
ce76f9fd 275 iismod &= ~S3C2412_IISMOD_SLAVE;
dc85447b
BD		 276 break;
277 default:
38e43c81 278 pr_err("unknwon master/slave format\n");
dc85447b
BD		 279 return -EINVAL;
280 }
281
282 iismod &= ~S3C2412_IISMOD_SDF_MASK;
283
284 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
285 case SND_SOC_DAIFMT_RIGHT_J:
fd5ad654 286 iismod |= S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 287 iismod |= S3C2412_IISMOD_SDF_MSB;
288 break;
289 case SND_SOC_DAIFMT_LEFT_J:
fd5ad654 290 iismod |= S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 291 iismod |= S3C2412_IISMOD_SDF_LSB;
292 break;
293 case SND_SOC_DAIFMT_I2S:
fd5ad654 294 iismod &= ~S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 295 iismod |= S3C2412_IISMOD_SDF_IIS;
296 break;
297 default:
38e43c81 298 pr_err("Unknown data format\n");
dc85447b
BD		 299 return -EINVAL;
300 }
301
302 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 303 pr_debug("hw_params w: IISMOD: %x \n", iismod);
dc85447b
BD		 304 return 0;
305}
306
9c9b1257 307static int s3c_i2sv2_hw_params(struct snd_pcm_substream *substream,
dc85447b
BD		 308 struct snd_pcm_hw_params *params,
309 struct snd_soc_dai *socdai)
310{
311 struct snd_soc_pcm_runtime *rtd = substream->private_data;
312 struct snd_soc_dai_link *dai = rtd->dai;
313 struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai);
fd23b7de 314 struct s3c_dma_params *dma_data;
dc85447b
BD		 315 u32 iismod;
316
ee7d4767 317 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 318
319 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
fd23b7de 320 dma_data = i2s->dma_playback;
dc85447b 321 else
fd23b7de
DM		 322 dma_data = i2s->dma_capture;
323
324 snd_soc_dai_set_dma_data(dai->cpu_dai, substream, dma_data);
dc85447b
BD		 325
326 /* Working copies of register */
327 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 328 pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
dc85447b 329
bf328826 330 iismod &= ~S3C64XX_IISMOD_BLC_MASK;
553b1dd5
MB		 331 /* Sample size */
332 switch (params_format(params)) {
333 case SNDRV_PCM_FORMAT_S8:
bf328826 334 iismod |= S3C64XX_IISMOD_BLC_8BIT;
553b1dd5
MB		 335 break;
336 case SNDRV_PCM_FORMAT_S16_LE:
553b1dd5
MB		 337 break;
338 case SNDRV_PCM_FORMAT_S24_LE:
bf328826 339 iismod |= S3C64XX_IISMOD_BLC_24BIT;
553b1dd5
MB		 340 break;
341 }
dc85447b
BD		 342
343 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 344 pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
8a7c2518
JB		 345
346 return 0;
347}
348
349static int s3c_i2sv2_set_sysclk(struct snd_soc_dai *cpu_dai,
350 int clk_id, unsigned int freq, int dir)
351{
352 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
353 u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
354
355 pr_debug("Entered %s\n", __func__);
356 pr_debug("%s r: IISMOD: %x\n", __func__, iismod);
357
358 switch (clk_id) {
359 case S3C_I2SV2_CLKSRC_PCLK:
360 iismod &= ~S3C2412_IISMOD_IMS_SYSMUX;
361 break;
362
363 case S3C_I2SV2_CLKSRC_AUDIOBUS:
364 iismod |= S3C2412_IISMOD_IMS_SYSMUX;
365 break;
366
367 case S3C_I2SV2_CLKSRC_CDCLK:
368 /* Error if controller doesn't have the CDCLKCON bit */
369 if (!(i2s->feature & S3C_FEATURE_CDCLKCON))
370 return -EINVAL;
371
372 switch (dir) {
373 case SND_SOC_CLOCK_IN:
374 iismod |= S3C64XX_IISMOD_CDCLKCON;
375 break;
376 case SND_SOC_CLOCK_OUT:
377 iismod &= ~S3C64XX_IISMOD_CDCLKCON;
378 break;
379 default:
380 return -EINVAL;
381 }
382 break;
383
384 default:
385 return -EINVAL;
386 }
387
388 writel(iismod, i2s->regs + S3C2412_IISMOD);
389 pr_debug("%s w: IISMOD: %x\n", __func__, iismod);
390
dc85447b
BD		 391 return 0;
392}
393
394static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
395 struct snd_soc_dai *dai)
396{
397 struct snd_soc_pcm_runtime *rtd = substream->private_data;
398 struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai);
399 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
400 unsigned long irqs;
401 int ret = 0;
fd23b7de
DM		 402 struct s3c_dma_params *dma_data =
403 snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream);
dc85447b 404
ee7d4767 405 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 406
407 switch (cmd) {
408 case SNDRV_PCM_TRIGGER_START:
409 /* On start, ensure that the FIFOs are cleared and reset. */
410
411 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
412 i2s->regs + S3C2412_IISFIC);
413
414 /* clear again, just in case */
415 writel(0x0, i2s->regs + S3C2412_IISFIC);
416
417 case SNDRV_PCM_TRIGGER_RESUME:
418 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
419 if (!i2s->master) {
420 ret = s3c2412_snd_lrsync(i2s);
421 if (ret)
422 goto exit_err;
423 }
424
425 local_irq_save(irqs);
426
427 if (capture)
428 s3c2412_snd_rxctrl(i2s, 1);
429 else
430 s3c2412_snd_txctrl(i2s, 1);
431
432 local_irq_restore(irqs);
faf907c7
SL		 433
434 /*
435 * Load the next buffer to DMA to meet the reqirement
436 * of the auto reload mechanism of S3C24XX.
437 * This call won't bother S3C64XX.
438 */
fd23b7de 439 s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
faf907c7 440
dc85447b
BD		 441 break;
442
443 case SNDRV_PCM_TRIGGER_STOP:
444 case SNDRV_PCM_TRIGGER_SUSPEND:
445 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
446 local_irq_save(irqs);
447
448 if (capture)
449 s3c2412_snd_rxctrl(i2s, 0);
450 else
451 s3c2412_snd_txctrl(i2s, 0);
452
453 local_irq_restore(irqs);
454 break;
455 default:
456 ret = -EINVAL;
457 break;
458 }
459
460exit_err:
461 return ret;
462}
463
464/*
465 * Set S3C2412 Clock dividers
466 */
467static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
468 int div_id, int div)
469{
470 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
471 u32 reg;
472
ee7d4767 473 pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
dc85447b
BD		 474
475 switch (div_id) {
476 case S3C_I2SV2_DIV_BCLK:
51c6ab13
JB		 477 switch (div) {
478 case 16:
479 div = S3C2412_IISMOD_BCLK_16FS;
480 break;
fd5ad654 481
51c6ab13
JB		 482 case 32:
483 div = S3C2412_IISMOD_BCLK_32FS;
484 break;
fd5ad654 485
51c6ab13
JB		 486 case 24:
487 div = S3C2412_IISMOD_BCLK_24FS;
488 break;
fd5ad654 489
51c6ab13
JB		 490 case 48:
491 div = S3C2412_IISMOD_BCLK_48FS;
492 break;
fd5ad654 493
51c6ab13
JB		 494 default:
495 return -EINVAL;
fd5ad654
J		 496 }
497
dc85447b
BD		 498 reg = readl(i2s->regs + S3C2412_IISMOD);
499 reg &= ~S3C2412_IISMOD_BCLK_MASK;
500 writel(reg | div, i2s->regs + S3C2412_IISMOD);
501
ee7d4767 502 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 503 break;
504
505 case S3C_I2SV2_DIV_RCLK:
51c6ab13
JB		 506 switch (div) {
507 case 256:
508 div = S3C2412_IISMOD_RCLK_256FS;
509 break;
dc85447b 510
51c6ab13
JB		 511 case 384:
512 div = S3C2412_IISMOD_RCLK_384FS;
513 break;
dc85447b 514
51c6ab13
JB		 515 case 512:
516 div = S3C2412_IISMOD_RCLK_512FS;
517 break;
dc85447b 518
51c6ab13
JB		 519 case 768:
520 div = S3C2412_IISMOD_RCLK_768FS;
521 break;
dc85447b 522
51c6ab13
JB		 523 default:
524 return -EINVAL;
dc85447b
BD		 525 }
526
527 reg = readl(i2s->regs + S3C2412_IISMOD);
528 reg &= ~S3C2412_IISMOD_RCLK_MASK;
529 writel(reg | div, i2s->regs + S3C2412_IISMOD);
ee7d4767 530 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 531 break;
532
533 case S3C_I2SV2_DIV_PRESCALER:
534 if (div >= 0) {
535 writel((div << 8) | S3C2412_IISPSR_PSREN,
536 i2s->regs + S3C2412_IISPSR);
537 } else {
538 writel(0x0, i2s->regs + S3C2412_IISPSR);
539 }
ee7d4767 540 pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
dc85447b
BD		 541 break;
542
543 default:
544 return -EINVAL;
545 }
546
547 return 0;
548}
549
1ca75780
MB		 550static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream,
551 struct snd_soc_dai *dai)
552{
553 struct s3c_i2sv2_info *i2s = to_info(dai);
554 u32 reg = readl(i2s->regs + S3C2412_IISFIC);
555 snd_pcm_sframes_t delay;
556
557 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
558 delay = S3C2412_IISFIC_TXCOUNT(reg);
559 else
560 delay = S3C2412_IISFIC_RXCOUNT(reg);
561
562 return delay;
563}
564
57282427
JB		 565struct clk *s3c_i2sv2_get_clock(struct snd_soc_dai *cpu_dai)
566{
567 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
568 u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
569
570 if (iismod & S3C2412_IISMOD_IMS_SYSMUX)
571 return i2s->iis_cclk;
572 else
573 return i2s->iis_pclk;
574}
575EXPORT_SYMBOL_GPL(s3c_i2sv2_get_clock);
576
dc85447b
BD		 577/* default table of all avaialable root fs divisors */
578static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
579
1d2b7ae9
BD		 580int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
581 unsigned int *fstab,
582 unsigned int rate, struct clk *clk)
dc85447b
BD		 583{
584 unsigned long clkrate = clk_get_rate(clk);
585 unsigned int div;
586 unsigned int fsclk;
587 unsigned int actual;
588 unsigned int fs;
589 unsigned int fsdiv;
590 signed int deviation = 0;
591 unsigned int best_fs = 0;
592 unsigned int best_div = 0;
593 unsigned int best_rate = 0;
594 unsigned int best_deviation = INT_MAX;
595
af3ea7bd
MB		 596 pr_debug("Input clock rate %ldHz\n", clkrate);
597
dc85447b
BD		 598 if (fstab == NULL)
599 fstab = iis_fs_tab;
600
601 for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
602 fsdiv = iis_fs_tab[fs];
603
604 fsclk = clkrate / fsdiv;
605 div = fsclk / rate;
606
607 if ((fsclk % rate) > (rate / 2))
608 div++;
609
610 if (div <= 1)
611 continue;
612
613 actual = clkrate / (fsdiv * div);
614 deviation = actual - rate;
615
449bd54d 616 printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
dc85447b
BD		 617 fsdiv, div, actual, deviation);
618
619 deviation = abs(deviation);
620
621 if (deviation < best_deviation) {
622 best_fs = fsdiv;
623 best_div = div;
624 best_rate = actual;
625 best_deviation = deviation;
626 }
627
628 if (deviation == 0)
629 break;
630 }
631
449bd54d 632 printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
dc85447b
BD		 633 best_fs, best_div, best_rate);
634
635 info->fs_div = best_fs;
636 info->clk_div = best_div;
637
638 return 0;
639}
1d2b7ae9 640EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
dc85447b
BD		 641
642int s3c_i2sv2_probe(struct platform_device *pdev,
643 struct snd_soc_dai *dai,
644 struct s3c_i2sv2_info *i2s,
645 unsigned long base)
646{
647 struct device *dev = &pdev->dev;
07736d48 648 unsigned int iismod;
dc85447b
BD		 649
650 i2s->dev = dev;
651
652 /* record our i2s structure for later use in the callbacks */
653 dai->private_data = i2s;
654
c86bde54
MB		 655 if (!base) {
656 struct resource *res = platform_get_resource(pdev,
657 IORESOURCE_MEM,
658 0);
659 if (!res) {
660 dev_err(dev, "Unable to get register resource\n");
661 return -ENXIO;
662 }
663
664 if (!request_mem_region(res->start, resource_size(res),
665 "s3c64xx-i2s-v4")) {
666 dev_err(dev, "Unable to request register region\n");
667 return -EBUSY;
668 }
669
670 base = res->start;
671 }
672
dc85447b
BD		 673 i2s->regs = ioremap(base, 0x100);
674 if (i2s->regs == NULL) {
675 dev_err(dev, "cannot ioremap registers\n");
676 return -ENXIO;
677 }
678
679 i2s->iis_pclk = clk_get(dev, "iis");
fd5ad654 680 if (IS_ERR(i2s->iis_pclk)) {
b52a5195 681 dev_err(dev, "failed to get iis_clock\n");
dc85447b
BD		 682 iounmap(i2s->regs);
683 return -ENOENT;
684 }
685
686 clk_enable(i2s->iis_pclk);
687
07736d48
MB		 688 /* Mark ourselves as in TXRX mode so we can run through our cleanup
689 * process without warnings. */
690 iismod = readl(i2s->regs + S3C2412_IISMOD);
691 iismod |= S3C2412_IISMOD_MODE_TXRX;
692 writel(iismod, i2s->regs + S3C2412_IISMOD);
dc85447b
BD		 693 s3c2412_snd_txctrl(i2s, 0);
694 s3c2412_snd_rxctrl(i2s, 0);
695
696 return 0;
697}
dc85447b
BD		 698EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
699
700#ifdef CONFIG_PM
701static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
702{
703 struct s3c_i2sv2_info *i2s = to_info(dai);
704 u32 iismod;
705
706 if (dai->active) {
707 i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
708 i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
709 i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
710
711 /* some basic suspend checks */
712
713 iismod = readl(i2s->regs + S3C2412_IISMOD);
714
715 if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
716 pr_warning("%s: RXDMA active?\n", __func__);
717
718 if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
719 pr_warning("%s: TXDMA active?\n", __func__);
720
721 if (iismod & S3C2412_IISCON_IIS_ACTIVE)
722 pr_warning("%s: IIS active\n", __func__);
723 }
724
725 return 0;
726}
727
728static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
729{
730 struct s3c_i2sv2_info *i2s = to_info(dai);
731
732 pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
733 dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
734
735 if (dai->active) {
736 writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
737 writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
738 writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
739
740 writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
741 i2s->regs + S3C2412_IISFIC);
742
743 ndelay(250);
744 writel(0x0, i2s->regs + S3C2412_IISFIC);
745 }
746
747 return 0;
748}
749#else
750#define s3c2412_i2s_suspend NULL
751#define s3c2412_i2s_resume NULL
752#endif
753
754int s3c_i2sv2_register_dai(struct snd_soc_dai *dai)
755{
3715c6aa
BD		 756 struct snd_soc_dai_ops *ops = dai->ops;
757
758 ops->trigger = s3c2412_i2s_trigger;
9c9b1257
JB		 759 if (!ops->hw_params)
760 ops->hw_params = s3c_i2sv2_hw_params;
3715c6aa
BD		 761 ops->set_fmt = s3c2412_i2s_set_fmt;
762 ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
8a7c2518 763 ops->set_sysclk = s3c_i2sv2_set_sysclk;
dc85447b 764
1ca75780
MB		 765 /* Allow overriding by (for example) IISv4 */
766 if (!ops->delay)
08226614 767 ops->delay = s3c2412_i2s_delay;
1ca75780 768
dc85447b
BD		 769 dai->suspend = s3c2412_i2s_suspend;
770 dai->resume = s3c2412_i2s_resume;
771
772 return snd_soc_register_dai(dai);
773}
dc85447b 774EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai);
a396e32e
MB		 775
776MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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