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ASoC: Fix display of stream name in DAPM debugfs
[deliverable/linux.git] / sound / soc / s3c24xx / s3c-i2s-v2.c
CommitLineData
dc85447b
BD		 1/* sound/soc/s3c24xx/s3c-i2c-v2.c
2 *
3 * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
4 *
5 * Copyright (c) 2006 Wolfson Microelectronics PLC.
6 * Graeme Gregory graeme.gregory@wolfsonmicro.com
7 * linux@wolfsonmicro.com
8 *
9 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 * Ben Dooks <ben@simtec.co.uk>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/device.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/kernel.h>
25#include <linux/io.h>
26
27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/initval.h>
31#include <sound/soc.h>
32
33#include <plat/regs-s3c2412-iis.h>
34
35#include <plat/audio.h>
36#include <mach/dma.h>
37
38#include "s3c-i2s-v2.h"
5dc07481 39#include "s3c24xx-pcm.h"
dc85447b 40
8a0f62b8
MB		 41#undef S3C_IIS_V2_SUPPORTED
42
43#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
44#define S3C_IIS_V2_SUPPORTED
45#endif
46
47#ifdef CONFIG_PLAT_S3C64XX
48#define S3C_IIS_V2_SUPPORTED
49#endif
50
51#ifndef S3C_IIS_V2_SUPPORTED
52#error Unsupported CPU model
53#endif
54
dc85447b 55#define S3C2412_I2S_DEBUG_CON 0
dc85447b
BD		 56
57static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
58{
59 return cpu_dai->private_data;
60}
61
62#define bit_set(v, b) (((v) & (b)) ? 1 : 0)
63
64#if S3C2412_I2S_DEBUG_CON
65static void dbg_showcon(const char *fn, u32 con)
66{
67 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
68 bit_set(con, S3C2412_IISCON_LRINDEX),
69 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
70 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
71 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
72 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
73
74 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
75 fn,
76 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
77 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
78 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
79 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
80 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
81 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
82 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
83 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
84}
85#else
86static inline void dbg_showcon(const char *fn, u32 con)
87{
88}
89#endif
90
91
92/* Turn on or off the transmission path. */
abbc8246 93static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 94{
95 void __iomem *regs = i2s->regs;
96 u32 fic, con, mod;
97
ee7d4767 98 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 99
100 fic = readl(regs + S3C2412_IISFIC);
101 con = readl(regs + S3C2412_IISCON);
102 mod = readl(regs + S3C2412_IISMOD);
103
ee7d4767 104 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 105
106 if (on) {
107 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
108 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
109 con &= ~S3C2412_IISCON_TXCH_PAUSE;
110
111 switch (mod & S3C2412_IISMOD_MODE_MASK) {
112 case S3C2412_IISMOD_MODE_TXONLY:
113 case S3C2412_IISMOD_MODE_TXRX:
114 /* do nothing, we are in the right mode */
115 break;
116
117 case S3C2412_IISMOD_MODE_RXONLY:
118 mod &= ~S3C2412_IISMOD_MODE_MASK;
119 mod |= S3C2412_IISMOD_MODE_TXRX;
120 break;
121
122 default:
abbc8246
MB		 123 dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
124 mod & S3C2412_IISMOD_MODE_MASK);
125 break;
dc85447b
BD		 126 }
127
128 writel(con, regs + S3C2412_IISCON);
129 writel(mod, regs + S3C2412_IISMOD);
130 } else {
131 /* Note, we do not have any indication that the FIFO problems
132 * tha the S3C2410/2440 had apply here, so we should be able
133 * to disable the DMA and TX without resetting the FIFOS.
134 */
135
136 con |= S3C2412_IISCON_TXDMA_PAUSE;
137 con |= S3C2412_IISCON_TXCH_PAUSE;
138 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
139
140 switch (mod & S3C2412_IISMOD_MODE_MASK) {
141 case S3C2412_IISMOD_MODE_TXRX:
142 mod &= ~S3C2412_IISMOD_MODE_MASK;
143 mod |= S3C2412_IISMOD_MODE_RXONLY;
144 break;
145
146 case S3C2412_IISMOD_MODE_TXONLY:
147 mod &= ~S3C2412_IISMOD_MODE_MASK;
148 con &= ~S3C2412_IISCON_IIS_ACTIVE;
149 break;
150
151 default:
abbc8246
MB		 152 dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
153 mod & S3C2412_IISMOD_MODE_MASK);
154 break;
dc85447b
BD		 155 }
156
157 writel(mod, regs + S3C2412_IISMOD);
158 writel(con, regs + S3C2412_IISCON);
159 }
160
161 fic = readl(regs + S3C2412_IISFIC);
162 dbg_showcon(__func__, con);
ee7d4767 163 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 164}
dc85447b 165
abbc8246 166static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 167{
168 void __iomem *regs = i2s->regs;
169 u32 fic, con, mod;
170
ee7d4767 171 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 172
173 fic = readl(regs + S3C2412_IISFIC);
174 con = readl(regs + S3C2412_IISCON);
175 mod = readl(regs + S3C2412_IISMOD);
176
ee7d4767 177 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 178
179 if (on) {
180 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
181 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
182 con &= ~S3C2412_IISCON_RXCH_PAUSE;
183
184 switch (mod & S3C2412_IISMOD_MODE_MASK) {
185 case S3C2412_IISMOD_MODE_TXRX:
186 case S3C2412_IISMOD_MODE_RXONLY:
187 /* do nothing, we are in the right mode */
188 break;
189
190 case S3C2412_IISMOD_MODE_TXONLY:
191 mod &= ~S3C2412_IISMOD_MODE_MASK;
192 mod |= S3C2412_IISMOD_MODE_TXRX;
193 break;
194
195 default:
abbc8246
MB		 196 dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
197 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 198 }
199
200 writel(mod, regs + S3C2412_IISMOD);
201 writel(con, regs + S3C2412_IISCON);
202 } else {
203 /* See txctrl notes on FIFOs. */
204
205 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
206 con |= S3C2412_IISCON_RXDMA_PAUSE;
207 con |= S3C2412_IISCON_RXCH_PAUSE;
208
209 switch (mod & S3C2412_IISMOD_MODE_MASK) {
210 case S3C2412_IISMOD_MODE_RXONLY:
211 con &= ~S3C2412_IISCON_IIS_ACTIVE;
212 mod &= ~S3C2412_IISMOD_MODE_MASK;
213 break;
214
215 case S3C2412_IISMOD_MODE_TXRX:
216 mod &= ~S3C2412_IISMOD_MODE_MASK;
217 mod |= S3C2412_IISMOD_MODE_TXONLY;
218 break;
219
220 default:
abbc8246
MB		 221 dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
222 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 223 }
224
225 writel(con, regs + S3C2412_IISCON);
226 writel(mod, regs + S3C2412_IISMOD);
227 }
228
229 fic = readl(regs + S3C2412_IISFIC);
ee7d4767 230 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 231}
dc85447b
BD		 232
233/*
234 * Wait for the LR signal to allow synchronisation to the L/R clock
235 * from the codec. May only be needed for slave mode.
236 */
237static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
238{
239 u32 iiscon;
240 unsigned long timeout = jiffies + msecs_to_jiffies(5);
241
ee7d4767 242 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 243
244 while (1) {
245 iiscon = readl(i2s->regs + S3C2412_IISCON);
246 if (iiscon & S3C2412_IISCON_LRINDEX)
247 break;
248
249 if (timeout < jiffies) {
250 printk(KERN_ERR "%s: timeout\n", __func__);
251 return -ETIMEDOUT;
252 }
253 }
254
255 return 0;
256}
257
258/*
259 * Set S3C2412 I2S DAI format
260 */
261static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
262 unsigned int fmt)
263{
264 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
265 u32 iismod;
266
ee7d4767 267 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 268
269 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 270 pr_debug("hw_params r: IISMOD: %x \n", iismod);
dc85447b
BD		 271
272#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
273#define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
274#define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
275#define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
276#endif
277
278#if defined(CONFIG_PLAT_S3C64XX)
279/* From Rev1.1 datasheet, we have two master and two slave modes:
280 * IMS[11:10]:
281 * 00 = master mode, fed from PCLK
282 * 01 = master mode, fed from CLKAUDIO
283 * 10 = slave mode, using PCLK
284 * 11 = slave mode, using I2SCLK
285 */
286#define IISMOD_MASTER_MASK (1 << 11)
287#define IISMOD_SLAVE (1 << 11)
553b1dd5 288#define IISMOD_MASTER (0 << 11)
dc85447b
BD		 289#endif
290
291 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
292 case SND_SOC_DAIFMT_CBM_CFM:
293 i2s->master = 0;
294 iismod &= ~IISMOD_MASTER_MASK;
295 iismod |= IISMOD_SLAVE;
296 break;
297 case SND_SOC_DAIFMT_CBS_CFS:
298 i2s->master = 1;
299 iismod &= ~IISMOD_MASTER_MASK;
300 iismod |= IISMOD_MASTER;
301 break;
302 default:
38e43c81 303 pr_err("unknwon master/slave format\n");
dc85447b
BD		 304 return -EINVAL;
305 }
306
307 iismod &= ~S3C2412_IISMOD_SDF_MASK;
308
309 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
310 case SND_SOC_DAIFMT_RIGHT_J:
311 iismod |= S3C2412_IISMOD_SDF_MSB;
312 break;
313 case SND_SOC_DAIFMT_LEFT_J:
314 iismod |= S3C2412_IISMOD_SDF_LSB;
315 break;
316 case SND_SOC_DAIFMT_I2S:
317 iismod |= S3C2412_IISMOD_SDF_IIS;
318 break;
319 default:
38e43c81 320 pr_err("Unknown data format\n");
dc85447b
BD		 321 return -EINVAL;
322 }
323
324 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 325 pr_debug("hw_params w: IISMOD: %x \n", iismod);
dc85447b
BD		 326 return 0;
327}
328
329static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
330 struct snd_pcm_hw_params *params,
331 struct snd_soc_dai *socdai)
332{
333 struct snd_soc_pcm_runtime *rtd = substream->private_data;
334 struct snd_soc_dai_link *dai = rtd->dai;
335 struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai);
336 u32 iismod;
337
ee7d4767 338 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 339
340 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
341 dai->cpu_dai->dma_data = i2s->dma_playback;
342 else
343 dai->cpu_dai->dma_data = i2s->dma_capture;
344
345 /* Working copies of register */
346 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 347 pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
dc85447b 348
553b1dd5 349#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
dc85447b
BD		 350 switch (params_format(params)) {
351 case SNDRV_PCM_FORMAT_S8:
352 iismod |= S3C2412_IISMOD_8BIT;
353 break;
354 case SNDRV_PCM_FORMAT_S16_LE:
355 iismod &= ~S3C2412_IISMOD_8BIT;
356 break;
357 }
553b1dd5
MB		 358#endif
359
360#ifdef CONFIG_PLAT_S3C64XX
0914b93f 361 iismod &= ~(S3C64XX_IISMOD_BLC_MASK | S3C2412_IISMOD_BCLK_MASK);
553b1dd5
MB		 362 /* Sample size */
363 switch (params_format(params)) {
364 case SNDRV_PCM_FORMAT_S8:
365 /* 8 bit sample, 16fs BCLK */
0914b93f 366 iismod |= (S3C64XX_IISMOD_BLC_8BIT | S3C2412_IISMOD_BCLK_16FS);
553b1dd5
MB		 367 break;
368 case SNDRV_PCM_FORMAT_S16_LE:
369 /* 16 bit sample, 32fs BCLK */
370 break;
371 case SNDRV_PCM_FORMAT_S24_LE:
372 /* 24 bit sample, 48fs BCLK */
0914b93f 373 iismod |= (S3C64XX_IISMOD_BLC_24BIT | S3C2412_IISMOD_BCLK_48FS);
553b1dd5
MB		 374 break;
375 }
376#endif
dc85447b
BD		 377
378 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 379 pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
dc85447b
BD		 380 return 0;
381}
382
383static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
384 struct snd_soc_dai *dai)
385{
386 struct snd_soc_pcm_runtime *rtd = substream->private_data;
387 struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai);
388 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
389 unsigned long irqs;
390 int ret = 0;
faf907c7
SL		 391 int channel = ((struct s3c24xx_pcm_dma_params *)
392 rtd->dai->cpu_dai->dma_data)->channel;
dc85447b 393
ee7d4767 394 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 395
396 switch (cmd) {
397 case SNDRV_PCM_TRIGGER_START:
398 /* On start, ensure that the FIFOs are cleared and reset. */
399
400 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
401 i2s->regs + S3C2412_IISFIC);
402
403 /* clear again, just in case */
404 writel(0x0, i2s->regs + S3C2412_IISFIC);
405
406 case SNDRV_PCM_TRIGGER_RESUME:
407 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
408 if (!i2s->master) {
409 ret = s3c2412_snd_lrsync(i2s);
410 if (ret)
411 goto exit_err;
412 }
413
414 local_irq_save(irqs);
415
416 if (capture)
417 s3c2412_snd_rxctrl(i2s, 1);
418 else
419 s3c2412_snd_txctrl(i2s, 1);
420
421 local_irq_restore(irqs);
faf907c7
SL		 422
423 /*
424 * Load the next buffer to DMA to meet the reqirement
425 * of the auto reload mechanism of S3C24XX.
426 * This call won't bother S3C64XX.
427 */
428 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);
429
dc85447b
BD		 430 break;
431
432 case SNDRV_PCM_TRIGGER_STOP:
433 case SNDRV_PCM_TRIGGER_SUSPEND:
434 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
435 local_irq_save(irqs);
436
437 if (capture)
438 s3c2412_snd_rxctrl(i2s, 0);
439 else
440 s3c2412_snd_txctrl(i2s, 0);
441
442 local_irq_restore(irqs);
443 break;
444 default:
445 ret = -EINVAL;
446 break;
447 }
448
449exit_err:
450 return ret;
451}
452
453/*
454 * Set S3C2412 Clock dividers
455 */
456static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
457 int div_id, int div)
458{
459 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
460 u32 reg;
461
ee7d4767 462 pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
dc85447b
BD		 463
464 switch (div_id) {
465 case S3C_I2SV2_DIV_BCLK:
466 reg = readl(i2s->regs + S3C2412_IISMOD);
467 reg &= ~S3C2412_IISMOD_BCLK_MASK;
468 writel(reg | div, i2s->regs + S3C2412_IISMOD);
469
ee7d4767 470 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 471 break;
472
473 case S3C_I2SV2_DIV_RCLK:
474 if (div > 3) {
475 /* convert value to bit field */
476
477 switch (div) {
478 case 256:
479 div = S3C2412_IISMOD_RCLK_256FS;
480 break;
481
482 case 384:
483 div = S3C2412_IISMOD_RCLK_384FS;
484 break;
485
486 case 512:
487 div = S3C2412_IISMOD_RCLK_512FS;
488 break;
489
490 case 768:
491 div = S3C2412_IISMOD_RCLK_768FS;
492 break;
493
494 default:
495 return -EINVAL;
496 }
497 }
498
499 reg = readl(i2s->regs + S3C2412_IISMOD);
500 reg &= ~S3C2412_IISMOD_RCLK_MASK;
501 writel(reg | div, i2s->regs + S3C2412_IISMOD);
ee7d4767 502 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 503 break;
504
505 case S3C_I2SV2_DIV_PRESCALER:
506 if (div >= 0) {
507 writel((div << 8) | S3C2412_IISPSR_PSREN,
508 i2s->regs + S3C2412_IISPSR);
509 } else {
510 writel(0x0, i2s->regs + S3C2412_IISPSR);
511 }
ee7d4767 512 pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
dc85447b
BD		 513 break;
514
515 default:
516 return -EINVAL;
517 }
518
519 return 0;
520}
521
522/* default table of all avaialable root fs divisors */
523static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
524
1d2b7ae9
BD		 525int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
526 unsigned int *fstab,
527 unsigned int rate, struct clk *clk)
dc85447b
BD		 528{
529 unsigned long clkrate = clk_get_rate(clk);
530 unsigned int div;
531 unsigned int fsclk;
532 unsigned int actual;
533 unsigned int fs;
534 unsigned int fsdiv;
535 signed int deviation = 0;
536 unsigned int best_fs = 0;
537 unsigned int best_div = 0;
538 unsigned int best_rate = 0;
539 unsigned int best_deviation = INT_MAX;
540
af3ea7bd
MB		 541 pr_debug("Input clock rate %ldHz\n", clkrate);
542
dc85447b
BD		 543 if (fstab == NULL)
544 fstab = iis_fs_tab;
545
546 for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
547 fsdiv = iis_fs_tab[fs];
548
549 fsclk = clkrate / fsdiv;
550 div = fsclk / rate;
551
552 if ((fsclk % rate) > (rate / 2))
553 div++;
554
555 if (div <= 1)
556 continue;
557
558 actual = clkrate / (fsdiv * div);
559 deviation = actual - rate;
560
449bd54d 561 printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
dc85447b
BD		 562 fsdiv, div, actual, deviation);
563
564 deviation = abs(deviation);
565
566 if (deviation < best_deviation) {
567 best_fs = fsdiv;
568 best_div = div;
569 best_rate = actual;
570 best_deviation = deviation;
571 }
572
573 if (deviation == 0)
574 break;
575 }
576
449bd54d 577 printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
dc85447b
BD		 578 best_fs, best_div, best_rate);
579
580 info->fs_div = best_fs;
581 info->clk_div = best_div;
582
583 return 0;
584}
1d2b7ae9 585EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
dc85447b
BD		 586
587int s3c_i2sv2_probe(struct platform_device *pdev,
588 struct snd_soc_dai *dai,
589 struct s3c_i2sv2_info *i2s,
590 unsigned long base)
591{
592 struct device *dev = &pdev->dev;
07736d48 593 unsigned int iismod;
dc85447b
BD		 594
595 i2s->dev = dev;
596
597 /* record our i2s structure for later use in the callbacks */
598 dai->private_data = i2s;
599
c86bde54
MB		 600 if (!base) {
601 struct resource *res = platform_get_resource(pdev,
602 IORESOURCE_MEM,
603 0);
604 if (!res) {
605 dev_err(dev, "Unable to get register resource\n");
606 return -ENXIO;
607 }
608
609 if (!request_mem_region(res->start, resource_size(res),
610 "s3c64xx-i2s-v4")) {
611 dev_err(dev, "Unable to request register region\n");
612 return -EBUSY;
613 }
614
615 base = res->start;
616 }
617
dc85447b
BD		 618 i2s->regs = ioremap(base, 0x100);
619 if (i2s->regs == NULL) {
620 dev_err(dev, "cannot ioremap registers\n");
621 return -ENXIO;
622 }
623
624 i2s->iis_pclk = clk_get(dev, "iis");
625 if (i2s->iis_pclk == NULL) {
b52a5195 626 dev_err(dev, "failed to get iis_clock\n");
dc85447b
BD		 627 iounmap(i2s->regs);
628 return -ENOENT;
629 }
630
631 clk_enable(i2s->iis_pclk);
632
07736d48
MB		 633 /* Mark ourselves as in TXRX mode so we can run through our cleanup
634 * process without warnings. */
635 iismod = readl(i2s->regs + S3C2412_IISMOD);
636 iismod |= S3C2412_IISMOD_MODE_TXRX;
637 writel(iismod, i2s->regs + S3C2412_IISMOD);
dc85447b
BD		 638 s3c2412_snd_txctrl(i2s, 0);
639 s3c2412_snd_rxctrl(i2s, 0);
640
641 return 0;
642}
dc85447b
BD		 643EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
644
645#ifdef CONFIG_PM
646static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
647{
648 struct s3c_i2sv2_info *i2s = to_info(dai);
649 u32 iismod;
650
651 if (dai->active) {
652 i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
653 i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
654 i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
655
656 /* some basic suspend checks */
657
658 iismod = readl(i2s->regs + S3C2412_IISMOD);
659
660 if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
661 pr_warning("%s: RXDMA active?\n", __func__);
662
663 if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
664 pr_warning("%s: TXDMA active?\n", __func__);
665
666 if (iismod & S3C2412_IISCON_IIS_ACTIVE)
667 pr_warning("%s: IIS active\n", __func__);
668 }
669
670 return 0;
671}
672
673static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
674{
675 struct s3c_i2sv2_info *i2s = to_info(dai);
676
677 pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
678 dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
679
680 if (dai->active) {
681 writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
682 writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
683 writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
684
685 writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
686 i2s->regs + S3C2412_IISFIC);
687
688 ndelay(250);
689 writel(0x0, i2s->regs + S3C2412_IISFIC);
690 }
691
692 return 0;
693}
694#else
695#define s3c2412_i2s_suspend NULL
696#define s3c2412_i2s_resume NULL
697#endif
698
699int s3c_i2sv2_register_dai(struct snd_soc_dai *dai)
700{
3715c6aa
BD		 701 struct snd_soc_dai_ops *ops = dai->ops;
702
703 ops->trigger = s3c2412_i2s_trigger;
704 ops->hw_params = s3c2412_i2s_hw_params;
705 ops->set_fmt = s3c2412_i2s_set_fmt;
706 ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
dc85447b
BD		 707
708 dai->suspend = s3c2412_i2s_suspend;
709 dai->resume = s3c2412_i2s_resume;
710
711 return snd_soc_register_dai(dai);
712}
dc85447b 713EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai);
a396e32e
MB		 714
715MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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