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ASoC: Make S3C64xx clock export function to return struct clk
[deliverable/linux.git] / sound / soc / s3c24xx / s3c-i2s-v2.c
CommitLineData
dc85447b
BD		 1/* sound/soc/s3c24xx/s3c-i2c-v2.c
2 *
3 * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
4 *
5 * Copyright (c) 2006 Wolfson Microelectronics PLC.
6 * Graeme Gregory graeme.gregory@wolfsonmicro.com
7 * linux@wolfsonmicro.com
8 *
9 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 * Ben Dooks <ben@simtec.co.uk>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/device.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/kernel.h>
25#include <linux/io.h>
26
27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/initval.h>
31#include <sound/soc.h>
32
33#include <plat/regs-s3c2412-iis.h>
34
35#include <plat/audio.h>
36#include <mach/dma.h>
37
38#include "s3c-i2s-v2.h"
39
8a0f62b8
MB		 40#undef S3C_IIS_V2_SUPPORTED
41
42#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
43#define S3C_IIS_V2_SUPPORTED
44#endif
45
46#ifdef CONFIG_PLAT_S3C64XX
47#define S3C_IIS_V2_SUPPORTED
48#endif
49
50#ifndef S3C_IIS_V2_SUPPORTED
51#error Unsupported CPU model
52#endif
53
dc85447b 54#define S3C2412_I2S_DEBUG_CON 0
dc85447b
BD		 55
56static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
57{
58 return cpu_dai->private_data;
59}
60
61#define bit_set(v, b) (((v) & (b)) ? 1 : 0)
62
63#if S3C2412_I2S_DEBUG_CON
64static void dbg_showcon(const char *fn, u32 con)
65{
66 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
67 bit_set(con, S3C2412_IISCON_LRINDEX),
68 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
69 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
70 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
71 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
72
73 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
74 fn,
75 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
76 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
77 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
78 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
79 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
80 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
81 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
82 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
83}
84#else
85static inline void dbg_showcon(const char *fn, u32 con)
86{
87}
88#endif
89
90
91/* Turn on or off the transmission path. */
92void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
93{
94 void __iomem *regs = i2s->regs;
95 u32 fic, con, mod;
96
ee7d4767 97 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 98
99 fic = readl(regs + S3C2412_IISFIC);
100 con = readl(regs + S3C2412_IISCON);
101 mod = readl(regs + S3C2412_IISMOD);
102
ee7d4767 103 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 104
105 if (on) {
106 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
107 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
108 con &= ~S3C2412_IISCON_TXCH_PAUSE;
109
110 switch (mod & S3C2412_IISMOD_MODE_MASK) {
111 case S3C2412_IISMOD_MODE_TXONLY:
112 case S3C2412_IISMOD_MODE_TXRX:
113 /* do nothing, we are in the right mode */
114 break;
115
116 case S3C2412_IISMOD_MODE_RXONLY:
117 mod &= ~S3C2412_IISMOD_MODE_MASK;
118 mod |= S3C2412_IISMOD_MODE_TXRX;
119 break;
120
121 default:
a7be4d92 122 dev_err(i2s->dev, "TXEN: Invalid MODE in IISMOD\n");
dc85447b
BD		 123 }
124
125 writel(con, regs + S3C2412_IISCON);
126 writel(mod, regs + S3C2412_IISMOD);
127 } else {
128 /* Note, we do not have any indication that the FIFO problems
129 * tha the S3C2410/2440 had apply here, so we should be able
130 * to disable the DMA and TX without resetting the FIFOS.
131 */
132
133 con |= S3C2412_IISCON_TXDMA_PAUSE;
134 con |= S3C2412_IISCON_TXCH_PAUSE;
135 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
136
137 switch (mod & S3C2412_IISMOD_MODE_MASK) {
138 case S3C2412_IISMOD_MODE_TXRX:
139 mod &= ~S3C2412_IISMOD_MODE_MASK;
140 mod |= S3C2412_IISMOD_MODE_RXONLY;
141 break;
142
143 case S3C2412_IISMOD_MODE_TXONLY:
144 mod &= ~S3C2412_IISMOD_MODE_MASK;
145 con &= ~S3C2412_IISCON_IIS_ACTIVE;
146 break;
147
148 default:
a7be4d92 149 dev_err(i2s->dev, "TXDIS: Invalid MODE in IISMOD\n");
dc85447b
BD		 150 }
151
152 writel(mod, regs + S3C2412_IISMOD);
153 writel(con, regs + S3C2412_IISCON);
154 }
155
156 fic = readl(regs + S3C2412_IISFIC);
157 dbg_showcon(__func__, con);
ee7d4767 158 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 159}
160EXPORT_SYMBOL_GPL(s3c2412_snd_txctrl);
161
162void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
163{
164 void __iomem *regs = i2s->regs;
165 u32 fic, con, mod;
166
ee7d4767 167 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 168
169 fic = readl(regs + S3C2412_IISFIC);
170 con = readl(regs + S3C2412_IISCON);
171 mod = readl(regs + S3C2412_IISMOD);
172
ee7d4767 173 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 174
175 if (on) {
176 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
177 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
178 con &= ~S3C2412_IISCON_RXCH_PAUSE;
179
180 switch (mod & S3C2412_IISMOD_MODE_MASK) {
181 case S3C2412_IISMOD_MODE_TXRX:
182 case S3C2412_IISMOD_MODE_RXONLY:
183 /* do nothing, we are in the right mode */
184 break;
185
186 case S3C2412_IISMOD_MODE_TXONLY:
187 mod &= ~S3C2412_IISMOD_MODE_MASK;
188 mod |= S3C2412_IISMOD_MODE_TXRX;
189 break;
190
191 default:
a7be4d92 192 dev_err(i2s->dev, "RXEN: Invalid MODE in IISMOD\n");
dc85447b
BD		 193 }
194
195 writel(mod, regs + S3C2412_IISMOD);
196 writel(con, regs + S3C2412_IISCON);
197 } else {
198 /* See txctrl notes on FIFOs. */
199
200 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
201 con |= S3C2412_IISCON_RXDMA_PAUSE;
202 con |= S3C2412_IISCON_RXCH_PAUSE;
203
204 switch (mod & S3C2412_IISMOD_MODE_MASK) {
205 case S3C2412_IISMOD_MODE_RXONLY:
206 con &= ~S3C2412_IISCON_IIS_ACTIVE;
207 mod &= ~S3C2412_IISMOD_MODE_MASK;
208 break;
209
210 case S3C2412_IISMOD_MODE_TXRX:
211 mod &= ~S3C2412_IISMOD_MODE_MASK;
212 mod |= S3C2412_IISMOD_MODE_TXONLY;
213 break;
214
215 default:
a7be4d92 216 dev_err(i2s->dev, "RXEN: Invalid MODE in IISMOD\n");
dc85447b
BD		 217 }
218
219 writel(con, regs + S3C2412_IISCON);
220 writel(mod, regs + S3C2412_IISMOD);
221 }
222
223 fic = readl(regs + S3C2412_IISFIC);
ee7d4767 224 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 225}
226EXPORT_SYMBOL_GPL(s3c2412_snd_rxctrl);
227
228/*
229 * Wait for the LR signal to allow synchronisation to the L/R clock
230 * from the codec. May only be needed for slave mode.
231 */
232static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
233{
234 u32 iiscon;
235 unsigned long timeout = jiffies + msecs_to_jiffies(5);
236
ee7d4767 237 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 238
239 while (1) {
240 iiscon = readl(i2s->regs + S3C2412_IISCON);
241 if (iiscon & S3C2412_IISCON_LRINDEX)
242 break;
243
244 if (timeout < jiffies) {
245 printk(KERN_ERR "%s: timeout\n", __func__);
246 return -ETIMEDOUT;
247 }
248 }
249
250 return 0;
251}
252
253/*
254 * Set S3C2412 I2S DAI format
255 */
256static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
257 unsigned int fmt)
258{
259 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
260 u32 iismod;
261
ee7d4767 262 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 263
264 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 265 pr_debug("hw_params r: IISMOD: %x \n", iismod);
dc85447b
BD		 266
267#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
268#define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
269#define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
270#define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
271#endif
272
273#if defined(CONFIG_PLAT_S3C64XX)
274/* From Rev1.1 datasheet, we have two master and two slave modes:
275 * IMS[11:10]:
276 * 00 = master mode, fed from PCLK
277 * 01 = master mode, fed from CLKAUDIO
278 * 10 = slave mode, using PCLK
279 * 11 = slave mode, using I2SCLK
280 */
281#define IISMOD_MASTER_MASK (1 << 11)
282#define IISMOD_SLAVE (1 << 11)
283#define IISMOD_MASTER (0x0)
284#endif
285
286 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
287 case SND_SOC_DAIFMT_CBM_CFM:
288 i2s->master = 0;
289 iismod &= ~IISMOD_MASTER_MASK;
290 iismod |= IISMOD_SLAVE;
291 break;
292 case SND_SOC_DAIFMT_CBS_CFS:
293 i2s->master = 1;
294 iismod &= ~IISMOD_MASTER_MASK;
295 iismod |= IISMOD_MASTER;
296 break;
297 default:
a7be4d92 298 pr_debug("unknwon master/slave format\n");
dc85447b
BD		 299 return -EINVAL;
300 }
301
302 iismod &= ~S3C2412_IISMOD_SDF_MASK;
303
304 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
305 case SND_SOC_DAIFMT_RIGHT_J:
306 iismod |= S3C2412_IISMOD_SDF_MSB;
307 break;
308 case SND_SOC_DAIFMT_LEFT_J:
309 iismod |= S3C2412_IISMOD_SDF_LSB;
310 break;
311 case SND_SOC_DAIFMT_I2S:
312 iismod |= S3C2412_IISMOD_SDF_IIS;
313 break;
314 default:
a7be4d92 315 pr_debug("Unknown data format\n");
dc85447b
BD		 316 return -EINVAL;
317 }
318
319 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 320 pr_debug("hw_params w: IISMOD: %x \n", iismod);
dc85447b
BD		 321 return 0;
322}
323
324static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
325 struct snd_pcm_hw_params *params,
326 struct snd_soc_dai *socdai)
327{
328 struct snd_soc_pcm_runtime *rtd = substream->private_data;
329 struct snd_soc_dai_link *dai = rtd->dai;
330 struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai);
331 u32 iismod;
332
ee7d4767 333 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 334
335 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
336 dai->cpu_dai->dma_data = i2s->dma_playback;
337 else
338 dai->cpu_dai->dma_data = i2s->dma_capture;
339
340 /* Working copies of register */
341 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 342 pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
dc85447b
BD		 343
344 switch (params_format(params)) {
345 case SNDRV_PCM_FORMAT_S8:
346 iismod |= S3C2412_IISMOD_8BIT;
347 break;
348 case SNDRV_PCM_FORMAT_S16_LE:
349 iismod &= ~S3C2412_IISMOD_8BIT;
350 break;
351 }
352
353 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 354 pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
dc85447b
BD		 355 return 0;
356}
357
358static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
359 struct snd_soc_dai *dai)
360{
361 struct snd_soc_pcm_runtime *rtd = substream->private_data;
362 struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai);
363 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
364 unsigned long irqs;
365 int ret = 0;
366
ee7d4767 367 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 368
369 switch (cmd) {
370 case SNDRV_PCM_TRIGGER_START:
371 /* On start, ensure that the FIFOs are cleared and reset. */
372
373 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
374 i2s->regs + S3C2412_IISFIC);
375
376 /* clear again, just in case */
377 writel(0x0, i2s->regs + S3C2412_IISFIC);
378
379 case SNDRV_PCM_TRIGGER_RESUME:
380 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
381 if (!i2s->master) {
382 ret = s3c2412_snd_lrsync(i2s);
383 if (ret)
384 goto exit_err;
385 }
386
387 local_irq_save(irqs);
388
389 if (capture)
390 s3c2412_snd_rxctrl(i2s, 1);
391 else
392 s3c2412_snd_txctrl(i2s, 1);
393
394 local_irq_restore(irqs);
395 break;
396
397 case SNDRV_PCM_TRIGGER_STOP:
398 case SNDRV_PCM_TRIGGER_SUSPEND:
399 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
400 local_irq_save(irqs);
401
402 if (capture)
403 s3c2412_snd_rxctrl(i2s, 0);
404 else
405 s3c2412_snd_txctrl(i2s, 0);
406
407 local_irq_restore(irqs);
408 break;
409 default:
410 ret = -EINVAL;
411 break;
412 }
413
414exit_err:
415 return ret;
416}
417
418/*
419 * Set S3C2412 Clock dividers
420 */
421static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
422 int div_id, int div)
423{
424 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
425 u32 reg;
426
ee7d4767 427 pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
dc85447b
BD		 428
429 switch (div_id) {
430 case S3C_I2SV2_DIV_BCLK:
431 reg = readl(i2s->regs + S3C2412_IISMOD);
432 reg &= ~S3C2412_IISMOD_BCLK_MASK;
433 writel(reg | div, i2s->regs + S3C2412_IISMOD);
434
ee7d4767 435 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 436 break;
437
438 case S3C_I2SV2_DIV_RCLK:
439 if (div > 3) {
440 /* convert value to bit field */
441
442 switch (div) {
443 case 256:
444 div = S3C2412_IISMOD_RCLK_256FS;
445 break;
446
447 case 384:
448 div = S3C2412_IISMOD_RCLK_384FS;
449 break;
450
451 case 512:
452 div = S3C2412_IISMOD_RCLK_512FS;
453 break;
454
455 case 768:
456 div = S3C2412_IISMOD_RCLK_768FS;
457 break;
458
459 default:
460 return -EINVAL;
461 }
462 }
463
464 reg = readl(i2s->regs + S3C2412_IISMOD);
465 reg &= ~S3C2412_IISMOD_RCLK_MASK;
466 writel(reg | div, i2s->regs + S3C2412_IISMOD);
ee7d4767 467 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 468 break;
469
470 case S3C_I2SV2_DIV_PRESCALER:
471 if (div >= 0) {
472 writel((div << 8) | S3C2412_IISPSR_PSREN,
473 i2s->regs + S3C2412_IISPSR);
474 } else {
475 writel(0x0, i2s->regs + S3C2412_IISPSR);
476 }
ee7d4767 477 pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
dc85447b
BD		 478 break;
479
480 default:
481 return -EINVAL;
482 }
483
484 return 0;
485}
486
487/* default table of all avaialable root fs divisors */
488static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
489
1d2b7ae9
BD		 490int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
491 unsigned int *fstab,
492 unsigned int rate, struct clk *clk)
dc85447b
BD		 493{
494 unsigned long clkrate = clk_get_rate(clk);
495 unsigned int div;
496 unsigned int fsclk;
497 unsigned int actual;
498 unsigned int fs;
499 unsigned int fsdiv;
500 signed int deviation = 0;
501 unsigned int best_fs = 0;
502 unsigned int best_div = 0;
503 unsigned int best_rate = 0;
504 unsigned int best_deviation = INT_MAX;
505
506 if (fstab == NULL)
507 fstab = iis_fs_tab;
508
509 for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
510 fsdiv = iis_fs_tab[fs];
511
512 fsclk = clkrate / fsdiv;
513 div = fsclk / rate;
514
515 if ((fsclk % rate) > (rate / 2))
516 div++;
517
518 if (div <= 1)
519 continue;
520
521 actual = clkrate / (fsdiv * div);
522 deviation = actual - rate;
523
524 printk(KERN_DEBUG "%dfs: div %d => result %d, deviation %d\n",
525 fsdiv, div, actual, deviation);
526
527 deviation = abs(deviation);
528
529 if (deviation < best_deviation) {
530 best_fs = fsdiv;
531 best_div = div;
532 best_rate = actual;
533 best_deviation = deviation;
534 }
535
536 if (deviation == 0)
537 break;
538 }
539
540 printk(KERN_DEBUG "best: fs=%d, div=%d, rate=%d\n",
541 best_fs, best_div, best_rate);
542
543 info->fs_div = best_fs;
544 info->clk_div = best_div;
545
546 return 0;
547}
1d2b7ae9 548EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
dc85447b
BD		 549
550int s3c_i2sv2_probe(struct platform_device *pdev,
551 struct snd_soc_dai *dai,
552 struct s3c_i2sv2_info *i2s,
553 unsigned long base)
554{
555 struct device *dev = &pdev->dev;
556
557 i2s->dev = dev;
558
559 /* record our i2s structure for later use in the callbacks */
560 dai->private_data = i2s;
561
562 i2s->regs = ioremap(base, 0x100);
563 if (i2s->regs == NULL) {
564 dev_err(dev, "cannot ioremap registers\n");
565 return -ENXIO;
566 }
567
568 i2s->iis_pclk = clk_get(dev, "iis");
569 if (i2s->iis_pclk == NULL) {
b52a5195 570 dev_err(dev, "failed to get iis_clock\n");
dc85447b
BD		 571 iounmap(i2s->regs);
572 return -ENOENT;
573 }
574
575 clk_enable(i2s->iis_pclk);
576
577 s3c2412_snd_txctrl(i2s, 0);
578 s3c2412_snd_rxctrl(i2s, 0);
579
580 return 0;
581}
582
583EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
584
585#ifdef CONFIG_PM
586static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
587{
588 struct s3c_i2sv2_info *i2s = to_info(dai);
589 u32 iismod;
590
591 if (dai->active) {
592 i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
593 i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
594 i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
595
596 /* some basic suspend checks */
597
598 iismod = readl(i2s->regs + S3C2412_IISMOD);
599
600 if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
601 pr_warning("%s: RXDMA active?\n", __func__);
602
603 if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
604 pr_warning("%s: TXDMA active?\n", __func__);
605
606 if (iismod & S3C2412_IISCON_IIS_ACTIVE)
607 pr_warning("%s: IIS active\n", __func__);
608 }
609
610 return 0;
611}
612
613static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
614{
615 struct s3c_i2sv2_info *i2s = to_info(dai);
616
617 pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
618 dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
619
620 if (dai->active) {
621 writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
622 writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
623 writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
624
625 writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
626 i2s->regs + S3C2412_IISFIC);
627
628 ndelay(250);
629 writel(0x0, i2s->regs + S3C2412_IISFIC);
630 }
631
632 return 0;
633}
634#else
635#define s3c2412_i2s_suspend NULL
636#define s3c2412_i2s_resume NULL
637#endif
638
639int s3c_i2sv2_register_dai(struct snd_soc_dai *dai)
640{
3715c6aa
BD		 641 struct snd_soc_dai_ops *ops = dai->ops;
642
643 ops->trigger = s3c2412_i2s_trigger;
644 ops->hw_params = s3c2412_i2s_hw_params;
645 ops->set_fmt = s3c2412_i2s_set_fmt;
646 ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
dc85447b
BD		 647
648 dai->suspend = s3c2412_i2s_suspend;
649 dai->resume = s3c2412_i2s_resume;
650
651 return snd_soc_register_dai(dai);
652}
dc85447b 653EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai);
a396e32e
MB		 654
655MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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