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ALSA: ASoC: move dma_data from snd_soc_dai to snd_soc_pcm_stream
[deliverable/linux.git] / sound / soc / s3c24xx / s3c-i2s-v2.c
CommitLineData
dc85447b
BD		 1/* sound/soc/s3c24xx/s3c-i2c-v2.c
2 *
3 * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
4 *
5 * Copyright (c) 2006 Wolfson Microelectronics PLC.
6 * Graeme Gregory graeme.gregory@wolfsonmicro.com
7 * linux@wolfsonmicro.com
8 *
9 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 * Ben Dooks <ben@simtec.co.uk>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/device.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/kernel.h>
25#include <linux/io.h>
26
27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/initval.h>
31#include <sound/soc.h>
32
33#include <plat/regs-s3c2412-iis.h>
34
dc85447b
BD		 35#include <mach/dma.h>
36
37#include "s3c-i2s-v2.h"
d3ff5a3e 38#include "s3c-dma.h"
dc85447b 39
8a0f62b8
MB		 40#undef S3C_IIS_V2_SUPPORTED
41
42#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
43#define S3C_IIS_V2_SUPPORTED
44#endif
45
46#ifdef CONFIG_PLAT_S3C64XX
47#define S3C_IIS_V2_SUPPORTED
48#endif
49
50#ifndef S3C_IIS_V2_SUPPORTED
51#error Unsupported CPU model
52#endif
53
dc85447b 54#define S3C2412_I2S_DEBUG_CON 0
dc85447b
BD		 55
56static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
57{
58 return cpu_dai->private_data;
59}
60
61#define bit_set(v, b) (((v) & (b)) ? 1 : 0)
62
63#if S3C2412_I2S_DEBUG_CON
64static void dbg_showcon(const char *fn, u32 con)
65{
66 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
67 bit_set(con, S3C2412_IISCON_LRINDEX),
68 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
69 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
70 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
71 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
72
73 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
74 fn,
75 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
76 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
77 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
78 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
79 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
80 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
81 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
82 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
83}
84#else
85static inline void dbg_showcon(const char *fn, u32 con)
86{
87}
88#endif
89
90
91/* Turn on or off the transmission path. */
abbc8246 92static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 93{
94 void __iomem *regs = i2s->regs;
95 u32 fic, con, mod;
96
ee7d4767 97 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 98
99 fic = readl(regs + S3C2412_IISFIC);
100 con = readl(regs + S3C2412_IISCON);
101 mod = readl(regs + S3C2412_IISMOD);
102
ee7d4767 103 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 104
105 if (on) {
106 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
107 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
108 con &= ~S3C2412_IISCON_TXCH_PAUSE;
109
110 switch (mod & S3C2412_IISMOD_MODE_MASK) {
111 case S3C2412_IISMOD_MODE_TXONLY:
112 case S3C2412_IISMOD_MODE_TXRX:
113 /* do nothing, we are in the right mode */
114 break;
115
116 case S3C2412_IISMOD_MODE_RXONLY:
117 mod &= ~S3C2412_IISMOD_MODE_MASK;
118 mod |= S3C2412_IISMOD_MODE_TXRX;
119 break;
120
121 default:
abbc8246
MB		 122 dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
123 mod & S3C2412_IISMOD_MODE_MASK);
124 break;
dc85447b
BD		 125 }
126
127 writel(con, regs + S3C2412_IISCON);
128 writel(mod, regs + S3C2412_IISMOD);
129 } else {
130 /* Note, we do not have any indication that the FIFO problems
131 * tha the S3C2410/2440 had apply here, so we should be able
132 * to disable the DMA and TX without resetting the FIFOS.
133 */
134
135 con |= S3C2412_IISCON_TXDMA_PAUSE;
136 con |= S3C2412_IISCON_TXCH_PAUSE;
137 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
138
139 switch (mod & S3C2412_IISMOD_MODE_MASK) {
140 case S3C2412_IISMOD_MODE_TXRX:
141 mod &= ~S3C2412_IISMOD_MODE_MASK;
142 mod |= S3C2412_IISMOD_MODE_RXONLY;
143 break;
144
145 case S3C2412_IISMOD_MODE_TXONLY:
146 mod &= ~S3C2412_IISMOD_MODE_MASK;
147 con &= ~S3C2412_IISCON_IIS_ACTIVE;
148 break;
149
150 default:
abbc8246
MB		 151 dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
152 mod & S3C2412_IISMOD_MODE_MASK);
153 break;
dc85447b
BD		 154 }
155
156 writel(mod, regs + S3C2412_IISMOD);
157 writel(con, regs + S3C2412_IISCON);
158 }
159
160 fic = readl(regs + S3C2412_IISFIC);
161 dbg_showcon(__func__, con);
ee7d4767 162 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 163}
dc85447b 164
abbc8246 165static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 166{
167 void __iomem *regs = i2s->regs;
168 u32 fic, con, mod;
169
ee7d4767 170 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 171
172 fic = readl(regs + S3C2412_IISFIC);
173 con = readl(regs + S3C2412_IISCON);
174 mod = readl(regs + S3C2412_IISMOD);
175
ee7d4767 176 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 177
178 if (on) {
179 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
180 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
181 con &= ~S3C2412_IISCON_RXCH_PAUSE;
182
183 switch (mod & S3C2412_IISMOD_MODE_MASK) {
184 case S3C2412_IISMOD_MODE_TXRX:
185 case S3C2412_IISMOD_MODE_RXONLY:
186 /* do nothing, we are in the right mode */
187 break;
188
189 case S3C2412_IISMOD_MODE_TXONLY:
190 mod &= ~S3C2412_IISMOD_MODE_MASK;
191 mod |= S3C2412_IISMOD_MODE_TXRX;
192 break;
193
194 default:
abbc8246
MB		 195 dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
196 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 197 }
198
199 writel(mod, regs + S3C2412_IISMOD);
200 writel(con, regs + S3C2412_IISCON);
201 } else {
202 /* See txctrl notes on FIFOs. */
203
204 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
205 con |= S3C2412_IISCON_RXDMA_PAUSE;
206 con |= S3C2412_IISCON_RXCH_PAUSE;
207
208 switch (mod & S3C2412_IISMOD_MODE_MASK) {
209 case S3C2412_IISMOD_MODE_RXONLY:
210 con &= ~S3C2412_IISCON_IIS_ACTIVE;
211 mod &= ~S3C2412_IISMOD_MODE_MASK;
212 break;
213
214 case S3C2412_IISMOD_MODE_TXRX:
215 mod &= ~S3C2412_IISMOD_MODE_MASK;
216 mod |= S3C2412_IISMOD_MODE_TXONLY;
217 break;
218
219 default:
abbc8246
MB		 220 dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
221 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 222 }
223
224 writel(con, regs + S3C2412_IISCON);
225 writel(mod, regs + S3C2412_IISMOD);
226 }
227
228 fic = readl(regs + S3C2412_IISFIC);
ee7d4767 229 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 230}
dc85447b 231
fa68e002
J		 232#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
233
dc85447b
BD		 234/*
235 * Wait for the LR signal to allow synchronisation to the L/R clock
236 * from the codec. May only be needed for slave mode.
237 */
238static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
239{
240 u32 iiscon;
fa68e002 241 unsigned long loops = msecs_to_loops(5);
dc85447b 242
ee7d4767 243 pr_debug("Entered %s\n", __func__);
dc85447b 244
fa68e002 245 while (--loops) {
dc85447b
BD		 246 iiscon = readl(i2s->regs + S3C2412_IISCON);
247 if (iiscon & S3C2412_IISCON_LRINDEX)
248 break;
249
fa68e002
J		 250 cpu_relax();
251 }
252
253 if (!loops) {
254 printk(KERN_ERR "%s: timeout\n", __func__);
255 return -ETIMEDOUT;
dc85447b
BD		 256 }
257
258 return 0;
259}
260
261/*
262 * Set S3C2412 I2S DAI format
263 */
264static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
265 unsigned int fmt)
266{
267 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
268 u32 iismod;
269
ee7d4767 270 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 271
272 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 273 pr_debug("hw_params r: IISMOD: %x \n", iismod);
dc85447b
BD		 274
275#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
276#define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
277#define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
278#define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
279#endif
280
281#if defined(CONFIG_PLAT_S3C64XX)
282/* From Rev1.1 datasheet, we have two master and two slave modes:
283 * IMS[11:10]:
284 * 00 = master mode, fed from PCLK
285 * 01 = master mode, fed from CLKAUDIO
286 * 10 = slave mode, using PCLK
287 * 11 = slave mode, using I2SCLK
288 */
289#define IISMOD_MASTER_MASK (1 << 11)
290#define IISMOD_SLAVE (1 << 11)
553b1dd5 291#define IISMOD_MASTER (0 << 11)
dc85447b
BD		 292#endif
293
294 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
295 case SND_SOC_DAIFMT_CBM_CFM:
296 i2s->master = 0;
297 iismod &= ~IISMOD_MASTER_MASK;
298 iismod |= IISMOD_SLAVE;
299 break;
300 case SND_SOC_DAIFMT_CBS_CFS:
301 i2s->master = 1;
302 iismod &= ~IISMOD_MASTER_MASK;
303 iismod |= IISMOD_MASTER;
304 break;
305 default:
38e43c81 306 pr_err("unknwon master/slave format\n");
dc85447b
BD		 307 return -EINVAL;
308 }
309
310 iismod &= ~S3C2412_IISMOD_SDF_MASK;
311
312 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
313 case SND_SOC_DAIFMT_RIGHT_J:
fd5ad654 314 iismod |= S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 315 iismod |= S3C2412_IISMOD_SDF_MSB;
316 break;
317 case SND_SOC_DAIFMT_LEFT_J:
fd5ad654 318 iismod |= S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 319 iismod |= S3C2412_IISMOD_SDF_LSB;
320 break;
321 case SND_SOC_DAIFMT_I2S:
fd5ad654 322 iismod &= ~S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 323 iismod |= S3C2412_IISMOD_SDF_IIS;
324 break;
325 default:
38e43c81 326 pr_err("Unknown data format\n");
dc85447b
BD		 327 return -EINVAL;
328 }
329
330 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 331 pr_debug("hw_params w: IISMOD: %x \n", iismod);
dc85447b
BD		 332 return 0;
333}
334
335static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
336 struct snd_pcm_hw_params *params,
337 struct snd_soc_dai *socdai)
338{
339 struct snd_soc_pcm_runtime *rtd = substream->private_data;
340 struct snd_soc_dai_link *dai = rtd->dai;
341 struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai);
5f712b2b 342 struct s3c_dma_params *dma_data;
dc85447b
BD		 343 u32 iismod;
344
ee7d4767 345 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 346
347 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5f712b2b 348 dma_data = i2s->dma_playback;
dc85447b 349 else
5f712b2b
DM		 350 dma_data = i2s->dma_capture;
351
352 snd_soc_dai_set_dma_data(dai->cpu_dai, substream, dma_data);
dc85447b
BD		 353
354 /* Working copies of register */
355 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 356 pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
dc85447b 357
553b1dd5 358#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
dc85447b
BD		 359 switch (params_format(params)) {
360 case SNDRV_PCM_FORMAT_S8:
361 iismod |= S3C2412_IISMOD_8BIT;
362 break;
363 case SNDRV_PCM_FORMAT_S16_LE:
364 iismod &= ~S3C2412_IISMOD_8BIT;
365 break;
366 }
553b1dd5
MB		 367#endif
368
369#ifdef CONFIG_PLAT_S3C64XX
0914b93f 370 iismod &= ~(S3C64XX_IISMOD_BLC_MASK | S3C2412_IISMOD_BCLK_MASK);
553b1dd5
MB		 371 /* Sample size */
372 switch (params_format(params)) {
373 case SNDRV_PCM_FORMAT_S8:
374 /* 8 bit sample, 16fs BCLK */
0914b93f 375 iismod |= (S3C64XX_IISMOD_BLC_8BIT | S3C2412_IISMOD_BCLK_16FS);
553b1dd5
MB		 376 break;
377 case SNDRV_PCM_FORMAT_S16_LE:
378 /* 16 bit sample, 32fs BCLK */
379 break;
380 case SNDRV_PCM_FORMAT_S24_LE:
381 /* 24 bit sample, 48fs BCLK */
0914b93f 382 iismod |= (S3C64XX_IISMOD_BLC_24BIT | S3C2412_IISMOD_BCLK_48FS);
553b1dd5
MB		 383 break;
384 }
385#endif
dc85447b
BD		 386
387 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 388 pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
dc85447b
BD		 389 return 0;
390}
391
392static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
393 struct snd_soc_dai *dai)
394{
395 struct snd_soc_pcm_runtime *rtd = substream->private_data;
396 struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai);
397 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
398 unsigned long irqs;
399 int ret = 0;
5f712b2b
DM		 400 struct s3c_dma_params *dma_data =
401 snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream);
dc85447b 402
ee7d4767 403 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 404
405 switch (cmd) {
406 case SNDRV_PCM_TRIGGER_START:
407 /* On start, ensure that the FIFOs are cleared and reset. */
408
409 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
410 i2s->regs + S3C2412_IISFIC);
411
412 /* clear again, just in case */
413 writel(0x0, i2s->regs + S3C2412_IISFIC);
414
415 case SNDRV_PCM_TRIGGER_RESUME:
416 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
417 if (!i2s->master) {
418 ret = s3c2412_snd_lrsync(i2s);
419 if (ret)
420 goto exit_err;
421 }
422
423 local_irq_save(irqs);
424
425 if (capture)
426 s3c2412_snd_rxctrl(i2s, 1);
427 else
428 s3c2412_snd_txctrl(i2s, 1);
429
430 local_irq_restore(irqs);
faf907c7
SL		 431
432 /*
433 * Load the next buffer to DMA to meet the reqirement
434 * of the auto reload mechanism of S3C24XX.
435 * This call won't bother S3C64XX.
436 */
5f712b2b 437 s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
faf907c7 438
dc85447b
BD		 439 break;
440
441 case SNDRV_PCM_TRIGGER_STOP:
442 case SNDRV_PCM_TRIGGER_SUSPEND:
443 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
444 local_irq_save(irqs);
445
446 if (capture)
447 s3c2412_snd_rxctrl(i2s, 0);
448 else
449 s3c2412_snd_txctrl(i2s, 0);
450
451 local_irq_restore(irqs);
452 break;
453 default:
454 ret = -EINVAL;
455 break;
456 }
457
458exit_err:
459 return ret;
460}
461
462/*
463 * Set S3C2412 Clock dividers
464 */
465static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
466 int div_id, int div)
467{
468 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
469 u32 reg;
470
ee7d4767 471 pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
dc85447b
BD		 472
473 switch (div_id) {
474 case S3C_I2SV2_DIV_BCLK:
fd5ad654
J		 475 if (div > 3) {
476 /* convert value to bit field */
477
478 switch (div) {
479 case 16:
480 div = S3C2412_IISMOD_BCLK_16FS;
481 break;
482
483 case 32:
484 div = S3C2412_IISMOD_BCLK_32FS;
485 break;
486
487 case 24:
488 div = S3C2412_IISMOD_BCLK_24FS;
489 break;
490
491 case 48:
492 div = S3C2412_IISMOD_BCLK_48FS;
493 break;
494
495 default:
496 return -EINVAL;
497 }
498 }
499
dc85447b
BD		 500 reg = readl(i2s->regs + S3C2412_IISMOD);
501 reg &= ~S3C2412_IISMOD_BCLK_MASK;
502 writel(reg | div, i2s->regs + S3C2412_IISMOD);
503
ee7d4767 504 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 505 break;
506
507 case S3C_I2SV2_DIV_RCLK:
508 if (div > 3) {
509 /* convert value to bit field */
510
511 switch (div) {
512 case 256:
513 div = S3C2412_IISMOD_RCLK_256FS;
514 break;
515
516 case 384:
517 div = S3C2412_IISMOD_RCLK_384FS;
518 break;
519
520 case 512:
521 div = S3C2412_IISMOD_RCLK_512FS;
522 break;
523
524 case 768:
525 div = S3C2412_IISMOD_RCLK_768FS;
526 break;
527
528 default:
529 return -EINVAL;
530 }
531 }
532
533 reg = readl(i2s->regs + S3C2412_IISMOD);
534 reg &= ~S3C2412_IISMOD_RCLK_MASK;
535 writel(reg | div, i2s->regs + S3C2412_IISMOD);
ee7d4767 536 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 537 break;
538
539 case S3C_I2SV2_DIV_PRESCALER:
540 if (div >= 0) {
541 writel((div << 8) | S3C2412_IISPSR_PSREN,
542 i2s->regs + S3C2412_IISPSR);
543 } else {
544 writel(0x0, i2s->regs + S3C2412_IISPSR);
545 }
ee7d4767 546 pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
dc85447b
BD		 547 break;
548
549 default:
550 return -EINVAL;
551 }
552
553 return 0;
554}
555
556/* default table of all avaialable root fs divisors */
557static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
558
1d2b7ae9
BD		 559int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
560 unsigned int *fstab,
561 unsigned int rate, struct clk *clk)
dc85447b
BD		 562{
563 unsigned long clkrate = clk_get_rate(clk);
564 unsigned int div;
565 unsigned int fsclk;
566 unsigned int actual;
567 unsigned int fs;
568 unsigned int fsdiv;
569 signed int deviation = 0;
570 unsigned int best_fs = 0;
571 unsigned int best_div = 0;
572 unsigned int best_rate = 0;
573 unsigned int best_deviation = INT_MAX;
574
af3ea7bd
MB		 575 pr_debug("Input clock rate %ldHz\n", clkrate);
576
dc85447b
BD		 577 if (fstab == NULL)
578 fstab = iis_fs_tab;
579
580 for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
581 fsdiv = iis_fs_tab[fs];
582
583 fsclk = clkrate / fsdiv;
584 div = fsclk / rate;
585
586 if ((fsclk % rate) > (rate / 2))
587 div++;
588
589 if (div <= 1)
590 continue;
591
592 actual = clkrate / (fsdiv * div);
593 deviation = actual - rate;
594
449bd54d 595 printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
dc85447b
BD		 596 fsdiv, div, actual, deviation);
597
598 deviation = abs(deviation);
599
600 if (deviation < best_deviation) {
601 best_fs = fsdiv;
602 best_div = div;
603 best_rate = actual;
604 best_deviation = deviation;
605 }
606
607 if (deviation == 0)
608 break;
609 }
610
449bd54d 611 printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
dc85447b
BD		 612 best_fs, best_div, best_rate);
613
614 info->fs_div = best_fs;
615 info->clk_div = best_div;
616
617 return 0;
618}
1d2b7ae9 619EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
dc85447b
BD		 620
621int s3c_i2sv2_probe(struct platform_device *pdev,
622 struct snd_soc_dai *dai,
623 struct s3c_i2sv2_info *i2s,
624 unsigned long base)
625{
626 struct device *dev = &pdev->dev;
07736d48 627 unsigned int iismod;
dc85447b
BD		 628
629 i2s->dev = dev;
630
631 /* record our i2s structure for later use in the callbacks */
632 dai->private_data = i2s;
633
c86bde54
MB		 634 if (!base) {
635 struct resource *res = platform_get_resource(pdev,
636 IORESOURCE_MEM,
637 0);
638 if (!res) {
639 dev_err(dev, "Unable to get register resource\n");
640 return -ENXIO;
641 }
642
643 if (!request_mem_region(res->start, resource_size(res),
644 "s3c64xx-i2s-v4")) {
645 dev_err(dev, "Unable to request register region\n");
646 return -EBUSY;
647 }
648
649 base = res->start;
650 }
651
dc85447b
BD		 652 i2s->regs = ioremap(base, 0x100);
653 if (i2s->regs == NULL) {
654 dev_err(dev, "cannot ioremap registers\n");
655 return -ENXIO;
656 }
657
658 i2s->iis_pclk = clk_get(dev, "iis");
fd5ad654 659 if (IS_ERR(i2s->iis_pclk)) {
b52a5195 660 dev_err(dev, "failed to get iis_clock\n");
dc85447b
BD		 661 iounmap(i2s->regs);
662 return -ENOENT;
663 }
664
665 clk_enable(i2s->iis_pclk);
666
07736d48
MB		 667 /* Mark ourselves as in TXRX mode so we can run through our cleanup
668 * process without warnings. */
669 iismod = readl(i2s->regs + S3C2412_IISMOD);
670 iismod |= S3C2412_IISMOD_MODE_TXRX;
671 writel(iismod, i2s->regs + S3C2412_IISMOD);
dc85447b
BD		 672 s3c2412_snd_txctrl(i2s, 0);
673 s3c2412_snd_rxctrl(i2s, 0);
674
675 return 0;
676}
dc85447b
BD		 677EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
678
679#ifdef CONFIG_PM
680static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
681{
682 struct s3c_i2sv2_info *i2s = to_info(dai);
683 u32 iismod;
684
685 if (dai->active) {
686 i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
687 i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
688 i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
689
690 /* some basic suspend checks */
691
692 iismod = readl(i2s->regs + S3C2412_IISMOD);
693
694 if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
695 pr_warning("%s: RXDMA active?\n", __func__);
696
697 if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
698 pr_warning("%s: TXDMA active?\n", __func__);
699
700 if (iismod & S3C2412_IISCON_IIS_ACTIVE)
701 pr_warning("%s: IIS active\n", __func__);
702 }
703
704 return 0;
705}
706
707static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
708{
709 struct s3c_i2sv2_info *i2s = to_info(dai);
710
711 pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
712 dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
713
714 if (dai->active) {
715 writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
716 writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
717 writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
718
719 writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
720 i2s->regs + S3C2412_IISFIC);
721
722 ndelay(250);
723 writel(0x0, i2s->regs + S3C2412_IISFIC);
724 }
725
726 return 0;
727}
728#else
729#define s3c2412_i2s_suspend NULL
730#define s3c2412_i2s_resume NULL
731#endif
732
733int s3c_i2sv2_register_dai(struct snd_soc_dai *dai)
734{
3715c6aa
BD		 735 struct snd_soc_dai_ops *ops = dai->ops;
736
737 ops->trigger = s3c2412_i2s_trigger;
738 ops->hw_params = s3c2412_i2s_hw_params;
739 ops->set_fmt = s3c2412_i2s_set_fmt;
740 ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
dc85447b
BD		 741
742 dai->suspend = s3c2412_i2s_suspend;
743 dai->resume = s3c2412_i2s_resume;
744
745 return snd_soc_register_dai(dai);
746}
dc85447b 747EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai);
a396e32e
MB		 748
749MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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