[deliverable/linux.git] / sound / soc / s3c24xx / s3c-i2s-v2.c

/* sound/soc/s3c24xx/s3c-i2c-v2.c
 *
 * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
 *
 * Copyright (c) 2006 Wolfson Microelectronics PLC.
 *	Graeme Gregory graeme.gregory@wolfsonmicro.com
 *	linux@wolfsonmicro.com
 *
 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/io.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include <plat/regs-s3c2412-iis.h>

#include <plat/audio.h>
#include <mach/dma.h>

#include "s3c-i2s-v2.h"

#undef S3C_IIS_V2_SUPPORTED

#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
#define S3C_IIS_V2_SUPPORTED
#endif

#ifdef CONFIG_PLAT_S3C64XX
#define S3C_IIS_V2_SUPPORTED
#endif

#ifndef S3C_IIS_V2_SUPPORTED
#error Unsupported CPU model
#endif

#define S3C2412_I2S_DEBUG_CON 0

static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
{
	return cpu_dai->private_data;
}

#define bit_set(v, b) (((v) & (b)) ? 1 : 0)

#if S3C2412_I2S_DEBUG_CON
static void dbg_showcon(const char *fn, u32 con)
{
	printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
	       bit_set(con, S3C2412_IISCON_LRINDEX),
	       bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
	       bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
	       bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
	       bit_set(con, S3C2412_IISCON_RXFIFO_FULL));

	printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
	       fn,
	       bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
	       bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
	       bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
	       bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
	printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
	       bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
	       bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
	       bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
}
#else
static inline void dbg_showcon(const char *fn, u32 con)
{
}
#endif


/* Turn on or off the transmission path. */
static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
{
	void __iomem *regs = i2s->regs;
	u32 fic, con, mod;

	pr_debug("%s(%d)\n", __func__, on);

	fic = readl(regs + S3C2412_IISFIC);
	con = readl(regs + S3C2412_IISCON);
	mod = readl(regs + S3C2412_IISMOD);

	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);

	if (on) {
		con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
		con &= ~S3C2412_IISCON_TXDMA_PAUSE;
		con &= ~S3C2412_IISCON_TXCH_PAUSE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_TXONLY:
		case S3C2412_IISMOD_MODE_TXRX:
			/* do nothing, we are in the right mode */
			break;

		case S3C2412_IISMOD_MODE_RXONLY:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_TXRX;
			break;

		default:
			dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
			break;
		}

		writel(con, regs + S3C2412_IISCON);
		writel(mod, regs + S3C2412_IISMOD);
	} else {
		/* Note, we do not have any indication that the FIFO problems
		 * tha the S3C2410/2440 had apply here, so we should be able
		 * to disable the DMA and TX without resetting the FIFOS.
		 */

		con |=  S3C2412_IISCON_TXDMA_PAUSE;
		con |=  S3C2412_IISCON_TXCH_PAUSE;
		con &= ~S3C2412_IISCON_TXDMA_ACTIVE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_TXRX:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_RXONLY;
			break;

		case S3C2412_IISMOD_MODE_TXONLY:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			con &= ~S3C2412_IISCON_IIS_ACTIVE;
			break;

		default:
			dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
			break;
		}

		writel(mod, regs + S3C2412_IISMOD);
		writel(con, regs + S3C2412_IISCON);
	}

	fic = readl(regs + S3C2412_IISFIC);
	dbg_showcon(__func__, con);
	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
}

static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
{
	void __iomem *regs = i2s->regs;
	u32 fic, con, mod;

	pr_debug("%s(%d)\n", __func__, on);

	fic = readl(regs + S3C2412_IISFIC);
	con = readl(regs + S3C2412_IISCON);
	mod = readl(regs + S3C2412_IISMOD);

	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);

	if (on) {
		con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
		con &= ~S3C2412_IISCON_RXDMA_PAUSE;
		con &= ~S3C2412_IISCON_RXCH_PAUSE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_TXRX:
		case S3C2412_IISMOD_MODE_RXONLY:
			/* do nothing, we are in the right mode */
			break;

		case S3C2412_IISMOD_MODE_TXONLY:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_TXRX;
			break;

		default:
			dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
		}

		writel(mod, regs + S3C2412_IISMOD);
		writel(con, regs + S3C2412_IISCON);
	} else {
		/* See txctrl notes on FIFOs. */

		con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
		con |=  S3C2412_IISCON_RXDMA_PAUSE;
		con |=  S3C2412_IISCON_RXCH_PAUSE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_RXONLY:
			con &= ~S3C2412_IISCON_IIS_ACTIVE;
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			break;

		case S3C2412_IISMOD_MODE_TXRX:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_TXONLY;
			break;

		default:
			dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
		}

		writel(con, regs + S3C2412_IISCON);
		writel(mod, regs + S3C2412_IISMOD);
	}

	fic = readl(regs + S3C2412_IISFIC);
	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
}

/*
 * Wait for the LR signal to allow synchronisation to the L/R clock
 * from the codec. May only be needed for slave mode.
 */
static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
{
	u32 iiscon;
	unsigned long timeout = jiffies + msecs_to_jiffies(5);

	pr_debug("Entered %s\n", __func__);

	while (1) {
		iiscon = readl(i2s->regs + S3C2412_IISCON);
		if (iiscon & S3C2412_IISCON_LRINDEX)
			break;

		if (timeout < jiffies) {
			printk(KERN_ERR "%s: timeout\n", __func__);
			return -ETIMEDOUT;
		}
	}

	return 0;
}

/*
 * Set S3C2412 I2S DAI format
 */
static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
			       unsigned int fmt)
{
	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iismod = readl(i2s->regs + S3C2412_IISMOD);
	pr_debug("hw_params r: IISMOD: %x \n", iismod);

#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
#define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
#define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
#define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
#endif

#if defined(CONFIG_PLAT_S3C64XX)
/* From Rev1.1 datasheet, we have two master and two slave modes:
 * IMS[11:10]:
 *	00 = master mode, fed from PCLK
 *	01 = master mode, fed from CLKAUDIO
 *	10 = slave mode, using PCLK
 *	11 = slave mode, using I2SCLK
 */
#define IISMOD_MASTER_MASK (1 << 11)
#define IISMOD_SLAVE (1 << 11)
#define IISMOD_MASTER (0 << 11)
#endif

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		i2s->master = 0;
		iismod &= ~IISMOD_MASTER_MASK;
		iismod |= IISMOD_SLAVE;
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
		i2s->master = 1;
		iismod &= ~IISMOD_MASTER_MASK;
		iismod |= IISMOD_MASTER;
		break;
	default:
		pr_err("unknwon master/slave format\n");
		return -EINVAL;
	}

	iismod &= ~S3C2412_IISMOD_SDF_MASK;

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		iismod |= S3C2412_IISMOD_SDF_MSB;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		iismod |= S3C2412_IISMOD_SDF_LSB;
		break;
	case SND_SOC_DAIFMT_I2S:
		iismod |= S3C2412_IISMOD_SDF_IIS;
		break;
	default:
		pr_err("Unknown data format\n");
		return -EINVAL;
	}

	writel(iismod, i2s->regs + S3C2412_IISMOD);
	pr_debug("hw_params w: IISMOD: %x \n", iismod);
	return 0;
}

static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *socdai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai_link *dai = rtd->dai;
	struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai);
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		dai->cpu_dai->dma_data = i2s->dma_playback;
	else
		dai->cpu_dai->dma_data = i2s->dma_capture;

	/* Working copies of register */
	iismod = readl(i2s->regs + S3C2412_IISMOD);
	pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);

#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		iismod |= S3C2412_IISMOD_8BIT;
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		iismod &= ~S3C2412_IISMOD_8BIT;
		break;
	}
#endif

#ifdef CONFIG_PLAT_S3C64XX
	iismod &= ~(S3C64XX_IISMOD_BLC_MASK | S3C2412_IISMOD_BCLK_MASK);
	/* Sample size */
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		/* 8 bit sample, 16fs BCLK */
		iismod |= (S3C64XX_IISMOD_BLC_8BIT | S3C2412_IISMOD_BCLK_16FS);
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		/* 16 bit sample, 32fs BCLK */
		break;
	case SNDRV_PCM_FORMAT_S24_LE:
		/* 24 bit sample, 48fs BCLK */
		iismod |= (S3C64XX_IISMOD_BLC_24BIT | S3C2412_IISMOD_BCLK_48FS);
		break;
	}
#endif

	writel(iismod, i2s->regs + S3C2412_IISMOD);
	pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
	return 0;
}

static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai);
	int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
	unsigned long irqs;
	int ret = 0;
	int channel = ((struct s3c24xx_pcm_dma_params *)
		  rtd->dai->cpu_dai->dma_data)->channel;

	pr_debug("Entered %s\n", __func__);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
		/* On start, ensure that the FIFOs are cleared and reset. */

		writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
		       i2s->regs + S3C2412_IISFIC);

		/* clear again, just in case */
		writel(0x0, i2s->regs + S3C2412_IISFIC);

	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (!i2s->master) {
			ret = s3c2412_snd_lrsync(i2s);
			if (ret)
				goto exit_err;
		}

		local_irq_save(irqs);

		if (capture)
			s3c2412_snd_rxctrl(i2s, 1);
		else
			s3c2412_snd_txctrl(i2s, 1);

		local_irq_restore(irqs);

		/*
		 * Load the next buffer to DMA to meet the reqirement
		 * of the auto reload mechanism of S3C24XX.
		 * This call won't bother S3C64XX.
		 */
		s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);

		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		local_irq_save(irqs);

		if (capture)
			s3c2412_snd_rxctrl(i2s, 0);
		else
			s3c2412_snd_txctrl(i2s, 0);

		local_irq_restore(irqs);
		break;
	default:
		ret = -EINVAL;
		break;
	}

exit_err:
	return ret;
}

/*
 * Set S3C2412 Clock dividers
 */
static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
				  int div_id, int div)
{
	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	u32 reg;

	pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);

	switch (div_id) {
	case S3C_I2SV2_DIV_BCLK:
		reg = readl(i2s->regs + S3C2412_IISMOD);
		reg &= ~S3C2412_IISMOD_BCLK_MASK;
		writel(reg | div, i2s->regs + S3C2412_IISMOD);

		pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
		break;

	case S3C_I2SV2_DIV_RCLK:
		if (div > 3) {
			/* convert value to bit field */

			switch (div) {
			case 256:
				div = S3C2412_IISMOD_RCLK_256FS;
				break;

			case 384:
				div = S3C2412_IISMOD_RCLK_384FS;
				break;

			case 512:
				div = S3C2412_IISMOD_RCLK_512FS;
				break;

			case 768:
				div = S3C2412_IISMOD_RCLK_768FS;
				break;

			default:
				return -EINVAL;
			}
		}

		reg = readl(i2s->regs + S3C2412_IISMOD);
		reg &= ~S3C2412_IISMOD_RCLK_MASK;
		writel(reg | div, i2s->regs + S3C2412_IISMOD);
		pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
		break;

	case S3C_I2SV2_DIV_PRESCALER:
		if (div >= 0) {
			writel((div << 8) | S3C2412_IISPSR_PSREN,
			       i2s->regs + S3C2412_IISPSR);
		} else {
			writel(0x0, i2s->regs + S3C2412_IISPSR);
		}
		pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

/* default table of all avaialable root fs divisors */
static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };

int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
			    unsigned int *fstab,
			    unsigned int rate, struct clk *clk)
{
	unsigned long clkrate = clk_get_rate(clk);
	unsigned int div;
	unsigned int fsclk;
	unsigned int actual;
	unsigned int fs;
	unsigned int fsdiv;
	signed int deviation = 0;
	unsigned int best_fs = 0;
	unsigned int best_div = 0;
	unsigned int best_rate = 0;
	unsigned int best_deviation = INT_MAX;

	pr_debug("Input clock rate %ldHz\n", clkrate);

	if (fstab == NULL)
		fstab = iis_fs_tab;

	for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
		fsdiv = iis_fs_tab[fs];

		fsclk = clkrate / fsdiv;
		div = fsclk / rate;

		if ((fsclk % rate) > (rate / 2))
			div++;

		if (div <= 1)
			continue;

		actual = clkrate / (fsdiv * div);
		deviation = actual - rate;

		printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
		       fsdiv, div, actual, deviation);

		deviation = abs(deviation);

		if (deviation < best_deviation) {
			best_fs = fsdiv;
			best_div = div;
			best_rate = actual;
			best_deviation = deviation;
		}

		if (deviation == 0)
			break;
	}

	printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
	       best_fs, best_div, best_rate);

	info->fs_div = best_fs;
	info->clk_div = best_div;

	return 0;
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);

int s3c_i2sv2_probe(struct platform_device *pdev,
		    struct snd_soc_dai *dai,
		    struct s3c_i2sv2_info *i2s,
		    unsigned long base)
{
	struct device *dev = &pdev->dev;
	unsigned int iismod;

	i2s->dev = dev;

	/* record our i2s structure for later use in the callbacks */
	dai->private_data = i2s;

	if (!base) {
		struct resource *res = platform_get_resource(pdev,
							     IORESOURCE_MEM,
							     0);
		if (!res) {
			dev_err(dev, "Unable to get register resource\n");
			return -ENXIO;
		}

		if (!request_mem_region(res->start, resource_size(res),
					"s3c64xx-i2s-v4")) {
			dev_err(dev, "Unable to request register region\n");
			return -EBUSY;
		}

		base = res->start;
	}

	i2s->regs = ioremap(base, 0x100);
	if (i2s->regs == NULL) {
		dev_err(dev, "cannot ioremap registers\n");
		return -ENXIO;
	}

	i2s->iis_pclk = clk_get(dev, "iis");
	if (i2s->iis_pclk == NULL) {
		dev_err(dev, "failed to get iis_clock\n");
		iounmap(i2s->regs);
		return -ENOENT;
	}

	clk_enable(i2s->iis_pclk);

	/* Mark ourselves as in TXRX mode so we can run through our cleanup
	 * process without warnings. */
	iismod = readl(i2s->regs + S3C2412_IISMOD);
	iismod |= S3C2412_IISMOD_MODE_TXRX;
	writel(iismod, i2s->regs + S3C2412_IISMOD);
	s3c2412_snd_txctrl(i2s, 0);
	s3c2412_snd_rxctrl(i2s, 0);

	return 0;
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);

#ifdef CONFIG_PM
static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
{
	struct s3c_i2sv2_info *i2s = to_info(dai);
	u32 iismod;

	if (dai->active) {
		i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
		i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
		i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);

		/* some basic suspend checks */

		iismod = readl(i2s->regs + S3C2412_IISMOD);

		if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
			pr_warning("%s: RXDMA active?\n", __func__);

		if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
			pr_warning("%s: TXDMA active?\n", __func__);

		if (iismod & S3C2412_IISCON_IIS_ACTIVE)
			pr_warning("%s: IIS active\n", __func__);
	}

	return 0;
}

static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
{
	struct s3c_i2sv2_info *i2s = to_info(dai);

	pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
		dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);

	if (dai->active) {
		writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
		writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
		writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);

		writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
		       i2s->regs + S3C2412_IISFIC);

		ndelay(250);
		writel(0x0, i2s->regs + S3C2412_IISFIC);
	}

	return 0;
}
#else
#define s3c2412_i2s_suspend NULL
#define s3c2412_i2s_resume  NULL
#endif

int s3c_i2sv2_register_dai(struct snd_soc_dai *dai)
{
	struct snd_soc_dai_ops *ops = dai->ops;

	ops->trigger = s3c2412_i2s_trigger;
	ops->hw_params = s3c2412_i2s_hw_params;
	ops->set_fmt = s3c2412_i2s_set_fmt;
	ops->set_clkdiv = s3c2412_i2s_set_clkdiv;

	dai->suspend = s3c2412_i2s_suspend;
	dai->resume = s3c2412_i2s_resume;

	return snd_soc_register_dai(dai);
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai);

MODULE_LICENSE("GPL");
Commit	Line	Data
dc85447b BD	1	/* sound/soc/s3c24xx/s3c-i2c-v2.c
	2	*
	3	* ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
	4	*
	5	* Copyright (c) 2006 Wolfson Microelectronics PLC.
	6	* Graeme Gregory graeme.gregory@wolfsonmicro.com
	7	* linux@wolfsonmicro.com
	8	*
	9	* Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
	10	* http://armlinux.simtec.co.uk/
	11	* Ben Dooks <ben@simtec.co.uk>
	12	*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms of the GNU General Public License as published by the
	15	* Free Software Foundation; either version 2 of the License, or (at your
	16	* option) any later version.
	17	*/
	18
	19	#include <linux/init.h>
	20	#include <linux/module.h>
	21	#include <linux/device.h>
	22	#include <linux/delay.h>
	23	#include <linux/clk.h>
	24	#include <linux/kernel.h>
	25	#include <linux/io.h>
	26
	27	#include <sound/core.h>
	28	#include <sound/pcm.h>
	29	#include <sound/pcm_params.h>
	30	#include <sound/initval.h>
	31	#include <sound/soc.h>
	32
	33	#include <plat/regs-s3c2412-iis.h>
	34
	35	#include <plat/audio.h>
	36	#include <mach/dma.h>
	37
	38	#include "s3c-i2s-v2.h"
	39
8a0f62b8 MB	40	#undef S3C_IIS_V2_SUPPORTED
	41
	42	#if defined(CONFIG_CPU_S3C2412) \|\| defined(CONFIG_CPU_S3C2413)
	43	#define S3C_IIS_V2_SUPPORTED
	44	#endif
	45
	46	#ifdef CONFIG_PLAT_S3C64XX
	47	#define S3C_IIS_V2_SUPPORTED
	48	#endif
	49
	50	#ifndef S3C_IIS_V2_SUPPORTED
	51	#error Unsupported CPU model
	52	#endif
	53
dc85447b	54	#define S3C2412_I2S_DEBUG_CON 0
dc85447b BD	55
	56	static inline struct s3c_i2sv2_info to_info(struct snd_soc_dai cpu_dai)
	57	{
	58	return cpu_dai->private_data;
	59	}
	60
	61	#define bit_set(v, b) (((v) & (b)) ? 1 : 0)
	62
	63	#if S3C2412_I2S_DEBUG_CON
	64	static void dbg_showcon(const char *fn, u32 con)
	65	{
	66	printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
	67	bit_set(con, S3C2412_IISCON_LRINDEX),
	68	bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
	69	bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
	70	bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
	71	bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
	72
	73	printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
	74	fn,
	75	bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
	76	bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
	77	bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
	78	bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
	79	printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
	80	bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
	81	bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
	82	bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
	83	}
	84	#else
	85	static inline void dbg_showcon(const char *fn, u32 con)
	86	{
	87	}
	88	#endif
	89
	90
	91	/* Turn on or off the transmission path. */
abbc8246	92	static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b BD	93	{
	94	void __iomem *regs = i2s->regs;
	95	u32 fic, con, mod;
	96
ee7d4767	97	pr_debug("%s(%d)\n", __func__, on);
dc85447b BD	98
	99	fic = readl(regs + S3C2412_IISFIC);
	100	con = readl(regs + S3C2412_IISCON);
	101	mod = readl(regs + S3C2412_IISMOD);
	102
ee7d4767	103	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b BD	104
	105	if (on) {
	106	con \|= S3C2412_IISCON_TXDMA_ACTIVE \| S3C2412_IISCON_IIS_ACTIVE;
	107	con &= ~S3C2412_IISCON_TXDMA_PAUSE;
	108	con &= ~S3C2412_IISCON_TXCH_PAUSE;
	109
	110	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	111	case S3C2412_IISMOD_MODE_TXONLY:
	112	case S3C2412_IISMOD_MODE_TXRX:
	113	/* do nothing, we are in the right mode */
	114	break;
	115
	116	case S3C2412_IISMOD_MODE_RXONLY:
	117	mod &= ~S3C2412_IISMOD_MODE_MASK;
	118	mod \|= S3C2412_IISMOD_MODE_TXRX;
	119	break;
	120
	121	default:
abbc8246 MB	122	dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
	123	mod & S3C2412_IISMOD_MODE_MASK);
	124	break;
dc85447b BD	125	}
	126
	127	writel(con, regs + S3C2412_IISCON);
	128	writel(mod, regs + S3C2412_IISMOD);
	129	} else {
	130	/* Note, we do not have any indication that the FIFO problems
	131	* tha the S3C2410/2440 had apply here, so we should be able
	132	* to disable the DMA and TX without resetting the FIFOS.
	133	*/
	134
	135	con \|= S3C2412_IISCON_TXDMA_PAUSE;
	136	con \|= S3C2412_IISCON_TXCH_PAUSE;
	137	con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
	138
	139	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	140	case S3C2412_IISMOD_MODE_TXRX:
	141	mod &= ~S3C2412_IISMOD_MODE_MASK;
	142	mod \|= S3C2412_IISMOD_MODE_RXONLY;
	143	break;
	144
	145	case S3C2412_IISMOD_MODE_TXONLY:
	146	mod &= ~S3C2412_IISMOD_MODE_MASK;
	147	con &= ~S3C2412_IISCON_IIS_ACTIVE;
	148	break;
	149
	150	default:
abbc8246 MB	151	dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
	152	mod & S3C2412_IISMOD_MODE_MASK);
	153	break;
dc85447b BD	154	}
	155
	156	writel(mod, regs + S3C2412_IISMOD);
	157	writel(con, regs + S3C2412_IISCON);
	158	}
	159
	160	fic = readl(regs + S3C2412_IISFIC);
	161	dbg_showcon(__func__, con);
ee7d4767	162	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b	163	}
dc85447b	164
abbc8246	165	static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b BD	166	{
	167	void __iomem *regs = i2s->regs;
	168	u32 fic, con, mod;
	169
ee7d4767	170	pr_debug("%s(%d)\n", __func__, on);
dc85447b BD	171
	172	fic = readl(regs + S3C2412_IISFIC);
	173	con = readl(regs + S3C2412_IISCON);
	174	mod = readl(regs + S3C2412_IISMOD);
	175
ee7d4767	176	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b BD	177
	178	if (on) {
	179	con \|= S3C2412_IISCON_RXDMA_ACTIVE \| S3C2412_IISCON_IIS_ACTIVE;
	180	con &= ~S3C2412_IISCON_RXDMA_PAUSE;
	181	con &= ~S3C2412_IISCON_RXCH_PAUSE;
	182
	183	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	184	case S3C2412_IISMOD_MODE_TXRX:
	185	case S3C2412_IISMOD_MODE_RXONLY:
	186	/* do nothing, we are in the right mode */
	187	break;
	188
	189	case S3C2412_IISMOD_MODE_TXONLY:
	190	mod &= ~S3C2412_IISMOD_MODE_MASK;
	191	mod \|= S3C2412_IISMOD_MODE_TXRX;
	192	break;
	193
	194	default:
abbc8246 MB	195	dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
abbc8246 MB	196	mod & S3C2412_IISMOD_MODE_MASK);
dc85447b BD	197	}
	198
	199	writel(mod, regs + S3C2412_IISMOD);
	200	writel(con, regs + S3C2412_IISCON);
	201	} else {
	202	/* See txctrl notes on FIFOs. */
	203
	204	con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
	205	con \|= S3C2412_IISCON_RXDMA_PAUSE;
	206	con \|= S3C2412_IISCON_RXCH_PAUSE;
	207
	208	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	209	case S3C2412_IISMOD_MODE_RXONLY:
	210	con &= ~S3C2412_IISCON_IIS_ACTIVE;
	211	mod &= ~S3C2412_IISMOD_MODE_MASK;
	212	break;
	213
	214	case S3C2412_IISMOD_MODE_TXRX:
	215	mod &= ~S3C2412_IISMOD_MODE_MASK;
	216	mod \|= S3C2412_IISMOD_MODE_TXONLY;
	217	break;
	218
	219	default:
abbc8246 MB	220	dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
abbc8246 MB	221	mod & S3C2412_IISMOD_MODE_MASK);
dc85447b BD	222	}
	223
	224	writel(con, regs + S3C2412_IISCON);
	225	writel(mod, regs + S3C2412_IISMOD);
	226	}
	227
	228	fic = readl(regs + S3C2412_IISFIC);
ee7d4767	229	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b	230	}
dc85447b BD	231
	232	/*
	233	* Wait for the LR signal to allow synchronisation to the L/R clock
	234	* from the codec. May only be needed for slave mode.
	235	*/
	236	static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
	237	{
	238	u32 iiscon;
	239	unsigned long timeout = jiffies + msecs_to_jiffies(5);
	240
ee7d4767	241	pr_debug("Entered %s\n", __func__);
dc85447b BD	242
	243	while (1) {
	244	iiscon = readl(i2s->regs + S3C2412_IISCON);
	245	if (iiscon & S3C2412_IISCON_LRINDEX)
	246	break;
	247
	248	if (timeout < jiffies) {
	249	printk(KERN_ERR "%s: timeout\n", __func__);
	250	return -ETIMEDOUT;
	251	}
	252	}
	253
	254	return 0;
	255	}
	256
	257	/*
	258	* Set S3C2412 I2S DAI format
	259	*/
	260	static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
	261	unsigned int fmt)
	262	{
	263	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	264	u32 iismod;
	265
ee7d4767	266	pr_debug("Entered %s\n", __func__);
dc85447b BD	267
dc85447b BD	268	iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767	269	pr_debug("hw_params r: IISMOD: %x \n", iismod);
dc85447b BD	270
	271	#if defined(CONFIG_CPU_S3C2412) \|\| defined(CONFIG_CPU_S3C2413)
	272	#define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
	273	#define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
	274	#define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
	275	#endif
	276
	277	#if defined(CONFIG_PLAT_S3C64XX)
	278	/* From Rev1.1 datasheet, we have two master and two slave modes:
	279	* IMS[11:10]:
	280	* 00 = master mode, fed from PCLK
	281	* 01 = master mode, fed from CLKAUDIO
	282	* 10 = slave mode, using PCLK
	283	* 11 = slave mode, using I2SCLK
	284	*/
	285	#define IISMOD_MASTER_MASK (1 << 11)
	286	#define IISMOD_SLAVE (1 << 11)
553b1dd5	287	#define IISMOD_MASTER (0 << 11)
dc85447b BD	288	#endif
	289
	290	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	291	case SND_SOC_DAIFMT_CBM_CFM:
	292	i2s->master = 0;
	293	iismod &= ~IISMOD_MASTER_MASK;
	294	iismod \|= IISMOD_SLAVE;
	295	break;
	296	case SND_SOC_DAIFMT_CBS_CFS:
	297	i2s->master = 1;
	298	iismod &= ~IISMOD_MASTER_MASK;
	299	iismod \|= IISMOD_MASTER;
	300	break;
	301	default:
38e43c81	302	pr_err("unknwon master/slave format\n");
dc85447b BD	303	return -EINVAL;
	304	}
	305
	306	iismod &= ~S3C2412_IISMOD_SDF_MASK;
	307
	308	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	309	case SND_SOC_DAIFMT_RIGHT_J:
	310	iismod \|= S3C2412_IISMOD_SDF_MSB;
	311	break;
	312	case SND_SOC_DAIFMT_LEFT_J:
	313	iismod \|= S3C2412_IISMOD_SDF_LSB;
	314	break;
	315	case SND_SOC_DAIFMT_I2S:
	316	iismod \|= S3C2412_IISMOD_SDF_IIS;
	317	break;
	318	default:
38e43c81	319	pr_err("Unknown data format\n");
dc85447b BD	320	return -EINVAL;
	321	}
	322
	323	writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767	324	pr_debug("hw_params w: IISMOD: %x \n", iismod);
dc85447b BD	325	return 0;
	326	}
	327
	328	static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
	329	struct snd_pcm_hw_params *params,
	330	struct snd_soc_dai *socdai)
	331	{
	332	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	333	struct snd_soc_dai_link *dai = rtd->dai;
	334	struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai);
	335	u32 iismod;
	336
ee7d4767	337	pr_debug("Entered %s\n", __func__);
dc85447b BD	338
	339	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	340	dai->cpu_dai->dma_data = i2s->dma_playback;
	341	else
	342	dai->cpu_dai->dma_data = i2s->dma_capture;
	343
	344	/* Working copies of register */
	345	iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767	346	pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
dc85447b	347
553b1dd5	348	#if defined(CONFIG_CPU_S3C2412) \|\| defined(CONFIG_CPU_S3C2413)
dc85447b BD	349	switch (params_format(params)) {
	350	case SNDRV_PCM_FORMAT_S8:
	351	iismod \|= S3C2412_IISMOD_8BIT;
	352	break;
	353	case SNDRV_PCM_FORMAT_S16_LE:
	354	iismod &= ~S3C2412_IISMOD_8BIT;
	355	break;
	356	}
553b1dd5 MB	357	#endif
	358
	359	#ifdef CONFIG_PLAT_S3C64XX
0914b93f	360	iismod &= ~(S3C64XX_IISMOD_BLC_MASK \| S3C2412_IISMOD_BCLK_MASK);
553b1dd5 MB	361	/* Sample size */
	362	switch (params_format(params)) {
	363	case SNDRV_PCM_FORMAT_S8:
	364	/* 8 bit sample, 16fs BCLK */
0914b93f	365	iismod \|= (S3C64XX_IISMOD_BLC_8BIT \| S3C2412_IISMOD_BCLK_16FS);
553b1dd5 MB	366	break;
	367	case SNDRV_PCM_FORMAT_S16_LE:
	368	/* 16 bit sample, 32fs BCLK */
	369	break;
	370	case SNDRV_PCM_FORMAT_S24_LE:
	371	/* 24 bit sample, 48fs BCLK */
0914b93f	372	iismod \|= (S3C64XX_IISMOD_BLC_24BIT \| S3C2412_IISMOD_BCLK_48FS);
553b1dd5 MB	373	break;
	374	}
	375	#endif
dc85447b BD	376
dc85447b BD	377	writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767	378	pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
dc85447b BD	379	return 0;
	380	}
	381
	382	static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
	383	struct snd_soc_dai *dai)
	384	{
	385	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	386	struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai);
	387	int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
	388	unsigned long irqs;
	389	int ret = 0;
faf907c7 SL	390	int channel = ((struct s3c24xx_pcm_dma_params *)
faf907c7 SL	391	rtd->dai->cpu_dai->dma_data)->channel;
dc85447b	392
ee7d4767	393	pr_debug("Entered %s\n", __func__);
dc85447b BD	394
	395	switch (cmd) {
	396	case SNDRV_PCM_TRIGGER_START:
	397	/* On start, ensure that the FIFOs are cleared and reset. */
	398
	399	writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
	400	i2s->regs + S3C2412_IISFIC);
	401
	402	/* clear again, just in case */
	403	writel(0x0, i2s->regs + S3C2412_IISFIC);
	404
	405	case SNDRV_PCM_TRIGGER_RESUME:
	406	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	407	if (!i2s->master) {
	408	ret = s3c2412_snd_lrsync(i2s);
	409	if (ret)
	410	goto exit_err;
	411	}
	412
	413	local_irq_save(irqs);
	414
	415	if (capture)
	416	s3c2412_snd_rxctrl(i2s, 1);
	417	else
	418	s3c2412_snd_txctrl(i2s, 1);
	419
	420	local_irq_restore(irqs);
faf907c7 SL	421
	422	/*
	423	* Load the next buffer to DMA to meet the reqirement
	424	* of the auto reload mechanism of S3C24XX.
	425	* This call won't bother S3C64XX.
	426	*/
	427	s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);
	428
dc85447b BD	429	break;
	430
	431	case SNDRV_PCM_TRIGGER_STOP:
	432	case SNDRV_PCM_TRIGGER_SUSPEND:
	433	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	434	local_irq_save(irqs);
	435
	436	if (capture)
	437	s3c2412_snd_rxctrl(i2s, 0);
	438	else
	439	s3c2412_snd_txctrl(i2s, 0);
	440
	441	local_irq_restore(irqs);
	442	break;
	443	default:
	444	ret = -EINVAL;
	445	break;
	446	}
	447
	448	exit_err:
	449	return ret;
	450	}
	451
	452	/*
	453	* Set S3C2412 Clock dividers
	454	*/
	455	static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
	456	int div_id, int div)
	457	{
	458	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	459	u32 reg;
	460
ee7d4767	461	pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
dc85447b BD	462
	463	switch (div_id) {
	464	case S3C_I2SV2_DIV_BCLK:
	465	reg = readl(i2s->regs + S3C2412_IISMOD);
	466	reg &= ~S3C2412_IISMOD_BCLK_MASK;
	467	writel(reg \| div, i2s->regs + S3C2412_IISMOD);
	468
ee7d4767	469	pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b BD	470	break;
	471
	472	case S3C_I2SV2_DIV_RCLK:
	473	if (div > 3) {
	474	/* convert value to bit field */
	475
	476	switch (div) {
	477	case 256:
	478	div = S3C2412_IISMOD_RCLK_256FS;
	479	break;
	480
	481	case 384:
	482	div = S3C2412_IISMOD_RCLK_384FS;
	483	break;
	484
	485	case 512:
	486	div = S3C2412_IISMOD_RCLK_512FS;
	487	break;
	488
	489	case 768:
	490	div = S3C2412_IISMOD_RCLK_768FS;
	491	break;
	492
	493	default:
	494	return -EINVAL;
	495	}
	496	}
	497
	498	reg = readl(i2s->regs + S3C2412_IISMOD);
	499	reg &= ~S3C2412_IISMOD_RCLK_MASK;
	500	writel(reg \| div, i2s->regs + S3C2412_IISMOD);
ee7d4767	501	pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b BD	502	break;
	503
	504	case S3C_I2SV2_DIV_PRESCALER:
	505	if (div >= 0) {
	506	writel((div << 8) \| S3C2412_IISPSR_PSREN,
	507	i2s->regs + S3C2412_IISPSR);
	508	} else {
	509	writel(0x0, i2s->regs + S3C2412_IISPSR);
	510	}
ee7d4767	511	pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
dc85447b BD	512	break;
	513
	514	default:
	515	return -EINVAL;
	516	}
	517
	518	return 0;
	519	}
	520
	521	/* default table of all avaialable root fs divisors */
	522	static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
	523
1d2b7ae9 BD	524	int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
	525	unsigned int *fstab,
	526	unsigned int rate, struct clk *clk)
dc85447b BD	527	{
	528	unsigned long clkrate = clk_get_rate(clk);
	529	unsigned int div;
	530	unsigned int fsclk;
	531	unsigned int actual;
	532	unsigned int fs;
	533	unsigned int fsdiv;
	534	signed int deviation = 0;
	535	unsigned int best_fs = 0;
	536	unsigned int best_div = 0;
	537	unsigned int best_rate = 0;
	538	unsigned int best_deviation = INT_MAX;
	539
af3ea7bd MB	540	pr_debug("Input clock rate %ldHz\n", clkrate);
af3ea7bd MB	541
dc85447b BD	542	if (fstab == NULL)
	543	fstab = iis_fs_tab;
	544
	545	for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
	546	fsdiv = iis_fs_tab[fs];
	547
	548	fsclk = clkrate / fsdiv;
	549	div = fsclk / rate;
	550
	551	if ((fsclk % rate) > (rate / 2))
	552	div++;
	553
	554	if (div <= 1)
	555	continue;
	556
	557	actual = clkrate / (fsdiv * div);
	558	deviation = actual - rate;
	559
449bd54d	560	printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
dc85447b BD	561	fsdiv, div, actual, deviation);
	562
	563	deviation = abs(deviation);
	564
	565	if (deviation < best_deviation) {
	566	best_fs = fsdiv;
	567	best_div = div;
	568	best_rate = actual;
	569	best_deviation = deviation;
	570	}
	571
	572	if (deviation == 0)
	573	break;
	574	}
	575
449bd54d	576	printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
dc85447b BD	577	best_fs, best_div, best_rate);
	578
	579	info->fs_div = best_fs;
	580	info->clk_div = best_div;
	581
	582	return 0;
	583	}
1d2b7ae9	584	EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
dc85447b BD	585
	586	int s3c_i2sv2_probe(struct platform_device *pdev,
	587	struct snd_soc_dai *dai,
	588	struct s3c_i2sv2_info *i2s,
	589	unsigned long base)
	590	{
	591	struct device *dev = &pdev->dev;
07736d48	592	unsigned int iismod;
dc85447b BD	593
	594	i2s->dev = dev;
	595
	596	/* record our i2s structure for later use in the callbacks */
	597	dai->private_data = i2s;
	598
c86bde54 MB	599	if (!base) {
	600	struct resource *res = platform_get_resource(pdev,
	601	IORESOURCE_MEM,
	602	0);
	603	if (!res) {
	604	dev_err(dev, "Unable to get register resource\n");
	605	return -ENXIO;
	606	}
	607
	608	if (!request_mem_region(res->start, resource_size(res),
	609	"s3c64xx-i2s-v4")) {
	610	dev_err(dev, "Unable to request register region\n");
	611	return -EBUSY;
	612	}
	613
	614	base = res->start;
	615	}
	616
dc85447b BD	617	i2s->regs = ioremap(base, 0x100);
	618	if (i2s->regs == NULL) {
	619	dev_err(dev, "cannot ioremap registers\n");
	620	return -ENXIO;
	621	}
	622
	623	i2s->iis_pclk = clk_get(dev, "iis");
	624	if (i2s->iis_pclk == NULL) {
b52a5195	625	dev_err(dev, "failed to get iis_clock\n");
dc85447b BD	626	iounmap(i2s->regs);
	627	return -ENOENT;
	628	}
	629
	630	clk_enable(i2s->iis_pclk);
	631
07736d48 MB	632	/* Mark ourselves as in TXRX mode so we can run through our cleanup
	633	* process without warnings. */
	634	iismod = readl(i2s->regs + S3C2412_IISMOD);
	635	iismod \|= S3C2412_IISMOD_MODE_TXRX;
	636	writel(iismod, i2s->regs + S3C2412_IISMOD);
dc85447b BD	637	s3c2412_snd_txctrl(i2s, 0);
	638	s3c2412_snd_rxctrl(i2s, 0);
	639
	640	return 0;
	641	}
dc85447b BD	642	EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
	643
	644	#ifdef CONFIG_PM
	645	static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
	646	{
	647	struct s3c_i2sv2_info *i2s = to_info(dai);
	648	u32 iismod;
	649
	650	if (dai->active) {
	651	i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
	652	i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
	653	i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
	654
	655	/* some basic suspend checks */
	656
	657	iismod = readl(i2s->regs + S3C2412_IISMOD);
	658
	659	if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
	660	pr_warning("%s: RXDMA active?\n", __func__);
	661
	662	if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
	663	pr_warning("%s: TXDMA active?\n", __func__);
	664
	665	if (iismod & S3C2412_IISCON_IIS_ACTIVE)
	666	pr_warning("%s: IIS active\n", __func__);
	667	}
	668
	669	return 0;
	670	}
	671
	672	static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
	673	{
	674	struct s3c_i2sv2_info *i2s = to_info(dai);
	675
	676	pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
	677	dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
	678
	679	if (dai->active) {
	680	writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
	681	writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
	682	writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
	683
	684	writel(S3C2412_IISFIC_RXFLUSH \| S3C2412_IISFIC_TXFLUSH,
	685	i2s->regs + S3C2412_IISFIC);
	686
	687	ndelay(250);
	688	writel(0x0, i2s->regs + S3C2412_IISFIC);
	689	}
	690
	691	return 0;
	692	}
	693	#else
	694	#define s3c2412_i2s_suspend NULL
	695	#define s3c2412_i2s_resume NULL
	696	#endif
	697
	698	int s3c_i2sv2_register_dai(struct snd_soc_dai *dai)
	699	{
3715c6aa BD	700	struct snd_soc_dai_ops *ops = dai->ops;
	701
	702	ops->trigger = s3c2412_i2s_trigger;
	703	ops->hw_params = s3c2412_i2s_hw_params;
	704	ops->set_fmt = s3c2412_i2s_set_fmt;
	705	ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
dc85447b BD	706
	707	dai->suspend = s3c2412_i2s_suspend;
	708	dai->resume = s3c2412_i2s_resume;
	709
	710	return snd_soc_register_dai(dai);
	711	}
dc85447b	712	EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai);
a396e32e MB	713
a396e32e MB	714	MODULE_LICENSE("GPL");