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ASoC: Add debug output tracing all cache register writes
[deliverable/linux.git] / sound / soc / s3c24xx / s3c-i2s-v2.c
CommitLineData
dc85447b
BD		 1/* sound/soc/s3c24xx/s3c-i2c-v2.c
2 *
3 * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
4 *
5 * Copyright (c) 2006 Wolfson Microelectronics PLC.
6 * Graeme Gregory graeme.gregory@wolfsonmicro.com
7 * linux@wolfsonmicro.com
8 *
9 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 * Ben Dooks <ben@simtec.co.uk>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
dc85447b
BD		 19#include <linux/delay.h>
20#include <linux/clk.h>
dc85447b
BD		 21#include <linux/io.h>
22
dc85447b
BD		 23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
dc85447b
BD		 25#include <sound/soc.h>
26
27#include <plat/regs-s3c2412-iis.h>
28
dc85447b
BD		 29#include <mach/dma.h>
30
31#include "s3c-i2s-v2.h"
d3ff5a3e 32#include "s3c-dma.h"
dc85447b 33
8a0f62b8
MB		 34#undef S3C_IIS_V2_SUPPORTED
35
36#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
37#define S3C_IIS_V2_SUPPORTED
38#endif
39
40#ifdef CONFIG_PLAT_S3C64XX
41#define S3C_IIS_V2_SUPPORTED
42#endif
43
44#ifndef S3C_IIS_V2_SUPPORTED
45#error Unsupported CPU model
46#endif
47
dc85447b 48#define S3C2412_I2S_DEBUG_CON 0
dc85447b
BD		 49
50static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
51{
52 return cpu_dai->private_data;
53}
54
55#define bit_set(v, b) (((v) & (b)) ? 1 : 0)
56
57#if S3C2412_I2S_DEBUG_CON
58static void dbg_showcon(const char *fn, u32 con)
59{
60 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
61 bit_set(con, S3C2412_IISCON_LRINDEX),
62 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
63 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
64 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
65 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
66
67 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
68 fn,
69 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
70 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
71 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
72 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
73 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
74 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
75 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
76 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
77}
78#else
79static inline void dbg_showcon(const char *fn, u32 con)
80{
81}
82#endif
83
84
85/* Turn on or off the transmission path. */
abbc8246 86static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 87{
88 void __iomem *regs = i2s->regs;
89 u32 fic, con, mod;
90
ee7d4767 91 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 92
93 fic = readl(regs + S3C2412_IISFIC);
94 con = readl(regs + S3C2412_IISCON);
95 mod = readl(regs + S3C2412_IISMOD);
96
ee7d4767 97 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 98
99 if (on) {
100 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
101 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
102 con &= ~S3C2412_IISCON_TXCH_PAUSE;
103
104 switch (mod & S3C2412_IISMOD_MODE_MASK) {
105 case S3C2412_IISMOD_MODE_TXONLY:
106 case S3C2412_IISMOD_MODE_TXRX:
107 /* do nothing, we are in the right mode */
108 break;
109
110 case S3C2412_IISMOD_MODE_RXONLY:
111 mod &= ~S3C2412_IISMOD_MODE_MASK;
112 mod |= S3C2412_IISMOD_MODE_TXRX;
113 break;
114
115 default:
abbc8246
MB		 116 dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
117 mod & S3C2412_IISMOD_MODE_MASK);
118 break;
dc85447b
BD		 119 }
120
121 writel(con, regs + S3C2412_IISCON);
122 writel(mod, regs + S3C2412_IISMOD);
123 } else {
124 /* Note, we do not have any indication that the FIFO problems
125 * tha the S3C2410/2440 had apply here, so we should be able
126 * to disable the DMA and TX without resetting the FIFOS.
127 */
128
129 con |= S3C2412_IISCON_TXDMA_PAUSE;
130 con |= S3C2412_IISCON_TXCH_PAUSE;
131 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
132
133 switch (mod & S3C2412_IISMOD_MODE_MASK) {
134 case S3C2412_IISMOD_MODE_TXRX:
135 mod &= ~S3C2412_IISMOD_MODE_MASK;
136 mod |= S3C2412_IISMOD_MODE_RXONLY;
137 break;
138
139 case S3C2412_IISMOD_MODE_TXONLY:
140 mod &= ~S3C2412_IISMOD_MODE_MASK;
141 con &= ~S3C2412_IISCON_IIS_ACTIVE;
142 break;
143
144 default:
abbc8246
MB		 145 dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
146 mod & S3C2412_IISMOD_MODE_MASK);
147 break;
dc85447b
BD		 148 }
149
150 writel(mod, regs + S3C2412_IISMOD);
151 writel(con, regs + S3C2412_IISCON);
152 }
153
154 fic = readl(regs + S3C2412_IISFIC);
155 dbg_showcon(__func__, con);
ee7d4767 156 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 157}
dc85447b 158
abbc8246 159static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 160{
161 void __iomem *regs = i2s->regs;
162 u32 fic, con, mod;
163
ee7d4767 164 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 165
166 fic = readl(regs + S3C2412_IISFIC);
167 con = readl(regs + S3C2412_IISCON);
168 mod = readl(regs + S3C2412_IISMOD);
169
ee7d4767 170 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 171
172 if (on) {
173 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
174 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
175 con &= ~S3C2412_IISCON_RXCH_PAUSE;
176
177 switch (mod & S3C2412_IISMOD_MODE_MASK) {
178 case S3C2412_IISMOD_MODE_TXRX:
179 case S3C2412_IISMOD_MODE_RXONLY:
180 /* do nothing, we are in the right mode */
181 break;
182
183 case S3C2412_IISMOD_MODE_TXONLY:
184 mod &= ~S3C2412_IISMOD_MODE_MASK;
185 mod |= S3C2412_IISMOD_MODE_TXRX;
186 break;
187
188 default:
abbc8246
MB		 189 dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
190 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 191 }
192
193 writel(mod, regs + S3C2412_IISMOD);
194 writel(con, regs + S3C2412_IISCON);
195 } else {
196 /* See txctrl notes on FIFOs. */
197
198 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
199 con |= S3C2412_IISCON_RXDMA_PAUSE;
200 con |= S3C2412_IISCON_RXCH_PAUSE;
201
202 switch (mod & S3C2412_IISMOD_MODE_MASK) {
203 case S3C2412_IISMOD_MODE_RXONLY:
204 con &= ~S3C2412_IISCON_IIS_ACTIVE;
205 mod &= ~S3C2412_IISMOD_MODE_MASK;
206 break;
207
208 case S3C2412_IISMOD_MODE_TXRX:
209 mod &= ~S3C2412_IISMOD_MODE_MASK;
210 mod |= S3C2412_IISMOD_MODE_TXONLY;
211 break;
212
213 default:
abbc8246
MB		 214 dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
215 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 216 }
217
218 writel(con, regs + S3C2412_IISCON);
219 writel(mod, regs + S3C2412_IISMOD);
220 }
221
222 fic = readl(regs + S3C2412_IISFIC);
ee7d4767 223 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 224}
dc85447b 225
fa68e002
J		 226#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
227
dc85447b
BD		 228/*
229 * Wait for the LR signal to allow synchronisation to the L/R clock
230 * from the codec. May only be needed for slave mode.
231 */
232static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
233{
234 u32 iiscon;
fa68e002 235 unsigned long loops = msecs_to_loops(5);
dc85447b 236
ee7d4767 237 pr_debug("Entered %s\n", __func__);
dc85447b 238
fa68e002 239 while (--loops) {
dc85447b
BD		 240 iiscon = readl(i2s->regs + S3C2412_IISCON);
241 if (iiscon & S3C2412_IISCON_LRINDEX)
242 break;
243
fa68e002
J		 244 cpu_relax();
245 }
246
247 if (!loops) {
248 printk(KERN_ERR "%s: timeout\n", __func__);
249 return -ETIMEDOUT;
dc85447b
BD		 250 }
251
252 return 0;
253}
254
255/*
256 * Set S3C2412 I2S DAI format
257 */
258static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
259 unsigned int fmt)
260{
261 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
262 u32 iismod;
263
ee7d4767 264 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 265
266 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 267 pr_debug("hw_params r: IISMOD: %x \n", iismod);
dc85447b
BD		 268
269#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
270#define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
271#define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
272#define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
273#endif
274
275#if defined(CONFIG_PLAT_S3C64XX)
276/* From Rev1.1 datasheet, we have two master and two slave modes:
277 * IMS[11:10]:
278 * 00 = master mode, fed from PCLK
279 * 01 = master mode, fed from CLKAUDIO
280 * 10 = slave mode, using PCLK
281 * 11 = slave mode, using I2SCLK
282 */
283#define IISMOD_MASTER_MASK (1 << 11)
284#define IISMOD_SLAVE (1 << 11)
553b1dd5 285#define IISMOD_MASTER (0 << 11)
dc85447b
BD		 286#endif
287
288 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
289 case SND_SOC_DAIFMT_CBM_CFM:
290 i2s->master = 0;
291 iismod &= ~IISMOD_MASTER_MASK;
292 iismod |= IISMOD_SLAVE;
293 break;
294 case SND_SOC_DAIFMT_CBS_CFS:
295 i2s->master = 1;
296 iismod &= ~IISMOD_MASTER_MASK;
297 iismod |= IISMOD_MASTER;
298 break;
299 default:
38e43c81 300 pr_err("unknwon master/slave format\n");
dc85447b
BD		 301 return -EINVAL;
302 }
303
304 iismod &= ~S3C2412_IISMOD_SDF_MASK;
305
306 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
307 case SND_SOC_DAIFMT_RIGHT_J:
fd5ad654 308 iismod |= S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 309 iismod |= S3C2412_IISMOD_SDF_MSB;
310 break;
311 case SND_SOC_DAIFMT_LEFT_J:
fd5ad654 312 iismod |= S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 313 iismod |= S3C2412_IISMOD_SDF_LSB;
314 break;
315 case SND_SOC_DAIFMT_I2S:
fd5ad654 316 iismod &= ~S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 317 iismod |= S3C2412_IISMOD_SDF_IIS;
318 break;
319 default:
38e43c81 320 pr_err("Unknown data format\n");
dc85447b
BD		 321 return -EINVAL;
322 }
323
324 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 325 pr_debug("hw_params w: IISMOD: %x \n", iismod);
dc85447b
BD		 326 return 0;
327}
328
9c9b1257 329static int s3c_i2sv2_hw_params(struct snd_pcm_substream *substream,
dc85447b
BD		 330 struct snd_pcm_hw_params *params,
331 struct snd_soc_dai *socdai)
332{
333 struct snd_soc_pcm_runtime *rtd = substream->private_data;
334 struct snd_soc_dai_link *dai = rtd->dai;
335 struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai);
fd23b7de 336 struct s3c_dma_params *dma_data;
dc85447b
BD		 337 u32 iismod;
338
ee7d4767 339 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 340
341 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
fd23b7de 342 dma_data = i2s->dma_playback;
dc85447b 343 else
fd23b7de
DM		 344 dma_data = i2s->dma_capture;
345
346 snd_soc_dai_set_dma_data(dai->cpu_dai, substream, dma_data);
dc85447b
BD		 347
348 /* Working copies of register */
349 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 350 pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
dc85447b 351
bf328826 352 iismod &= ~S3C64XX_IISMOD_BLC_MASK;
553b1dd5
MB		 353 /* Sample size */
354 switch (params_format(params)) {
355 case SNDRV_PCM_FORMAT_S8:
bf328826 356 iismod |= S3C64XX_IISMOD_BLC_8BIT;
553b1dd5
MB		 357 break;
358 case SNDRV_PCM_FORMAT_S16_LE:
553b1dd5
MB		 359 break;
360 case SNDRV_PCM_FORMAT_S24_LE:
bf328826 361 iismod |= S3C64XX_IISMOD_BLC_24BIT;
553b1dd5
MB		 362 break;
363 }
dc85447b
BD		 364
365 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 366 pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
dc85447b
BD		 367 return 0;
368}
369
370static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
371 struct snd_soc_dai *dai)
372{
373 struct snd_soc_pcm_runtime *rtd = substream->private_data;
374 struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai);
375 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
376 unsigned long irqs;
377 int ret = 0;
fd23b7de
DM		 378 struct s3c_dma_params *dma_data =
379 snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream);
dc85447b 380
ee7d4767 381 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 382
383 switch (cmd) {
384 case SNDRV_PCM_TRIGGER_START:
385 /* On start, ensure that the FIFOs are cleared and reset. */
386
387 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
388 i2s->regs + S3C2412_IISFIC);
389
390 /* clear again, just in case */
391 writel(0x0, i2s->regs + S3C2412_IISFIC);
392
393 case SNDRV_PCM_TRIGGER_RESUME:
394 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
395 if (!i2s->master) {
396 ret = s3c2412_snd_lrsync(i2s);
397 if (ret)
398 goto exit_err;
399 }
400
401 local_irq_save(irqs);
402
403 if (capture)
404 s3c2412_snd_rxctrl(i2s, 1);
405 else
406 s3c2412_snd_txctrl(i2s, 1);
407
408 local_irq_restore(irqs);
faf907c7
SL		 409
410 /*
411 * Load the next buffer to DMA to meet the reqirement
412 * of the auto reload mechanism of S3C24XX.
413 * This call won't bother S3C64XX.
414 */
fd23b7de 415 s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
faf907c7 416
dc85447b
BD		 417 break;
418
419 case SNDRV_PCM_TRIGGER_STOP:
420 case SNDRV_PCM_TRIGGER_SUSPEND:
421 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
422 local_irq_save(irqs);
423
424 if (capture)
425 s3c2412_snd_rxctrl(i2s, 0);
426 else
427 s3c2412_snd_txctrl(i2s, 0);
428
429 local_irq_restore(irqs);
430 break;
431 default:
432 ret = -EINVAL;
433 break;
434 }
435
436exit_err:
437 return ret;
438}
439
440/*
441 * Set S3C2412 Clock dividers
442 */
443static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
444 int div_id, int div)
445{
446 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
447 u32 reg;
448
ee7d4767 449 pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
dc85447b
BD		 450
451 switch (div_id) {
452 case S3C_I2SV2_DIV_BCLK:
51c6ab13
JB		 453 switch (div) {
454 case 16:
455 div = S3C2412_IISMOD_BCLK_16FS;
456 break;
fd5ad654 457
51c6ab13
JB		 458 case 32:
459 div = S3C2412_IISMOD_BCLK_32FS;
460 break;
fd5ad654 461
51c6ab13
JB		 462 case 24:
463 div = S3C2412_IISMOD_BCLK_24FS;
464 break;
fd5ad654 465
51c6ab13
JB		 466 case 48:
467 div = S3C2412_IISMOD_BCLK_48FS;
468 break;
fd5ad654 469
51c6ab13
JB		 470 default:
471 return -EINVAL;
fd5ad654
J		 472 }
473
dc85447b
BD		 474 reg = readl(i2s->regs + S3C2412_IISMOD);
475 reg &= ~S3C2412_IISMOD_BCLK_MASK;
476 writel(reg | div, i2s->regs + S3C2412_IISMOD);
477
ee7d4767 478 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 479 break;
480
481 case S3C_I2SV2_DIV_RCLK:
51c6ab13
JB		 482 switch (div) {
483 case 256:
484 div = S3C2412_IISMOD_RCLK_256FS;
485 break;
dc85447b 486
51c6ab13
JB		 487 case 384:
488 div = S3C2412_IISMOD_RCLK_384FS;
489 break;
dc85447b 490
51c6ab13
JB		 491 case 512:
492 div = S3C2412_IISMOD_RCLK_512FS;
493 break;
dc85447b 494
51c6ab13
JB		 495 case 768:
496 div = S3C2412_IISMOD_RCLK_768FS;
497 break;
dc85447b 498
51c6ab13
JB		 499 default:
500 return -EINVAL;
dc85447b
BD		 501 }
502
503 reg = readl(i2s->regs + S3C2412_IISMOD);
504 reg &= ~S3C2412_IISMOD_RCLK_MASK;
505 writel(reg | div, i2s->regs + S3C2412_IISMOD);
ee7d4767 506 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 507 break;
508
509 case S3C_I2SV2_DIV_PRESCALER:
510 if (div >= 0) {
511 writel((div << 8) | S3C2412_IISPSR_PSREN,
512 i2s->regs + S3C2412_IISPSR);
513 } else {
514 writel(0x0, i2s->regs + S3C2412_IISPSR);
515 }
ee7d4767 516 pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
dc85447b
BD		 517 break;
518
519 default:
520 return -EINVAL;
521 }
522
523 return 0;
524}
525
1ca75780
MB		 526static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream,
527 struct snd_soc_dai *dai)
528{
529 struct s3c_i2sv2_info *i2s = to_info(dai);
530 u32 reg = readl(i2s->regs + S3C2412_IISFIC);
531 snd_pcm_sframes_t delay;
532
533 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
534 delay = S3C2412_IISFIC_TXCOUNT(reg);
535 else
536 delay = S3C2412_IISFIC_RXCOUNT(reg);
537
538 return delay;
539}
540
dc85447b
BD		 541/* default table of all avaialable root fs divisors */
542static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
543
1d2b7ae9
BD		 544int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
545 unsigned int *fstab,
546 unsigned int rate, struct clk *clk)
dc85447b
BD		 547{
548 unsigned long clkrate = clk_get_rate(clk);
549 unsigned int div;
550 unsigned int fsclk;
551 unsigned int actual;
552 unsigned int fs;
553 unsigned int fsdiv;
554 signed int deviation = 0;
555 unsigned int best_fs = 0;
556 unsigned int best_div = 0;
557 unsigned int best_rate = 0;
558 unsigned int best_deviation = INT_MAX;
559
af3ea7bd
MB		 560 pr_debug("Input clock rate %ldHz\n", clkrate);
561
dc85447b
BD		 562 if (fstab == NULL)
563 fstab = iis_fs_tab;
564
565 for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
566 fsdiv = iis_fs_tab[fs];
567
568 fsclk = clkrate / fsdiv;
569 div = fsclk / rate;
570
571 if ((fsclk % rate) > (rate / 2))
572 div++;
573
574 if (div <= 1)
575 continue;
576
577 actual = clkrate / (fsdiv * div);
578 deviation = actual - rate;
579
449bd54d 580 printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
dc85447b
BD		 581 fsdiv, div, actual, deviation);
582
583 deviation = abs(deviation);
584
585 if (deviation < best_deviation) {
586 best_fs = fsdiv;
587 best_div = div;
588 best_rate = actual;
589 best_deviation = deviation;
590 }
591
592 if (deviation == 0)
593 break;
594 }
595
449bd54d 596 printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
dc85447b
BD		 597 best_fs, best_div, best_rate);
598
599 info->fs_div = best_fs;
600 info->clk_div = best_div;
601
602 return 0;
603}
1d2b7ae9 604EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
dc85447b
BD		 605
606int s3c_i2sv2_probe(struct platform_device *pdev,
607 struct snd_soc_dai *dai,
608 struct s3c_i2sv2_info *i2s,
609 unsigned long base)
610{
611 struct device *dev = &pdev->dev;
07736d48 612 unsigned int iismod;
dc85447b
BD		 613
614 i2s->dev = dev;
615
616 /* record our i2s structure for later use in the callbacks */
617 dai->private_data = i2s;
618
c86bde54
MB		 619 if (!base) {
620 struct resource *res = platform_get_resource(pdev,
621 IORESOURCE_MEM,
622 0);
623 if (!res) {
624 dev_err(dev, "Unable to get register resource\n");
625 return -ENXIO;
626 }
627
628 if (!request_mem_region(res->start, resource_size(res),
629 "s3c64xx-i2s-v4")) {
630 dev_err(dev, "Unable to request register region\n");
631 return -EBUSY;
632 }
633
634 base = res->start;
635 }
636
dc85447b
BD		 637 i2s->regs = ioremap(base, 0x100);
638 if (i2s->regs == NULL) {
639 dev_err(dev, "cannot ioremap registers\n");
640 return -ENXIO;
641 }
642
643 i2s->iis_pclk = clk_get(dev, "iis");
fd5ad654 644 if (IS_ERR(i2s->iis_pclk)) {
b52a5195 645 dev_err(dev, "failed to get iis_clock\n");
dc85447b
BD		 646 iounmap(i2s->regs);
647 return -ENOENT;
648 }
649
650 clk_enable(i2s->iis_pclk);
651
07736d48
MB		 652 /* Mark ourselves as in TXRX mode so we can run through our cleanup
653 * process without warnings. */
654 iismod = readl(i2s->regs + S3C2412_IISMOD);
655 iismod |= S3C2412_IISMOD_MODE_TXRX;
656 writel(iismod, i2s->regs + S3C2412_IISMOD);
dc85447b
BD		 657 s3c2412_snd_txctrl(i2s, 0);
658 s3c2412_snd_rxctrl(i2s, 0);
659
660 return 0;
661}
dc85447b
BD		 662EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
663
664#ifdef CONFIG_PM
665static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
666{
667 struct s3c_i2sv2_info *i2s = to_info(dai);
668 u32 iismod;
669
670 if (dai->active) {
671 i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
672 i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
673 i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
674
675 /* some basic suspend checks */
676
677 iismod = readl(i2s->regs + S3C2412_IISMOD);
678
679 if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
680 pr_warning("%s: RXDMA active?\n", __func__);
681
682 if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
683 pr_warning("%s: TXDMA active?\n", __func__);
684
685 if (iismod & S3C2412_IISCON_IIS_ACTIVE)
686 pr_warning("%s: IIS active\n", __func__);
687 }
688
689 return 0;
690}
691
692static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
693{
694 struct s3c_i2sv2_info *i2s = to_info(dai);
695
696 pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
697 dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
698
699 if (dai->active) {
700 writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
701 writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
702 writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
703
704 writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
705 i2s->regs + S3C2412_IISFIC);
706
707 ndelay(250);
708 writel(0x0, i2s->regs + S3C2412_IISFIC);
709 }
710
711 return 0;
712}
713#else
714#define s3c2412_i2s_suspend NULL
715#define s3c2412_i2s_resume NULL
716#endif
717
718int s3c_i2sv2_register_dai(struct snd_soc_dai *dai)
719{
3715c6aa
BD		 720 struct snd_soc_dai_ops *ops = dai->ops;
721
722 ops->trigger = s3c2412_i2s_trigger;
9c9b1257
JB		 723 if (!ops->hw_params)
724 ops->hw_params = s3c_i2sv2_hw_params;
3715c6aa
BD		 725 ops->set_fmt = s3c2412_i2s_set_fmt;
726 ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
dc85447b 727
1ca75780
MB		 728 /* Allow overriding by (for example) IISv4 */
729 if (!ops->delay)
08226614 730 ops->delay = s3c2412_i2s_delay;
1ca75780 731
dc85447b
BD		 732 dai->suspend = s3c2412_i2s_suspend;
733 dai->resume = s3c2412_i2s_resume;
734
735 return snd_soc_register_dai(dai);
736}
dc85447b 737EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai);
a396e32e
MB		 738
739MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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