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ASoC: SAMSUNG: I2S: Add bit definitions
[deliverable/linux.git] / sound / soc / s3c24xx / s3c-i2s-v2.c
CommitLineData
dc85447b
BD		 1/* sound/soc/s3c24xx/s3c-i2c-v2.c
2 *
3 * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
4 *
5 * Copyright (c) 2006 Wolfson Microelectronics PLC.
6 * Graeme Gregory graeme.gregory@wolfsonmicro.com
7 * linux@wolfsonmicro.com
8 *
9 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 * Ben Dooks <ben@simtec.co.uk>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
dc85447b
BD		 19#include <linux/delay.h>
20#include <linux/clk.h>
dc85447b
BD		 21#include <linux/io.h>
22
dc85447b
BD		 23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
dc85447b
BD		 25#include <sound/soc.h>
26
dc85447b
BD		 27#include <mach/dma.h>
28
d07e7ce9 29#include "regs-i2s-v2.h"
dc85447b 30#include "s3c-i2s-v2.h"
d3ff5a3e 31#include "s3c-dma.h"
dc85447b 32
8a0f62b8
MB		 33#undef S3C_IIS_V2_SUPPORTED
34
35#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
36#define S3C_IIS_V2_SUPPORTED
37#endif
38
39#ifdef CONFIG_PLAT_S3C64XX
40#define S3C_IIS_V2_SUPPORTED
41#endif
42
43#ifndef S3C_IIS_V2_SUPPORTED
44#error Unsupported CPU model
45#endif
46
dc85447b 47#define S3C2412_I2S_DEBUG_CON 0
dc85447b
BD		 48
49static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
50{
51 return cpu_dai->private_data;
52}
53
54#define bit_set(v, b) (((v) & (b)) ? 1 : 0)
55
56#if S3C2412_I2S_DEBUG_CON
57static void dbg_showcon(const char *fn, u32 con)
58{
59 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
60 bit_set(con, S3C2412_IISCON_LRINDEX),
61 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
62 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
63 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
64 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
65
66 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
67 fn,
68 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
69 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
70 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
71 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
72 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
73 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
74 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
75 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
76}
77#else
78static inline void dbg_showcon(const char *fn, u32 con)
79{
80}
81#endif
82
83
84/* Turn on or off the transmission path. */
abbc8246 85static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 86{
87 void __iomem *regs = i2s->regs;
88 u32 fic, con, mod;
89
ee7d4767 90 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 91
92 fic = readl(regs + S3C2412_IISFIC);
93 con = readl(regs + S3C2412_IISCON);
94 mod = readl(regs + S3C2412_IISMOD);
95
ee7d4767 96 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 97
98 if (on) {
99 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
100 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
101 con &= ~S3C2412_IISCON_TXCH_PAUSE;
102
103 switch (mod & S3C2412_IISMOD_MODE_MASK) {
104 case S3C2412_IISMOD_MODE_TXONLY:
105 case S3C2412_IISMOD_MODE_TXRX:
106 /* do nothing, we are in the right mode */
107 break;
108
109 case S3C2412_IISMOD_MODE_RXONLY:
110 mod &= ~S3C2412_IISMOD_MODE_MASK;
111 mod |= S3C2412_IISMOD_MODE_TXRX;
112 break;
113
114 default:
abbc8246
MB		 115 dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
116 mod & S3C2412_IISMOD_MODE_MASK);
117 break;
dc85447b
BD		 118 }
119
120 writel(con, regs + S3C2412_IISCON);
121 writel(mod, regs + S3C2412_IISMOD);
122 } else {
123 /* Note, we do not have any indication that the FIFO problems
124 * tha the S3C2410/2440 had apply here, so we should be able
125 * to disable the DMA and TX without resetting the FIFOS.
126 */
127
128 con |= S3C2412_IISCON_TXDMA_PAUSE;
129 con |= S3C2412_IISCON_TXCH_PAUSE;
130 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
131
132 switch (mod & S3C2412_IISMOD_MODE_MASK) {
133 case S3C2412_IISMOD_MODE_TXRX:
134 mod &= ~S3C2412_IISMOD_MODE_MASK;
135 mod |= S3C2412_IISMOD_MODE_RXONLY;
136 break;
137
138 case S3C2412_IISMOD_MODE_TXONLY:
139 mod &= ~S3C2412_IISMOD_MODE_MASK;
140 con &= ~S3C2412_IISCON_IIS_ACTIVE;
141 break;
142
143 default:
abbc8246
MB		 144 dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
145 mod & S3C2412_IISMOD_MODE_MASK);
146 break;
dc85447b
BD		 147 }
148
149 writel(mod, regs + S3C2412_IISMOD);
150 writel(con, regs + S3C2412_IISCON);
151 }
152
153 fic = readl(regs + S3C2412_IISFIC);
154 dbg_showcon(__func__, con);
ee7d4767 155 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 156}
dc85447b 157
abbc8246 158static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 159{
160 void __iomem *regs = i2s->regs;
161 u32 fic, con, mod;
162
ee7d4767 163 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 164
165 fic = readl(regs + S3C2412_IISFIC);
166 con = readl(regs + S3C2412_IISCON);
167 mod = readl(regs + S3C2412_IISMOD);
168
ee7d4767 169 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 170
171 if (on) {
172 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
173 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
174 con &= ~S3C2412_IISCON_RXCH_PAUSE;
175
176 switch (mod & S3C2412_IISMOD_MODE_MASK) {
177 case S3C2412_IISMOD_MODE_TXRX:
178 case S3C2412_IISMOD_MODE_RXONLY:
179 /* do nothing, we are in the right mode */
180 break;
181
182 case S3C2412_IISMOD_MODE_TXONLY:
183 mod &= ~S3C2412_IISMOD_MODE_MASK;
184 mod |= S3C2412_IISMOD_MODE_TXRX;
185 break;
186
187 default:
abbc8246
MB		 188 dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
189 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 190 }
191
192 writel(mod, regs + S3C2412_IISMOD);
193 writel(con, regs + S3C2412_IISCON);
194 } else {
195 /* See txctrl notes on FIFOs. */
196
197 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
198 con |= S3C2412_IISCON_RXDMA_PAUSE;
199 con |= S3C2412_IISCON_RXCH_PAUSE;
200
201 switch (mod & S3C2412_IISMOD_MODE_MASK) {
202 case S3C2412_IISMOD_MODE_RXONLY:
203 con &= ~S3C2412_IISCON_IIS_ACTIVE;
204 mod &= ~S3C2412_IISMOD_MODE_MASK;
205 break;
206
207 case S3C2412_IISMOD_MODE_TXRX:
208 mod &= ~S3C2412_IISMOD_MODE_MASK;
209 mod |= S3C2412_IISMOD_MODE_TXONLY;
210 break;
211
212 default:
abbc8246
MB		 213 dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
214 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 215 }
216
217 writel(con, regs + S3C2412_IISCON);
218 writel(mod, regs + S3C2412_IISMOD);
219 }
220
221 fic = readl(regs + S3C2412_IISFIC);
ee7d4767 222 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 223}
dc85447b 224
fa68e002
J		 225#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
226
dc85447b
BD		 227/*
228 * Wait for the LR signal to allow synchronisation to the L/R clock
229 * from the codec. May only be needed for slave mode.
230 */
231static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
232{
233 u32 iiscon;
fa68e002 234 unsigned long loops = msecs_to_loops(5);
dc85447b 235
ee7d4767 236 pr_debug("Entered %s\n", __func__);
dc85447b 237
fa68e002 238 while (--loops) {
dc85447b
BD		 239 iiscon = readl(i2s->regs + S3C2412_IISCON);
240 if (iiscon & S3C2412_IISCON_LRINDEX)
241 break;
242
fa68e002
J		 243 cpu_relax();
244 }
245
246 if (!loops) {
247 printk(KERN_ERR "%s: timeout\n", __func__);
248 return -ETIMEDOUT;
dc85447b
BD		 249 }
250
251 return 0;
252}
253
254/*
255 * Set S3C2412 I2S DAI format
256 */
257static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
258 unsigned int fmt)
259{
260 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
261 u32 iismod;
262
ee7d4767 263 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 264
265 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 266 pr_debug("hw_params r: IISMOD: %x \n", iismod);
dc85447b
BD		 267
268#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
269#define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
270#define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
271#define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
272#endif
273
274#if defined(CONFIG_PLAT_S3C64XX)
275/* From Rev1.1 datasheet, we have two master and two slave modes:
276 * IMS[11:10]:
277 * 00 = master mode, fed from PCLK
278 * 01 = master mode, fed from CLKAUDIO
279 * 10 = slave mode, using PCLK
280 * 11 = slave mode, using I2SCLK
281 */
282#define IISMOD_MASTER_MASK (1 << 11)
283#define IISMOD_SLAVE (1 << 11)
553b1dd5 284#define IISMOD_MASTER (0 << 11)
dc85447b
BD		 285#endif
286
287 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
288 case SND_SOC_DAIFMT_CBM_CFM:
289 i2s->master = 0;
290 iismod &= ~IISMOD_MASTER_MASK;
291 iismod |= IISMOD_SLAVE;
292 break;
293 case SND_SOC_DAIFMT_CBS_CFS:
294 i2s->master = 1;
295 iismod &= ~IISMOD_MASTER_MASK;
296 iismod |= IISMOD_MASTER;
297 break;
298 default:
38e43c81 299 pr_err("unknwon master/slave format\n");
dc85447b
BD		 300 return -EINVAL;
301 }
302
303 iismod &= ~S3C2412_IISMOD_SDF_MASK;
304
305 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
306 case SND_SOC_DAIFMT_RIGHT_J:
fd5ad654 307 iismod |= S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 308 iismod |= S3C2412_IISMOD_SDF_MSB;
309 break;
310 case SND_SOC_DAIFMT_LEFT_J:
fd5ad654 311 iismod |= S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 312 iismod |= S3C2412_IISMOD_SDF_LSB;
313 break;
314 case SND_SOC_DAIFMT_I2S:
fd5ad654 315 iismod &= ~S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 316 iismod |= S3C2412_IISMOD_SDF_IIS;
317 break;
318 default:
38e43c81 319 pr_err("Unknown data format\n");
dc85447b
BD		 320 return -EINVAL;
321 }
322
323 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 324 pr_debug("hw_params w: IISMOD: %x \n", iismod);
dc85447b
BD		 325 return 0;
326}
327
9c9b1257 328static int s3c_i2sv2_hw_params(struct snd_pcm_substream *substream,
dc85447b
BD		 329 struct snd_pcm_hw_params *params,
330 struct snd_soc_dai *socdai)
331{
332 struct snd_soc_pcm_runtime *rtd = substream->private_data;
333 struct snd_soc_dai_link *dai = rtd->dai;
334 struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai);
fd23b7de 335 struct s3c_dma_params *dma_data;
dc85447b
BD		 336 u32 iismod;
337
ee7d4767 338 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 339
340 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
fd23b7de 341 dma_data = i2s->dma_playback;
dc85447b 342 else
fd23b7de
DM		 343 dma_data = i2s->dma_capture;
344
345 snd_soc_dai_set_dma_data(dai->cpu_dai, substream, dma_data);
dc85447b
BD		 346
347 /* Working copies of register */
348 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 349 pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
dc85447b 350
bf328826 351 iismod &= ~S3C64XX_IISMOD_BLC_MASK;
553b1dd5
MB		 352 /* Sample size */
353 switch (params_format(params)) {
354 case SNDRV_PCM_FORMAT_S8:
bf328826 355 iismod |= S3C64XX_IISMOD_BLC_8BIT;
553b1dd5
MB		 356 break;
357 case SNDRV_PCM_FORMAT_S16_LE:
553b1dd5
MB		 358 break;
359 case SNDRV_PCM_FORMAT_S24_LE:
bf328826 360 iismod |= S3C64XX_IISMOD_BLC_24BIT;
553b1dd5
MB		 361 break;
362 }
dc85447b
BD		 363
364 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 365 pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
dc85447b
BD		 366 return 0;
367}
368
369static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
370 struct snd_soc_dai *dai)
371{
372 struct snd_soc_pcm_runtime *rtd = substream->private_data;
373 struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai);
374 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
375 unsigned long irqs;
376 int ret = 0;
fd23b7de
DM		 377 struct s3c_dma_params *dma_data =
378 snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream);
dc85447b 379
ee7d4767 380 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 381
382 switch (cmd) {
383 case SNDRV_PCM_TRIGGER_START:
384 /* On start, ensure that the FIFOs are cleared and reset. */
385
386 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
387 i2s->regs + S3C2412_IISFIC);
388
389 /* clear again, just in case */
390 writel(0x0, i2s->regs + S3C2412_IISFIC);
391
392 case SNDRV_PCM_TRIGGER_RESUME:
393 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
394 if (!i2s->master) {
395 ret = s3c2412_snd_lrsync(i2s);
396 if (ret)
397 goto exit_err;
398 }
399
400 local_irq_save(irqs);
401
402 if (capture)
403 s3c2412_snd_rxctrl(i2s, 1);
404 else
405 s3c2412_snd_txctrl(i2s, 1);
406
407 local_irq_restore(irqs);
faf907c7
SL		 408
409 /*
410 * Load the next buffer to DMA to meet the reqirement
411 * of the auto reload mechanism of S3C24XX.
412 * This call won't bother S3C64XX.
413 */
fd23b7de 414 s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
faf907c7 415
dc85447b
BD		 416 break;
417
418 case SNDRV_PCM_TRIGGER_STOP:
419 case SNDRV_PCM_TRIGGER_SUSPEND:
420 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
421 local_irq_save(irqs);
422
423 if (capture)
424 s3c2412_snd_rxctrl(i2s, 0);
425 else
426 s3c2412_snd_txctrl(i2s, 0);
427
428 local_irq_restore(irqs);
429 break;
430 default:
431 ret = -EINVAL;
432 break;
433 }
434
435exit_err:
436 return ret;
437}
438
439/*
440 * Set S3C2412 Clock dividers
441 */
442static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
443 int div_id, int div)
444{
445 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
446 u32 reg;
447
ee7d4767 448 pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
dc85447b
BD		 449
450 switch (div_id) {
451 case S3C_I2SV2_DIV_BCLK:
51c6ab13
JB		 452 switch (div) {
453 case 16:
454 div = S3C2412_IISMOD_BCLK_16FS;
455 break;
fd5ad654 456
51c6ab13
JB		 457 case 32:
458 div = S3C2412_IISMOD_BCLK_32FS;
459 break;
fd5ad654 460
51c6ab13
JB		 461 case 24:
462 div = S3C2412_IISMOD_BCLK_24FS;
463 break;
fd5ad654 464
51c6ab13
JB		 465 case 48:
466 div = S3C2412_IISMOD_BCLK_48FS;
467 break;
fd5ad654 468
51c6ab13
JB		 469 default:
470 return -EINVAL;
fd5ad654
J		 471 }
472
dc85447b
BD		 473 reg = readl(i2s->regs + S3C2412_IISMOD);
474 reg &= ~S3C2412_IISMOD_BCLK_MASK;
475 writel(reg | div, i2s->regs + S3C2412_IISMOD);
476
ee7d4767 477 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 478 break;
479
480 case S3C_I2SV2_DIV_RCLK:
51c6ab13
JB		 481 switch (div) {
482 case 256:
483 div = S3C2412_IISMOD_RCLK_256FS;
484 break;
dc85447b 485
51c6ab13
JB		 486 case 384:
487 div = S3C2412_IISMOD_RCLK_384FS;
488 break;
dc85447b 489
51c6ab13
JB		 490 case 512:
491 div = S3C2412_IISMOD_RCLK_512FS;
492 break;
dc85447b 493
51c6ab13
JB		 494 case 768:
495 div = S3C2412_IISMOD_RCLK_768FS;
496 break;
dc85447b 497
51c6ab13
JB		 498 default:
499 return -EINVAL;
dc85447b
BD		 500 }
501
502 reg = readl(i2s->regs + S3C2412_IISMOD);
503 reg &= ~S3C2412_IISMOD_RCLK_MASK;
504 writel(reg | div, i2s->regs + S3C2412_IISMOD);
ee7d4767 505 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 506 break;
507
508 case S3C_I2SV2_DIV_PRESCALER:
509 if (div >= 0) {
510 writel((div << 8) | S3C2412_IISPSR_PSREN,
511 i2s->regs + S3C2412_IISPSR);
512 } else {
513 writel(0x0, i2s->regs + S3C2412_IISPSR);
514 }
ee7d4767 515 pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
dc85447b
BD		 516 break;
517
518 default:
519 return -EINVAL;
520 }
521
522 return 0;
523}
524
1ca75780
MB		 525static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream,
526 struct snd_soc_dai *dai)
527{
528 struct s3c_i2sv2_info *i2s = to_info(dai);
529 u32 reg = readl(i2s->regs + S3C2412_IISFIC);
530 snd_pcm_sframes_t delay;
531
532 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
533 delay = S3C2412_IISFIC_TXCOUNT(reg);
534 else
535 delay = S3C2412_IISFIC_RXCOUNT(reg);
536
537 return delay;
538}
539
dc85447b
BD		 540/* default table of all avaialable root fs divisors */
541static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
542
1d2b7ae9
BD		 543int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
544 unsigned int *fstab,
545 unsigned int rate, struct clk *clk)
dc85447b
BD		 546{
547 unsigned long clkrate = clk_get_rate(clk);
548 unsigned int div;
549 unsigned int fsclk;
550 unsigned int actual;
551 unsigned int fs;
552 unsigned int fsdiv;
553 signed int deviation = 0;
554 unsigned int best_fs = 0;
555 unsigned int best_div = 0;
556 unsigned int best_rate = 0;
557 unsigned int best_deviation = INT_MAX;
558
af3ea7bd
MB		 559 pr_debug("Input clock rate %ldHz\n", clkrate);
560
dc85447b
BD		 561 if (fstab == NULL)
562 fstab = iis_fs_tab;
563
564 for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
565 fsdiv = iis_fs_tab[fs];
566
567 fsclk = clkrate / fsdiv;
568 div = fsclk / rate;
569
570 if ((fsclk % rate) > (rate / 2))
571 div++;
572
573 if (div <= 1)
574 continue;
575
576 actual = clkrate / (fsdiv * div);
577 deviation = actual - rate;
578
449bd54d 579 printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
dc85447b
BD		 580 fsdiv, div, actual, deviation);
581
582 deviation = abs(deviation);
583
584 if (deviation < best_deviation) {
585 best_fs = fsdiv;
586 best_div = div;
587 best_rate = actual;
588 best_deviation = deviation;
589 }
590
591 if (deviation == 0)
592 break;
593 }
594
449bd54d 595 printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
dc85447b
BD		 596 best_fs, best_div, best_rate);
597
598 info->fs_div = best_fs;
599 info->clk_div = best_div;
600
601 return 0;
602}
1d2b7ae9 603EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
dc85447b
BD		 604
605int s3c_i2sv2_probe(struct platform_device *pdev,
606 struct snd_soc_dai *dai,
607 struct s3c_i2sv2_info *i2s,
608 unsigned long base)
609{
610 struct device *dev = &pdev->dev;
07736d48 611 unsigned int iismod;
dc85447b
BD		 612
613 i2s->dev = dev;
614
615 /* record our i2s structure for later use in the callbacks */
616 dai->private_data = i2s;
617
c86bde54
MB		 618 if (!base) {
619 struct resource *res = platform_get_resource(pdev,
620 IORESOURCE_MEM,
621 0);
622 if (!res) {
623 dev_err(dev, "Unable to get register resource\n");
624 return -ENXIO;
625 }
626
627 if (!request_mem_region(res->start, resource_size(res),
628 "s3c64xx-i2s-v4")) {
629 dev_err(dev, "Unable to request register region\n");
630 return -EBUSY;
631 }
632
633 base = res->start;
634 }
635
dc85447b
BD		 636 i2s->regs = ioremap(base, 0x100);
637 if (i2s->regs == NULL) {
638 dev_err(dev, "cannot ioremap registers\n");
639 return -ENXIO;
640 }
641
642 i2s->iis_pclk = clk_get(dev, "iis");
fd5ad654 643 if (IS_ERR(i2s->iis_pclk)) {
b52a5195 644 dev_err(dev, "failed to get iis_clock\n");
dc85447b
BD		 645 iounmap(i2s->regs);
646 return -ENOENT;
647 }
648
649 clk_enable(i2s->iis_pclk);
650
07736d48
MB		 651 /* Mark ourselves as in TXRX mode so we can run through our cleanup
652 * process without warnings. */
653 iismod = readl(i2s->regs + S3C2412_IISMOD);
654 iismod |= S3C2412_IISMOD_MODE_TXRX;
655 writel(iismod, i2s->regs + S3C2412_IISMOD);
dc85447b
BD		 656 s3c2412_snd_txctrl(i2s, 0);
657 s3c2412_snd_rxctrl(i2s, 0);
658
659 return 0;
660}
dc85447b
BD		 661EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
662
663#ifdef CONFIG_PM
664static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
665{
666 struct s3c_i2sv2_info *i2s = to_info(dai);
667 u32 iismod;
668
669 if (dai->active) {
670 i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
671 i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
672 i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
673
674 /* some basic suspend checks */
675
676 iismod = readl(i2s->regs + S3C2412_IISMOD);
677
678 if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
679 pr_warning("%s: RXDMA active?\n", __func__);
680
681 if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
682 pr_warning("%s: TXDMA active?\n", __func__);
683
684 if (iismod & S3C2412_IISCON_IIS_ACTIVE)
685 pr_warning("%s: IIS active\n", __func__);
686 }
687
688 return 0;
689}
690
691static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
692{
693 struct s3c_i2sv2_info *i2s = to_info(dai);
694
695 pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
696 dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
697
698 if (dai->active) {
699 writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
700 writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
701 writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
702
703 writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
704 i2s->regs + S3C2412_IISFIC);
705
706 ndelay(250);
707 writel(0x0, i2s->regs + S3C2412_IISFIC);
708 }
709
710 return 0;
711}
712#else
713#define s3c2412_i2s_suspend NULL
714#define s3c2412_i2s_resume NULL
715#endif
716
717int s3c_i2sv2_register_dai(struct snd_soc_dai *dai)
718{
3715c6aa
BD		 719 struct snd_soc_dai_ops *ops = dai->ops;
720
721 ops->trigger = s3c2412_i2s_trigger;
9c9b1257
JB		 722 if (!ops->hw_params)
723 ops->hw_params = s3c_i2sv2_hw_params;
3715c6aa
BD		 724 ops->set_fmt = s3c2412_i2s_set_fmt;
725 ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
dc85447b 726
1ca75780
MB		 727 /* Allow overriding by (for example) IISv4 */
728 if (!ops->delay)
08226614 729 ops->delay = s3c2412_i2s_delay;
1ca75780 730
dc85447b
BD		 731 dai->suspend = s3c2412_i2s_suspend;
732 dai->resume = s3c2412_i2s_resume;
733
734 return snd_soc_register_dai(dai);
735}
dc85447b 736EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai);
a396e32e
MB		 737
738MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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