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ASoC: TWL4030: Capture route runtime DAPM ordering fix
[deliverable/linux.git] / sound / soc / s3c24xx / s3c-i2s-v2.c
CommitLineData
dc85447b
BD		 1/* sound/soc/s3c24xx/s3c-i2c-v2.c
2 *
3 * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
4 *
5 * Copyright (c) 2006 Wolfson Microelectronics PLC.
6 * Graeme Gregory graeme.gregory@wolfsonmicro.com
7 * linux@wolfsonmicro.com
8 *
9 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 * Ben Dooks <ben@simtec.co.uk>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
dc85447b
BD		 19#include <linux/delay.h>
20#include <linux/clk.h>
dc85447b
BD		 21#include <linux/io.h>
22
dc85447b
BD		 23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
dc85447b
BD		 25#include <sound/soc.h>
26
dc85447b
BD		 27#include <mach/dma.h>
28
d07e7ce9 29#include "regs-i2s-v2.h"
dc85447b 30#include "s3c-i2s-v2.h"
d3ff5a3e 31#include "s3c-dma.h"
dc85447b 32
8a0f62b8
MB		 33#undef S3C_IIS_V2_SUPPORTED
34
5c519767
CC		 35#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) \
36 || defined(CONFIG_CPU_S5PV210)
8a0f62b8
MB		 37#define S3C_IIS_V2_SUPPORTED
38#endif
39
40#ifdef CONFIG_PLAT_S3C64XX
41#define S3C_IIS_V2_SUPPORTED
42#endif
43
44#ifndef S3C_IIS_V2_SUPPORTED
45#error Unsupported CPU model
46#endif
47
dc85447b 48#define S3C2412_I2S_DEBUG_CON 0
dc85447b
BD		 49
50static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
51{
52 return cpu_dai->private_data;
53}
54
55#define bit_set(v, b) (((v) & (b)) ? 1 : 0)
56
57#if S3C2412_I2S_DEBUG_CON
58static void dbg_showcon(const char *fn, u32 con)
59{
60 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
61 bit_set(con, S3C2412_IISCON_LRINDEX),
62 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
63 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
64 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
65 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
66
67 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
68 fn,
69 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
70 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
71 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
72 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
73 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
74 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
75 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
76 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
77}
78#else
79static inline void dbg_showcon(const char *fn, u32 con)
80{
81}
82#endif
83
84
85/* Turn on or off the transmission path. */
abbc8246 86static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 87{
88 void __iomem *regs = i2s->regs;
89 u32 fic, con, mod;
90
ee7d4767 91 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 92
93 fic = readl(regs + S3C2412_IISFIC);
94 con = readl(regs + S3C2412_IISCON);
95 mod = readl(regs + S3C2412_IISMOD);
96
ee7d4767 97 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 98
99 if (on) {
100 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
101 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
102 con &= ~S3C2412_IISCON_TXCH_PAUSE;
103
104 switch (mod & S3C2412_IISMOD_MODE_MASK) {
105 case S3C2412_IISMOD_MODE_TXONLY:
106 case S3C2412_IISMOD_MODE_TXRX:
107 /* do nothing, we are in the right mode */
108 break;
109
110 case S3C2412_IISMOD_MODE_RXONLY:
111 mod &= ~S3C2412_IISMOD_MODE_MASK;
112 mod |= S3C2412_IISMOD_MODE_TXRX;
113 break;
114
115 default:
abbc8246
MB		 116 dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
117 mod & S3C2412_IISMOD_MODE_MASK);
118 break;
dc85447b
BD		 119 }
120
121 writel(con, regs + S3C2412_IISCON);
122 writel(mod, regs + S3C2412_IISMOD);
123 } else {
124 /* Note, we do not have any indication that the FIFO problems
125 * tha the S3C2410/2440 had apply here, so we should be able
126 * to disable the DMA and TX without resetting the FIFOS.
127 */
128
129 con |= S3C2412_IISCON_TXDMA_PAUSE;
130 con |= S3C2412_IISCON_TXCH_PAUSE;
131 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
132
133 switch (mod & S3C2412_IISMOD_MODE_MASK) {
134 case S3C2412_IISMOD_MODE_TXRX:
135 mod &= ~S3C2412_IISMOD_MODE_MASK;
136 mod |= S3C2412_IISMOD_MODE_RXONLY;
137 break;
138
139 case S3C2412_IISMOD_MODE_TXONLY:
140 mod &= ~S3C2412_IISMOD_MODE_MASK;
141 con &= ~S3C2412_IISCON_IIS_ACTIVE;
142 break;
143
144 default:
abbc8246
MB		 145 dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
146 mod & S3C2412_IISMOD_MODE_MASK);
147 break;
dc85447b
BD		 148 }
149
150 writel(mod, regs + S3C2412_IISMOD);
151 writel(con, regs + S3C2412_IISCON);
152 }
153
154 fic = readl(regs + S3C2412_IISFIC);
155 dbg_showcon(__func__, con);
ee7d4767 156 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 157}
dc85447b 158
abbc8246 159static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 160{
161 void __iomem *regs = i2s->regs;
162 u32 fic, con, mod;
163
ee7d4767 164 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 165
166 fic = readl(regs + S3C2412_IISFIC);
167 con = readl(regs + S3C2412_IISCON);
168 mod = readl(regs + S3C2412_IISMOD);
169
ee7d4767 170 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 171
172 if (on) {
173 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
174 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
175 con &= ~S3C2412_IISCON_RXCH_PAUSE;
176
177 switch (mod & S3C2412_IISMOD_MODE_MASK) {
178 case S3C2412_IISMOD_MODE_TXRX:
179 case S3C2412_IISMOD_MODE_RXONLY:
180 /* do nothing, we are in the right mode */
181 break;
182
183 case S3C2412_IISMOD_MODE_TXONLY:
184 mod &= ~S3C2412_IISMOD_MODE_MASK;
185 mod |= S3C2412_IISMOD_MODE_TXRX;
186 break;
187
188 default:
abbc8246
MB		 189 dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
190 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 191 }
192
193 writel(mod, regs + S3C2412_IISMOD);
194 writel(con, regs + S3C2412_IISCON);
195 } else {
196 /* See txctrl notes on FIFOs. */
197
198 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
199 con |= S3C2412_IISCON_RXDMA_PAUSE;
200 con |= S3C2412_IISCON_RXCH_PAUSE;
201
202 switch (mod & S3C2412_IISMOD_MODE_MASK) {
203 case S3C2412_IISMOD_MODE_RXONLY:
204 con &= ~S3C2412_IISCON_IIS_ACTIVE;
205 mod &= ~S3C2412_IISMOD_MODE_MASK;
206 break;
207
208 case S3C2412_IISMOD_MODE_TXRX:
209 mod &= ~S3C2412_IISMOD_MODE_MASK;
210 mod |= S3C2412_IISMOD_MODE_TXONLY;
211 break;
212
213 default:
abbc8246
MB		 214 dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
215 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 216 }
217
218 writel(con, regs + S3C2412_IISCON);
219 writel(mod, regs + S3C2412_IISMOD);
220 }
221
222 fic = readl(regs + S3C2412_IISFIC);
ee7d4767 223 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 224}
dc85447b 225
fa68e002
J		 226#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
227
dc85447b
BD		 228/*
229 * Wait for the LR signal to allow synchronisation to the L/R clock
230 * from the codec. May only be needed for slave mode.
231 */
232static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
233{
234 u32 iiscon;
fa68e002 235 unsigned long loops = msecs_to_loops(5);
dc85447b 236
ee7d4767 237 pr_debug("Entered %s\n", __func__);
dc85447b 238
fa68e002 239 while (--loops) {
dc85447b
BD		 240 iiscon = readl(i2s->regs + S3C2412_IISCON);
241 if (iiscon & S3C2412_IISCON_LRINDEX)
242 break;
243
fa68e002
J		 244 cpu_relax();
245 }
246
247 if (!loops) {
248 printk(KERN_ERR "%s: timeout\n", __func__);
249 return -ETIMEDOUT;
dc85447b
BD		 250 }
251
252 return 0;
253}
254
255/*
256 * Set S3C2412 I2S DAI format
257 */
258static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
259 unsigned int fmt)
260{
261 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
262 u32 iismod;
263
ee7d4767 264 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 265
266 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 267 pr_debug("hw_params r: IISMOD: %x \n", iismod);
dc85447b 268
dc85447b
BD		 269 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
270 case SND_SOC_DAIFMT_CBM_CFM:
271 i2s->master = 0;
ce76f9fd 272 iismod |= S3C2412_IISMOD_SLAVE;
dc85447b
BD		 273 break;
274 case SND_SOC_DAIFMT_CBS_CFS:
275 i2s->master = 1;
ce76f9fd 276 iismod &= ~S3C2412_IISMOD_SLAVE;
dc85447b
BD		 277 break;
278 default:
38e43c81 279 pr_err("unknwon master/slave format\n");
dc85447b
BD		 280 return -EINVAL;
281 }
282
283 iismod &= ~S3C2412_IISMOD_SDF_MASK;
284
285 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
286 case SND_SOC_DAIFMT_RIGHT_J:
fd5ad654 287 iismod |= S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 288 iismod |= S3C2412_IISMOD_SDF_MSB;
289 break;
290 case SND_SOC_DAIFMT_LEFT_J:
fd5ad654 291 iismod |= S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 292 iismod |= S3C2412_IISMOD_SDF_LSB;
293 break;
294 case SND_SOC_DAIFMT_I2S:
fd5ad654 295 iismod &= ~S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 296 iismod |= S3C2412_IISMOD_SDF_IIS;
297 break;
298 default:
38e43c81 299 pr_err("Unknown data format\n");
dc85447b
BD		 300 return -EINVAL;
301 }
302
303 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 304 pr_debug("hw_params w: IISMOD: %x \n", iismod);
dc85447b
BD		 305 return 0;
306}
307
9c9b1257 308static int s3c_i2sv2_hw_params(struct snd_pcm_substream *substream,
dc85447b
BD		 309 struct snd_pcm_hw_params *params,
310 struct snd_soc_dai *socdai)
311{
312 struct snd_soc_pcm_runtime *rtd = substream->private_data;
313 struct snd_soc_dai_link *dai = rtd->dai;
314 struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai);
fd23b7de 315 struct s3c_dma_params *dma_data;
dc85447b
BD		 316 u32 iismod;
317
ee7d4767 318 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 319
320 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
fd23b7de 321 dma_data = i2s->dma_playback;
dc85447b 322 else
fd23b7de
DM		 323 dma_data = i2s->dma_capture;
324
325 snd_soc_dai_set_dma_data(dai->cpu_dai, substream, dma_data);
dc85447b
BD		 326
327 /* Working copies of register */
328 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 329 pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
dc85447b 330
bf328826 331 iismod &= ~S3C64XX_IISMOD_BLC_MASK;
553b1dd5
MB		 332 /* Sample size */
333 switch (params_format(params)) {
334 case SNDRV_PCM_FORMAT_S8:
bf328826 335 iismod |= S3C64XX_IISMOD_BLC_8BIT;
553b1dd5
MB		 336 break;
337 case SNDRV_PCM_FORMAT_S16_LE:
553b1dd5
MB		 338 break;
339 case SNDRV_PCM_FORMAT_S24_LE:
bf328826 340 iismod |= S3C64XX_IISMOD_BLC_24BIT;
553b1dd5
MB		 341 break;
342 }
dc85447b
BD		 343
344 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 345 pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
8a7c2518
JB		 346
347 return 0;
348}
349
350static int s3c_i2sv2_set_sysclk(struct snd_soc_dai *cpu_dai,
351 int clk_id, unsigned int freq, int dir)
352{
353 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
354 u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
355
356 pr_debug("Entered %s\n", __func__);
357 pr_debug("%s r: IISMOD: %x\n", __func__, iismod);
358
359 switch (clk_id) {
360 case S3C_I2SV2_CLKSRC_PCLK:
361 iismod &= ~S3C2412_IISMOD_IMS_SYSMUX;
362 break;
363
364 case S3C_I2SV2_CLKSRC_AUDIOBUS:
365 iismod |= S3C2412_IISMOD_IMS_SYSMUX;
366 break;
367
368 case S3C_I2SV2_CLKSRC_CDCLK:
369 /* Error if controller doesn't have the CDCLKCON bit */
370 if (!(i2s->feature & S3C_FEATURE_CDCLKCON))
371 return -EINVAL;
372
373 switch (dir) {
374 case SND_SOC_CLOCK_IN:
375 iismod |= S3C64XX_IISMOD_CDCLKCON;
376 break;
377 case SND_SOC_CLOCK_OUT:
378 iismod &= ~S3C64XX_IISMOD_CDCLKCON;
379 break;
380 default:
381 return -EINVAL;
382 }
383 break;
384
385 default:
386 return -EINVAL;
387 }
388
389 writel(iismod, i2s->regs + S3C2412_IISMOD);
390 pr_debug("%s w: IISMOD: %x\n", __func__, iismod);
391
dc85447b
BD		 392 return 0;
393}
394
395static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
396 struct snd_soc_dai *dai)
397{
398 struct snd_soc_pcm_runtime *rtd = substream->private_data;
399 struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai);
400 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
401 unsigned long irqs;
402 int ret = 0;
fd23b7de
DM		 403 struct s3c_dma_params *dma_data =
404 snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream);
dc85447b 405
ee7d4767 406 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 407
408 switch (cmd) {
409 case SNDRV_PCM_TRIGGER_START:
410 /* On start, ensure that the FIFOs are cleared and reset. */
411
412 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
413 i2s->regs + S3C2412_IISFIC);
414
415 /* clear again, just in case */
416 writel(0x0, i2s->regs + S3C2412_IISFIC);
417
418 case SNDRV_PCM_TRIGGER_RESUME:
419 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
420 if (!i2s->master) {
421 ret = s3c2412_snd_lrsync(i2s);
422 if (ret)
423 goto exit_err;
424 }
425
426 local_irq_save(irqs);
427
428 if (capture)
429 s3c2412_snd_rxctrl(i2s, 1);
430 else
431 s3c2412_snd_txctrl(i2s, 1);
432
433 local_irq_restore(irqs);
faf907c7
SL		 434
435 /*
436 * Load the next buffer to DMA to meet the reqirement
437 * of the auto reload mechanism of S3C24XX.
438 * This call won't bother S3C64XX.
439 */
fd23b7de 440 s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
faf907c7 441
dc85447b
BD		 442 break;
443
444 case SNDRV_PCM_TRIGGER_STOP:
445 case SNDRV_PCM_TRIGGER_SUSPEND:
446 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
447 local_irq_save(irqs);
448
449 if (capture)
450 s3c2412_snd_rxctrl(i2s, 0);
451 else
452 s3c2412_snd_txctrl(i2s, 0);
453
454 local_irq_restore(irqs);
455 break;
456 default:
457 ret = -EINVAL;
458 break;
459 }
460
461exit_err:
462 return ret;
463}
464
465/*
466 * Set S3C2412 Clock dividers
467 */
468static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
469 int div_id, int div)
470{
471 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
472 u32 reg;
473
ee7d4767 474 pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
dc85447b
BD		 475
476 switch (div_id) {
477 case S3C_I2SV2_DIV_BCLK:
51c6ab13
JB		 478 switch (div) {
479 case 16:
480 div = S3C2412_IISMOD_BCLK_16FS;
481 break;
fd5ad654 482
51c6ab13
JB		 483 case 32:
484 div = S3C2412_IISMOD_BCLK_32FS;
485 break;
fd5ad654 486
51c6ab13
JB		 487 case 24:
488 div = S3C2412_IISMOD_BCLK_24FS;
489 break;
fd5ad654 490
51c6ab13
JB		 491 case 48:
492 div = S3C2412_IISMOD_BCLK_48FS;
493 break;
fd5ad654 494
51c6ab13
JB		 495 default:
496 return -EINVAL;
fd5ad654
J		 497 }
498
dc85447b
BD		 499 reg = readl(i2s->regs + S3C2412_IISMOD);
500 reg &= ~S3C2412_IISMOD_BCLK_MASK;
501 writel(reg | div, i2s->regs + S3C2412_IISMOD);
502
ee7d4767 503 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 504 break;
505
506 case S3C_I2SV2_DIV_RCLK:
51c6ab13
JB		 507 switch (div) {
508 case 256:
509 div = S3C2412_IISMOD_RCLK_256FS;
510 break;
dc85447b 511
51c6ab13
JB		 512 case 384:
513 div = S3C2412_IISMOD_RCLK_384FS;
514 break;
dc85447b 515
51c6ab13
JB		 516 case 512:
517 div = S3C2412_IISMOD_RCLK_512FS;
518 break;
dc85447b 519
51c6ab13
JB		 520 case 768:
521 div = S3C2412_IISMOD_RCLK_768FS;
522 break;
dc85447b 523
51c6ab13
JB		 524 default:
525 return -EINVAL;
dc85447b
BD		 526 }
527
528 reg = readl(i2s->regs + S3C2412_IISMOD);
529 reg &= ~S3C2412_IISMOD_RCLK_MASK;
530 writel(reg | div, i2s->regs + S3C2412_IISMOD);
ee7d4767 531 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 532 break;
533
534 case S3C_I2SV2_DIV_PRESCALER:
535 if (div >= 0) {
536 writel((div << 8) | S3C2412_IISPSR_PSREN,
537 i2s->regs + S3C2412_IISPSR);
538 } else {
539 writel(0x0, i2s->regs + S3C2412_IISPSR);
540 }
ee7d4767 541 pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
dc85447b
BD		 542 break;
543
544 default:
545 return -EINVAL;
546 }
547
548 return 0;
549}
550
1ca75780
MB		 551static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream,
552 struct snd_soc_dai *dai)
553{
554 struct s3c_i2sv2_info *i2s = to_info(dai);
555 u32 reg = readl(i2s->regs + S3C2412_IISFIC);
556 snd_pcm_sframes_t delay;
557
558 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
559 delay = S3C2412_IISFIC_TXCOUNT(reg);
560 else
561 delay = S3C2412_IISFIC_RXCOUNT(reg);
562
563 return delay;
564}
565
57282427
JB		 566struct clk *s3c_i2sv2_get_clock(struct snd_soc_dai *cpu_dai)
567{
568 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
569 u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
570
571 if (iismod & S3C2412_IISMOD_IMS_SYSMUX)
572 return i2s->iis_cclk;
573 else
574 return i2s->iis_pclk;
575}
576EXPORT_SYMBOL_GPL(s3c_i2sv2_get_clock);
577
dc85447b
BD		 578/* default table of all avaialable root fs divisors */
579static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
580
1d2b7ae9
BD		 581int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
582 unsigned int *fstab,
583 unsigned int rate, struct clk *clk)
dc85447b
BD		 584{
585 unsigned long clkrate = clk_get_rate(clk);
586 unsigned int div;
587 unsigned int fsclk;
588 unsigned int actual;
589 unsigned int fs;
590 unsigned int fsdiv;
591 signed int deviation = 0;
592 unsigned int best_fs = 0;
593 unsigned int best_div = 0;
594 unsigned int best_rate = 0;
595 unsigned int best_deviation = INT_MAX;
596
af3ea7bd
MB		 597 pr_debug("Input clock rate %ldHz\n", clkrate);
598
dc85447b
BD		 599 if (fstab == NULL)
600 fstab = iis_fs_tab;
601
602 for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
603 fsdiv = iis_fs_tab[fs];
604
605 fsclk = clkrate / fsdiv;
606 div = fsclk / rate;
607
608 if ((fsclk % rate) > (rate / 2))
609 div++;
610
611 if (div <= 1)
612 continue;
613
614 actual = clkrate / (fsdiv * div);
615 deviation = actual - rate;
616
449bd54d 617 printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
dc85447b
BD		 618 fsdiv, div, actual, deviation);
619
620 deviation = abs(deviation);
621
622 if (deviation < best_deviation) {
623 best_fs = fsdiv;
624 best_div = div;
625 best_rate = actual;
626 best_deviation = deviation;
627 }
628
629 if (deviation == 0)
630 break;
631 }
632
449bd54d 633 printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
dc85447b
BD		 634 best_fs, best_div, best_rate);
635
636 info->fs_div = best_fs;
637 info->clk_div = best_div;
638
639 return 0;
640}
1d2b7ae9 641EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
dc85447b
BD		 642
643int s3c_i2sv2_probe(struct platform_device *pdev,
644 struct snd_soc_dai *dai,
645 struct s3c_i2sv2_info *i2s,
646 unsigned long base)
647{
648 struct device *dev = &pdev->dev;
07736d48 649 unsigned int iismod;
dc85447b
BD		 650
651 i2s->dev = dev;
652
653 /* record our i2s structure for later use in the callbacks */
654 dai->private_data = i2s;
655
c86bde54
MB		 656 if (!base) {
657 struct resource *res = platform_get_resource(pdev,
658 IORESOURCE_MEM,
659 0);
660 if (!res) {
661 dev_err(dev, "Unable to get register resource\n");
662 return -ENXIO;
663 }
664
665 if (!request_mem_region(res->start, resource_size(res),
666 "s3c64xx-i2s-v4")) {
667 dev_err(dev, "Unable to request register region\n");
668 return -EBUSY;
669 }
670
671 base = res->start;
672 }
673
dc85447b
BD		 674 i2s->regs = ioremap(base, 0x100);
675 if (i2s->regs == NULL) {
676 dev_err(dev, "cannot ioremap registers\n");
677 return -ENXIO;
678 }
679
680 i2s->iis_pclk = clk_get(dev, "iis");
fd5ad654 681 if (IS_ERR(i2s->iis_pclk)) {
b52a5195 682 dev_err(dev, "failed to get iis_clock\n");
dc85447b
BD		 683 iounmap(i2s->regs);
684 return -ENOENT;
685 }
686
687 clk_enable(i2s->iis_pclk);
688
07736d48
MB		 689 /* Mark ourselves as in TXRX mode so we can run through our cleanup
690 * process without warnings. */
691 iismod = readl(i2s->regs + S3C2412_IISMOD);
692 iismod |= S3C2412_IISMOD_MODE_TXRX;
693 writel(iismod, i2s->regs + S3C2412_IISMOD);
dc85447b
BD		 694 s3c2412_snd_txctrl(i2s, 0);
695 s3c2412_snd_rxctrl(i2s, 0);
696
697 return 0;
698}
dc85447b
BD		 699EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
700
701#ifdef CONFIG_PM
702static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
703{
704 struct s3c_i2sv2_info *i2s = to_info(dai);
705 u32 iismod;
706
707 if (dai->active) {
708 i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
709 i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
710 i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
711
712 /* some basic suspend checks */
713
714 iismod = readl(i2s->regs + S3C2412_IISMOD);
715
716 if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
717 pr_warning("%s: RXDMA active?\n", __func__);
718
719 if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
720 pr_warning("%s: TXDMA active?\n", __func__);
721
722 if (iismod & S3C2412_IISCON_IIS_ACTIVE)
723 pr_warning("%s: IIS active\n", __func__);
724 }
725
726 return 0;
727}
728
729static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
730{
731 struct s3c_i2sv2_info *i2s = to_info(dai);
732
733 pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
734 dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
735
736 if (dai->active) {
737 writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
738 writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
739 writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
740
741 writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
742 i2s->regs + S3C2412_IISFIC);
743
744 ndelay(250);
745 writel(0x0, i2s->regs + S3C2412_IISFIC);
746 }
747
748 return 0;
749}
750#else
751#define s3c2412_i2s_suspend NULL
752#define s3c2412_i2s_resume NULL
753#endif
754
755int s3c_i2sv2_register_dai(struct snd_soc_dai *dai)
756{
3715c6aa
BD		 757 struct snd_soc_dai_ops *ops = dai->ops;
758
759 ops->trigger = s3c2412_i2s_trigger;
9c9b1257
JB		 760 if (!ops->hw_params)
761 ops->hw_params = s3c_i2sv2_hw_params;
3715c6aa
BD		 762 ops->set_fmt = s3c2412_i2s_set_fmt;
763 ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
8a7c2518 764 ops->set_sysclk = s3c_i2sv2_set_sysclk;
dc85447b 765
1ca75780
MB		 766 /* Allow overriding by (for example) IISv4 */
767 if (!ops->delay)
08226614 768 ops->delay = s3c2412_i2s_delay;
1ca75780 769
dc85447b
BD		 770 dai->suspend = s3c2412_i2s_suspend;
771 dai->resume = s3c2412_i2s_resume;
772
773 return snd_soc_register_dai(dai);
774}
dc85447b 775EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai);
a396e32e
MB		 776
777MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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