[deliverable/linux.git] / sound / soc / s3c24xx / s3c-i2s-v2.c

/* sound/soc/s3c24xx/s3c-i2c-v2.c
 *
 * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
 *
 * Copyright (c) 2006 Wolfson Microelectronics PLC.
 *	Graeme Gregory graeme.gregory@wolfsonmicro.com
 *	linux@wolfsonmicro.com
 *
 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include <plat/regs-s3c2412-iis.h>

#include <mach/dma.h>

#include "s3c-i2s-v2.h"
#include "s3c-dma.h"

#undef S3C_IIS_V2_SUPPORTED

#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
#define S3C_IIS_V2_SUPPORTED
#endif

#ifdef CONFIG_PLAT_S3C64XX
#define S3C_IIS_V2_SUPPORTED
#endif

#ifndef S3C_IIS_V2_SUPPORTED
#error Unsupported CPU model
#endif

#define S3C2412_I2S_DEBUG_CON 0

static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
{
	return cpu_dai->private_data;
}

#define bit_set(v, b) (((v) & (b)) ? 1 : 0)

#if S3C2412_I2S_DEBUG_CON
static void dbg_showcon(const char *fn, u32 con)
{
	printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
	       bit_set(con, S3C2412_IISCON_LRINDEX),
	       bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
	       bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
	       bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
	       bit_set(con, S3C2412_IISCON_RXFIFO_FULL));

	printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
	       fn,
	       bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
	       bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
	       bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
	       bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
	printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
	       bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
	       bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
	       bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
}
#else
static inline void dbg_showcon(const char *fn, u32 con)
{
}
#endif


/* Turn on or off the transmission path. */
static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
{
	void __iomem *regs = i2s->regs;
	u32 fic, con, mod;

	pr_debug("%s(%d)\n", __func__, on);

	fic = readl(regs + S3C2412_IISFIC);
	con = readl(regs + S3C2412_IISCON);
	mod = readl(regs + S3C2412_IISMOD);

	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);

	if (on) {
		con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
		con &= ~S3C2412_IISCON_TXDMA_PAUSE;
		con &= ~S3C2412_IISCON_TXCH_PAUSE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_TXONLY:
		case S3C2412_IISMOD_MODE_TXRX:
			/* do nothing, we are in the right mode */
			break;

		case S3C2412_IISMOD_MODE_RXONLY:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_TXRX;
			break;

		default:
			dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
			break;
		}

		writel(con, regs + S3C2412_IISCON);
		writel(mod, regs + S3C2412_IISMOD);
	} else {
		/* Note, we do not have any indication that the FIFO problems
		 * tha the S3C2410/2440 had apply here, so we should be able
		 * to disable the DMA and TX without resetting the FIFOS.
		 */

		con |=  S3C2412_IISCON_TXDMA_PAUSE;
		con |=  S3C2412_IISCON_TXCH_PAUSE;
		con &= ~S3C2412_IISCON_TXDMA_ACTIVE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_TXRX:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_RXONLY;
			break;

		case S3C2412_IISMOD_MODE_TXONLY:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			con &= ~S3C2412_IISCON_IIS_ACTIVE;
			break;

		default:
			dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
			break;
		}

		writel(mod, regs + S3C2412_IISMOD);
		writel(con, regs + S3C2412_IISCON);
	}

	fic = readl(regs + S3C2412_IISFIC);
	dbg_showcon(__func__, con);
	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
}

static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
{
	void __iomem *regs = i2s->regs;
	u32 fic, con, mod;

	pr_debug("%s(%d)\n", __func__, on);

	fic = readl(regs + S3C2412_IISFIC);
	con = readl(regs + S3C2412_IISCON);
	mod = readl(regs + S3C2412_IISMOD);

	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);

	if (on) {
		con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
		con &= ~S3C2412_IISCON_RXDMA_PAUSE;
		con &= ~S3C2412_IISCON_RXCH_PAUSE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_TXRX:
		case S3C2412_IISMOD_MODE_RXONLY:
			/* do nothing, we are in the right mode */
			break;

		case S3C2412_IISMOD_MODE_TXONLY:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_TXRX;
			break;

		default:
			dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
		}

		writel(mod, regs + S3C2412_IISMOD);
		writel(con, regs + S3C2412_IISCON);
	} else {
		/* See txctrl notes on FIFOs. */

		con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
		con |=  S3C2412_IISCON_RXDMA_PAUSE;
		con |=  S3C2412_IISCON_RXCH_PAUSE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_RXONLY:
			con &= ~S3C2412_IISCON_IIS_ACTIVE;
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			break;

		case S3C2412_IISMOD_MODE_TXRX:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_TXONLY;
			break;

		default:
			dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
		}

		writel(con, regs + S3C2412_IISCON);
		writel(mod, regs + S3C2412_IISMOD);
	}

	fic = readl(regs + S3C2412_IISFIC);
	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
}

#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)

/*
 * Wait for the LR signal to allow synchronisation to the L/R clock
 * from the codec. May only be needed for slave mode.
 */
static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
{
	u32 iiscon;
	unsigned long loops = msecs_to_loops(5);

	pr_debug("Entered %s\n", __func__);

	while (--loops) {
		iiscon = readl(i2s->regs + S3C2412_IISCON);
		if (iiscon & S3C2412_IISCON_LRINDEX)
			break;

		cpu_relax();
	}

	if (!loops) {
		printk(KERN_ERR "%s: timeout\n", __func__);
		return -ETIMEDOUT;
	}

	return 0;
}

/*
 * Set S3C2412 I2S DAI format
 */
static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
			       unsigned int fmt)
{
	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iismod = readl(i2s->regs + S3C2412_IISMOD);
	pr_debug("hw_params r: IISMOD: %x \n", iismod);

#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
#define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
#define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
#define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
#endif

#if defined(CONFIG_PLAT_S3C64XX)
/* From Rev1.1 datasheet, we have two master and two slave modes:
 * IMS[11:10]:
 *	00 = master mode, fed from PCLK
 *	01 = master mode, fed from CLKAUDIO
 *	10 = slave mode, using PCLK
 *	11 = slave mode, using I2SCLK
 */
#define IISMOD_MASTER_MASK (1 << 11)
#define IISMOD_SLAVE (1 << 11)
#define IISMOD_MASTER (0 << 11)
#endif

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		i2s->master = 0;
		iismod &= ~IISMOD_MASTER_MASK;
		iismod |= IISMOD_SLAVE;
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
		i2s->master = 1;
		iismod &= ~IISMOD_MASTER_MASK;
		iismod |= IISMOD_MASTER;
		break;
	default:
		pr_err("unknwon master/slave format\n");
		return -EINVAL;
	}

	iismod &= ~S3C2412_IISMOD_SDF_MASK;

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		iismod |= S3C2412_IISMOD_LR_RLOW;
		iismod |= S3C2412_IISMOD_SDF_MSB;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		iismod |= S3C2412_IISMOD_LR_RLOW;
		iismod |= S3C2412_IISMOD_SDF_LSB;
		break;
	case SND_SOC_DAIFMT_I2S:
		iismod &= ~S3C2412_IISMOD_LR_RLOW;
		iismod |= S3C2412_IISMOD_SDF_IIS;
		break;
	default:
		pr_err("Unknown data format\n");
		return -EINVAL;
	}

	writel(iismod, i2s->regs + S3C2412_IISMOD);
	pr_debug("hw_params w: IISMOD: %x \n", iismod);
	return 0;
}

static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *socdai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai_link *dai = rtd->dai;
	struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai);
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		dai->cpu_dai->dma_data = i2s->dma_playback;
	else
		dai->cpu_dai->dma_data = i2s->dma_capture;

	/* Working copies of register */
	iismod = readl(i2s->regs + S3C2412_IISMOD);
	pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);

#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		iismod |= S3C2412_IISMOD_8BIT;
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		iismod &= ~S3C2412_IISMOD_8BIT;
		break;
	}
#endif

#ifdef CONFIG_PLAT_S3C64XX
	iismod &= ~S3C64XX_IISMOD_BLC_MASK;
	/* Sample size */
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		iismod |= S3C64XX_IISMOD_BLC_8BIT;
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		break;
	case SNDRV_PCM_FORMAT_S24_LE:
		iismod |= S3C64XX_IISMOD_BLC_24BIT;
		break;
	}
#endif

	writel(iismod, i2s->regs + S3C2412_IISMOD);
	pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
	return 0;
}

static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai);
	int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
	unsigned long irqs;
	int ret = 0;
	int channel = ((struct s3c_dma_params *)
		  rtd->dai->cpu_dai->dma_data)->channel;

	pr_debug("Entered %s\n", __func__);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
		/* On start, ensure that the FIFOs are cleared and reset. */

		writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
		       i2s->regs + S3C2412_IISFIC);

		/* clear again, just in case */
		writel(0x0, i2s->regs + S3C2412_IISFIC);

	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (!i2s->master) {
			ret = s3c2412_snd_lrsync(i2s);
			if (ret)
				goto exit_err;
		}

		local_irq_save(irqs);

		if (capture)
			s3c2412_snd_rxctrl(i2s, 1);
		else
			s3c2412_snd_txctrl(i2s, 1);

		local_irq_restore(irqs);

		/*
		 * Load the next buffer to DMA to meet the reqirement
		 * of the auto reload mechanism of S3C24XX.
		 * This call won't bother S3C64XX.
		 */
		s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);

		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		local_irq_save(irqs);

		if (capture)
			s3c2412_snd_rxctrl(i2s, 0);
		else
			s3c2412_snd_txctrl(i2s, 0);

		local_irq_restore(irqs);
		break;
	default:
		ret = -EINVAL;
		break;
	}

exit_err:
	return ret;
}

/*
 * Set S3C2412 Clock dividers
 */
static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
				  int div_id, int div)
{
	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	u32 reg;

	pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);

	switch (div_id) {
	case S3C_I2SV2_DIV_BCLK:
		switch (div) {
		case 16:
			div = S3C2412_IISMOD_BCLK_16FS;
			break;

		case 32:
			div = S3C2412_IISMOD_BCLK_32FS;
			break;

		case 24:
			div = S3C2412_IISMOD_BCLK_24FS;
			break;

		case 48:
			div = S3C2412_IISMOD_BCLK_48FS;
			break;

		default:
			return -EINVAL;
		}

		reg = readl(i2s->regs + S3C2412_IISMOD);
		reg &= ~S3C2412_IISMOD_BCLK_MASK;
		writel(reg | div, i2s->regs + S3C2412_IISMOD);

		pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
		break;

	case S3C_I2SV2_DIV_RCLK:
		switch (div) {
		case 256:
			div = S3C2412_IISMOD_RCLK_256FS;
			break;

		case 384:
			div = S3C2412_IISMOD_RCLK_384FS;
			break;

		case 512:
			div = S3C2412_IISMOD_RCLK_512FS;
			break;

		case 768:
			div = S3C2412_IISMOD_RCLK_768FS;
			break;

		default:
			return -EINVAL;
		}

		reg = readl(i2s->regs + S3C2412_IISMOD);
		reg &= ~S3C2412_IISMOD_RCLK_MASK;
		writel(reg | div, i2s->regs + S3C2412_IISMOD);
		pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
		break;

	case S3C_I2SV2_DIV_PRESCALER:
		if (div >= 0) {
			writel((div << 8) | S3C2412_IISPSR_PSREN,
			       i2s->regs + S3C2412_IISPSR);
		} else {
			writel(0x0, i2s->regs + S3C2412_IISPSR);
		}
		pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream,
					   struct snd_soc_dai *dai)
{
	struct s3c_i2sv2_info *i2s = to_info(dai);
	u32 reg = readl(i2s->regs + S3C2412_IISFIC);
	snd_pcm_sframes_t delay;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		delay = S3C2412_IISFIC_TXCOUNT(reg);
	else
		delay = S3C2412_IISFIC_RXCOUNT(reg);

	return delay;
}

/* default table of all avaialable root fs divisors */
static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };

int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
			    unsigned int *fstab,
			    unsigned int rate, struct clk *clk)
{
	unsigned long clkrate = clk_get_rate(clk);
	unsigned int div;
	unsigned int fsclk;
	unsigned int actual;
	unsigned int fs;
	unsigned int fsdiv;
	signed int deviation = 0;
	unsigned int best_fs = 0;
	unsigned int best_div = 0;
	unsigned int best_rate = 0;
	unsigned int best_deviation = INT_MAX;

	pr_debug("Input clock rate %ldHz\n", clkrate);

	if (fstab == NULL)
		fstab = iis_fs_tab;

	for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
		fsdiv = iis_fs_tab[fs];

		fsclk = clkrate / fsdiv;
		div = fsclk / rate;

		if ((fsclk % rate) > (rate / 2))
			div++;

		if (div <= 1)
			continue;

		actual = clkrate / (fsdiv * div);
		deviation = actual - rate;

		printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
		       fsdiv, div, actual, deviation);

		deviation = abs(deviation);

		if (deviation < best_deviation) {
			best_fs = fsdiv;
			best_div = div;
			best_rate = actual;
			best_deviation = deviation;
		}

		if (deviation == 0)
			break;
	}

	printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
	       best_fs, best_div, best_rate);

	info->fs_div = best_fs;
	info->clk_div = best_div;

	return 0;
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);

int s3c_i2sv2_probe(struct platform_device *pdev,
		    struct snd_soc_dai *dai,
		    struct s3c_i2sv2_info *i2s,
		    unsigned long base)
{
	struct device *dev = &pdev->dev;
	unsigned int iismod;

	i2s->dev = dev;

	/* record our i2s structure for later use in the callbacks */
	dai->private_data = i2s;

	if (!base) {
		struct resource *res = platform_get_resource(pdev,
							     IORESOURCE_MEM,
							     0);
		if (!res) {
			dev_err(dev, "Unable to get register resource\n");
			return -ENXIO;
		}

		if (!request_mem_region(res->start, resource_size(res),
					"s3c64xx-i2s-v4")) {
			dev_err(dev, "Unable to request register region\n");
			return -EBUSY;
		}

		base = res->start;
	}

	i2s->regs = ioremap(base, 0x100);
	if (i2s->regs == NULL) {
		dev_err(dev, "cannot ioremap registers\n");
		return -ENXIO;
	}

	i2s->iis_pclk = clk_get(dev, "iis");
	if (IS_ERR(i2s->iis_pclk)) {
		dev_err(dev, "failed to get iis_clock\n");
		iounmap(i2s->regs);
		return -ENOENT;
	}

	clk_enable(i2s->iis_pclk);

	/* Mark ourselves as in TXRX mode so we can run through our cleanup
	 * process without warnings. */
	iismod = readl(i2s->regs + S3C2412_IISMOD);
	iismod |= S3C2412_IISMOD_MODE_TXRX;
	writel(iismod, i2s->regs + S3C2412_IISMOD);
	s3c2412_snd_txctrl(i2s, 0);
	s3c2412_snd_rxctrl(i2s, 0);

	return 0;
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);

#ifdef CONFIG_PM
static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
{
	struct s3c_i2sv2_info *i2s = to_info(dai);
	u32 iismod;

	if (dai->active) {
		i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
		i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
		i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);

		/* some basic suspend checks */

		iismod = readl(i2s->regs + S3C2412_IISMOD);

		if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
			pr_warning("%s: RXDMA active?\n", __func__);

		if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
			pr_warning("%s: TXDMA active?\n", __func__);

		if (iismod & S3C2412_IISCON_IIS_ACTIVE)
			pr_warning("%s: IIS active\n", __func__);
	}

	return 0;
}

static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
{
	struct s3c_i2sv2_info *i2s = to_info(dai);

	pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
		dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);

	if (dai->active) {
		writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
		writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
		writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);

		writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
		       i2s->regs + S3C2412_IISFIC);

		ndelay(250);
		writel(0x0, i2s->regs + S3C2412_IISFIC);
	}

	return 0;
}
#else
#define s3c2412_i2s_suspend NULL
#define s3c2412_i2s_resume  NULL
#endif

int s3c_i2sv2_register_dai(struct snd_soc_dai *dai)
{
	struct snd_soc_dai_ops *ops = dai->ops;

	ops->trigger = s3c2412_i2s_trigger;
	ops->hw_params = s3c2412_i2s_hw_params;
	ops->set_fmt = s3c2412_i2s_set_fmt;
	ops->set_clkdiv = s3c2412_i2s_set_clkdiv;

	/* Allow overriding by (for example) IISv4 */
	if (!ops->delay)
		ops->delay = s3c2412_i2s_delay;

	dai->suspend = s3c2412_i2s_suspend;
	dai->resume = s3c2412_i2s_resume;

	return snd_soc_register_dai(dai);
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai);

MODULE_LICENSE("GPL");
Commit	Line	Data
dc85447b BD	1	/* sound/soc/s3c24xx/s3c-i2c-v2.c
	2	*
	3	* ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
	4	*
	5	* Copyright (c) 2006 Wolfson Microelectronics PLC.
	6	* Graeme Gregory graeme.gregory@wolfsonmicro.com
	7	* linux@wolfsonmicro.com
	8	*
	9	* Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
	10	* http://armlinux.simtec.co.uk/
	11	* Ben Dooks <ben@simtec.co.uk>
	12	*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms of the GNU General Public License as published by the
	15	* Free Software Foundation; either version 2 of the License, or (at your
	16	* option) any later version.
	17	*/
	18
dc85447b BD	19	#include <linux/delay.h>
dc85447b BD	20	#include <linux/clk.h>
dc85447b BD	21	#include <linux/io.h>
dc85447b BD	22
dc85447b BD	23	#include <sound/pcm.h>
dc85447b BD	24	#include <sound/pcm_params.h>
dc85447b BD	25	#include <sound/soc.h>
	26
	27	#include <plat/regs-s3c2412-iis.h>
	28
dc85447b BD	29	#include <mach/dma.h>
	30
	31	#include "s3c-i2s-v2.h"
d3ff5a3e	32	#include "s3c-dma.h"
dc85447b	33
8a0f62b8 MB	34	#undef S3C_IIS_V2_SUPPORTED
	35
	36	#if defined(CONFIG_CPU_S3C2412) \|\| defined(CONFIG_CPU_S3C2413)
	37	#define S3C_IIS_V2_SUPPORTED
	38	#endif
	39
	40	#ifdef CONFIG_PLAT_S3C64XX
	41	#define S3C_IIS_V2_SUPPORTED
	42	#endif
	43
	44	#ifndef S3C_IIS_V2_SUPPORTED
	45	#error Unsupported CPU model
	46	#endif
	47
dc85447b	48	#define S3C2412_I2S_DEBUG_CON 0
dc85447b BD	49
	50	static inline struct s3c_i2sv2_info to_info(struct snd_soc_dai cpu_dai)
	51	{
	52	return cpu_dai->private_data;
	53	}
	54
	55	#define bit_set(v, b) (((v) & (b)) ? 1 : 0)
	56
	57	#if S3C2412_I2S_DEBUG_CON
	58	static void dbg_showcon(const char *fn, u32 con)
	59	{
	60	printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
	61	bit_set(con, S3C2412_IISCON_LRINDEX),
	62	bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
	63	bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
	64	bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
	65	bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
	66
	67	printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
	68	fn,
	69	bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
	70	bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
	71	bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
	72	bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
	73	printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
	74	bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
	75	bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
	76	bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
	77	}
	78	#else
	79	static inline void dbg_showcon(const char *fn, u32 con)
	80	{
	81	}
	82	#endif
	83
	84
	85	/* Turn on or off the transmission path. */
abbc8246	86	static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b BD	87	{
	88	void __iomem *regs = i2s->regs;
	89	u32 fic, con, mod;
	90
ee7d4767	91	pr_debug("%s(%d)\n", __func__, on);
dc85447b BD	92
	93	fic = readl(regs + S3C2412_IISFIC);
	94	con = readl(regs + S3C2412_IISCON);
	95	mod = readl(regs + S3C2412_IISMOD);
	96
ee7d4767	97	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b BD	98
	99	if (on) {
	100	con \|= S3C2412_IISCON_TXDMA_ACTIVE \| S3C2412_IISCON_IIS_ACTIVE;
	101	con &= ~S3C2412_IISCON_TXDMA_PAUSE;
	102	con &= ~S3C2412_IISCON_TXCH_PAUSE;
	103
	104	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	105	case S3C2412_IISMOD_MODE_TXONLY:
	106	case S3C2412_IISMOD_MODE_TXRX:
	107	/* do nothing, we are in the right mode */
	108	break;
	109
	110	case S3C2412_IISMOD_MODE_RXONLY:
	111	mod &= ~S3C2412_IISMOD_MODE_MASK;
	112	mod \|= S3C2412_IISMOD_MODE_TXRX;
	113	break;
	114
	115	default:
abbc8246 MB	116	dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
	117	mod & S3C2412_IISMOD_MODE_MASK);
	118	break;
dc85447b BD	119	}
	120
	121	writel(con, regs + S3C2412_IISCON);
	122	writel(mod, regs + S3C2412_IISMOD);
	123	} else {
	124	/* Note, we do not have any indication that the FIFO problems
	125	* tha the S3C2410/2440 had apply here, so we should be able
	126	* to disable the DMA and TX without resetting the FIFOS.
	127	*/
	128
	129	con \|= S3C2412_IISCON_TXDMA_PAUSE;
	130	con \|= S3C2412_IISCON_TXCH_PAUSE;
	131	con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
	132
	133	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	134	case S3C2412_IISMOD_MODE_TXRX:
	135	mod &= ~S3C2412_IISMOD_MODE_MASK;
	136	mod \|= S3C2412_IISMOD_MODE_RXONLY;
	137	break;
	138
	139	case S3C2412_IISMOD_MODE_TXONLY:
	140	mod &= ~S3C2412_IISMOD_MODE_MASK;
	141	con &= ~S3C2412_IISCON_IIS_ACTIVE;
	142	break;
	143
	144	default:
abbc8246 MB	145	dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
	146	mod & S3C2412_IISMOD_MODE_MASK);
	147	break;
dc85447b BD	148	}
	149
	150	writel(mod, regs + S3C2412_IISMOD);
	151	writel(con, regs + S3C2412_IISCON);
	152	}
	153
	154	fic = readl(regs + S3C2412_IISFIC);
	155	dbg_showcon(__func__, con);
ee7d4767	156	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b	157	}
dc85447b	158
abbc8246	159	static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b BD	160	{
	161	void __iomem *regs = i2s->regs;
	162	u32 fic, con, mod;
	163
ee7d4767	164	pr_debug("%s(%d)\n", __func__, on);
dc85447b BD	165
	166	fic = readl(regs + S3C2412_IISFIC);
	167	con = readl(regs + S3C2412_IISCON);
	168	mod = readl(regs + S3C2412_IISMOD);
	169
ee7d4767	170	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b BD	171
	172	if (on) {
	173	con \|= S3C2412_IISCON_RXDMA_ACTIVE \| S3C2412_IISCON_IIS_ACTIVE;
	174	con &= ~S3C2412_IISCON_RXDMA_PAUSE;
	175	con &= ~S3C2412_IISCON_RXCH_PAUSE;
	176
	177	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	178	case S3C2412_IISMOD_MODE_TXRX:
	179	case S3C2412_IISMOD_MODE_RXONLY:
	180	/* do nothing, we are in the right mode */
	181	break;
	182
	183	case S3C2412_IISMOD_MODE_TXONLY:
	184	mod &= ~S3C2412_IISMOD_MODE_MASK;
	185	mod \|= S3C2412_IISMOD_MODE_TXRX;
	186	break;
	187
	188	default:
abbc8246 MB	189	dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
abbc8246 MB	190	mod & S3C2412_IISMOD_MODE_MASK);
dc85447b BD	191	}
	192
	193	writel(mod, regs + S3C2412_IISMOD);
	194	writel(con, regs + S3C2412_IISCON);
	195	} else {
	196	/* See txctrl notes on FIFOs. */
	197
	198	con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
	199	con \|= S3C2412_IISCON_RXDMA_PAUSE;
	200	con \|= S3C2412_IISCON_RXCH_PAUSE;
	201
	202	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	203	case S3C2412_IISMOD_MODE_RXONLY:
	204	con &= ~S3C2412_IISCON_IIS_ACTIVE;
	205	mod &= ~S3C2412_IISMOD_MODE_MASK;
	206	break;
	207
	208	case S3C2412_IISMOD_MODE_TXRX:
	209	mod &= ~S3C2412_IISMOD_MODE_MASK;
	210	mod \|= S3C2412_IISMOD_MODE_TXONLY;
	211	break;
	212
	213	default:
abbc8246 MB	214	dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
abbc8246 MB	215	mod & S3C2412_IISMOD_MODE_MASK);
dc85447b BD	216	}
	217
	218	writel(con, regs + S3C2412_IISCON);
	219	writel(mod, regs + S3C2412_IISMOD);
	220	}
	221
	222	fic = readl(regs + S3C2412_IISFIC);
ee7d4767	223	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b	224	}
dc85447b	225
fa68e002 J	226	#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
fa68e002 J	227
dc85447b BD	228	/*
	229	* Wait for the LR signal to allow synchronisation to the L/R clock
	230	* from the codec. May only be needed for slave mode.
	231	*/
	232	static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
	233	{
	234	u32 iiscon;
fa68e002	235	unsigned long loops = msecs_to_loops(5);
dc85447b	236
ee7d4767	237	pr_debug("Entered %s\n", __func__);
dc85447b	238
fa68e002	239	while (--loops) {
dc85447b BD	240	iiscon = readl(i2s->regs + S3C2412_IISCON);
	241	if (iiscon & S3C2412_IISCON_LRINDEX)
	242	break;
	243
fa68e002 J	244	cpu_relax();
	245	}
	246
	247	if (!loops) {
	248	printk(KERN_ERR "%s: timeout\n", __func__);
	249	return -ETIMEDOUT;
dc85447b BD	250	}
	251
	252	return 0;
	253	}
	254
	255	/*
	256	* Set S3C2412 I2S DAI format
	257	*/
	258	static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
	259	unsigned int fmt)
	260	{
	261	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	262	u32 iismod;
	263
ee7d4767	264	pr_debug("Entered %s\n", __func__);
dc85447b BD	265
dc85447b BD	266	iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767	267	pr_debug("hw_params r: IISMOD: %x \n", iismod);
dc85447b BD	268
	269	#if defined(CONFIG_CPU_S3C2412) \|\| defined(CONFIG_CPU_S3C2413)
	270	#define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
	271	#define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
	272	#define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
	273	#endif
	274
	275	#if defined(CONFIG_PLAT_S3C64XX)
	276	/* From Rev1.1 datasheet, we have two master and two slave modes:
	277	* IMS[11:10]:
	278	* 00 = master mode, fed from PCLK
	279	* 01 = master mode, fed from CLKAUDIO
	280	* 10 = slave mode, using PCLK
	281	* 11 = slave mode, using I2SCLK
	282	*/
	283	#define IISMOD_MASTER_MASK (1 << 11)
	284	#define IISMOD_SLAVE (1 << 11)
553b1dd5	285	#define IISMOD_MASTER (0 << 11)
dc85447b BD	286	#endif
	287
	288	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	289	case SND_SOC_DAIFMT_CBM_CFM:
	290	i2s->master = 0;
	291	iismod &= ~IISMOD_MASTER_MASK;
	292	iismod \|= IISMOD_SLAVE;
	293	break;
	294	case SND_SOC_DAIFMT_CBS_CFS:
	295	i2s->master = 1;
	296	iismod &= ~IISMOD_MASTER_MASK;
	297	iismod \|= IISMOD_MASTER;
	298	break;
	299	default:
38e43c81	300	pr_err("unknwon master/slave format\n");
dc85447b BD	301	return -EINVAL;
	302	}
	303
	304	iismod &= ~S3C2412_IISMOD_SDF_MASK;
	305
	306	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	307	case SND_SOC_DAIFMT_RIGHT_J:
fd5ad654	308	iismod \|= S3C2412_IISMOD_LR_RLOW;
dc85447b BD	309	iismod \|= S3C2412_IISMOD_SDF_MSB;
	310	break;
	311	case SND_SOC_DAIFMT_LEFT_J:
fd5ad654	312	iismod \|= S3C2412_IISMOD_LR_RLOW;
dc85447b BD	313	iismod \|= S3C2412_IISMOD_SDF_LSB;
	314	break;
	315	case SND_SOC_DAIFMT_I2S:
fd5ad654	316	iismod &= ~S3C2412_IISMOD_LR_RLOW;
dc85447b BD	317	iismod \|= S3C2412_IISMOD_SDF_IIS;
	318	break;
	319	default:
38e43c81	320	pr_err("Unknown data format\n");
dc85447b BD	321	return -EINVAL;
	322	}
	323
	324	writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767	325	pr_debug("hw_params w: IISMOD: %x \n", iismod);
dc85447b BD	326	return 0;
	327	}
	328
	329	static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
	330	struct snd_pcm_hw_params *params,
	331	struct snd_soc_dai *socdai)
	332	{
	333	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	334	struct snd_soc_dai_link *dai = rtd->dai;
	335	struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai);
	336	u32 iismod;
	337
ee7d4767	338	pr_debug("Entered %s\n", __func__);
dc85447b BD	339
	340	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	341	dai->cpu_dai->dma_data = i2s->dma_playback;
	342	else
	343	dai->cpu_dai->dma_data = i2s->dma_capture;
	344
	345	/* Working copies of register */
	346	iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767	347	pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
dc85447b	348
553b1dd5	349	#if defined(CONFIG_CPU_S3C2412) \|\| defined(CONFIG_CPU_S3C2413)
dc85447b BD	350	switch (params_format(params)) {
	351	case SNDRV_PCM_FORMAT_S8:
	352	iismod \|= S3C2412_IISMOD_8BIT;
	353	break;
	354	case SNDRV_PCM_FORMAT_S16_LE:
	355	iismod &= ~S3C2412_IISMOD_8BIT;
	356	break;
	357	}
553b1dd5 MB	358	#endif
	359
	360	#ifdef CONFIG_PLAT_S3C64XX
bf328826	361	iismod &= ~S3C64XX_IISMOD_BLC_MASK;
553b1dd5 MB	362	/* Sample size */
	363	switch (params_format(params)) {
	364	case SNDRV_PCM_FORMAT_S8:
bf328826	365	iismod \|= S3C64XX_IISMOD_BLC_8BIT;
553b1dd5 MB	366	break;
553b1dd5 MB	367	case SNDRV_PCM_FORMAT_S16_LE:
553b1dd5 MB	368	break;
553b1dd5 MB	369	case SNDRV_PCM_FORMAT_S24_LE:
bf328826	370	iismod \|= S3C64XX_IISMOD_BLC_24BIT;
553b1dd5 MB	371	break;
	372	}
	373	#endif
dc85447b BD	374
dc85447b BD	375	writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767	376	pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
dc85447b BD	377	return 0;
	378	}
	379
	380	static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
	381	struct snd_soc_dai *dai)
	382	{
	383	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	384	struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai);
	385	int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
	386	unsigned long irqs;
	387	int ret = 0;
faa31776	388	int channel = ((struct s3c_dma_params *)
faf907c7	389	rtd->dai->cpu_dai->dma_data)->channel;
dc85447b	390
ee7d4767	391	pr_debug("Entered %s\n", __func__);
dc85447b BD	392
	393	switch (cmd) {
	394	case SNDRV_PCM_TRIGGER_START:
	395	/* On start, ensure that the FIFOs are cleared and reset. */
	396
	397	writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
	398	i2s->regs + S3C2412_IISFIC);
	399
	400	/* clear again, just in case */
	401	writel(0x0, i2s->regs + S3C2412_IISFIC);
	402
	403	case SNDRV_PCM_TRIGGER_RESUME:
	404	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	405	if (!i2s->master) {
	406	ret = s3c2412_snd_lrsync(i2s);
	407	if (ret)
	408	goto exit_err;
	409	}
	410
	411	local_irq_save(irqs);
	412
	413	if (capture)
	414	s3c2412_snd_rxctrl(i2s, 1);
	415	else
	416	s3c2412_snd_txctrl(i2s, 1);
	417
	418	local_irq_restore(irqs);
faf907c7 SL	419
	420	/*
	421	* Load the next buffer to DMA to meet the reqirement
	422	* of the auto reload mechanism of S3C24XX.
	423	* This call won't bother S3C64XX.
	424	*/
	425	s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);
	426
dc85447b BD	427	break;
	428
	429	case SNDRV_PCM_TRIGGER_STOP:
	430	case SNDRV_PCM_TRIGGER_SUSPEND:
	431	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	432	local_irq_save(irqs);
	433
	434	if (capture)
	435	s3c2412_snd_rxctrl(i2s, 0);
	436	else
	437	s3c2412_snd_txctrl(i2s, 0);
	438
	439	local_irq_restore(irqs);
	440	break;
	441	default:
	442	ret = -EINVAL;
	443	break;
	444	}
	445
	446	exit_err:
	447	return ret;
	448	}
	449
	450	/*
	451	* Set S3C2412 Clock dividers
	452	*/
	453	static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
	454	int div_id, int div)
	455	{
	456	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	457	u32 reg;
	458
ee7d4767	459	pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
dc85447b BD	460
	461	switch (div_id) {
	462	case S3C_I2SV2_DIV_BCLK:
51c6ab13 JB	463	switch (div) {
	464	case 16:
	465	div = S3C2412_IISMOD_BCLK_16FS;
	466	break;
fd5ad654	467
51c6ab13 JB	468	case 32:
	469	div = S3C2412_IISMOD_BCLK_32FS;
	470	break;
fd5ad654	471
51c6ab13 JB	472	case 24:
	473	div = S3C2412_IISMOD_BCLK_24FS;
	474	break;
fd5ad654	475
51c6ab13 JB	476	case 48:
	477	div = S3C2412_IISMOD_BCLK_48FS;
	478	break;
fd5ad654	479
51c6ab13 JB	480	default:
51c6ab13 JB	481	return -EINVAL;
fd5ad654 J	482	}
fd5ad654 J	483
dc85447b BD	484	reg = readl(i2s->regs + S3C2412_IISMOD);
	485	reg &= ~S3C2412_IISMOD_BCLK_MASK;
	486	writel(reg \| div, i2s->regs + S3C2412_IISMOD);
	487
ee7d4767	488	pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b BD	489	break;
	490
	491	case S3C_I2SV2_DIV_RCLK:
51c6ab13 JB	492	switch (div) {
	493	case 256:
	494	div = S3C2412_IISMOD_RCLK_256FS;
	495	break;
dc85447b	496
51c6ab13 JB	497	case 384:
	498	div = S3C2412_IISMOD_RCLK_384FS;
	499	break;
dc85447b	500
51c6ab13 JB	501	case 512:
	502	div = S3C2412_IISMOD_RCLK_512FS;
	503	break;
dc85447b	504
51c6ab13 JB	505	case 768:
	506	div = S3C2412_IISMOD_RCLK_768FS;
	507	break;
dc85447b	508
51c6ab13 JB	509	default:
51c6ab13 JB	510	return -EINVAL;
dc85447b BD	511	}
	512
	513	reg = readl(i2s->regs + S3C2412_IISMOD);
	514	reg &= ~S3C2412_IISMOD_RCLK_MASK;
	515	writel(reg \| div, i2s->regs + S3C2412_IISMOD);
ee7d4767	516	pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b BD	517	break;
	518
	519	case S3C_I2SV2_DIV_PRESCALER:
	520	if (div >= 0) {
	521	writel((div << 8) \| S3C2412_IISPSR_PSREN,
	522	i2s->regs + S3C2412_IISPSR);
	523	} else {
	524	writel(0x0, i2s->regs + S3C2412_IISPSR);
	525	}
ee7d4767	526	pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
dc85447b BD	527	break;
	528
	529	default:
	530	return -EINVAL;
	531	}
	532
	533	return 0;
	534	}
	535
1ca75780 MB	536	static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream,
	537	struct snd_soc_dai *dai)
	538	{
	539	struct s3c_i2sv2_info *i2s = to_info(dai);
	540	u32 reg = readl(i2s->regs + S3C2412_IISFIC);
	541	snd_pcm_sframes_t delay;
	542
	543	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	544	delay = S3C2412_IISFIC_TXCOUNT(reg);
	545	else
	546	delay = S3C2412_IISFIC_RXCOUNT(reg);
	547
	548	return delay;
	549	}
	550
dc85447b BD	551	/* default table of all avaialable root fs divisors */
	552	static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
	553
1d2b7ae9 BD	554	int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
	555	unsigned int *fstab,
	556	unsigned int rate, struct clk *clk)
dc85447b BD	557	{
	558	unsigned long clkrate = clk_get_rate(clk);
	559	unsigned int div;
	560	unsigned int fsclk;
	561	unsigned int actual;
	562	unsigned int fs;
	563	unsigned int fsdiv;
	564	signed int deviation = 0;
	565	unsigned int best_fs = 0;
	566	unsigned int best_div = 0;
	567	unsigned int best_rate = 0;
	568	unsigned int best_deviation = INT_MAX;
	569
af3ea7bd MB	570	pr_debug("Input clock rate %ldHz\n", clkrate);
af3ea7bd MB	571
dc85447b BD	572	if (fstab == NULL)
	573	fstab = iis_fs_tab;
	574
	575	for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
	576	fsdiv = iis_fs_tab[fs];
	577
	578	fsclk = clkrate / fsdiv;
	579	div = fsclk / rate;
	580
	581	if ((fsclk % rate) > (rate / 2))
	582	div++;
	583
	584	if (div <= 1)
	585	continue;
	586
	587	actual = clkrate / (fsdiv * div);
	588	deviation = actual - rate;
	589
449bd54d	590	printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
dc85447b BD	591	fsdiv, div, actual, deviation);
	592
	593	deviation = abs(deviation);
	594
	595	if (deviation < best_deviation) {
	596	best_fs = fsdiv;
	597	best_div = div;
	598	best_rate = actual;
	599	best_deviation = deviation;
	600	}
	601
	602	if (deviation == 0)
	603	break;
	604	}
	605
449bd54d	606	printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
dc85447b BD	607	best_fs, best_div, best_rate);
	608
	609	info->fs_div = best_fs;
	610	info->clk_div = best_div;
	611
	612	return 0;
	613	}
1d2b7ae9	614	EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
dc85447b BD	615
	616	int s3c_i2sv2_probe(struct platform_device *pdev,
	617	struct snd_soc_dai *dai,
	618	struct s3c_i2sv2_info *i2s,
	619	unsigned long base)
	620	{
	621	struct device *dev = &pdev->dev;
07736d48	622	unsigned int iismod;
dc85447b BD	623
	624	i2s->dev = dev;
	625
	626	/* record our i2s structure for later use in the callbacks */
	627	dai->private_data = i2s;
	628
c86bde54 MB	629	if (!base) {
	630	struct resource *res = platform_get_resource(pdev,
	631	IORESOURCE_MEM,
	632	0);
	633	if (!res) {
	634	dev_err(dev, "Unable to get register resource\n");
	635	return -ENXIO;
	636	}
	637
	638	if (!request_mem_region(res->start, resource_size(res),
	639	"s3c64xx-i2s-v4")) {
	640	dev_err(dev, "Unable to request register region\n");
	641	return -EBUSY;
	642	}
	643
	644	base = res->start;
	645	}
	646
dc85447b BD	647	i2s->regs = ioremap(base, 0x100);
	648	if (i2s->regs == NULL) {
	649	dev_err(dev, "cannot ioremap registers\n");
	650	return -ENXIO;
	651	}
	652
	653	i2s->iis_pclk = clk_get(dev, "iis");
fd5ad654	654	if (IS_ERR(i2s->iis_pclk)) {
b52a5195	655	dev_err(dev, "failed to get iis_clock\n");
dc85447b BD	656	iounmap(i2s->regs);
	657	return -ENOENT;
	658	}
	659
	660	clk_enable(i2s->iis_pclk);
	661
07736d48 MB	662	/* Mark ourselves as in TXRX mode so we can run through our cleanup
	663	* process without warnings. */
	664	iismod = readl(i2s->regs + S3C2412_IISMOD);
	665	iismod \|= S3C2412_IISMOD_MODE_TXRX;
	666	writel(iismod, i2s->regs + S3C2412_IISMOD);
dc85447b BD	667	s3c2412_snd_txctrl(i2s, 0);
	668	s3c2412_snd_rxctrl(i2s, 0);
	669
	670	return 0;
	671	}
dc85447b BD	672	EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
	673
	674	#ifdef CONFIG_PM
	675	static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
	676	{
	677	struct s3c_i2sv2_info *i2s = to_info(dai);
	678	u32 iismod;
	679
	680	if (dai->active) {
	681	i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
	682	i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
	683	i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
	684
	685	/* some basic suspend checks */
	686
	687	iismod = readl(i2s->regs + S3C2412_IISMOD);
	688
	689	if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
	690	pr_warning("%s: RXDMA active?\n", __func__);
	691
	692	if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
	693	pr_warning("%s: TXDMA active?\n", __func__);
	694
	695	if (iismod & S3C2412_IISCON_IIS_ACTIVE)
	696	pr_warning("%s: IIS active\n", __func__);
	697	}
	698
	699	return 0;
	700	}
	701
	702	static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
	703	{
	704	struct s3c_i2sv2_info *i2s = to_info(dai);
	705
	706	pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
	707	dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
	708
	709	if (dai->active) {
	710	writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
	711	writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
	712	writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
	713
	714	writel(S3C2412_IISFIC_RXFLUSH \| S3C2412_IISFIC_TXFLUSH,
	715	i2s->regs + S3C2412_IISFIC);
	716
	717	ndelay(250);
	718	writel(0x0, i2s->regs + S3C2412_IISFIC);
	719	}
	720
	721	return 0;
	722	}
	723	#else
	724	#define s3c2412_i2s_suspend NULL
	725	#define s3c2412_i2s_resume NULL
	726	#endif
	727
	728	int s3c_i2sv2_register_dai(struct snd_soc_dai *dai)
	729	{
3715c6aa BD	730	struct snd_soc_dai_ops *ops = dai->ops;
	731
	732	ops->trigger = s3c2412_i2s_trigger;
	733	ops->hw_params = s3c2412_i2s_hw_params;
	734	ops->set_fmt = s3c2412_i2s_set_fmt;
	735	ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
dc85447b	736
1ca75780 MB	737	/* Allow overriding by (for example) IISv4 */
1ca75780 MB	738	if (!ops->delay)
08226614	739	ops->delay = s3c2412_i2s_delay;
1ca75780	740
dc85447b BD	741	dai->suspend = s3c2412_i2s_suspend;
	742	dai->resume = s3c2412_i2s_resume;
	743
	744	return snd_soc_register_dai(dai);
	745	}
dc85447b	746	EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai);
a396e32e MB	747
a396e32e MB	748	MODULE_LICENSE("GPL");