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ARM: OMAP: McBSP: Merge two functions into omap_mcbsp_start/_stop
[deliverable/linux.git] / sound / soc / s3c24xx / s3c-i2s-v2.c
CommitLineData
dc85447b
BD		 1/* sound/soc/s3c24xx/s3c-i2c-v2.c
2 *
3 * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
4 *
5 * Copyright (c) 2006 Wolfson Microelectronics PLC.
6 * Graeme Gregory graeme.gregory@wolfsonmicro.com
7 * linux@wolfsonmicro.com
8 *
9 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 * Ben Dooks <ben@simtec.co.uk>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/device.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/kernel.h>
25#include <linux/io.h>
26
27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/initval.h>
31#include <sound/soc.h>
32
33#include <plat/regs-s3c2412-iis.h>
34
35#include <plat/audio.h>
36#include <mach/dma.h>
37
38#include "s3c-i2s-v2.h"
39
8a0f62b8
MB		 40#undef S3C_IIS_V2_SUPPORTED
41
42#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
43#define S3C_IIS_V2_SUPPORTED
44#endif
45
46#ifdef CONFIG_PLAT_S3C64XX
47#define S3C_IIS_V2_SUPPORTED
48#endif
49
50#ifndef S3C_IIS_V2_SUPPORTED
51#error Unsupported CPU model
52#endif
53
dc85447b 54#define S3C2412_I2S_DEBUG_CON 0
dc85447b
BD		 55
56static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
57{
58 return cpu_dai->private_data;
59}
60
61#define bit_set(v, b) (((v) & (b)) ? 1 : 0)
62
63#if S3C2412_I2S_DEBUG_CON
64static void dbg_showcon(const char *fn, u32 con)
65{
66 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
67 bit_set(con, S3C2412_IISCON_LRINDEX),
68 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
69 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
70 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
71 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
72
73 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
74 fn,
75 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
76 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
77 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
78 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
79 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
80 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
81 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
82 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
83}
84#else
85static inline void dbg_showcon(const char *fn, u32 con)
86{
87}
88#endif
89
90
91/* Turn on or off the transmission path. */
abbc8246 92static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 93{
94 void __iomem *regs = i2s->regs;
95 u32 fic, con, mod;
96
ee7d4767 97 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 98
99 fic = readl(regs + S3C2412_IISFIC);
100 con = readl(regs + S3C2412_IISCON);
101 mod = readl(regs + S3C2412_IISMOD);
102
ee7d4767 103 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 104
105 if (on) {
106 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
107 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
108 con &= ~S3C2412_IISCON_TXCH_PAUSE;
109
110 switch (mod & S3C2412_IISMOD_MODE_MASK) {
111 case S3C2412_IISMOD_MODE_TXONLY:
112 case S3C2412_IISMOD_MODE_TXRX:
113 /* do nothing, we are in the right mode */
114 break;
115
116 case S3C2412_IISMOD_MODE_RXONLY:
117 mod &= ~S3C2412_IISMOD_MODE_MASK;
118 mod |= S3C2412_IISMOD_MODE_TXRX;
119 break;
120
121 default:
abbc8246
MB		 122 dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
123 mod & S3C2412_IISMOD_MODE_MASK);
124 break;
dc85447b
BD		 125 }
126
127 writel(con, regs + S3C2412_IISCON);
128 writel(mod, regs + S3C2412_IISMOD);
129 } else {
130 /* Note, we do not have any indication that the FIFO problems
131 * tha the S3C2410/2440 had apply here, so we should be able
132 * to disable the DMA and TX without resetting the FIFOS.
133 */
134
135 con |= S3C2412_IISCON_TXDMA_PAUSE;
136 con |= S3C2412_IISCON_TXCH_PAUSE;
137 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
138
139 switch (mod & S3C2412_IISMOD_MODE_MASK) {
140 case S3C2412_IISMOD_MODE_TXRX:
141 mod &= ~S3C2412_IISMOD_MODE_MASK;
142 mod |= S3C2412_IISMOD_MODE_RXONLY;
143 break;
144
145 case S3C2412_IISMOD_MODE_TXONLY:
146 mod &= ~S3C2412_IISMOD_MODE_MASK;
147 con &= ~S3C2412_IISCON_IIS_ACTIVE;
148 break;
149
150 default:
abbc8246
MB		 151 dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
152 mod & S3C2412_IISMOD_MODE_MASK);
153 break;
dc85447b
BD		 154 }
155
156 writel(mod, regs + S3C2412_IISMOD);
157 writel(con, regs + S3C2412_IISCON);
158 }
159
160 fic = readl(regs + S3C2412_IISFIC);
161 dbg_showcon(__func__, con);
ee7d4767 162 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 163}
dc85447b 164
abbc8246 165static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 166{
167 void __iomem *regs = i2s->regs;
168 u32 fic, con, mod;
169
ee7d4767 170 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 171
172 fic = readl(regs + S3C2412_IISFIC);
173 con = readl(regs + S3C2412_IISCON);
174 mod = readl(regs + S3C2412_IISMOD);
175
ee7d4767 176 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 177
178 if (on) {
179 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
180 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
181 con &= ~S3C2412_IISCON_RXCH_PAUSE;
182
183 switch (mod & S3C2412_IISMOD_MODE_MASK) {
184 case S3C2412_IISMOD_MODE_TXRX:
185 case S3C2412_IISMOD_MODE_RXONLY:
186 /* do nothing, we are in the right mode */
187 break;
188
189 case S3C2412_IISMOD_MODE_TXONLY:
190 mod &= ~S3C2412_IISMOD_MODE_MASK;
191 mod |= S3C2412_IISMOD_MODE_TXRX;
192 break;
193
194 default:
abbc8246
MB		 195 dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
196 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 197 }
198
199 writel(mod, regs + S3C2412_IISMOD);
200 writel(con, regs + S3C2412_IISCON);
201 } else {
202 /* See txctrl notes on FIFOs. */
203
204 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
205 con |= S3C2412_IISCON_RXDMA_PAUSE;
206 con |= S3C2412_IISCON_RXCH_PAUSE;
207
208 switch (mod & S3C2412_IISMOD_MODE_MASK) {
209 case S3C2412_IISMOD_MODE_RXONLY:
210 con &= ~S3C2412_IISCON_IIS_ACTIVE;
211 mod &= ~S3C2412_IISMOD_MODE_MASK;
212 break;
213
214 case S3C2412_IISMOD_MODE_TXRX:
215 mod &= ~S3C2412_IISMOD_MODE_MASK;
216 mod |= S3C2412_IISMOD_MODE_TXONLY;
217 break;
218
219 default:
abbc8246
MB		 220 dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
221 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 222 }
223
224 writel(con, regs + S3C2412_IISCON);
225 writel(mod, regs + S3C2412_IISMOD);
226 }
227
228 fic = readl(regs + S3C2412_IISFIC);
ee7d4767 229 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 230}
dc85447b
BD		 231
232/*
233 * Wait for the LR signal to allow synchronisation to the L/R clock
234 * from the codec. May only be needed for slave mode.
235 */
236static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
237{
238 u32 iiscon;
239 unsigned long timeout = jiffies + msecs_to_jiffies(5);
240
ee7d4767 241 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 242
243 while (1) {
244 iiscon = readl(i2s->regs + S3C2412_IISCON);
245 if (iiscon & S3C2412_IISCON_LRINDEX)
246 break;
247
248 if (timeout < jiffies) {
249 printk(KERN_ERR "%s: timeout\n", __func__);
250 return -ETIMEDOUT;
251 }
252 }
253
254 return 0;
255}
256
257/*
258 * Set S3C2412 I2S DAI format
259 */
260static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
261 unsigned int fmt)
262{
263 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
264 u32 iismod;
265
ee7d4767 266 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 267
268 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 269 pr_debug("hw_params r: IISMOD: %x \n", iismod);
dc85447b
BD		 270
271#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
272#define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
273#define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
274#define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
275#endif
276
277#if defined(CONFIG_PLAT_S3C64XX)
278/* From Rev1.1 datasheet, we have two master and two slave modes:
279 * IMS[11:10]:
280 * 00 = master mode, fed from PCLK
281 * 01 = master mode, fed from CLKAUDIO
282 * 10 = slave mode, using PCLK
283 * 11 = slave mode, using I2SCLK
284 */
285#define IISMOD_MASTER_MASK (1 << 11)
286#define IISMOD_SLAVE (1 << 11)
553b1dd5 287#define IISMOD_MASTER (0 << 11)
dc85447b
BD		 288#endif
289
290 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
291 case SND_SOC_DAIFMT_CBM_CFM:
292 i2s->master = 0;
293 iismod &= ~IISMOD_MASTER_MASK;
294 iismod |= IISMOD_SLAVE;
295 break;
296 case SND_SOC_DAIFMT_CBS_CFS:
297 i2s->master = 1;
298 iismod &= ~IISMOD_MASTER_MASK;
299 iismod |= IISMOD_MASTER;
300 break;
301 default:
38e43c81 302 pr_err("unknwon master/slave format\n");
dc85447b
BD		 303 return -EINVAL;
304 }
305
306 iismod &= ~S3C2412_IISMOD_SDF_MASK;
307
308 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
309 case SND_SOC_DAIFMT_RIGHT_J:
310 iismod |= S3C2412_IISMOD_SDF_MSB;
311 break;
312 case SND_SOC_DAIFMT_LEFT_J:
313 iismod |= S3C2412_IISMOD_SDF_LSB;
314 break;
315 case SND_SOC_DAIFMT_I2S:
316 iismod |= S3C2412_IISMOD_SDF_IIS;
317 break;
318 default:
38e43c81 319 pr_err("Unknown data format\n");
dc85447b
BD		 320 return -EINVAL;
321 }
322
323 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 324 pr_debug("hw_params w: IISMOD: %x \n", iismod);
dc85447b
BD		 325 return 0;
326}
327
328static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
329 struct snd_pcm_hw_params *params,
330 struct snd_soc_dai *socdai)
331{
332 struct snd_soc_pcm_runtime *rtd = substream->private_data;
333 struct snd_soc_dai_link *dai = rtd->dai;
334 struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai);
335 u32 iismod;
336
ee7d4767 337 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 338
339 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
340 dai->cpu_dai->dma_data = i2s->dma_playback;
341 else
342 dai->cpu_dai->dma_data = i2s->dma_capture;
343
344 /* Working copies of register */
345 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 346 pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
dc85447b 347
553b1dd5 348#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
dc85447b
BD		 349 switch (params_format(params)) {
350 case SNDRV_PCM_FORMAT_S8:
351 iismod |= S3C2412_IISMOD_8BIT;
352 break;
353 case SNDRV_PCM_FORMAT_S16_LE:
354 iismod &= ~S3C2412_IISMOD_8BIT;
355 break;
356 }
553b1dd5
MB		 357#endif
358
359#ifdef CONFIG_PLAT_S3C64XX
0914b93f 360 iismod &= ~(S3C64XX_IISMOD_BLC_MASK | S3C2412_IISMOD_BCLK_MASK);
553b1dd5
MB		 361 /* Sample size */
362 switch (params_format(params)) {
363 case SNDRV_PCM_FORMAT_S8:
364 /* 8 bit sample, 16fs BCLK */
0914b93f 365 iismod |= (S3C64XX_IISMOD_BLC_8BIT | S3C2412_IISMOD_BCLK_16FS);
553b1dd5
MB		 366 break;
367 case SNDRV_PCM_FORMAT_S16_LE:
368 /* 16 bit sample, 32fs BCLK */
369 break;
370 case SNDRV_PCM_FORMAT_S24_LE:
371 /* 24 bit sample, 48fs BCLK */
0914b93f 372 iismod |= (S3C64XX_IISMOD_BLC_24BIT | S3C2412_IISMOD_BCLK_48FS);
553b1dd5
MB		 373 break;
374 }
375#endif
dc85447b
BD		 376
377 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 378 pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
dc85447b
BD		 379 return 0;
380}
381
382static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
383 struct snd_soc_dai *dai)
384{
385 struct snd_soc_pcm_runtime *rtd = substream->private_data;
386 struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai);
387 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
388 unsigned long irqs;
389 int ret = 0;
390
ee7d4767 391 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 392
393 switch (cmd) {
394 case SNDRV_PCM_TRIGGER_START:
395 /* On start, ensure that the FIFOs are cleared and reset. */
396
397 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
398 i2s->regs + S3C2412_IISFIC);
399
400 /* clear again, just in case */
401 writel(0x0, i2s->regs + S3C2412_IISFIC);
402
403 case SNDRV_PCM_TRIGGER_RESUME:
404 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
405 if (!i2s->master) {
406 ret = s3c2412_snd_lrsync(i2s);
407 if (ret)
408 goto exit_err;
409 }
410
411 local_irq_save(irqs);
412
413 if (capture)
414 s3c2412_snd_rxctrl(i2s, 1);
415 else
416 s3c2412_snd_txctrl(i2s, 1);
417
418 local_irq_restore(irqs);
419 break;
420
421 case SNDRV_PCM_TRIGGER_STOP:
422 case SNDRV_PCM_TRIGGER_SUSPEND:
423 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
424 local_irq_save(irqs);
425
426 if (capture)
427 s3c2412_snd_rxctrl(i2s, 0);
428 else
429 s3c2412_snd_txctrl(i2s, 0);
430
431 local_irq_restore(irqs);
432 break;
433 default:
434 ret = -EINVAL;
435 break;
436 }
437
438exit_err:
439 return ret;
440}
441
442/*
443 * Set S3C2412 Clock dividers
444 */
445static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
446 int div_id, int div)
447{
448 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
449 u32 reg;
450
ee7d4767 451 pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
dc85447b
BD		 452
453 switch (div_id) {
454 case S3C_I2SV2_DIV_BCLK:
455 reg = readl(i2s->regs + S3C2412_IISMOD);
456 reg &= ~S3C2412_IISMOD_BCLK_MASK;
457 writel(reg | div, i2s->regs + S3C2412_IISMOD);
458
ee7d4767 459 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 460 break;
461
462 case S3C_I2SV2_DIV_RCLK:
463 if (div > 3) {
464 /* convert value to bit field */
465
466 switch (div) {
467 case 256:
468 div = S3C2412_IISMOD_RCLK_256FS;
469 break;
470
471 case 384:
472 div = S3C2412_IISMOD_RCLK_384FS;
473 break;
474
475 case 512:
476 div = S3C2412_IISMOD_RCLK_512FS;
477 break;
478
479 case 768:
480 div = S3C2412_IISMOD_RCLK_768FS;
481 break;
482
483 default:
484 return -EINVAL;
485 }
486 }
487
488 reg = readl(i2s->regs + S3C2412_IISMOD);
489 reg &= ~S3C2412_IISMOD_RCLK_MASK;
490 writel(reg | div, i2s->regs + S3C2412_IISMOD);
ee7d4767 491 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 492 break;
493
494 case S3C_I2SV2_DIV_PRESCALER:
495 if (div >= 0) {
496 writel((div << 8) | S3C2412_IISPSR_PSREN,
497 i2s->regs + S3C2412_IISPSR);
498 } else {
499 writel(0x0, i2s->regs + S3C2412_IISPSR);
500 }
ee7d4767 501 pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
dc85447b
BD		 502 break;
503
504 default:
505 return -EINVAL;
506 }
507
508 return 0;
509}
510
511/* default table of all avaialable root fs divisors */
512static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
513
1d2b7ae9
BD		 514int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
515 unsigned int *fstab,
516 unsigned int rate, struct clk *clk)
dc85447b
BD		 517{
518 unsigned long clkrate = clk_get_rate(clk);
519 unsigned int div;
520 unsigned int fsclk;
521 unsigned int actual;
522 unsigned int fs;
523 unsigned int fsdiv;
524 signed int deviation = 0;
525 unsigned int best_fs = 0;
526 unsigned int best_div = 0;
527 unsigned int best_rate = 0;
528 unsigned int best_deviation = INT_MAX;
529
af3ea7bd
MB		 530 pr_debug("Input clock rate %ldHz\n", clkrate);
531
dc85447b
BD		 532 if (fstab == NULL)
533 fstab = iis_fs_tab;
534
535 for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
536 fsdiv = iis_fs_tab[fs];
537
538 fsclk = clkrate / fsdiv;
539 div = fsclk / rate;
540
541 if ((fsclk % rate) > (rate / 2))
542 div++;
543
544 if (div <= 1)
545 continue;
546
547 actual = clkrate / (fsdiv * div);
548 deviation = actual - rate;
549
449bd54d 550 printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
dc85447b
BD		 551 fsdiv, div, actual, deviation);
552
553 deviation = abs(deviation);
554
555 if (deviation < best_deviation) {
556 best_fs = fsdiv;
557 best_div = div;
558 best_rate = actual;
559 best_deviation = deviation;
560 }
561
562 if (deviation == 0)
563 break;
564 }
565
449bd54d 566 printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
dc85447b
BD		 567 best_fs, best_div, best_rate);
568
569 info->fs_div = best_fs;
570 info->clk_div = best_div;
571
572 return 0;
573}
1d2b7ae9 574EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
dc85447b
BD		 575
576int s3c_i2sv2_probe(struct platform_device *pdev,
577 struct snd_soc_dai *dai,
578 struct s3c_i2sv2_info *i2s,
579 unsigned long base)
580{
581 struct device *dev = &pdev->dev;
07736d48 582 unsigned int iismod;
dc85447b
BD		 583
584 i2s->dev = dev;
585
586 /* record our i2s structure for later use in the callbacks */
587 dai->private_data = i2s;
588
c86bde54
MB		 589 if (!base) {
590 struct resource *res = platform_get_resource(pdev,
591 IORESOURCE_MEM,
592 0);
593 if (!res) {
594 dev_err(dev, "Unable to get register resource\n");
595 return -ENXIO;
596 }
597
598 if (!request_mem_region(res->start, resource_size(res),
599 "s3c64xx-i2s-v4")) {
600 dev_err(dev, "Unable to request register region\n");
601 return -EBUSY;
602 }
603
604 base = res->start;
605 }
606
dc85447b
BD		 607 i2s->regs = ioremap(base, 0x100);
608 if (i2s->regs == NULL) {
609 dev_err(dev, "cannot ioremap registers\n");
610 return -ENXIO;
611 }
612
613 i2s->iis_pclk = clk_get(dev, "iis");
614 if (i2s->iis_pclk == NULL) {
b52a5195 615 dev_err(dev, "failed to get iis_clock\n");
dc85447b
BD		 616 iounmap(i2s->regs);
617 return -ENOENT;
618 }
619
620 clk_enable(i2s->iis_pclk);
621
07736d48
MB		 622 /* Mark ourselves as in TXRX mode so we can run through our cleanup
623 * process without warnings. */
624 iismod = readl(i2s->regs + S3C2412_IISMOD);
625 iismod |= S3C2412_IISMOD_MODE_TXRX;
626 writel(iismod, i2s->regs + S3C2412_IISMOD);
dc85447b
BD		 627 s3c2412_snd_txctrl(i2s, 0);
628 s3c2412_snd_rxctrl(i2s, 0);
629
630 return 0;
631}
dc85447b
BD		 632EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
633
634#ifdef CONFIG_PM
635static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
636{
637 struct s3c_i2sv2_info *i2s = to_info(dai);
638 u32 iismod;
639
640 if (dai->active) {
641 i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
642 i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
643 i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
644
645 /* some basic suspend checks */
646
647 iismod = readl(i2s->regs + S3C2412_IISMOD);
648
649 if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
650 pr_warning("%s: RXDMA active?\n", __func__);
651
652 if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
653 pr_warning("%s: TXDMA active?\n", __func__);
654
655 if (iismod & S3C2412_IISCON_IIS_ACTIVE)
656 pr_warning("%s: IIS active\n", __func__);
657 }
658
659 return 0;
660}
661
662static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
663{
664 struct s3c_i2sv2_info *i2s = to_info(dai);
665
666 pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
667 dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
668
669 if (dai->active) {
670 writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
671 writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
672 writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
673
674 writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
675 i2s->regs + S3C2412_IISFIC);
676
677 ndelay(250);
678 writel(0x0, i2s->regs + S3C2412_IISFIC);
679 }
680
681 return 0;
682}
683#else
684#define s3c2412_i2s_suspend NULL
685#define s3c2412_i2s_resume NULL
686#endif
687
688int s3c_i2sv2_register_dai(struct snd_soc_dai *dai)
689{
3715c6aa
BD		 690 struct snd_soc_dai_ops *ops = dai->ops;
691
692 ops->trigger = s3c2412_i2s_trigger;
693 ops->hw_params = s3c2412_i2s_hw_params;
694 ops->set_fmt = s3c2412_i2s_set_fmt;
695 ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
dc85447b
BD		 696
697 dai->suspend = s3c2412_i2s_suspend;
698 dai->resume = s3c2412_i2s_resume;
699
700 return snd_soc_register_dai(dai);
701}
dc85447b 702EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai);
a396e32e
MB		 703
704MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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