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ASoC: S3C64XX: I2S: Move RATE and FMT defines to header
[deliverable/linux.git] / sound / soc / s3c24xx / s3c-i2s-v2.c
CommitLineData
dc85447b
BD		 1/* sound/soc/s3c24xx/s3c-i2c-v2.c
2 *
3 * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
4 *
5 * Copyright (c) 2006 Wolfson Microelectronics PLC.
6 * Graeme Gregory graeme.gregory@wolfsonmicro.com
7 * linux@wolfsonmicro.com
8 *
9 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 * Ben Dooks <ben@simtec.co.uk>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
dc85447b
BD		 19#include <linux/delay.h>
20#include <linux/clk.h>
dc85447b
BD		 21#include <linux/io.h>
22
dc85447b
BD		 23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
dc85447b
BD		 25#include <sound/soc.h>
26
27#include <plat/regs-s3c2412-iis.h>
28
dc85447b
BD		 29#include <mach/dma.h>
30
31#include "s3c-i2s-v2.h"
d3ff5a3e 32#include "s3c-dma.h"
dc85447b 33
8a0f62b8
MB		 34#undef S3C_IIS_V2_SUPPORTED
35
36#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
37#define S3C_IIS_V2_SUPPORTED
38#endif
39
40#ifdef CONFIG_PLAT_S3C64XX
41#define S3C_IIS_V2_SUPPORTED
42#endif
43
44#ifndef S3C_IIS_V2_SUPPORTED
45#error Unsupported CPU model
46#endif
47
dc85447b 48#define S3C2412_I2S_DEBUG_CON 0
dc85447b
BD		 49
50static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
51{
52 return cpu_dai->private_data;
53}
54
55#define bit_set(v, b) (((v) & (b)) ? 1 : 0)
56
57#if S3C2412_I2S_DEBUG_CON
58static void dbg_showcon(const char *fn, u32 con)
59{
60 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
61 bit_set(con, S3C2412_IISCON_LRINDEX),
62 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
63 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
64 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
65 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
66
67 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
68 fn,
69 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
70 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
71 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
72 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
73 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
74 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
75 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
76 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
77}
78#else
79static inline void dbg_showcon(const char *fn, u32 con)
80{
81}
82#endif
83
84
85/* Turn on or off the transmission path. */
abbc8246 86static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 87{
88 void __iomem *regs = i2s->regs;
89 u32 fic, con, mod;
90
ee7d4767 91 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 92
93 fic = readl(regs + S3C2412_IISFIC);
94 con = readl(regs + S3C2412_IISCON);
95 mod = readl(regs + S3C2412_IISMOD);
96
ee7d4767 97 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 98
99 if (on) {
100 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
101 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
102 con &= ~S3C2412_IISCON_TXCH_PAUSE;
103
104 switch (mod & S3C2412_IISMOD_MODE_MASK) {
105 case S3C2412_IISMOD_MODE_TXONLY:
106 case S3C2412_IISMOD_MODE_TXRX:
107 /* do nothing, we are in the right mode */
108 break;
109
110 case S3C2412_IISMOD_MODE_RXONLY:
111 mod &= ~S3C2412_IISMOD_MODE_MASK;
112 mod |= S3C2412_IISMOD_MODE_TXRX;
113 break;
114
115 default:
abbc8246
MB		 116 dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
117 mod & S3C2412_IISMOD_MODE_MASK);
118 break;
dc85447b
BD		 119 }
120
121 writel(con, regs + S3C2412_IISCON);
122 writel(mod, regs + S3C2412_IISMOD);
123 } else {
124 /* Note, we do not have any indication that the FIFO problems
125 * tha the S3C2410/2440 had apply here, so we should be able
126 * to disable the DMA and TX without resetting the FIFOS.
127 */
128
129 con |= S3C2412_IISCON_TXDMA_PAUSE;
130 con |= S3C2412_IISCON_TXCH_PAUSE;
131 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
132
133 switch (mod & S3C2412_IISMOD_MODE_MASK) {
134 case S3C2412_IISMOD_MODE_TXRX:
135 mod &= ~S3C2412_IISMOD_MODE_MASK;
136 mod |= S3C2412_IISMOD_MODE_RXONLY;
137 break;
138
139 case S3C2412_IISMOD_MODE_TXONLY:
140 mod &= ~S3C2412_IISMOD_MODE_MASK;
141 con &= ~S3C2412_IISCON_IIS_ACTIVE;
142 break;
143
144 default:
abbc8246
MB		 145 dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
146 mod & S3C2412_IISMOD_MODE_MASK);
147 break;
dc85447b
BD		 148 }
149
150 writel(mod, regs + S3C2412_IISMOD);
151 writel(con, regs + S3C2412_IISCON);
152 }
153
154 fic = readl(regs + S3C2412_IISFIC);
155 dbg_showcon(__func__, con);
ee7d4767 156 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 157}
dc85447b 158
abbc8246 159static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 160{
161 void __iomem *regs = i2s->regs;
162 u32 fic, con, mod;
163
ee7d4767 164 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 165
166 fic = readl(regs + S3C2412_IISFIC);
167 con = readl(regs + S3C2412_IISCON);
168 mod = readl(regs + S3C2412_IISMOD);
169
ee7d4767 170 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 171
172 if (on) {
173 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
174 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
175 con &= ~S3C2412_IISCON_RXCH_PAUSE;
176
177 switch (mod & S3C2412_IISMOD_MODE_MASK) {
178 case S3C2412_IISMOD_MODE_TXRX:
179 case S3C2412_IISMOD_MODE_RXONLY:
180 /* do nothing, we are in the right mode */
181 break;
182
183 case S3C2412_IISMOD_MODE_TXONLY:
184 mod &= ~S3C2412_IISMOD_MODE_MASK;
185 mod |= S3C2412_IISMOD_MODE_TXRX;
186 break;
187
188 default:
abbc8246
MB		 189 dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
190 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 191 }
192
193 writel(mod, regs + S3C2412_IISMOD);
194 writel(con, regs + S3C2412_IISCON);
195 } else {
196 /* See txctrl notes on FIFOs. */
197
198 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
199 con |= S3C2412_IISCON_RXDMA_PAUSE;
200 con |= S3C2412_IISCON_RXCH_PAUSE;
201
202 switch (mod & S3C2412_IISMOD_MODE_MASK) {
203 case S3C2412_IISMOD_MODE_RXONLY:
204 con &= ~S3C2412_IISCON_IIS_ACTIVE;
205 mod &= ~S3C2412_IISMOD_MODE_MASK;
206 break;
207
208 case S3C2412_IISMOD_MODE_TXRX:
209 mod &= ~S3C2412_IISMOD_MODE_MASK;
210 mod |= S3C2412_IISMOD_MODE_TXONLY;
211 break;
212
213 default:
abbc8246
MB		 214 dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
215 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 216 }
217
218 writel(con, regs + S3C2412_IISCON);
219 writel(mod, regs + S3C2412_IISMOD);
220 }
221
222 fic = readl(regs + S3C2412_IISFIC);
ee7d4767 223 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 224}
dc85447b 225
fa68e002
J		 226#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
227
dc85447b
BD		 228/*
229 * Wait for the LR signal to allow synchronisation to the L/R clock
230 * from the codec. May only be needed for slave mode.
231 */
232static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
233{
234 u32 iiscon;
fa68e002 235 unsigned long loops = msecs_to_loops(5);
dc85447b 236
ee7d4767 237 pr_debug("Entered %s\n", __func__);
dc85447b 238
fa68e002 239 while (--loops) {
dc85447b
BD		 240 iiscon = readl(i2s->regs + S3C2412_IISCON);
241 if (iiscon & S3C2412_IISCON_LRINDEX)
242 break;
243
fa68e002
J		 244 cpu_relax();
245 }
246
247 if (!loops) {
248 printk(KERN_ERR "%s: timeout\n", __func__);
249 return -ETIMEDOUT;
dc85447b
BD		 250 }
251
252 return 0;
253}
254
255/*
256 * Set S3C2412 I2S DAI format
257 */
258static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
259 unsigned int fmt)
260{
261 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
262 u32 iismod;
263
ee7d4767 264 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 265
266 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 267 pr_debug("hw_params r: IISMOD: %x \n", iismod);
dc85447b
BD		 268
269#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
270#define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
271#define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
272#define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
273#endif
274
275#if defined(CONFIG_PLAT_S3C64XX)
276/* From Rev1.1 datasheet, we have two master and two slave modes:
277 * IMS[11:10]:
278 * 00 = master mode, fed from PCLK
279 * 01 = master mode, fed from CLKAUDIO
280 * 10 = slave mode, using PCLK
281 * 11 = slave mode, using I2SCLK
282 */
283#define IISMOD_MASTER_MASK (1 << 11)
284#define IISMOD_SLAVE (1 << 11)
553b1dd5 285#define IISMOD_MASTER (0 << 11)
dc85447b
BD		 286#endif
287
288 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
289 case SND_SOC_DAIFMT_CBM_CFM:
290 i2s->master = 0;
291 iismod &= ~IISMOD_MASTER_MASK;
292 iismod |= IISMOD_SLAVE;
293 break;
294 case SND_SOC_DAIFMT_CBS_CFS:
295 i2s->master = 1;
296 iismod &= ~IISMOD_MASTER_MASK;
297 iismod |= IISMOD_MASTER;
298 break;
299 default:
38e43c81 300 pr_err("unknwon master/slave format\n");
dc85447b
BD		 301 return -EINVAL;
302 }
303
304 iismod &= ~S3C2412_IISMOD_SDF_MASK;
305
306 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
307 case SND_SOC_DAIFMT_RIGHT_J:
fd5ad654 308 iismod |= S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 309 iismod |= S3C2412_IISMOD_SDF_MSB;
310 break;
311 case SND_SOC_DAIFMT_LEFT_J:
fd5ad654 312 iismod |= S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 313 iismod |= S3C2412_IISMOD_SDF_LSB;
314 break;
315 case SND_SOC_DAIFMT_I2S:
fd5ad654 316 iismod &= ~S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 317 iismod |= S3C2412_IISMOD_SDF_IIS;
318 break;
319 default:
38e43c81 320 pr_err("Unknown data format\n");
dc85447b
BD		 321 return -EINVAL;
322 }
323
324 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 325 pr_debug("hw_params w: IISMOD: %x \n", iismod);
dc85447b
BD		 326 return 0;
327}
328
329static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
330 struct snd_pcm_hw_params *params,
331 struct snd_soc_dai *socdai)
332{
333 struct snd_soc_pcm_runtime *rtd = substream->private_data;
334 struct snd_soc_dai_link *dai = rtd->dai;
335 struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai);
336 u32 iismod;
337
ee7d4767 338 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 339
340 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
341 dai->cpu_dai->dma_data = i2s->dma_playback;
342 else
343 dai->cpu_dai->dma_data = i2s->dma_capture;
344
345 /* Working copies of register */
346 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 347 pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
dc85447b 348
553b1dd5 349#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
dc85447b
BD		 350 switch (params_format(params)) {
351 case SNDRV_PCM_FORMAT_S8:
352 iismod |= S3C2412_IISMOD_8BIT;
353 break;
354 case SNDRV_PCM_FORMAT_S16_LE:
355 iismod &= ~S3C2412_IISMOD_8BIT;
356 break;
357 }
553b1dd5
MB		 358#endif
359
360#ifdef CONFIG_PLAT_S3C64XX
0914b93f 361 iismod &= ~(S3C64XX_IISMOD_BLC_MASK | S3C2412_IISMOD_BCLK_MASK);
553b1dd5
MB		 362 /* Sample size */
363 switch (params_format(params)) {
364 case SNDRV_PCM_FORMAT_S8:
365 /* 8 bit sample, 16fs BCLK */
0914b93f 366 iismod |= (S3C64XX_IISMOD_BLC_8BIT | S3C2412_IISMOD_BCLK_16FS);
553b1dd5
MB		 367 break;
368 case SNDRV_PCM_FORMAT_S16_LE:
369 /* 16 bit sample, 32fs BCLK */
370 break;
371 case SNDRV_PCM_FORMAT_S24_LE:
372 /* 24 bit sample, 48fs BCLK */
0914b93f 373 iismod |= (S3C64XX_IISMOD_BLC_24BIT | S3C2412_IISMOD_BCLK_48FS);
553b1dd5
MB		 374 break;
375 }
376#endif
dc85447b
BD		 377
378 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 379 pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
dc85447b
BD		 380 return 0;
381}
382
383static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
384 struct snd_soc_dai *dai)
385{
386 struct snd_soc_pcm_runtime *rtd = substream->private_data;
387 struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai);
388 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
389 unsigned long irqs;
390 int ret = 0;
faa31776 391 int channel = ((struct s3c_dma_params *)
faf907c7 392 rtd->dai->cpu_dai->dma_data)->channel;
dc85447b 393
ee7d4767 394 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 395
396 switch (cmd) {
397 case SNDRV_PCM_TRIGGER_START:
398 /* On start, ensure that the FIFOs are cleared and reset. */
399
400 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
401 i2s->regs + S3C2412_IISFIC);
402
403 /* clear again, just in case */
404 writel(0x0, i2s->regs + S3C2412_IISFIC);
405
406 case SNDRV_PCM_TRIGGER_RESUME:
407 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
408 if (!i2s->master) {
409 ret = s3c2412_snd_lrsync(i2s);
410 if (ret)
411 goto exit_err;
412 }
413
414 local_irq_save(irqs);
415
416 if (capture)
417 s3c2412_snd_rxctrl(i2s, 1);
418 else
419 s3c2412_snd_txctrl(i2s, 1);
420
421 local_irq_restore(irqs);
faf907c7
SL		 422
423 /*
424 * Load the next buffer to DMA to meet the reqirement
425 * of the auto reload mechanism of S3C24XX.
426 * This call won't bother S3C64XX.
427 */
428 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);
429
dc85447b
BD		 430 break;
431
432 case SNDRV_PCM_TRIGGER_STOP:
433 case SNDRV_PCM_TRIGGER_SUSPEND:
434 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
435 local_irq_save(irqs);
436
437 if (capture)
438 s3c2412_snd_rxctrl(i2s, 0);
439 else
440 s3c2412_snd_txctrl(i2s, 0);
441
442 local_irq_restore(irqs);
443 break;
444 default:
445 ret = -EINVAL;
446 break;
447 }
448
449exit_err:
450 return ret;
451}
452
453/*
454 * Set S3C2412 Clock dividers
455 */
456static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
457 int div_id, int div)
458{
459 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
460 u32 reg;
461
ee7d4767 462 pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
dc85447b
BD		 463
464 switch (div_id) {
465 case S3C_I2SV2_DIV_BCLK:
fd5ad654
J		 466 if (div > 3) {
467 /* convert value to bit field */
468
469 switch (div) {
470 case 16:
471 div = S3C2412_IISMOD_BCLK_16FS;
472 break;
473
474 case 32:
475 div = S3C2412_IISMOD_BCLK_32FS;
476 break;
477
478 case 24:
479 div = S3C2412_IISMOD_BCLK_24FS;
480 break;
481
482 case 48:
483 div = S3C2412_IISMOD_BCLK_48FS;
484 break;
485
486 default:
487 return -EINVAL;
488 }
489 }
490
dc85447b
BD		 491 reg = readl(i2s->regs + S3C2412_IISMOD);
492 reg &= ~S3C2412_IISMOD_BCLK_MASK;
493 writel(reg | div, i2s->regs + S3C2412_IISMOD);
494
ee7d4767 495 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 496 break;
497
498 case S3C_I2SV2_DIV_RCLK:
499 if (div > 3) {
500 /* convert value to bit field */
501
502 switch (div) {
503 case 256:
504 div = S3C2412_IISMOD_RCLK_256FS;
505 break;
506
507 case 384:
508 div = S3C2412_IISMOD_RCLK_384FS;
509 break;
510
511 case 512:
512 div = S3C2412_IISMOD_RCLK_512FS;
513 break;
514
515 case 768:
516 div = S3C2412_IISMOD_RCLK_768FS;
517 break;
518
519 default:
520 return -EINVAL;
521 }
522 }
523
524 reg = readl(i2s->regs + S3C2412_IISMOD);
525 reg &= ~S3C2412_IISMOD_RCLK_MASK;
526 writel(reg | div, i2s->regs + S3C2412_IISMOD);
ee7d4767 527 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 528 break;
529
530 case S3C_I2SV2_DIV_PRESCALER:
531 if (div >= 0) {
532 writel((div << 8) | S3C2412_IISPSR_PSREN,
533 i2s->regs + S3C2412_IISPSR);
534 } else {
535 writel(0x0, i2s->regs + S3C2412_IISPSR);
536 }
ee7d4767 537 pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
dc85447b
BD		 538 break;
539
540 default:
541 return -EINVAL;
542 }
543
544 return 0;
545}
546
1ca75780
MB		 547static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream,
548 struct snd_soc_dai *dai)
549{
550 struct s3c_i2sv2_info *i2s = to_info(dai);
551 u32 reg = readl(i2s->regs + S3C2412_IISFIC);
552 snd_pcm_sframes_t delay;
553
554 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
555 delay = S3C2412_IISFIC_TXCOUNT(reg);
556 else
557 delay = S3C2412_IISFIC_RXCOUNT(reg);
558
559 return delay;
560}
561
dc85447b
BD		 562/* default table of all avaialable root fs divisors */
563static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
564
1d2b7ae9
BD		 565int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
566 unsigned int *fstab,
567 unsigned int rate, struct clk *clk)
dc85447b
BD		 568{
569 unsigned long clkrate = clk_get_rate(clk);
570 unsigned int div;
571 unsigned int fsclk;
572 unsigned int actual;
573 unsigned int fs;
574 unsigned int fsdiv;
575 signed int deviation = 0;
576 unsigned int best_fs = 0;
577 unsigned int best_div = 0;
578 unsigned int best_rate = 0;
579 unsigned int best_deviation = INT_MAX;
580
af3ea7bd
MB		 581 pr_debug("Input clock rate %ldHz\n", clkrate);
582
dc85447b
BD		 583 if (fstab == NULL)
584 fstab = iis_fs_tab;
585
586 for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
587 fsdiv = iis_fs_tab[fs];
588
589 fsclk = clkrate / fsdiv;
590 div = fsclk / rate;
591
592 if ((fsclk % rate) > (rate / 2))
593 div++;
594
595 if (div <= 1)
596 continue;
597
598 actual = clkrate / (fsdiv * div);
599 deviation = actual - rate;
600
449bd54d 601 printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
dc85447b
BD		 602 fsdiv, div, actual, deviation);
603
604 deviation = abs(deviation);
605
606 if (deviation < best_deviation) {
607 best_fs = fsdiv;
608 best_div = div;
609 best_rate = actual;
610 best_deviation = deviation;
611 }
612
613 if (deviation == 0)
614 break;
615 }
616
449bd54d 617 printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
dc85447b
BD		 618 best_fs, best_div, best_rate);
619
620 info->fs_div = best_fs;
621 info->clk_div = best_div;
622
623 return 0;
624}
1d2b7ae9 625EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
dc85447b
BD		 626
627int s3c_i2sv2_probe(struct platform_device *pdev,
628 struct snd_soc_dai *dai,
629 struct s3c_i2sv2_info *i2s,
630 unsigned long base)
631{
632 struct device *dev = &pdev->dev;
07736d48 633 unsigned int iismod;
dc85447b
BD		 634
635 i2s->dev = dev;
636
637 /* record our i2s structure for later use in the callbacks */
638 dai->private_data = i2s;
639
c86bde54
MB		 640 if (!base) {
641 struct resource *res = platform_get_resource(pdev,
642 IORESOURCE_MEM,
643 0);
644 if (!res) {
645 dev_err(dev, "Unable to get register resource\n");
646 return -ENXIO;
647 }
648
649 if (!request_mem_region(res->start, resource_size(res),
650 "s3c64xx-i2s-v4")) {
651 dev_err(dev, "Unable to request register region\n");
652 return -EBUSY;
653 }
654
655 base = res->start;
656 }
657
dc85447b
BD		 658 i2s->regs = ioremap(base, 0x100);
659 if (i2s->regs == NULL) {
660 dev_err(dev, "cannot ioremap registers\n");
661 return -ENXIO;
662 }
663
664 i2s->iis_pclk = clk_get(dev, "iis");
fd5ad654 665 if (IS_ERR(i2s->iis_pclk)) {
b52a5195 666 dev_err(dev, "failed to get iis_clock\n");
dc85447b
BD		 667 iounmap(i2s->regs);
668 return -ENOENT;
669 }
670
671 clk_enable(i2s->iis_pclk);
672
07736d48
MB		 673 /* Mark ourselves as in TXRX mode so we can run through our cleanup
674 * process without warnings. */
675 iismod = readl(i2s->regs + S3C2412_IISMOD);
676 iismod |= S3C2412_IISMOD_MODE_TXRX;
677 writel(iismod, i2s->regs + S3C2412_IISMOD);
dc85447b
BD		 678 s3c2412_snd_txctrl(i2s, 0);
679 s3c2412_snd_rxctrl(i2s, 0);
680
681 return 0;
682}
dc85447b
BD		 683EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
684
685#ifdef CONFIG_PM
686static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
687{
688 struct s3c_i2sv2_info *i2s = to_info(dai);
689 u32 iismod;
690
691 if (dai->active) {
692 i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
693 i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
694 i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
695
696 /* some basic suspend checks */
697
698 iismod = readl(i2s->regs + S3C2412_IISMOD);
699
700 if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
701 pr_warning("%s: RXDMA active?\n", __func__);
702
703 if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
704 pr_warning("%s: TXDMA active?\n", __func__);
705
706 if (iismod & S3C2412_IISCON_IIS_ACTIVE)
707 pr_warning("%s: IIS active\n", __func__);
708 }
709
710 return 0;
711}
712
713static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
714{
715 struct s3c_i2sv2_info *i2s = to_info(dai);
716
717 pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
718 dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
719
720 if (dai->active) {
721 writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
722 writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
723 writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
724
725 writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
726 i2s->regs + S3C2412_IISFIC);
727
728 ndelay(250);
729 writel(0x0, i2s->regs + S3C2412_IISFIC);
730 }
731
732 return 0;
733}
734#else
735#define s3c2412_i2s_suspend NULL
736#define s3c2412_i2s_resume NULL
737#endif
738
739int s3c_i2sv2_register_dai(struct snd_soc_dai *dai)
740{
3715c6aa
BD		 741 struct snd_soc_dai_ops *ops = dai->ops;
742
743 ops->trigger = s3c2412_i2s_trigger;
744 ops->hw_params = s3c2412_i2s_hw_params;
745 ops->set_fmt = s3c2412_i2s_set_fmt;
746 ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
dc85447b 747
1ca75780
MB		 748 /* Allow overriding by (for example) IISv4 */
749 if (!ops->delay)
08226614 750 ops->delay = s3c2412_i2s_delay;
1ca75780 751
dc85447b
BD		 752 dai->suspend = s3c2412_i2s_suspend;
753 dai->resume = s3c2412_i2s_resume;
754
755 return snd_soc_register_dai(dai);
756}
dc85447b 757EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai);
a396e32e
MB		 758
759MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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