[deliverable/linux.git] / sound / soc / s3c24xx / s3c2412-i2s.c

/* sound/soc/s3c24xx/s3c2412-i2s.c
 *
 * ALSA Soc Audio Layer - S3C2412 I2S driver
 *
 * Copyright (c) 2006 Wolfson Microelectronics PLC.
 *	Graeme Gregory graeme.gregory@wolfsonmicro.com
 *	linux@wolfsonmicro.com
 *
 * Copyright (c) 2007, 2004-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/io.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <mach/hardware.h>

#include <plat/regs-s3c2412-iis.h>

#include <mach/regs-gpio.h>
#include <mach/dma.h>

#include "s3c-dma.h"
#include "s3c2412-i2s.h"

#define S3C2412_I2S_DEBUG 0

static struct s3c2410_dma_client s3c2412_dma_client_out = {
	.name		= "I2S PCM Stereo out"
};

static struct s3c2410_dma_client s3c2412_dma_client_in = {
	.name		= "I2S PCM Stereo in"
};

static struct s3c_dma_params s3c2412_i2s_pcm_stereo_out = {
	.client		= &s3c2412_dma_client_out,
	.channel	= DMACH_I2S_OUT,
	.dma_addr	= S3C2410_PA_IIS + S3C2412_IISTXD,
	.dma_size	= 4,
};

static struct s3c_dma_params s3c2412_i2s_pcm_stereo_in = {
	.client		= &s3c2412_dma_client_in,
	.channel	= DMACH_I2S_IN,
	.dma_addr	= S3C2410_PA_IIS + S3C2412_IISRXD,
	.dma_size	= 4,
};

static struct s3c_i2sv2_info s3c2412_i2s;

/*
 * Set S3C2412 Clock source
 */
static int s3c2412_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
				  int clk_id, unsigned int freq, int dir)
{
	u32 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD);

	pr_debug("%s(%p, %d, %u, %d)\n", __func__, cpu_dai, clk_id,
	    freq, dir);

	switch (clk_id) {
	case S3C2412_CLKSRC_PCLK:
		s3c2412_i2s.master = 1;
		iismod &= ~S3C2412_IISMOD_MASTER_MASK;
		iismod |= S3C2412_IISMOD_MASTER_INTERNAL;
		break;
	case S3C2412_CLKSRC_I2SCLK:
		s3c2412_i2s.master = 0;
		iismod &= ~S3C2412_IISMOD_MASTER_MASK;
		iismod |= S3C2412_IISMOD_MASTER_EXTERNAL;
		break;
	default:
		return -EINVAL;
	}

	writel(iismod, s3c2412_i2s.regs + S3C2412_IISMOD);
	return 0;
}


struct clk *s3c2412_get_iisclk(void)
{
	return s3c2412_i2s.iis_clk;
}
EXPORT_SYMBOL_GPL(s3c2412_get_iisclk);

static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
{
	return cpu_dai->private_data;
}

static int s3c2412_i2s_probe(struct platform_device *pdev,
			     struct snd_soc_dai *dai)
{
	int ret;

	pr_debug("Entered %s\n", __func__);

	ret = s3c_i2sv2_probe(pdev, dai, &s3c2412_i2s, S3C2410_PA_IIS);
	if (ret)
		return ret;

	s3c2412_i2s.dma_capture = &s3c2412_i2s_pcm_stereo_in;
	s3c2412_i2s.dma_playback = &s3c2412_i2s_pcm_stereo_out;

	s3c2412_i2s.iis_cclk = clk_get(&pdev->dev, "i2sclk");
	if (s3c2412_i2s.iis_cclk == NULL) {
		pr_err("failed to get i2sclk clock\n");
		iounmap(s3c2412_i2s.regs);
		return -ENODEV;
	}

	/* Set MPLL as the source for IIS CLK */

	clk_set_parent(s3c2412_i2s.iis_cclk, clk_get(NULL, "mpll"));
	clk_enable(s3c2412_i2s.iis_cclk);

	s3c2412_i2s.iis_cclk = s3c2412_i2s.iis_pclk;

	/* Configure the I2S pins in correct mode */
	s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
	s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
	s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
	s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
	s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);

	return 0;
}

static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *cpu_dai)
{
	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		cpu_dai->dma_data = i2s->dma_playback;
	else
		cpu_dai->dma_data = i2s->dma_capture;

	iismod = readl(i2s->regs + S3C2412_IISMOD);
	pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		iismod |= S3C2412_IISMOD_8BIT;
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		iismod &= ~S3C2412_IISMOD_8BIT;
		break;
	}

	writel(iismod, i2s->regs + S3C2412_IISMOD);
	pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);

	return 0;
}

#define S3C2412_I2S_RATES \
	(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
	SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
	SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)

static struct snd_soc_dai_ops s3c2412_i2s_dai_ops = {
	.set_sysclk	= s3c2412_i2s_set_sysclk,
	.hw_params	= s3c2412_i2s_hw_params,
};

struct snd_soc_dai s3c2412_i2s_dai = {
	.name		= "s3c2412-i2s",
	.id		= 0,
	.probe		= s3c2412_i2s_probe,
	.playback = {
		.channels_min	= 2,
		.channels_max	= 2,
		.rates		= S3C2412_I2S_RATES,
		.formats	= SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
	},
	.capture = {
		.channels_min	= 2,
		.channels_max	= 2,
		.rates		= S3C2412_I2S_RATES,
		.formats	= SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops = &s3c2412_i2s_dai_ops,
};
EXPORT_SYMBOL_GPL(s3c2412_i2s_dai);

static int __init s3c2412_i2s_init(void)
{
	return  s3c_i2sv2_register_dai(&s3c2412_i2s_dai);
}
module_init(s3c2412_i2s_init);

static void __exit s3c2412_i2s_exit(void)
{
	snd_soc_unregister_dai(&s3c2412_i2s_dai);
}
module_exit(s3c2412_i2s_exit);

/* Module information */
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
MODULE_DESCRIPTION("S3C2412 I2S SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
49646dfa BD	1	/* sound/soc/s3c24xx/s3c2412-i2s.c
	2	*
	3	* ALSA Soc Audio Layer - S3C2412 I2S driver
	4	*
	5	* Copyright (c) 2006 Wolfson Microelectronics PLC.
	6	* Graeme Gregory graeme.gregory@wolfsonmicro.com
	7	* linux@wolfsonmicro.com
	8	*
	9	* Copyright (c) 2007, 2004-2005 Simtec Electronics
	10	* http://armlinux.simtec.co.uk/
	11	* Ben Dooks <ben@simtec.co.uk>
	12	*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms of the GNU General Public License as published by the
	15	* Free Software Foundation; either version 2 of the License, or (at your
	16	* option) any later version.
	17	*/
	18
	19	#include <linux/init.h>
	20	#include <linux/module.h>
	21	#include <linux/device.h>
	22	#include <linux/delay.h>
ec976d6e	23	#include <linux/gpio.h>
49646dfa BD	24	#include <linux/clk.h>
49646dfa BD	25	#include <linux/kernel.h>
8150bc88	26	#include <linux/io.h>
49646dfa BD	27
	28	#include <sound/core.h>
	29	#include <sound/pcm.h>
	30	#include <sound/pcm_params.h>
	31	#include <sound/initval.h>
	32	#include <sound/soc.h>
a09e64fb	33	#include <mach/hardware.h>
49646dfa	34
8150bc88	35	#include <plat/regs-s3c2412-iis.h>
49646dfa	36
76fff368	37	#include <mach/regs-gpio.h>
a09e64fb	38	#include <mach/dma.h>
49646dfa	39
d3ff5a3e	40	#include "s3c-dma.h"
49646dfa BD	41	#include "s3c2412-i2s.h"
	42
	43	#define S3C2412_I2S_DEBUG 0
49646dfa	44
49646dfa BD	45	static struct s3c2410_dma_client s3c2412_dma_client_out = {
	46	.name = "I2S PCM Stereo out"
	47	};
	48
	49	static struct s3c2410_dma_client s3c2412_dma_client_in = {
	50	.name = "I2S PCM Stereo in"
	51	};
	52
faa31776	53	static struct s3c_dma_params s3c2412_i2s_pcm_stereo_out = {
49646dfa BD	54	.client = &s3c2412_dma_client_out,
	55	.channel = DMACH_I2S_OUT,
	56	.dma_addr = S3C2410_PA_IIS + S3C2412_IISTXD,
	57	.dma_size = 4,
	58	};
	59
faa31776	60	static struct s3c_dma_params s3c2412_i2s_pcm_stereo_in = {
49646dfa BD	61	.client = &s3c2412_dma_client_in,
	62	.channel = DMACH_I2S_IN,
	63	.dma_addr = S3C2410_PA_IIS + S3C2412_IISRXD,
	64	.dma_size = 4,
	65	};
	66
dc85447b	67	static struct s3c_i2sv2_info s3c2412_i2s;
49646dfa BD	68
	69	/*
	70	* Set S3C2412 Clock source
	71	*/
1992a6fb	72	static int s3c2412_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
49646dfa BD	73	int clk_id, unsigned int freq, int dir)
	74	{
	75	u32 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
	76
ee7d4767	77	pr_debug("%s(%p, %d, %u, %d)\n", __func__, cpu_dai, clk_id,
49646dfa BD	78	freq, dir);
	79
	80	switch (clk_id) {
	81	case S3C2412_CLKSRC_PCLK:
dc85447b	82	s3c2412_i2s.master = 1;
49646dfa BD	83	iismod &= ~S3C2412_IISMOD_MASTER_MASK;
	84	iismod \|= S3C2412_IISMOD_MASTER_INTERNAL;
	85	break;
	86	case S3C2412_CLKSRC_I2SCLK:
dc85447b	87	s3c2412_i2s.master = 0;
49646dfa BD	88	iismod &= ~S3C2412_IISMOD_MASTER_MASK;
	89	iismod \|= S3C2412_IISMOD_MASTER_EXTERNAL;
	90	break;
	91	default:
	92	return -EINVAL;
	93	}
	94
	95	writel(iismod, s3c2412_i2s.regs + S3C2412_IISMOD);
	96	return 0;
	97	}
	98
49646dfa BD	99
	100	struct clk *s3c2412_get_iisclk(void)
	101	{
	102	return s3c2412_i2s.iis_clk;
	103	}
	104	EXPORT_SYMBOL_GPL(s3c2412_get_iisclk);
	105
9c9b1257 JB	106	static inline struct s3c_i2sv2_info to_info(struct snd_soc_dai cpu_dai)
	107	{
	108	return cpu_dai->private_data;
	109	}
49646dfa	110
bdb92876	111	static int s3c2412_i2s_probe(struct platform_device *pdev,
1992a6fb	112	struct snd_soc_dai *dai)
49646dfa	113	{
dc85447b	114	int ret;
49646dfa	115
ee7d4767	116	pr_debug("Entered %s\n", __func__);
49646dfa	117
dc85447b BD	118	ret = s3c_i2sv2_probe(pdev, dai, &s3c2412_i2s, S3C2410_PA_IIS);
	119	if (ret)
	120	return ret;
49646dfa	121
dc85447b BD	122	s3c2412_i2s.dma_capture = &s3c2412_i2s_pcm_stereo_in;
dc85447b BD	123	s3c2412_i2s.dma_playback = &s3c2412_i2s_pcm_stereo_out;
49646dfa BD	124
	125	s3c2412_i2s.iis_cclk = clk_get(&pdev->dev, "i2sclk");
	126	if (s3c2412_i2s.iis_cclk == NULL) {
008bec39	127	pr_err("failed to get i2sclk clock\n");
49646dfa BD	128	iounmap(s3c2412_i2s.regs);
	129	return -ENODEV;
	130	}
	131
dc85447b	132	/* Set MPLL as the source for IIS CLK */
49646dfa	133
dc85447b	134	clk_set_parent(s3c2412_i2s.iis_cclk, clk_get(NULL, "mpll"));
49646dfa BD	135	clk_enable(s3c2412_i2s.iis_cclk);
49646dfa BD	136
dc85447b	137	s3c2412_i2s.iis_cclk = s3c2412_i2s.iis_pclk;
49646dfa BD	138
	139	/* Configure the I2S pins in correct mode */
	140	s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
	141	s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
	142	s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
	143	s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
	144	s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
	145
6cab2d3d BD	146	return 0;
	147	}
	148
9c9b1257 JB	149	static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
	150	struct snd_pcm_hw_params *params,
	151	struct snd_soc_dai *cpu_dai)
	152	{
	153	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	154	u32 iismod;
	155
	156	pr_debug("Entered %s\n", __func__);
	157
	158	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	159	cpu_dai->dma_data = i2s->dma_playback;
	160	else
	161	cpu_dai->dma_data = i2s->dma_capture;
	162
	163	iismod = readl(i2s->regs + S3C2412_IISMOD);
	164	pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
	165
	166	switch (params_format(params)) {
	167	case SNDRV_PCM_FORMAT_S8:
	168	iismod \|= S3C2412_IISMOD_8BIT;
	169	break;
	170	case SNDRV_PCM_FORMAT_S16_LE:
	171	iismod &= ~S3C2412_IISMOD_8BIT;
	172	break;
	173	}
	174
	175	writel(iismod, i2s->regs + S3C2412_IISMOD);
	176	pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
	177
	178	return 0;
	179	}
	180
49646dfa BD	181	#define S3C2412_I2S_RATES \
	182	(SNDRV_PCM_RATE_8000 \| SNDRV_PCM_RATE_11025 \| SNDRV_PCM_RATE_16000 \| \
	183	SNDRV_PCM_RATE_22050 \| SNDRV_PCM_RATE_32000 \| SNDRV_PCM_RATE_44100 \| \
	184	SNDRV_PCM_RATE_48000 \| SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	185
6335d055	186	static struct snd_soc_dai_ops s3c2412_i2s_dai_ops = {
6335d055	187	.set_sysclk = s3c2412_i2s_set_sysclk,
9c9b1257	188	.hw_params = s3c2412_i2s_hw_params,
6335d055 EM	189	};
6335d055 EM	190
1992a6fb	191	struct snd_soc_dai s3c2412_i2s_dai = {
dc85447b BD	192	.name = "s3c2412-i2s",
	193	.id = 0,
	194	.probe = s3c2412_i2s_probe,
49646dfa BD	195	.playback = {
	196	.channels_min = 2,
	197	.channels_max = 2,
	198	.rates = S3C2412_I2S_RATES,
	199	.formats = SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE,
	200	},
	201	.capture = {
	202	.channels_min = 2,
	203	.channels_max = 2,
	204	.rates = S3C2412_I2S_RATES,
	205	.formats = SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE,
	206	},
6335d055	207	.ops = &s3c2412_i2s_dai_ops,
49646dfa BD	208	};
	209	EXPORT_SYMBOL_GPL(s3c2412_i2s_dai);
	210
c9b3a40f	211	static int __init s3c2412_i2s_init(void)
3f4b783c	212	{
dc85447b	213	return s3c_i2sv2_register_dai(&s3c2412_i2s_dai);
3f4b783c MB	214	}
	215	module_init(s3c2412_i2s_init);
	216
	217	static void __exit s3c2412_i2s_exit(void)
	218	{
	219	snd_soc_unregister_dai(&s3c2412_i2s_dai);
	220	}
	221	module_exit(s3c2412_i2s_exit);
	222
49646dfa BD	223	/* Module information */
	224	MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
	225	MODULE_DESCRIPTION("S3C2412 I2S SoC Interface");
	226	MODULE_LICENSE("GPL");