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49646dfa BD |
1 | /* sound/soc/s3c24xx/s3c2412-i2s.c |
2 | * | |
3 | * ALSA Soc Audio Layer - S3C2412 I2S driver | |
4 | * | |
5 | * Copyright (c) 2006 Wolfson Microelectronics PLC. | |
6 | * Graeme Gregory graeme.gregory@wolfsonmicro.com | |
7 | * linux@wolfsonmicro.com | |
8 | * | |
9 | * Copyright (c) 2007, 2004-2005 Simtec Electronics | |
10 | * http://armlinux.simtec.co.uk/ | |
11 | * Ben Dooks <ben@simtec.co.uk> | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/delay.h> | |
ec976d6e | 23 | #include <linux/gpio.h> |
49646dfa BD |
24 | #include <linux/clk.h> |
25 | #include <linux/kernel.h> | |
8150bc88 | 26 | #include <linux/io.h> |
49646dfa BD |
27 | |
28 | #include <sound/core.h> | |
29 | #include <sound/pcm.h> | |
30 | #include <sound/pcm_params.h> | |
31 | #include <sound/initval.h> | |
32 | #include <sound/soc.h> | |
a09e64fb | 33 | #include <mach/hardware.h> |
49646dfa | 34 | |
76fff368 | 35 | #include <mach/regs-gpio.h> |
a09e64fb | 36 | #include <mach/dma.h> |
49646dfa | 37 | |
d3ff5a3e | 38 | #include "s3c-dma.h" |
d07e7ce9 | 39 | #include "regs-i2s-v2.h" |
49646dfa BD |
40 | #include "s3c2412-i2s.h" |
41 | ||
42 | #define S3C2412_I2S_DEBUG 0 | |
49646dfa | 43 | |
49646dfa BD |
44 | static struct s3c2410_dma_client s3c2412_dma_client_out = { |
45 | .name = "I2S PCM Stereo out" | |
46 | }; | |
47 | ||
48 | static struct s3c2410_dma_client s3c2412_dma_client_in = { | |
49 | .name = "I2S PCM Stereo in" | |
50 | }; | |
51 | ||
faa31776 | 52 | static struct s3c_dma_params s3c2412_i2s_pcm_stereo_out = { |
49646dfa BD |
53 | .client = &s3c2412_dma_client_out, |
54 | .channel = DMACH_I2S_OUT, | |
55 | .dma_addr = S3C2410_PA_IIS + S3C2412_IISTXD, | |
56 | .dma_size = 4, | |
57 | }; | |
58 | ||
faa31776 | 59 | static struct s3c_dma_params s3c2412_i2s_pcm_stereo_in = { |
49646dfa BD |
60 | .client = &s3c2412_dma_client_in, |
61 | .channel = DMACH_I2S_IN, | |
62 | .dma_addr = S3C2410_PA_IIS + S3C2412_IISRXD, | |
63 | .dma_size = 4, | |
64 | }; | |
65 | ||
dc85447b | 66 | static struct s3c_i2sv2_info s3c2412_i2s; |
49646dfa | 67 | |
f0fba2ad | 68 | static int s3c2412_i2s_probe(struct snd_soc_dai *dai) |
49646dfa | 69 | { |
dc85447b | 70 | int ret; |
49646dfa | 71 | |
ee7d4767 | 72 | pr_debug("Entered %s\n", __func__); |
49646dfa | 73 | |
f0fba2ad | 74 | ret = s3c_i2sv2_probe(dai, &s3c2412_i2s, S3C2410_PA_IIS); |
dc85447b BD |
75 | if (ret) |
76 | return ret; | |
49646dfa | 77 | |
dc85447b BD |
78 | s3c2412_i2s.dma_capture = &s3c2412_i2s_pcm_stereo_in; |
79 | s3c2412_i2s.dma_playback = &s3c2412_i2s_pcm_stereo_out; | |
49646dfa | 80 | |
f0fba2ad | 81 | s3c2412_i2s.iis_cclk = clk_get(dai->dev, "i2sclk"); |
49646dfa | 82 | if (s3c2412_i2s.iis_cclk == NULL) { |
008bec39 | 83 | pr_err("failed to get i2sclk clock\n"); |
49646dfa BD |
84 | iounmap(s3c2412_i2s.regs); |
85 | return -ENODEV; | |
86 | } | |
87 | ||
dc85447b | 88 | /* Set MPLL as the source for IIS CLK */ |
49646dfa | 89 | |
dc85447b | 90 | clk_set_parent(s3c2412_i2s.iis_cclk, clk_get(NULL, "mpll")); |
49646dfa BD |
91 | clk_enable(s3c2412_i2s.iis_cclk); |
92 | ||
dc85447b | 93 | s3c2412_i2s.iis_cclk = s3c2412_i2s.iis_pclk; |
49646dfa BD |
94 | |
95 | /* Configure the I2S pins in correct mode */ | |
96 | s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK); | |
97 | s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK); | |
98 | s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK); | |
99 | s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI); | |
100 | s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO); | |
101 | ||
6cab2d3d BD |
102 | return 0; |
103 | } | |
104 | ||
f0fba2ad LG |
105 | static int s3c2412_i2s_remove(struct snd_soc_dai *dai) |
106 | { | |
107 | clk_disable(s3c2412_i2s.iis_cclk); | |
108 | clk_put(s3c2412_i2s.iis_cclk); | |
109 | iounmap(s3c2412_i2s.regs); | |
110 | ||
111 | return 0; | |
112 | } | |
113 | ||
9c9b1257 JB |
114 | static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream, |
115 | struct snd_pcm_hw_params *params, | |
116 | struct snd_soc_dai *cpu_dai) | |
117 | { | |
f0fba2ad | 118 | struct s3c_i2sv2_info *i2s = snd_soc_dai_get_drvdata(cpu_dai); |
fd23b7de | 119 | struct s3c_dma_params *dma_data; |
9c9b1257 JB |
120 | u32 iismod; |
121 | ||
122 | pr_debug("Entered %s\n", __func__); | |
123 | ||
124 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
fd23b7de | 125 | dma_data = i2s->dma_playback; |
9c9b1257 | 126 | else |
fd23b7de DM |
127 | dma_data = i2s->dma_capture; |
128 | ||
129 | snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data); | |
9c9b1257 JB |
130 | |
131 | iismod = readl(i2s->regs + S3C2412_IISMOD); | |
132 | pr_debug("%s: r: IISMOD: %x\n", __func__, iismod); | |
133 | ||
134 | switch (params_format(params)) { | |
135 | case SNDRV_PCM_FORMAT_S8: | |
136 | iismod |= S3C2412_IISMOD_8BIT; | |
137 | break; | |
138 | case SNDRV_PCM_FORMAT_S16_LE: | |
139 | iismod &= ~S3C2412_IISMOD_8BIT; | |
140 | break; | |
141 | } | |
142 | ||
143 | writel(iismod, i2s->regs + S3C2412_IISMOD); | |
144 | pr_debug("%s: w: IISMOD: %x\n", __func__, iismod); | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
49646dfa BD |
149 | #define S3C2412_I2S_RATES \ |
150 | (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \ | |
151 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ | |
152 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) | |
153 | ||
6335d055 | 154 | static struct snd_soc_dai_ops s3c2412_i2s_dai_ops = { |
9c9b1257 | 155 | .hw_params = s3c2412_i2s_hw_params, |
6335d055 EM |
156 | }; |
157 | ||
f0fba2ad | 158 | static struct snd_soc_dai_driver s3c2412_i2s_dai = { |
dc85447b | 159 | .probe = s3c2412_i2s_probe, |
f0fba2ad | 160 | .remove = s3c2412_i2s_remove, |
49646dfa BD |
161 | .playback = { |
162 | .channels_min = 2, | |
163 | .channels_max = 2, | |
164 | .rates = S3C2412_I2S_RATES, | |
165 | .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE, | |
166 | }, | |
167 | .capture = { | |
168 | .channels_min = 2, | |
169 | .channels_max = 2, | |
170 | .rates = S3C2412_I2S_RATES, | |
171 | .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE, | |
172 | }, | |
6335d055 | 173 | .ops = &s3c2412_i2s_dai_ops, |
49646dfa | 174 | }; |
f0fba2ad LG |
175 | |
176 | static __devinit int s3c2412_iis_dev_probe(struct platform_device *pdev) | |
177 | { | |
178 | return snd_soc_register_dai(&pdev->dev, &s3c2412_i2s_dai); | |
179 | } | |
180 | ||
181 | static __devexit int s3c2412_iis_dev_remove(struct platform_device *pdev) | |
182 | { | |
183 | snd_soc_unregister_dai(&pdev->dev); | |
184 | return 0; | |
185 | } | |
186 | ||
187 | static struct platform_driver s3c2412_iis_driver = { | |
188 | .probe = s3c2412_iis_dev_probe, | |
189 | .remove = s3c2412_iis_dev_remove, | |
190 | .driver = { | |
191 | .name = "s3c2412-iis", | |
192 | .owner = THIS_MODULE, | |
193 | }, | |
194 | }; | |
49646dfa | 195 | |
c9b3a40f | 196 | static int __init s3c2412_i2s_init(void) |
3f4b783c | 197 | { |
f0fba2ad | 198 | return platform_driver_register(&s3c2412_iis_driver); |
3f4b783c MB |
199 | } |
200 | module_init(s3c2412_i2s_init); | |
201 | ||
202 | static void __exit s3c2412_i2s_exit(void) | |
203 | { | |
f0fba2ad | 204 | platform_driver_unregister(&s3c2412_iis_driver); |
3f4b783c MB |
205 | } |
206 | module_exit(s3c2412_i2s_exit); | |
207 | ||
49646dfa BD |
208 | /* Module information */ |
209 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
210 | MODULE_DESCRIPTION("S3C2412 I2S SoC Interface"); | |
211 | MODULE_LICENSE("GPL"); |