Commit | Line | Data |
---|---|---|
050f05ea GG |
1 | /* |
2 | * s3c2443-ac97.c -- ALSA Soc Audio Layer | |
3 | * | |
4 | * (c) 2007 Wolfson Microelectronics PLC. | |
5 | * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com | |
6 | * | |
7 | * Copyright (C) 2005, Sean Choi <sh428.choi@samsung.com> | |
8 | * All rights reserved. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * Revision history | |
15 | * 21st Mar 2007 Initial Version | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/wait.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/clk.h> | |
25 | ||
050f05ea GG |
26 | #include <sound/core.h> |
27 | #include <sound/pcm.h> | |
28 | #include <sound/ac97_codec.h> | |
29 | #include <sound/initval.h> | |
30 | #include <sound/soc.h> | |
31 | ||
32 | #include <asm/hardware.h> | |
33 | #include <asm/io.h> | |
1700139a | 34 | #include <asm/plat-s3c/regs-ac97.h> |
050f05ea GG |
35 | #include <asm/arch/regs-gpio.h> |
36 | #include <asm/arch/regs-clock.h> | |
37 | #include <asm/arch/audio.h> | |
38 | #include <asm/dma.h> | |
39 | #include <asm/arch/dma.h> | |
40 | ||
41 | #include "s3c24xx-pcm.h" | |
42 | #include "s3c24xx-ac97.h" | |
43 | ||
44 | struct s3c24xx_ac97_info { | |
45 | void __iomem *regs; | |
46 | struct clk *ac97_clk; | |
47 | }; | |
48 | static struct s3c24xx_ac97_info s3c24xx_ac97; | |
49 | ||
50 | DECLARE_COMPLETION(ac97_completion); | |
51 | static u32 codec_ready; | |
52 | static DECLARE_MUTEX(ac97_mutex); | |
53 | ||
54 | static unsigned short s3c2443_ac97_read(struct snd_ac97 *ac97, | |
55 | unsigned short reg) | |
56 | { | |
57 | u32 ac_glbctrl; | |
58 | u32 ac_codec_cmd; | |
59 | u32 stat, addr, data; | |
60 | ||
61 | down(&ac97_mutex); | |
62 | ||
63 | codec_ready = S3C_AC97_GLBSTAT_CODECREADY; | |
64 | ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); | |
65 | ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg); | |
66 | writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); | |
67 | ||
68 | udelay(50); | |
69 | ||
70 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
71 | ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE; | |
72 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
73 | ||
74 | wait_for_completion(&ac97_completion); | |
75 | ||
76 | stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT); | |
77 | addr = (stat >> 16) & 0x7f; | |
78 | data = (stat & 0xffff); | |
79 | ||
80 | if (addr != reg) | |
81 | printk(KERN_ERR "s3c24xx-ac97: req addr = %02x," | |
82 | " rep addr = %02x\n", reg, addr); | |
83 | ||
84 | up(&ac97_mutex); | |
85 | ||
86 | return (unsigned short)data; | |
87 | } | |
88 | ||
89 | static void s3c2443_ac97_write(struct snd_ac97 *ac97, unsigned short reg, | |
90 | unsigned short val) | |
91 | { | |
92 | u32 ac_glbctrl; | |
93 | u32 ac_codec_cmd; | |
94 | ||
95 | down(&ac97_mutex); | |
96 | ||
97 | codec_ready = S3C_AC97_GLBSTAT_CODECREADY; | |
98 | ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); | |
99 | ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val); | |
100 | writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); | |
101 | ||
102 | udelay(50); | |
103 | ||
104 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
105 | ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE; | |
106 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
107 | ||
108 | wait_for_completion(&ac97_completion); | |
109 | ||
110 | ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); | |
111 | ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ; | |
112 | writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); | |
113 | ||
114 | up(&ac97_mutex); | |
115 | ||
116 | } | |
117 | ||
118 | static void s3c2443_ac97_warm_reset(struct snd_ac97 *ac97) | |
119 | { | |
120 | u32 ac_glbctrl; | |
121 | ||
122 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
123 | ac_glbctrl = S3C_AC97_GLBCTRL_WARMRESET; | |
124 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
125 | msleep(1); | |
126 | ||
127 | ac_glbctrl = 0; | |
128 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
129 | msleep(1); | |
130 | } | |
131 | ||
132 | static void s3c2443_ac97_cold_reset(struct snd_ac97 *ac97) | |
133 | { | |
134 | u32 ac_glbctrl; | |
135 | ||
136 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
137 | ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET; | |
138 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
139 | msleep(1); | |
140 | ||
141 | ac_glbctrl = 0; | |
142 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
143 | msleep(1); | |
144 | ||
145 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
146 | ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON; | |
147 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
148 | msleep(1); | |
149 | ||
150 | ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE; | |
151 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
152 | msleep(1); | |
153 | ||
154 | ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA | | |
155 | S3C_AC97_GLBCTRL_PCMINTM_DMA | S3C_AC97_GLBCTRL_MICINTM_DMA; | |
156 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
157 | } | |
158 | ||
159 | static irqreturn_t s3c2443_ac97_irq(int irq, void *dev_id) | |
160 | { | |
161 | int status; | |
162 | u32 ac_glbctrl; | |
163 | ||
164 | status = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT) & codec_ready; | |
165 | ||
166 | if (status) { | |
167 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
168 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE; | |
169 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
170 | complete(&ac97_completion); | |
171 | } | |
172 | return IRQ_HANDLED; | |
173 | } | |
174 | ||
175 | struct snd_ac97_bus_ops soc_ac97_ops = { | |
176 | .read = s3c2443_ac97_read, | |
177 | .write = s3c2443_ac97_write, | |
178 | .warm_reset = s3c2443_ac97_warm_reset, | |
179 | .reset = s3c2443_ac97_cold_reset, | |
180 | }; | |
181 | ||
182 | static struct s3c2410_dma_client s3c2443_dma_client_out = { | |
183 | .name = "AC97 PCM Stereo out" | |
184 | }; | |
185 | ||
186 | static struct s3c2410_dma_client s3c2443_dma_client_in = { | |
187 | .name = "AC97 PCM Stereo in" | |
188 | }; | |
189 | ||
190 | static struct s3c2410_dma_client s3c2443_dma_client_micin = { | |
191 | .name = "AC97 Mic Mono in" | |
192 | }; | |
193 | ||
194 | static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_out = { | |
195 | .client = &s3c2443_dma_client_out, | |
196 | .channel = DMACH_PCM_OUT, | |
197 | .dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA, | |
198 | .dma_size = 4, | |
199 | }; | |
200 | ||
201 | static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_in = { | |
202 | .client = &s3c2443_dma_client_in, | |
203 | .channel = DMACH_PCM_IN, | |
204 | .dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA, | |
205 | .dma_size = 4, | |
206 | }; | |
207 | ||
208 | static struct s3c24xx_pcm_dma_params s3c2443_ac97_mic_mono_in = { | |
209 | .client = &s3c2443_dma_client_micin, | |
210 | .channel = DMACH_MIC_IN, | |
211 | .dma_addr = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA, | |
212 | .dma_size = 4, | |
213 | }; | |
214 | ||
215 | static int s3c2443_ac97_probe(struct platform_device *pdev) | |
216 | { | |
217 | int ret; | |
218 | u32 ac_glbctrl; | |
219 | ||
220 | s3c24xx_ac97.regs = ioremap(S3C2440_PA_AC97, 0x100); | |
221 | if (s3c24xx_ac97.regs == NULL) | |
222 | return -ENXIO; | |
223 | ||
224 | s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97"); | |
225 | if (s3c24xx_ac97.ac97_clk == NULL) { | |
226 | printk(KERN_ERR "s3c2443-ac97 failed to get ac97_clock\n"); | |
227 | iounmap(s3c24xx_ac97.regs); | |
228 | return -ENODEV; | |
229 | } | |
230 | clk_enable(s3c24xx_ac97.ac97_clk); | |
231 | ||
232 | s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2443_GPE0_AC_nRESET); | |
233 | s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2443_GPE1_AC_SYNC); | |
234 | s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2443_GPE2_AC_BITCLK); | |
235 | s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2443_GPE3_AC_SDI); | |
236 | s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2443_GPE4_AC_SDO); | |
237 | ||
238 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
239 | ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET; | |
240 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
241 | msleep(1); | |
242 | ||
243 | ac_glbctrl = 0; | |
244 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
245 | msleep(1); | |
246 | ||
247 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
248 | ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON; | |
249 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
250 | msleep(1); | |
251 | ||
252 | ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE; | |
253 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
254 | ||
040956fa | 255 | ret = request_irq(IRQ_S3C244x_AC97, s3c2443_ac97_irq, |
050f05ea GG |
256 | IRQF_DISABLED, "AC97", NULL); |
257 | if (ret < 0) { | |
258 | printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n"); | |
259 | clk_disable(s3c24xx_ac97.ac97_clk); | |
260 | clk_put(s3c24xx_ac97.ac97_clk); | |
261 | iounmap(s3c24xx_ac97.regs); | |
262 | } | |
263 | return ret; | |
264 | } | |
265 | ||
266 | static void s3c2443_ac97_remove(struct platform_device *pdev) | |
267 | { | |
040956fa | 268 | free_irq(IRQ_S3C244x_AC97, NULL); |
050f05ea GG |
269 | clk_disable(s3c24xx_ac97.ac97_clk); |
270 | clk_put(s3c24xx_ac97.ac97_clk); | |
271 | iounmap(s3c24xx_ac97.regs); | |
272 | } | |
273 | ||
274 | static int s3c2443_ac97_hw_params(struct snd_pcm_substream *substream, | |
275 | struct snd_pcm_hw_params *params) | |
276 | { | |
277 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
278 | struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; | |
279 | ||
280 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
281 | cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_out; | |
282 | else | |
283 | cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_in; | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
288 | static int s3c2443_ac97_trigger(struct snd_pcm_substream *substream, int cmd) | |
289 | { | |
290 | u32 ac_glbctrl; | |
291 | ||
292 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
293 | switch(cmd) { | |
294 | case SNDRV_PCM_TRIGGER_START: | |
295 | case SNDRV_PCM_TRIGGER_RESUME: | |
296 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
297 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
298 | ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA; | |
299 | else | |
300 | ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA; | |
301 | break; | |
302 | case SNDRV_PCM_TRIGGER_STOP: | |
303 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
304 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
305 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
306 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK; | |
307 | else | |
308 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK; | |
309 | break; | |
310 | } | |
311 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
316 | static int s3c2443_ac97_hw_mic_params(struct snd_pcm_substream *substream, | |
317 | struct snd_pcm_hw_params *params) | |
318 | { | |
319 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
320 | struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; | |
321 | ||
322 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
323 | return -ENODEV; | |
324 | else | |
325 | cpu_dai->dma_data = &s3c2443_ac97_mic_mono_in; | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
330 | static int s3c2443_ac97_mic_trigger(struct snd_pcm_substream *substream, | |
331 | int cmd) | |
332 | { | |
333 | u32 ac_glbctrl; | |
334 | ||
335 | ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
336 | switch(cmd) { | |
337 | case SNDRV_PCM_TRIGGER_START: | |
338 | case SNDRV_PCM_TRIGGER_RESUME: | |
339 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
340 | ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA; | |
341 | break; | |
342 | case SNDRV_PCM_TRIGGER_STOP: | |
343 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
344 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
345 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK; | |
346 | } | |
347 | writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
352 | #define s3c2443_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ | |
353 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ | |
354 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) | |
355 | ||
356 | struct snd_soc_cpu_dai s3c2443_ac97_dai[] = { | |
357 | { | |
358 | .name = "s3c2443-ac97", | |
359 | .id = 0, | |
360 | .type = SND_SOC_DAI_AC97, | |
361 | .probe = s3c2443_ac97_probe, | |
362 | .remove = s3c2443_ac97_remove, | |
363 | .playback = { | |
364 | .stream_name = "AC97 Playback", | |
365 | .channels_min = 2, | |
366 | .channels_max = 2, | |
367 | .rates = s3c2443_AC97_RATES, | |
368 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
369 | .capture = { | |
370 | .stream_name = "AC97 Capture", | |
371 | .channels_min = 2, | |
372 | .channels_max = 2, | |
373 | .rates = s3c2443_AC97_RATES, | |
374 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
375 | .ops = { | |
376 | .hw_params = s3c2443_ac97_hw_params, | |
377 | .trigger = s3c2443_ac97_trigger}, | |
378 | }, | |
379 | { | |
380 | .name = "pxa2xx-ac97-mic", | |
381 | .id = 1, | |
382 | .type = SND_SOC_DAI_AC97, | |
383 | .capture = { | |
384 | .stream_name = "AC97 Mic Capture", | |
385 | .channels_min = 1, | |
386 | .channels_max = 1, | |
387 | .rates = s3c2443_AC97_RATES, | |
388 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
389 | .ops = { | |
390 | .hw_params = s3c2443_ac97_hw_mic_params, | |
391 | .trigger = s3c2443_ac97_mic_trigger,}, | |
392 | }, | |
393 | }; | |
394 | ||
395 | EXPORT_SYMBOL_GPL(s3c2443_ac97_dai); | |
396 | EXPORT_SYMBOL_GPL(soc_ac97_ops); | |
397 | ||
398 | MODULE_AUTHOR("Graeme Gregory"); | |
399 | MODULE_DESCRIPTION("AC97 driver for the Samsung s3c2443 chip"); | |
400 | MODULE_LICENSE("GPL"); |