[deliverable/linux.git] / sound / soc / s3c24xx / s3c2443-ac97.c

/*
 * s3c2443-ac97.c  --  ALSA Soc Audio Layer
 *
 * (c) 2007 Wolfson Microelectronics PLC.
 * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
 *
 *  Copyright (C) 2005, Sean Choi <sh428.choi@samsung.com>
 *  All rights reserved.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/wait.h>
#include <linux/delay.h>
#include <linux/clk.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include <mach/hardware.h>
#include <asm/plat-s3c/regs-ac97.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
#include <mach/audio.h>
#include <asm/dma.h>
#include <mach/dma.h>

#include "s3c24xx-pcm.h"
#include "s3c24xx-ac97.h"

struct s3c24xx_ac97_info {
	void __iomem	*regs;
	struct clk	*ac97_clk;
};
static struct s3c24xx_ac97_info s3c24xx_ac97;

static DECLARE_COMPLETION(ac97_completion);
static u32 codec_ready;
static DECLARE_MUTEX(ac97_mutex);

static unsigned short s3c2443_ac97_read(struct snd_ac97 *ac97,
	unsigned short reg)
{
	u32 ac_glbctrl;
	u32 ac_codec_cmd;
	u32 stat, addr, data;

	down(&ac97_mutex);

	codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
	ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
	ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
	writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);

	udelay(50);

	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);

	wait_for_completion(&ac97_completion);

	stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT);
	addr = (stat >> 16) & 0x7f;
	data = (stat & 0xffff);

	if (addr != reg)
		printk(KERN_ERR "s3c24xx-ac97: req addr = %02x,"
				" rep addr = %02x\n", reg, addr);

	up(&ac97_mutex);

	return (unsigned short)data;
}

static void s3c2443_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
	unsigned short val)
{
	u32 ac_glbctrl;
	u32 ac_codec_cmd;

	down(&ac97_mutex);

	codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
	ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
	ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
	writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);

	udelay(50);

	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);

	wait_for_completion(&ac97_completion);

	ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
	ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
	writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);

	up(&ac97_mutex);

}

static void s3c2443_ac97_warm_reset(struct snd_ac97 *ac97)
{
	u32 ac_glbctrl;

	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	ac_glbctrl = S3C_AC97_GLBCTRL_WARMRESET;
	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	msleep(1);

	ac_glbctrl = 0;
	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	msleep(1);
}

static void s3c2443_ac97_cold_reset(struct snd_ac97 *ac97)
{
	u32 ac_glbctrl;

	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	msleep(1);

	ac_glbctrl = 0;
	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	msleep(1);

	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	msleep(1);

	ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	msleep(1);

	ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA |
		S3C_AC97_GLBCTRL_PCMINTM_DMA | S3C_AC97_GLBCTRL_MICINTM_DMA;
	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
}

static irqreturn_t s3c2443_ac97_irq(int irq, void *dev_id)
{
	int status;
	u32 ac_glbctrl;

	status = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT) & codec_ready;

	if (status) {
		ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
		ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
		writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
		complete(&ac97_completion);
	}
	return IRQ_HANDLED;
}

struct snd_ac97_bus_ops soc_ac97_ops = {
	.read	= s3c2443_ac97_read,
	.write	= s3c2443_ac97_write,
	.warm_reset	= s3c2443_ac97_warm_reset,
	.reset	= s3c2443_ac97_cold_reset,
};

static struct s3c2410_dma_client s3c2443_dma_client_out = {
	.name = "AC97 PCM Stereo out"
};

static struct s3c2410_dma_client s3c2443_dma_client_in = {
	.name = "AC97 PCM Stereo in"
};

static struct s3c2410_dma_client s3c2443_dma_client_micin = {
	.name = "AC97 Mic Mono in"
};

static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_out = {
	.client		= &s3c2443_dma_client_out,
	.channel	= DMACH_PCM_OUT,
	.dma_addr	= S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
	.dma_size	= 4,
};

static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_in = {
	.client		= &s3c2443_dma_client_in,
	.channel	= DMACH_PCM_IN,
	.dma_addr	= S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
	.dma_size	= 4,
};

static struct s3c24xx_pcm_dma_params s3c2443_ac97_mic_mono_in = {
	.client		= &s3c2443_dma_client_micin,
	.channel	= DMACH_MIC_IN,
	.dma_addr	= S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
	.dma_size	= 4,
};

static int s3c2443_ac97_probe(struct platform_device *pdev,
			      struct snd_soc_dai *dai)
{
	int ret;
	u32 ac_glbctrl;

	s3c24xx_ac97.regs = ioremap(S3C2440_PA_AC97, 0x100);
	if (s3c24xx_ac97.regs == NULL)
		return -ENXIO;

	s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
	if (s3c24xx_ac97.ac97_clk == NULL) {
		printk(KERN_ERR "s3c2443-ac97 failed to get ac97_clock\n");
		iounmap(s3c24xx_ac97.regs);
		return -ENODEV;
	}
	clk_enable(s3c24xx_ac97.ac97_clk);

	s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2443_GPE0_AC_nRESET);
	s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2443_GPE1_AC_SYNC);
	s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2443_GPE2_AC_BITCLK);
	s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2443_GPE3_AC_SDI);
	s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2443_GPE4_AC_SDO);

	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	msleep(1);

	ac_glbctrl = 0;
	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	msleep(1);

	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	msleep(1);

	ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);

	ret = request_irq(IRQ_S3C244x_AC97, s3c2443_ac97_irq,
		IRQF_DISABLED, "AC97", NULL);
	if (ret < 0) {
		printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n");
		clk_disable(s3c24xx_ac97.ac97_clk);
		clk_put(s3c24xx_ac97.ac97_clk);
		iounmap(s3c24xx_ac97.regs);
	}
	return ret;
}

static void s3c2443_ac97_remove(struct platform_device *pdev,
				struct snd_soc_dai *dai)
{
	free_irq(IRQ_S3C244x_AC97, NULL);
	clk_disable(s3c24xx_ac97.ac97_clk);
	clk_put(s3c24xx_ac97.ac97_clk);
	iounmap(s3c24xx_ac97.regs);
}

static int s3c2443_ac97_hw_params(struct snd_pcm_substream *substream,
				  struct snd_pcm_hw_params *params,
				  struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_out;
	else
		cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_in;

	return 0;
}

static int s3c2443_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
				struct snd_soc_dai *dai)
{
	u32 ac_glbctrl;

	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
		else
			ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
		else
			ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
		break;
	}
	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);

	return 0;
}

static int s3c2443_ac97_hw_mic_params(struct snd_pcm_substream *substream,
				      struct snd_pcm_hw_params *params,
				      struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		return -ENODEV;
	else
		cpu_dai->dma_data = &s3c2443_ac97_mic_mono_in;

	return 0;
}

static int s3c2443_ac97_mic_trigger(struct snd_pcm_substream *substream,
				    int cmd, struct snd_soc_dai *dai)
{
	u32 ac_glbctrl;

	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
	}
	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);

	return 0;
}

#define s3c2443_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
		SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
		SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)

struct snd_soc_dai s3c2443_ac97_dai[] = {
{
	.name = "s3c2443-ac97",
	.id = 0,
	.ac97_control = 1,
	.probe = s3c2443_ac97_probe,
	.remove = s3c2443_ac97_remove,
	.playback = {
		.stream_name = "AC97 Playback",
		.channels_min = 2,
		.channels_max = 2,
		.rates = s3c2443_AC97_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.stream_name = "AC97 Capture",
		.channels_min = 2,
		.channels_max = 2,
		.rates = s3c2443_AC97_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = {
		.hw_params = s3c2443_ac97_hw_params,
		.trigger = s3c2443_ac97_trigger},
},
{
	.name = "pxa2xx-ac97-mic",
	.id = 1,
	.ac97_control = 1,
	.capture = {
		.stream_name = "AC97 Mic Capture",
		.channels_min = 1,
		.channels_max = 1,
		.rates = s3c2443_AC97_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = {
		.hw_params = s3c2443_ac97_hw_mic_params,
		.trigger = s3c2443_ac97_mic_trigger,},
},
};
EXPORT_SYMBOL_GPL(s3c2443_ac97_dai);
EXPORT_SYMBOL_GPL(soc_ac97_ops);

static int __init s3c2443_ac97_init(void)
{
	return snd_soc_register_dai(&s3c2443_ac97_dai);
}
module_init(s3c2443_ac97_init);

static void __exit s3c2443_ac97_exit(void)
{
	snd_soc_unregister_dai(&s3c2443_ac97_dai);
}
module_exit(s3c2443_ac97_exit);


MODULE_AUTHOR("Graeme Gregory");
MODULE_DESCRIPTION("AC97 driver for the Samsung s3c2443 chip");
MODULE_LICENSE("GPL");
Commit	Line	Data
050f05ea GG	1	/*
	2	* s3c2443-ac97.c -- ALSA Soc Audio Layer
	3	*
	4	* (c) 2007 Wolfson Microelectronics PLC.
	5	* Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
	6	*
	7	* Copyright (C) 2005, Sean Choi <sh428.choi@samsung.com>
	8	* All rights reserved.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
050f05ea GG	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/module.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/interrupt.h>
ccfdd6c2	19	#include <linux/io.h>
050f05ea GG	20	#include <linux/wait.h>
	21	#include <linux/delay.h>
	22	#include <linux/clk.h>
	23
050f05ea GG	24	#include <sound/core.h>
	25	#include <sound/pcm.h>
	26	#include <sound/ac97_codec.h>
	27	#include <sound/initval.h>
	28	#include <sound/soc.h>
	29
a09e64fb	30	#include <mach/hardware.h>
1700139a	31	#include <asm/plat-s3c/regs-ac97.h>
a09e64fb RK	32	#include <mach/regs-gpio.h>
	33	#include <mach/regs-clock.h>
	34	#include <mach/audio.h>
050f05ea	35	#include <asm/dma.h>
a09e64fb	36	#include <mach/dma.h>
050f05ea GG	37
	38	#include "s3c24xx-pcm.h"
	39	#include "s3c24xx-ac97.h"
	40
	41	struct s3c24xx_ac97_info {
	42	void __iomem *regs;
	43	struct clk *ac97_clk;
	44	};
	45	static struct s3c24xx_ac97_info s3c24xx_ac97;
	46
ccfdd6c2	47	static DECLARE_COMPLETION(ac97_completion);
050f05ea GG	48	static u32 codec_ready;
	49	static DECLARE_MUTEX(ac97_mutex);
	50
	51	static unsigned short s3c2443_ac97_read(struct snd_ac97 *ac97,
	52	unsigned short reg)
	53	{
	54	u32 ac_glbctrl;
	55	u32 ac_codec_cmd;
	56	u32 stat, addr, data;
	57
	58	down(&ac97_mutex);
	59
	60	codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
	61	ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
	62	ac_codec_cmd = S3C_AC97_CODEC_CMD_READ \| AC_CMD_ADDR(reg);
	63	writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
	64
	65	udelay(50);
	66
	67	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	68	ac_glbctrl \|= S3C_AC97_GLBCTRL_CODECREADYIE;
	69	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	70
	71	wait_for_completion(&ac97_completion);
	72
	73	stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT);
	74	addr = (stat >> 16) & 0x7f;
	75	data = (stat & 0xffff);
	76
	77	if (addr != reg)
	78	printk(KERN_ERR "s3c24xx-ac97: req addr = %02x,"
	79	" rep addr = %02x\n", reg, addr);
	80
	81	up(&ac97_mutex);
	82
	83	return (unsigned short)data;
	84	}
	85
	86	static void s3c2443_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
	87	unsigned short val)
	88	{
	89	u32 ac_glbctrl;
	90	u32 ac_codec_cmd;
	91
	92	down(&ac97_mutex);
	93
	94	codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
	95	ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
	96	ac_codec_cmd = AC_CMD_ADDR(reg) \| AC_CMD_DATA(val);
	97	writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
	98
	99	udelay(50);
	100
	101	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	102	ac_glbctrl \|= S3C_AC97_GLBCTRL_CODECREADYIE;
	103	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	104
	105	wait_for_completion(&ac97_completion);
	106
	107	ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
	108	ac_codec_cmd \|= S3C_AC97_CODEC_CMD_READ;
	109	writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
	110
	111	up(&ac97_mutex);
112
113	}
114
115	static void s3c2443_ac97_warm_reset(struct snd_ac97 *ac97)
116	{
117	u32 ac_glbctrl;
118
119	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
120	ac_glbctrl = S3C_AC97_GLBCTRL_WARMRESET;
121	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
122	msleep(1);
123
124	ac_glbctrl = 0;
125	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
126	msleep(1);
127	}
128
129	static void s3c2443_ac97_cold_reset(struct snd_ac97 *ac97)
130	{
131	u32 ac_glbctrl;
132
133	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
134	ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
135	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
136	msleep(1);
137
138	ac_glbctrl = 0;
139	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
140	msleep(1);
141
142	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
143	ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
144	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
145	msleep(1);
146
147	ac_glbctrl \|= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
148	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
149	msleep(1);
150
151	ac_glbctrl \|= S3C_AC97_GLBCTRL_PCMOUTTM_DMA \|
152	S3C_AC97_GLBCTRL_PCMINTM_DMA \| S3C_AC97_GLBCTRL_MICINTM_DMA;
153	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
154	}
155
156	static irqreturn_t s3c2443_ac97_irq(int irq, void *dev_id)
157	{
158	int status;
159	u32 ac_glbctrl;
160
161	status = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT) & codec_ready;
162
163	if (status) {
164	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
165	ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
166	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
167	complete(&ac97_completion);
168	}
169	return IRQ_HANDLED;
170	}
171
172	struct snd_ac97_bus_ops soc_ac97_ops = {
173	.read = s3c2443_ac97_read,
174	.write = s3c2443_ac97_write,
175	.warm_reset = s3c2443_ac97_warm_reset,
176	.reset = s3c2443_ac97_cold_reset,
177	};
178
179	static struct s3c2410_dma_client s3c2443_dma_client_out = {
180	.name = "AC97 PCM Stereo out"
181	};
182
183	static struct s3c2410_dma_client s3c2443_dma_client_in = {
184	.name = "AC97 PCM Stereo in"
185	};
186
187	static struct s3c2410_dma_client s3c2443_dma_client_micin = {
188	.name = "AC97 Mic Mono in"
189	};
190
191	static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_out = {
192	.client = &s3c2443_dma_client_out,
193	.channel = DMACH_PCM_OUT,
194	.dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
195	.dma_size = 4,
196	};
197
198	static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_in = {
199	.client = &s3c2443_dma_client_in,
200	.channel = DMACH_PCM_IN,
201	.dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
202	.dma_size = 4,
203	};
204
205	static struct s3c24xx_pcm_dma_params s3c2443_ac97_mic_mono_in = {
206	.client = &s3c2443_dma_client_micin,
207	.channel = DMACH_MIC_IN,
208	.dma_addr = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
209	.dma_size = 4,
210	};
211
bdb92876	212	static int s3c2443_ac97_probe(struct platform_device *pdev,
1992a6fb	213	struct snd_soc_dai *dai)
050f05ea GG	214	{
	215	int ret;
	216	u32 ac_glbctrl;
	217
	218	s3c24xx_ac97.regs = ioremap(S3C2440_PA_AC97, 0x100);
	219	if (s3c24xx_ac97.regs == NULL)
	220	return -ENXIO;
	221
	222	s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
	223	if (s3c24xx_ac97.ac97_clk == NULL) {
	224	printk(KERN_ERR "s3c2443-ac97 failed to get ac97_clock\n");
	225	iounmap(s3c24xx_ac97.regs);
	226	return -ENODEV;
	227	}
	228	clk_enable(s3c24xx_ac97.ac97_clk);
	229
	230	s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2443_GPE0_AC_nRESET);
	231	s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2443_GPE1_AC_SYNC);
	232	s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2443_GPE2_AC_BITCLK);
	233	s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2443_GPE3_AC_SDI);
	234	s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2443_GPE4_AC_SDO);
	235
	236	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	237	ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
	238	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	239	msleep(1);
	240
	241	ac_glbctrl = 0;
	242	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	243	msleep(1);
	244
	245	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	246	ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
	247	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	248	msleep(1);
	249
	250	ac_glbctrl \|= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
	251	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	252
040956fa	253	ret = request_irq(IRQ_S3C244x_AC97, s3c2443_ac97_irq,
050f05ea GG	254	IRQF_DISABLED, "AC97", NULL);
	255	if (ret < 0) {
	256	printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n");
	257	clk_disable(s3c24xx_ac97.ac97_clk);
	258	clk_put(s3c24xx_ac97.ac97_clk);
	259	iounmap(s3c24xx_ac97.regs);
	260	}
	261	return ret;
	262	}
	263
bdb92876	264	static void s3c2443_ac97_remove(struct platform_device *pdev,
1992a6fb	265	struct snd_soc_dai *dai)
050f05ea	266	{
040956fa	267	free_irq(IRQ_S3C244x_AC97, NULL);
050f05ea GG	268	clk_disable(s3c24xx_ac97.ac97_clk);
	269	clk_put(s3c24xx_ac97.ac97_clk);
	270	iounmap(s3c24xx_ac97.regs);
	271	}
	272
	273	static int s3c2443_ac97_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	274	struct snd_pcm_hw_params *params,
dee89c4d MB	275	struct snd_soc_dai *dai)
050f05ea GG	276	{
050f05ea GG	277	struct snd_soc_pcm_runtime *rtd = substream->private_data;
1992a6fb	278	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
050f05ea GG	279
	280	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	281	cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_out;
	282	else
	283	cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_in;
	284
	285	return 0;
	286	}
	287
682d5874 TI	288	static int s3c2443_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
682d5874 TI	289	struct snd_soc_dai *dai)
050f05ea GG	290	{
	291	u32 ac_glbctrl;
	292
	293	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
ccfdd6c2	294	switch (cmd) {
050f05ea GG	295	case SNDRV_PCM_TRIGGER_START:
	296	case SNDRV_PCM_TRIGGER_RESUME:
	297	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	298	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	299	ac_glbctrl \|= S3C_AC97_GLBCTRL_PCMINTM_DMA;
	300	else
	301	ac_glbctrl \|= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
	302	break;
	303	case SNDRV_PCM_TRIGGER_STOP:
	304	case SNDRV_PCM_TRIGGER_SUSPEND:
	305	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	306	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	307	ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
	308	else
	309	ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
	310	break;
	311	}
	312	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	313
	314	return 0;
	315	}
	316
	317	static int s3c2443_ac97_hw_mic_params(struct snd_pcm_substream *substream,
dee89c4d MB	318	struct snd_pcm_hw_params *params,
dee89c4d MB	319	struct snd_soc_dai *dai)
050f05ea GG	320	{
050f05ea GG	321	struct snd_soc_pcm_runtime *rtd = substream->private_data;
1992a6fb	322	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
050f05ea GG	323
	324	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	325	return -ENODEV;
	326	else
	327	cpu_dai->dma_data = &s3c2443_ac97_mic_mono_in;
	328
	329	return 0;
	330	}
	331
	332	static int s3c2443_ac97_mic_trigger(struct snd_pcm_substream *substream,
dee89c4d	333	int cmd, struct snd_soc_dai *dai)
050f05ea GG	334	{
	335	u32 ac_glbctrl;
	336
	337	ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
ccfdd6c2	338	switch (cmd) {
050f05ea GG	339	case SNDRV_PCM_TRIGGER_START:
	340	case SNDRV_PCM_TRIGGER_RESUME:
	341	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	342	ac_glbctrl \|= S3C_AC97_GLBCTRL_PCMINTM_DMA;
	343	break;
	344	case SNDRV_PCM_TRIGGER_STOP:
	345	case SNDRV_PCM_TRIGGER_SUSPEND:
	346	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	347	ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
	348	}
	349	writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
	350
	351	return 0;
	352	}
	353
	354	#define s3c2443_AC97_RATES (SNDRV_PCM_RATE_8000 \| SNDRV_PCM_RATE_11025 \|\
	355	SNDRV_PCM_RATE_16000 \| SNDRV_PCM_RATE_22050 \| \
	356	SNDRV_PCM_RATE_44100 \| SNDRV_PCM_RATE_48000)
	357
1992a6fb	358	struct snd_soc_dai s3c2443_ac97_dai[] = {
050f05ea GG	359	{
	360	.name = "s3c2443-ac97",
	361	.id = 0,
3ba9e10a	362	.ac97_control = 1,
050f05ea GG	363	.probe = s3c2443_ac97_probe,
	364	.remove = s3c2443_ac97_remove,
	365	.playback = {
	366	.stream_name = "AC97 Playback",
	367	.channels_min = 2,
	368	.channels_max = 2,
	369	.rates = s3c2443_AC97_RATES,
	370	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	371	.capture = {
	372	.stream_name = "AC97 Capture",
	373	.channels_min = 2,
	374	.channels_max = 2,
	375	.rates = s3c2443_AC97_RATES,
	376	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	377	.ops = {
	378	.hw_params = s3c2443_ac97_hw_params,
	379	.trigger = s3c2443_ac97_trigger},
	380	},
	381	{
	382	.name = "pxa2xx-ac97-mic",
	383	.id = 1,
3ba9e10a	384	.ac97_control = 1,
050f05ea GG	385	.capture = {
	386	.stream_name = "AC97 Mic Capture",
	387	.channels_min = 1,
	388	.channels_max = 1,
	389	.rates = s3c2443_AC97_RATES,
	390	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	391	.ops = {
	392	.hw_params = s3c2443_ac97_hw_mic_params,
	393	.trigger = s3c2443_ac97_mic_trigger,},
	394	},
	395	};
050f05ea GG	396	EXPORT_SYMBOL_GPL(s3c2443_ac97_dai);
	397	EXPORT_SYMBOL_GPL(soc_ac97_ops);
	398
c9b3a40f	399	static int __init s3c2443_ac97_init(void)
3f4b783c MB	400	{
	401	return snd_soc_register_dai(&s3c2443_ac97_dai);
	402	}
	403	module_init(s3c2443_ac97_init);
	404
	405	static void __exit s3c2443_ac97_exit(void)
	406	{
	407	snd_soc_unregister_dai(&s3c2443_ac97_dai);
	408	}
	409	module_exit(s3c2443_ac97_exit);
	410
	411
050f05ea GG	412	MODULE_AUTHOR("Graeme Gregory");
	413	MODULE_DESCRIPTION("AC97 driver for the Samsung s3c2443 chip");
	414	MODULE_LICENSE("GPL");