[deliverable/linux.git] / sound / soc / s3c24xx / s3c24xx-i2s.c

/*
 * s3c24xx-i2s.c  --  ALSA Soc Audio Layer
 *
 * (c) 2006 Wolfson Microelectronics PLC.
 * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
 *
 * Copyright 2004-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/jiffies.h>
#include <linux/io.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
#include <plat/audio.h>
#include <asm/dma.h>
#include <mach/dma.h>

#include <plat/regs-iis.h>

#include "s3c24xx-pcm.h"
#include "s3c24xx-i2s.h"

static struct s3c2410_dma_client s3c24xx_dma_client_out = {
	.name = "I2S PCM Stereo out"
};

static struct s3c2410_dma_client s3c24xx_dma_client_in = {
	.name = "I2S PCM Stereo in"
};

static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_out = {
	.client		= &s3c24xx_dma_client_out,
	.channel	= DMACH_I2S_OUT,
	.dma_addr	= S3C2410_PA_IIS + S3C2410_IISFIFO,
	.dma_size	= 2,
};

static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_in = {
	.client		= &s3c24xx_dma_client_in,
	.channel	= DMACH_I2S_IN,
	.dma_addr	= S3C2410_PA_IIS + S3C2410_IISFIFO,
	.dma_size	= 2,
};

struct s3c24xx_i2s_info {
	void __iomem	*regs;
	struct clk	*iis_clk;
	u32		iiscon;
	u32		iismod;
	u32		iisfcon;
	u32		iispsr;
};
static struct s3c24xx_i2s_info s3c24xx_i2s;

static void s3c24xx_snd_txctrl(int on)
{
	u32 iisfcon;
	u32 iiscon;
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);

	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);

	if (on) {
		iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
		iiscon  |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
		iiscon  &= ~S3C2410_IISCON_TXIDLE;
		iismod  |= S3C2410_IISMOD_TXMODE;

		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
	} else {
		/* note, we have to disable the FIFOs otherwise bad things
		 * seem to happen when the DMA stops. According to the
		 * Samsung supplied kernel, this should allow the DMA
		 * engine and FIFOs to reset. If this isn't allowed, the
		 * DMA engine will simply freeze randomly.
		 */

		iisfcon &= ~S3C2410_IISFCON_TXENABLE;
		iisfcon &= ~S3C2410_IISFCON_TXDMA;
		iiscon  |=  S3C2410_IISCON_TXIDLE;
		iiscon  &= ~S3C2410_IISCON_TXDMAEN;
		iismod  &= ~S3C2410_IISMOD_TXMODE;

		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
	}

	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
}

static void s3c24xx_snd_rxctrl(int on)
{
	u32 iisfcon;
	u32 iiscon;
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);

	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);

	if (on) {
		iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
		iiscon  |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
		iiscon  &= ~S3C2410_IISCON_RXIDLE;
		iismod  |= S3C2410_IISMOD_RXMODE;

		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
	} else {
		/* note, we have to disable the FIFOs otherwise bad things
		 * seem to happen when the DMA stops. According to the
		 * Samsung supplied kernel, this should allow the DMA
		 * engine and FIFOs to reset. If this isn't allowed, the
		 * DMA engine will simply freeze randomly.
		 */

		iisfcon &= ~S3C2410_IISFCON_RXENABLE;
		iisfcon &= ~S3C2410_IISFCON_RXDMA;
		iiscon  |= S3C2410_IISCON_RXIDLE;
		iiscon  &= ~S3C2410_IISCON_RXDMAEN;
		iismod  &= ~S3C2410_IISMOD_RXMODE;

		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
	}

	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
}

/*
 * Wait for the LR signal to allow synchronisation to the L/R clock
 * from the codec. May only be needed for slave mode.
 */
static int s3c24xx_snd_lrsync(void)
{
	u32 iiscon;
	int timeout = 50; /* 5ms */

	pr_debug("Entered %s\n", __func__);

	while (1) {
		iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
		if (iiscon & S3C2410_IISCON_LRINDEX)
			break;

		if (!timeout--)
			return -ETIMEDOUT;
		udelay(100);
	}

	return 0;
}

/*
 * Check whether CPU is the master or slave
 */
static inline int s3c24xx_snd_is_clkmaster(void)
{
	pr_debug("Entered %s\n", __func__);

	return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
}

/*
 * Set S3C24xx I2S DAI format
 */
static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
		unsigned int fmt)
{
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params r: IISMOD: %x \n", iismod);

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		iismod |= S3C2410_IISMOD_SLAVE;
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
		iismod &= ~S3C2410_IISMOD_SLAVE;
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_LEFT_J:
		iismod |= S3C2410_IISMOD_MSB;
		break;
	case SND_SOC_DAIFMT_I2S:
		iismod &= ~S3C2410_IISMOD_MSB;
		break;
	default:
		return -EINVAL;
	}

	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params w: IISMOD: %x \n", iismod);
	return 0;
}

static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
	else
		rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;

	/* Working copies of register */
	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params r: IISMOD: %x\n", iismod);

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		iismod &= ~S3C2410_IISMOD_16BIT;
		((struct s3c24xx_pcm_dma_params *)
		  rtd->dai->cpu_dai->dma_data)->dma_size = 1;
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		iismod |= S3C2410_IISMOD_16BIT;
		((struct s3c24xx_pcm_dma_params *)
		  rtd->dai->cpu_dai->dma_data)->dma_size = 2;
		break;
	default:
		return -EINVAL;
	}

	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params w: IISMOD: %x\n", iismod);
	return 0;
}

static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	int ret = 0;

	pr_debug("Entered %s\n", __func__);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (!s3c24xx_snd_is_clkmaster()) {
			ret = s3c24xx_snd_lrsync();
			if (ret)
				goto exit_err;
		}

		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			s3c24xx_snd_rxctrl(1);
		else
			s3c24xx_snd_txctrl(1);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			s3c24xx_snd_rxctrl(0);
		else
			s3c24xx_snd_txctrl(0);
		break;
	default:
		ret = -EINVAL;
		break;
	}

exit_err:
	return ret;
}

/*
 * Set S3C24xx Clock source
 */
static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
	int clk_id, unsigned int freq, int dir)
{
	u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);

	pr_debug("Entered %s\n", __func__);

	iismod &= ~S3C2440_IISMOD_MPLL;

	switch (clk_id) {
	case S3C24XX_CLKSRC_PCLK:
		break;
	case S3C24XX_CLKSRC_MPLL:
		iismod |= S3C2440_IISMOD_MPLL;
		break;
	default:
		return -EINVAL;
	}

	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	return 0;
}

/*
 * Set S3C24xx Clock dividers
 */
static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
	int div_id, int div)
{
	u32 reg;

	pr_debug("Entered %s\n", __func__);

	switch (div_id) {
	case S3C24XX_DIV_BCLK:
		reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
		writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
		break;
	case S3C24XX_DIV_MCLK:
		reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
		writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
		break;
	case S3C24XX_DIV_PRESCALER:
		writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
		reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
		writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

/*
 * To avoid duplicating clock code, allow machine driver to
 * get the clockrate from here.
 */
u32 s3c24xx_i2s_get_clockrate(void)
{
	return clk_get_rate(s3c24xx_i2s.iis_clk);
}
EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);

static int s3c24xx_i2s_probe(struct platform_device *pdev,
			     struct snd_soc_dai *dai)
{
	pr_debug("Entered %s\n", __func__);

	s3c24xx_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
	if (s3c24xx_i2s.regs == NULL)
		return -ENXIO;

	s3c24xx_i2s.iis_clk = clk_get(&pdev->dev, "iis");
	if (s3c24xx_i2s.iis_clk == NULL) {
		pr_err("failed to get iis_clock\n");
		iounmap(s3c24xx_i2s.regs);
		return -ENODEV;
	}
	clk_enable(s3c24xx_i2s.iis_clk);

	/* Configure the I2S pins in correct mode */
	s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
	s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
	s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
	s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
	s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);

	writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);

	s3c24xx_snd_txctrl(0);
	s3c24xx_snd_rxctrl(0);

	return 0;
}

#ifdef CONFIG_PM
static int s3c24xx_i2s_suspend(struct snd_soc_dai *cpu_dai)
{
	pr_debug("Entered %s\n", __func__);

	s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);

	clk_disable(s3c24xx_i2s.iis_clk);

	return 0;
}

static int s3c24xx_i2s_resume(struct snd_soc_dai *cpu_dai)
{
	pr_debug("Entered %s\n", __func__);
	clk_enable(s3c24xx_i2s.iis_clk);

	writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);

	return 0;
}
#else
#define s3c24xx_i2s_suspend NULL
#define s3c24xx_i2s_resume NULL
#endif


#define S3C24XX_I2S_RATES \
	(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
	SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
	SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)

static struct snd_soc_dai_ops s3c24xx_i2s_dai_ops = {
	.trigger	= s3c24xx_i2s_trigger,
	.hw_params	= s3c24xx_i2s_hw_params,
	.set_fmt	= s3c24xx_i2s_set_fmt,
	.set_clkdiv	= s3c24xx_i2s_set_clkdiv,
	.set_sysclk	= s3c24xx_i2s_set_sysclk,
};

struct snd_soc_dai s3c24xx_i2s_dai = {
	.name = "s3c24xx-i2s",
	.id = 0,
	.probe = s3c24xx_i2s_probe,
	.suspend = s3c24xx_i2s_suspend,
	.resume = s3c24xx_i2s_resume,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = S3C24XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = S3C24XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = &s3c24xx_i2s_dai_ops,
};
EXPORT_SYMBOL_GPL(s3c24xx_i2s_dai);

static int __init s3c24xx_i2s_init(void)
{
	return snd_soc_register_dai(&s3c24xx_i2s_dai);
}
module_init(s3c24xx_i2s_init);

static void __exit s3c24xx_i2s_exit(void)
{
	snd_soc_unregister_dai(&s3c24xx_i2s_dai);
}
module_exit(s3c24xx_i2s_exit);

/* Module information */
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
c1422a66 BD	1	/*
	2	* s3c24xx-i2s.c -- ALSA Soc Audio Layer
	3	*
	4	* (c) 2006 Wolfson Microelectronics PLC.
	5	* Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
	6	*
c8efef17	7	* Copyright 2004-2005 Simtec Electronics
c1422a66 BD	8	* http://armlinux.simtec.co.uk/
	9	* Ben Dooks <ben@simtec.co.uk>
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or (at your
	14	* option) any later version.
c1422a66 BD	15	*/
	16
	17	#include <linux/init.h>
	18	#include <linux/module.h>
	19	#include <linux/device.h>
	20	#include <linux/delay.h>
	21	#include <linux/clk.h>
f11b7992	22	#include <linux/jiffies.h>
40efc15f	23	#include <linux/io.h>
c1422a66 BD	24	#include <sound/core.h>
	25	#include <sound/pcm.h>
	26	#include <sound/pcm_params.h>
	27	#include <sound/initval.h>
	28	#include <sound/soc.h>
	29
a09e64fb RK	30	#include <mach/hardware.h>
	31	#include <mach/regs-gpio.h>
	32	#include <mach/regs-clock.h>
899e6cf5	33	#include <plat/audio.h>
c1422a66	34	#include <asm/dma.h>
a09e64fb	35	#include <mach/dma.h>
c1422a66	36
8150bc88	37	#include <plat/regs-iis.h>
aa9673cf	38
c1422a66 BD	39	#include "s3c24xx-pcm.h"
	40	#include "s3c24xx-i2s.h"
	41
c1422a66 BD	42	static struct s3c2410_dma_client s3c24xx_dma_client_out = {
	43	.name = "I2S PCM Stereo out"
	44	};
	45
	46	static struct s3c2410_dma_client s3c24xx_dma_client_in = {
	47	.name = "I2S PCM Stereo in"
	48	};
	49
	50	static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_out = {
	51	.client = &s3c24xx_dma_client_out,
	52	.channel = DMACH_I2S_OUT,
e81208fe GG	53	.dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
e81208fe GG	54	.dma_size = 2,
c1422a66 BD	55	};
	56
	57	static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_in = {
	58	.client = &s3c24xx_dma_client_in,
	59	.channel = DMACH_I2S_IN,
e81208fe GG	60	.dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
e81208fe GG	61	.dma_size = 2,
c1422a66 BD	62	};
	63
	64	struct s3c24xx_i2s_info {
	65	void __iomem *regs;
	66	struct clk *iis_clk;
5cd919a2 GG	67	u32 iiscon;
	68	u32 iismod;
	69	u32 iisfcon;
	70	u32 iispsr;
c1422a66 BD	71	};
	72	static struct s3c24xx_i2s_info s3c24xx_i2s;
	73
	74	static void s3c24xx_snd_txctrl(int on)
	75	{
	76	u32 iisfcon;
	77	u32 iiscon;
	78	u32 iismod;
	79
ee7d4767	80	pr_debug("Entered %s\n", __func__);
c1422a66 BD	81
	82	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	83	iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	84	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	85
5314adc3	86	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	87
	88	if (on) {
	89	iisfcon \|= S3C2410_IISFCON_TXDMA \| S3C2410_IISFCON_TXENABLE;
	90	iiscon \|= S3C2410_IISCON_TXDMAEN \| S3C2410_IISCON_IISEN;
	91	iiscon &= ~S3C2410_IISCON_TXIDLE;
	92	iismod \|= S3C2410_IISMOD_TXMODE;
	93
	94	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	95	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	96	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	97	} else {
	98	/* note, we have to disable the FIFOs otherwise bad things
	99	* seem to happen when the DMA stops. According to the
	100	* Samsung supplied kernel, this should allow the DMA
	101	* engine and FIFOs to reset. If this isn't allowed, the
	102	* DMA engine will simply freeze randomly.
	103	*/
	104
	105	iisfcon &= ~S3C2410_IISFCON_TXENABLE;
	106	iisfcon &= ~S3C2410_IISFCON_TXDMA;
	107	iiscon \|= S3C2410_IISCON_TXIDLE;
	108	iiscon &= ~S3C2410_IISCON_TXDMAEN;
	109	iismod &= ~S3C2410_IISMOD_TXMODE;
	110
	111	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	112	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	113	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	114	}
	115
5314adc3	116	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	117	}
	118
	119	static void s3c24xx_snd_rxctrl(int on)
	120	{
	121	u32 iisfcon;
	122	u32 iiscon;
	123	u32 iismod;
	124
ee7d4767	125	pr_debug("Entered %s\n", __func__);
c1422a66 BD	126
	127	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	128	iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	129	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	130
5314adc3	131	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	132
	133	if (on) {
	134	iisfcon \|= S3C2410_IISFCON_RXDMA \| S3C2410_IISFCON_RXENABLE;
	135	iiscon \|= S3C2410_IISCON_RXDMAEN \| S3C2410_IISCON_IISEN;
	136	iiscon &= ~S3C2410_IISCON_RXIDLE;
	137	iismod \|= S3C2410_IISMOD_RXMODE;
	138
	139	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	140	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	141	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	142	} else {
	143	/* note, we have to disable the FIFOs otherwise bad things
	144	* seem to happen when the DMA stops. According to the
	145	* Samsung supplied kernel, this should allow the DMA
	146	* engine and FIFOs to reset. If this isn't allowed, the
	147	* DMA engine will simply freeze randomly.
	148	*/
	149
0015e7d1 MB	150	iisfcon &= ~S3C2410_IISFCON_RXENABLE;
	151	iisfcon &= ~S3C2410_IISFCON_RXDMA;
	152	iiscon \|= S3C2410_IISCON_RXIDLE;
	153	iiscon &= ~S3C2410_IISCON_RXDMAEN;
c1422a66 BD	154	iismod &= ~S3C2410_IISMOD_RXMODE;
	155
	156	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	157	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	158	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	159	}
	160
5314adc3	161	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	162	}
	163
	164	/*
	165	* Wait for the LR signal to allow synchronisation to the L/R clock
	166	* from the codec. May only be needed for slave mode.
	167	*/
	168	static int s3c24xx_snd_lrsync(void)
	169	{
	170	u32 iiscon;
33e5b222	171	int timeout = 50; /* 5ms */
c1422a66	172
ee7d4767	173	pr_debug("Entered %s\n", __func__);
c1422a66 BD	174
	175	while (1) {
	176	iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	177	if (iiscon & S3C2410_IISCON_LRINDEX)
	178	break;
	179
33e5b222	180	if (!timeout--)
c1422a66	181	return -ETIMEDOUT;
33e5b222	182	udelay(100);
c1422a66 BD	183	}
	184
	185	return 0;
	186	}
	187
	188	/*
	189	* Check whether CPU is the master or slave
	190	*/
	191	static inline int s3c24xx_snd_is_clkmaster(void)
	192	{
ee7d4767	193	pr_debug("Entered %s\n", __func__);
c1422a66 BD	194
	195	return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
	196	}
	197
	198	/*
	199	* Set S3C24xx I2S DAI format
	200	*/
1992a6fb	201	static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
c1422a66 BD	202	unsigned int fmt)
	203	{
	204	u32 iismod;
	205
ee7d4767	206	pr_debug("Entered %s\n", __func__);
c1422a66 BD	207
c1422a66 BD	208	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	209	pr_debug("hw_params r: IISMOD: %x \n", iismod);
c1422a66 BD	210
	211	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	212	case SND_SOC_DAIFMT_CBM_CFM:
	213	iismod \|= S3C2410_IISMOD_SLAVE;
	214	break;
	215	case SND_SOC_DAIFMT_CBS_CFS:
2c36eecf	216	iismod &= ~S3C2410_IISMOD_SLAVE;
c1422a66 BD	217	break;
	218	default:
	219	return -EINVAL;
	220	}
	221
	222	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	223	case SND_SOC_DAIFMT_LEFT_J:
	224	iismod \|= S3C2410_IISMOD_MSB;
	225	break;
	226	case SND_SOC_DAIFMT_I2S:
2c36eecf	227	iismod &= ~S3C2410_IISMOD_MSB;
c1422a66 BD	228	break;
	229	default:
	230	return -EINVAL;
	231	}
	232
	233	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	234	pr_debug("hw_params w: IISMOD: %x \n", iismod);
c1422a66 BD	235	return 0;
	236	}
	237
	238	static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	239	struct snd_pcm_hw_params *params,
dee89c4d MB	240	struct snd_soc_dai *dai)
c1422a66 BD	241	{
	242	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	243	u32 iismod;
	244
ee7d4767	245	pr_debug("Entered %s\n", __func__);
c1422a66 BD	246
	247	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	248	rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
	249	else
	250	rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;
	251
	252	/* Working copies of register */
	253	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	254	pr_debug("hw_params r: IISMOD: %x\n", iismod);
c1422a66 BD	255
	256	switch (params_format(params)) {
	257	case SNDRV_PCM_FORMAT_S8:
53599bbc CP	258	iismod &= ~S3C2410_IISMOD_16BIT;
	259	((struct s3c24xx_pcm_dma_params *)
	260	rtd->dai->cpu_dai->dma_data)->dma_size = 1;
c1422a66 BD	261	break;
	262	case SNDRV_PCM_FORMAT_S16_LE:
	263	iismod \|= S3C2410_IISMOD_16BIT;
53599bbc CP	264	((struct s3c24xx_pcm_dma_params *)
53599bbc CP	265	rtd->dai->cpu_dai->dma_data)->dma_size = 2;
c1422a66	266	break;
53599bbc CP	267	default:
53599bbc CP	268	return -EINVAL;
c1422a66 BD	269	}
	270
	271	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	272	pr_debug("hw_params w: IISMOD: %x\n", iismod);
c1422a66 BD	273	return 0;
	274	}
	275
dee89c4d MB	276	static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
dee89c4d MB	277	struct snd_soc_dai *dai)
c1422a66 BD	278	{
	279	int ret = 0;
	280
ee7d4767	281	pr_debug("Entered %s\n", __func__);
c1422a66 BD	282
	283	switch (cmd) {
	284	case SNDRV_PCM_TRIGGER_START:
	285	case SNDRV_PCM_TRIGGER_RESUME:
	286	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	287	if (!s3c24xx_snd_is_clkmaster()) {
	288	ret = s3c24xx_snd_lrsync();
	289	if (ret)
	290	goto exit_err;
	291	}
	292
	293	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	294	s3c24xx_snd_rxctrl(1);
	295	else
	296	s3c24xx_snd_txctrl(1);
	297	break;
	298	case SNDRV_PCM_TRIGGER_STOP:
	299	case SNDRV_PCM_TRIGGER_SUSPEND:
	300	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	301	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	302	s3c24xx_snd_rxctrl(0);
	303	else
	304	s3c24xx_snd_txctrl(0);
	305	break;
	306	default:
	307	ret = -EINVAL;
	308	break;
	309	}
	310
	311	exit_err:
	312	return ret;
	313	}
	314
	315	/*
	316	* Set S3C24xx Clock source
	317	*/
1992a6fb	318	static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
c1422a66 BD	319	int clk_id, unsigned int freq, int dir)
	320	{
	321	u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	322
ee7d4767	323	pr_debug("Entered %s\n", __func__);
c1422a66 BD	324
	325	iismod &= ~S3C2440_IISMOD_MPLL;
	326
	327	switch (clk_id) {
	328	case S3C24XX_CLKSRC_PCLK:
	329	break;
	330	case S3C24XX_CLKSRC_MPLL:
	331	iismod \|= S3C2440_IISMOD_MPLL;
	332	break;
	333	default:
	334	return -EINVAL;
	335	}
	336
	337	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	338	return 0;
	339	}
	340
	341	/*
	342	* Set S3C24xx Clock dividers
	343	*/
1992a6fb	344	static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
c1422a66 BD	345	int div_id, int div)
	346	{
	347	u32 reg;
	348
ee7d4767	349	pr_debug("Entered %s\n", __func__);
c1422a66 BD	350
c1422a66 BD	351	switch (div_id) {
82fb159a	352	case S3C24XX_DIV_BCLK:
c1422a66 BD	353	reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
	354	writel(reg \| div, s3c24xx_i2s.regs + S3C2410_IISMOD);
	355	break;
82fb159a	356	case S3C24XX_DIV_MCLK:
c1422a66 BD	357	reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
	358	writel(reg \| div, s3c24xx_i2s.regs + S3C2410_IISMOD);
	359	break;
	360	case S3C24XX_DIV_PRESCALER:
	361	writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
	362	reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	363	writel(reg \| S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
	364	break;
	365	default:
	366	return -EINVAL;
	367	}
	368
	369	return 0;
	370	}
	371
	372	/*
	373	* To avoid duplicating clock code, allow machine driver to
	374	* get the clockrate from here.
	375	*/
	376	u32 s3c24xx_i2s_get_clockrate(void)
	377	{
	378	return clk_get_rate(s3c24xx_i2s.iis_clk);
	379	}
	380	EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
	381
bdb92876	382	static int s3c24xx_i2s_probe(struct platform_device *pdev,
1992a6fb	383	struct snd_soc_dai *dai)
c1422a66	384	{
ee7d4767	385	pr_debug("Entered %s\n", __func__);
c1422a66 BD	386
	387	s3c24xx_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
	388	if (s3c24xx_i2s.regs == NULL)
	389	return -ENXIO;
	390
0fe564a5	391	s3c24xx_i2s.iis_clk = clk_get(&pdev->dev, "iis");
c1422a66	392	if (s3c24xx_i2s.iis_clk == NULL) {
b52a5195	393	pr_err("failed to get iis_clock\n");
8642a4ba	394	iounmap(s3c24xx_i2s.regs);
c1422a66 BD	395	return -ENODEV;
	396	}
	397	clk_enable(s3c24xx_i2s.iis_clk);
	398
	399	/* Configure the I2S pins in correct mode */
	400	s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
	401	s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
	402	s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
	403	s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
	404	s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
	405
	406	writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
	407
	408	s3c24xx_snd_txctrl(0);
	409	s3c24xx_snd_rxctrl(0);
	410
	411	return 0;
	412	}
	413
5cd919a2	414	#ifdef CONFIG_PM
dc7d7b83	415	static int s3c24xx_i2s_suspend(struct snd_soc_dai *cpu_dai)
5cd919a2	416	{
ee7d4767	417	pr_debug("Entered %s\n", __func__);
40920307	418
5cd919a2 GG	419	s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	420	s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	421	s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	422	s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);
	423
	424	clk_disable(s3c24xx_i2s.iis_clk);
	425
	426	return 0;
	427	}
	428
dc7d7b83	429	static int s3c24xx_i2s_resume(struct snd_soc_dai *cpu_dai)
5cd919a2	430	{
ee7d4767	431	pr_debug("Entered %s\n", __func__);
5cd919a2 GG	432	clk_enable(s3c24xx_i2s.iis_clk);
	433
	434	writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	435	writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	436	writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	437	writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);
	438
	439	return 0;
	440	}
	441	#else
	442	#define s3c24xx_i2s_suspend NULL
	443	#define s3c24xx_i2s_resume NULL
	444	#endif
	445
	446
c1422a66 BD	447	#define S3C24XX_I2S_RATES \
	448	(SNDRV_PCM_RATE_8000 \| SNDRV_PCM_RATE_11025 \| SNDRV_PCM_RATE_16000 \| \
	449	SNDRV_PCM_RATE_22050 \| SNDRV_PCM_RATE_32000 \| SNDRV_PCM_RATE_44100 \| \
	450	SNDRV_PCM_RATE_48000 \| SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	451
6335d055 EM	452	static struct snd_soc_dai_ops s3c24xx_i2s_dai_ops = {
	453	.trigger = s3c24xx_i2s_trigger,
	454	.hw_params = s3c24xx_i2s_hw_params,
	455	.set_fmt = s3c24xx_i2s_set_fmt,
	456	.set_clkdiv = s3c24xx_i2s_set_clkdiv,
	457	.set_sysclk = s3c24xx_i2s_set_sysclk,
	458	};
	459
1992a6fb	460	struct snd_soc_dai s3c24xx_i2s_dai = {
c1422a66 BD	461	.name = "s3c24xx-i2s",
c1422a66 BD	462	.id = 0,
c1422a66	463	.probe = s3c24xx_i2s_probe,
5cd919a2 GG	464	.suspend = s3c24xx_i2s_suspend,
5cd919a2 GG	465	.resume = s3c24xx_i2s_resume,
c1422a66 BD	466	.playback = {
	467	.channels_min = 2,
	468	.channels_max = 2,
	469	.rates = S3C24XX_I2S_RATES,
	470	.formats = SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE,},
	471	.capture = {
	472	.channels_min = 2,
	473	.channels_max = 2,
	474	.rates = S3C24XX_I2S_RATES,
	475	.formats = SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE,},
6335d055	476	.ops = &s3c24xx_i2s_dai_ops,
c1422a66 BD	477	};
	478	EXPORT_SYMBOL_GPL(s3c24xx_i2s_dai);
	479
c9b3a40f	480	static int __init s3c24xx_i2s_init(void)
3f4b783c MB	481	{
	482	return snd_soc_register_dai(&s3c24xx_i2s_dai);
	483	}
	484	module_init(s3c24xx_i2s_init);
	485
	486	static void __exit s3c24xx_i2s_exit(void)
	487	{
	488	snd_soc_unregister_dai(&s3c24xx_i2s_dai);
	489	}
	490	module_exit(s3c24xx_i2s_exit);
	491
c1422a66 BD	492	/* Module information */
	493	MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
	494	MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
	495	MODULE_LICENSE("GPL");