[deliverable/linux.git] / sound / soc / s3c24xx / s3c24xx-i2s.c

/*
 * s3c24xx-i2s.c  --  ALSA Soc Audio Layer
 *
 * (c) 2006 Wolfson Microelectronics PLC.
 * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
 *
 * (c) 2004-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/jiffies.h>
#include <linux/io.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include <asm/hardware.h>
#include <asm/arch/regs-gpio.h>
#include <asm/arch/regs-clock.h>
#include <asm/arch/audio.h>
#include <asm/dma.h>
#include <asm/arch/dma.h>

#include <asm/plat-s3c24xx/regs-iis.h>

#include "s3c24xx-pcm.h"
#include "s3c24xx-i2s.h"

#define S3C24XX_I2S_DEBUG 0
#if S3C24XX_I2S_DEBUG
#define DBG(x...) printk(KERN_DEBUG "s3c24xx-i2s: " x)
#else
#define DBG(x...)
#endif

static struct s3c2410_dma_client s3c24xx_dma_client_out = {
	.name = "I2S PCM Stereo out"
};

static struct s3c2410_dma_client s3c24xx_dma_client_in = {
	.name = "I2S PCM Stereo in"
};

static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_out = {
	.client		= &s3c24xx_dma_client_out,
	.channel	= DMACH_I2S_OUT,
	.dma_addr	= S3C2410_PA_IIS + S3C2410_IISFIFO,
	.dma_size	= 2,
};

static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_in = {
	.client		= &s3c24xx_dma_client_in,
	.channel	= DMACH_I2S_IN,
	.dma_addr	= S3C2410_PA_IIS + S3C2410_IISFIFO,
	.dma_size	= 2,
};

struct s3c24xx_i2s_info {
	void __iomem	*regs;
	struct clk	*iis_clk;
	u32		iiscon;
	u32		iismod;
	u32		iisfcon;
	u32		iispsr;
};
static struct s3c24xx_i2s_info s3c24xx_i2s;

static void s3c24xx_snd_txctrl(int on)
{
	u32 iisfcon;
	u32 iiscon;
	u32 iismod;

	DBG("Entered %s\n", __func__);

	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);

	DBG("r: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);

	if (on) {
		iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
		iiscon  |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
		iiscon  &= ~S3C2410_IISCON_TXIDLE;
		iismod  |= S3C2410_IISMOD_TXMODE;

		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
	} else {
		/* note, we have to disable the FIFOs otherwise bad things
		 * seem to happen when the DMA stops. According to the
		 * Samsung supplied kernel, this should allow the DMA
		 * engine and FIFOs to reset. If this isn't allowed, the
		 * DMA engine will simply freeze randomly.
		 */

		iisfcon &= ~S3C2410_IISFCON_TXENABLE;
		iisfcon &= ~S3C2410_IISFCON_TXDMA;
		iiscon  |=  S3C2410_IISCON_TXIDLE;
		iiscon  &= ~S3C2410_IISCON_TXDMAEN;
		iismod  &= ~S3C2410_IISMOD_TXMODE;

		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
	}

	DBG("w: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
}

static void s3c24xx_snd_rxctrl(int on)
{
	u32 iisfcon;
	u32 iiscon;
	u32 iismod;

	DBG("Entered %s\n", __func__);

	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);

	DBG("r: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);

	if (on) {
		iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
		iiscon  |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
		iiscon  &= ~S3C2410_IISCON_RXIDLE;
		iismod  |= S3C2410_IISMOD_RXMODE;

		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
	} else {
		/* note, we have to disable the FIFOs otherwise bad things
		 * seem to happen when the DMA stops. According to the
		 * Samsung supplied kernel, this should allow the DMA
		 * engine and FIFOs to reset. If this isn't allowed, the
		 * DMA engine will simply freeze randomly.
		 */

		iisfcon &= ~S3C2410_IISFCON_RXENABLE;
		iisfcon &= ~S3C2410_IISFCON_RXDMA;
		iiscon  |= S3C2410_IISCON_RXIDLE;
		iiscon  &= ~S3C2410_IISCON_RXDMAEN;
		iismod  &= ~S3C2410_IISMOD_RXMODE;

		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
	}

	DBG("w: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
}

/*
 * Wait for the LR signal to allow synchronisation to the L/R clock
 * from the codec. May only be needed for slave mode.
 */
static int s3c24xx_snd_lrsync(void)
{
	u32 iiscon;
	unsigned long timeout = jiffies + msecs_to_jiffies(5);

	DBG("Entered %s\n", __func__);

	while (1) {
		iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
		if (iiscon & S3C2410_IISCON_LRINDEX)
			break;

		if (time_after(jiffies, timeout))
			return -ETIMEDOUT;
	}

	return 0;
}

/*
 * Check whether CPU is the master or slave
 */
static inline int s3c24xx_snd_is_clkmaster(void)
{
	DBG("Entered %s\n", __func__);

	return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
}

/*
 * Set S3C24xx I2S DAI format
 */
static int s3c24xx_i2s_set_fmt(struct snd_soc_cpu_dai *cpu_dai,
		unsigned int fmt)
{
	u32 iismod;

	DBG("Entered %s\n", __func__);

	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	DBG("hw_params r: IISMOD: %lx \n", iismod);

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		iismod |= S3C2410_IISMOD_SLAVE;
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
		iismod &= ~S3C2410_IISMOD_SLAVE;
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_LEFT_J:
		iismod |= S3C2410_IISMOD_MSB;
		break;
	case SND_SOC_DAIFMT_I2S:
		iismod &= ~S3C2410_IISMOD_MSB;
		break;
	default:
		return -EINVAL;
	}

	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	DBG("hw_params w: IISMOD: %lx \n", iismod);
	return 0;
}

static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	u32 iismod;

	DBG("Entered %s\n", __func__);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
	else
		rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;

	/* Working copies of register */
	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	DBG("hw_params r: IISMOD: %lx\n", iismod);

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		iismod |= S3C2410_IISMOD_16BIT;
		break;
	}

	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	DBG("hw_params w: IISMOD: %lx\n", iismod);
	return 0;
}

static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
{
	int ret = 0;

	DBG("Entered %s\n", __func__);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (!s3c24xx_snd_is_clkmaster()) {
			ret = s3c24xx_snd_lrsync();
			if (ret)
				goto exit_err;
		}

		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			s3c24xx_snd_rxctrl(1);
		else
			s3c24xx_snd_txctrl(1);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			s3c24xx_snd_rxctrl(0);
		else
			s3c24xx_snd_txctrl(0);
		break;
	default:
		ret = -EINVAL;
		break;
	}

exit_err:
	return ret;
}

/*
 * Set S3C24xx Clock source
 */
static int s3c24xx_i2s_set_sysclk(struct snd_soc_cpu_dai *cpu_dai,
	int clk_id, unsigned int freq, int dir)
{
	u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);

	DBG("Entered %s\n", __func__);

	iismod &= ~S3C2440_IISMOD_MPLL;

	switch (clk_id) {
	case S3C24XX_CLKSRC_PCLK:
		break;
	case S3C24XX_CLKSRC_MPLL:
		iismod |= S3C2440_IISMOD_MPLL;
		break;
	default:
		return -EINVAL;
	}

	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	return 0;
}

/*
 * Set S3C24xx Clock dividers
 */
static int s3c24xx_i2s_set_clkdiv(struct snd_soc_cpu_dai *cpu_dai,
	int div_id, int div)
{
	u32 reg;

	DBG("Entered %s\n", __func__);

	switch (div_id) {
	case S3C24XX_DIV_BCLK:
		reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
		writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
		break;
	case S3C24XX_DIV_MCLK:
		reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
		writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
		break;
	case S3C24XX_DIV_PRESCALER:
		writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
		reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
		writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

/*
 * To avoid duplicating clock code, allow machine driver to
 * get the clockrate from here.
 */
u32 s3c24xx_i2s_get_clockrate(void)
{
	return clk_get_rate(s3c24xx_i2s.iis_clk);
}
EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);

static int s3c24xx_i2s_probe(struct platform_device *pdev)
{
	DBG("Entered %s\n", __func__);

	s3c24xx_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
	if (s3c24xx_i2s.regs == NULL)
		return -ENXIO;

	s3c24xx_i2s.iis_clk = clk_get(&pdev->dev, "iis");
	if (s3c24xx_i2s.iis_clk == NULL) {
		DBG("failed to get iis_clock\n");
		iounmap(s3c24xx_i2s.regs);
		return -ENODEV;
	}
	clk_enable(s3c24xx_i2s.iis_clk);

	/* Configure the I2S pins in correct mode */
	s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
	s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
	s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
	s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
	s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);

	writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);

	s3c24xx_snd_txctrl(0);
	s3c24xx_snd_rxctrl(0);

	return 0;
}

#ifdef CONFIG_PM
static int s3c24xx_i2s_suspend(struct platform_device *pdev,
		struct snd_soc_cpu_dai *cpu_dai)
{
	DBG("Entered %s\n", __func__);

	s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);

	clk_disable(s3c24xx_i2s.iis_clk);

	return 0;
}

static int s3c24xx_i2s_resume(struct platform_device *pdev,
		struct snd_soc_cpu_dai *cpu_dai)
{
	DBG("Entered %s\n", __func__);
	clk_enable(s3c24xx_i2s.iis_clk);

	writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);

	return 0;
}
#else
#define s3c24xx_i2s_suspend NULL
#define s3c24xx_i2s_resume NULL
#endif


#define S3C24XX_I2S_RATES \
	(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
	SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
	SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)

struct snd_soc_cpu_dai s3c24xx_i2s_dai = {
	.name = "s3c24xx-i2s",
	.id = 0,
	.type = SND_SOC_DAI_I2S,
	.probe = s3c24xx_i2s_probe,
	.suspend = s3c24xx_i2s_suspend,
	.resume = s3c24xx_i2s_resume,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = S3C24XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = S3C24XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = {
		.trigger = s3c24xx_i2s_trigger,
		.hw_params = s3c24xx_i2s_hw_params,},
	.dai_ops = {
		.set_fmt = s3c24xx_i2s_set_fmt,
		.set_clkdiv = s3c24xx_i2s_set_clkdiv,
		.set_sysclk = s3c24xx_i2s_set_sysclk,
	},
};
EXPORT_SYMBOL_GPL(s3c24xx_i2s_dai);

/* Module information */
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
c1422a66 BD	1	/*
	2	* s3c24xx-i2s.c -- ALSA Soc Audio Layer
	3	*
	4	* (c) 2006 Wolfson Microelectronics PLC.
	5	* Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
	6	*
	7	* (c) 2004-2005 Simtec Electronics
	8	* http://armlinux.simtec.co.uk/
	9	* Ben Dooks <ben@simtec.co.uk>
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or (at your
	14	* option) any later version.
c1422a66 BD	15	*/
	16
	17	#include <linux/init.h>
	18	#include <linux/module.h>
	19	#include <linux/device.h>
	20	#include <linux/delay.h>
	21	#include <linux/clk.h>
f11b7992	22	#include <linux/jiffies.h>
40efc15f	23	#include <linux/io.h>
c1422a66 BD	24	#include <sound/core.h>
	25	#include <sound/pcm.h>
	26	#include <sound/pcm_params.h>
	27	#include <sound/initval.h>
	28	#include <sound/soc.h>
	29
	30	#include <asm/hardware.h>
c1422a66 BD	31	#include <asm/arch/regs-gpio.h>
	32	#include <asm/arch/regs-clock.h>
	33	#include <asm/arch/audio.h>
	34	#include <asm/dma.h>
	35	#include <asm/arch/dma.h>
	36
aa9673cf HW	37	#include <asm/plat-s3c24xx/regs-iis.h>
aa9673cf HW	38
c1422a66 BD	39	#include "s3c24xx-pcm.h"
	40	#include "s3c24xx-i2s.h"
	41
	42	#define S3C24XX_I2S_DEBUG 0
	43	#if S3C24XX_I2S_DEBUG
40920307	44	#define DBG(x...) printk(KERN_DEBUG "s3c24xx-i2s: " x)
c1422a66 BD	45	#else
	46	#define DBG(x...)
	47	#endif
	48
	49	static struct s3c2410_dma_client s3c24xx_dma_client_out = {
	50	.name = "I2S PCM Stereo out"
	51	};
	52
	53	static struct s3c2410_dma_client s3c24xx_dma_client_in = {
	54	.name = "I2S PCM Stereo in"
	55	};
	56
	57	static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_out = {
	58	.client = &s3c24xx_dma_client_out,
	59	.channel = DMACH_I2S_OUT,
e81208fe GG	60	.dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
e81208fe GG	61	.dma_size = 2,
c1422a66 BD	62	};
	63
	64	static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_in = {
	65	.client = &s3c24xx_dma_client_in,
	66	.channel = DMACH_I2S_IN,
e81208fe GG	67	.dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
e81208fe GG	68	.dma_size = 2,
c1422a66 BD	69	};
	70
	71	struct s3c24xx_i2s_info {
	72	void __iomem *regs;
	73	struct clk *iis_clk;
5cd919a2 GG	74	u32 iiscon;
	75	u32 iismod;
	76	u32 iisfcon;
	77	u32 iispsr;
c1422a66 BD	78	};
	79	static struct s3c24xx_i2s_info s3c24xx_i2s;
	80
	81	static void s3c24xx_snd_txctrl(int on)
	82	{
	83	u32 iisfcon;
	84	u32 iiscon;
	85	u32 iismod;
	86
9bf8e7dd	87	DBG("Entered %s\n", __func__);
c1422a66 BD	88
	89	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	90	iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	91	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	92
	93	DBG("r: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
	94
	95	if (on) {
	96	iisfcon \|= S3C2410_IISFCON_TXDMA \| S3C2410_IISFCON_TXENABLE;
	97	iiscon \|= S3C2410_IISCON_TXDMAEN \| S3C2410_IISCON_IISEN;
	98	iiscon &= ~S3C2410_IISCON_TXIDLE;
	99	iismod \|= S3C2410_IISMOD_TXMODE;
	100
	101	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	102	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	103	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	104	} else {
	105	/* note, we have to disable the FIFOs otherwise bad things
	106	* seem to happen when the DMA stops. According to the
	107	* Samsung supplied kernel, this should allow the DMA
	108	* engine and FIFOs to reset. If this isn't allowed, the
	109	* DMA engine will simply freeze randomly.
	110	*/
	111
	112	iisfcon &= ~S3C2410_IISFCON_TXENABLE;
	113	iisfcon &= ~S3C2410_IISFCON_TXDMA;
	114	iiscon \|= S3C2410_IISCON_TXIDLE;
	115	iiscon &= ~S3C2410_IISCON_TXDMAEN;
	116	iismod &= ~S3C2410_IISMOD_TXMODE;
	117
	118	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	119	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	120	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	121	}
	122
	123	DBG("w: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
	124	}
	125
	126	static void s3c24xx_snd_rxctrl(int on)
	127	{
	128	u32 iisfcon;
	129	u32 iiscon;
	130	u32 iismod;
	131
9bf8e7dd	132	DBG("Entered %s\n", __func__);
c1422a66 BD	133
	134	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	135	iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	136	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	137
	138	DBG("r: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
	139
	140	if (on) {
	141	iisfcon \|= S3C2410_IISFCON_RXDMA \| S3C2410_IISFCON_RXENABLE;
	142	iiscon \|= S3C2410_IISCON_RXDMAEN \| S3C2410_IISCON_IISEN;
	143	iiscon &= ~S3C2410_IISCON_RXIDLE;
	144	iismod \|= S3C2410_IISMOD_RXMODE;
	145
	146	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	147	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	148	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	149	} else {
	150	/* note, we have to disable the FIFOs otherwise bad things
	151	* seem to happen when the DMA stops. According to the
	152	* Samsung supplied kernel, this should allow the DMA
	153	* engine and FIFOs to reset. If this isn't allowed, the
	154	* DMA engine will simply freeze randomly.
	155	*/
	156
0015e7d1 MB	157	iisfcon &= ~S3C2410_IISFCON_RXENABLE;
	158	iisfcon &= ~S3C2410_IISFCON_RXDMA;
	159	iiscon \|= S3C2410_IISCON_RXIDLE;
	160	iiscon &= ~S3C2410_IISCON_RXDMAEN;
c1422a66 BD	161	iismod &= ~S3C2410_IISMOD_RXMODE;
	162
	163	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	164	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	165	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	166	}
	167
	168	DBG("w: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
	169	}
	170
	171	/*
	172	* Wait for the LR signal to allow synchronisation to the L/R clock
	173	* from the codec. May only be needed for slave mode.
	174	*/
	175	static int s3c24xx_snd_lrsync(void)
	176	{
	177	u32 iiscon;
	178	unsigned long timeout = jiffies + msecs_to_jiffies(5);
	179
9bf8e7dd	180	DBG("Entered %s\n", __func__);
c1422a66 BD	181
	182	while (1) {
	183	iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	184	if (iiscon & S3C2410_IISCON_LRINDEX)
	185	break;
	186
f11b7992	187	if (time_after(jiffies, timeout))
c1422a66 BD	188	return -ETIMEDOUT;
	189	}
	190
	191	return 0;
	192	}
	193
	194	/*
	195	* Check whether CPU is the master or slave
	196	*/
	197	static inline int s3c24xx_snd_is_clkmaster(void)
	198	{
9bf8e7dd	199	DBG("Entered %s\n", __func__);
c1422a66 BD	200
	201	return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
	202	}
	203
	204	/*
	205	* Set S3C24xx I2S DAI format
	206	*/
	207	static int s3c24xx_i2s_set_fmt(struct snd_soc_cpu_dai *cpu_dai,
	208	unsigned int fmt)
	209	{
	210	u32 iismod;
	211
9bf8e7dd	212	DBG("Entered %s\n", __func__);
c1422a66 BD	213
	214	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	215	DBG("hw_params r: IISMOD: %lx \n", iismod);
	216
	217	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	218	case SND_SOC_DAIFMT_CBM_CFM:
	219	iismod \|= S3C2410_IISMOD_SLAVE;
	220	break;
	221	case SND_SOC_DAIFMT_CBS_CFS:
2c36eecf	222	iismod &= ~S3C2410_IISMOD_SLAVE;
c1422a66 BD	223	break;
	224	default:
	225	return -EINVAL;
	226	}
	227
	228	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	229	case SND_SOC_DAIFMT_LEFT_J:
	230	iismod \|= S3C2410_IISMOD_MSB;
	231	break;
	232	case SND_SOC_DAIFMT_I2S:
2c36eecf	233	iismod &= ~S3C2410_IISMOD_MSB;
c1422a66 BD	234	break;
	235	default:
	236	return -EINVAL;
	237	}
	238
	239	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	240	DBG("hw_params w: IISMOD: %lx \n", iismod);
	241	return 0;
	242	}
	243
	244	static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
	245	struct snd_pcm_hw_params *params)
	246	{
	247	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	248	u32 iismod;
	249
9bf8e7dd	250	DBG("Entered %s\n", __func__);
c1422a66 BD	251
	252	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	253	rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
	254	else
	255	rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;
	256
	257	/* Working copies of register */
	258	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	259	DBG("hw_params r: IISMOD: %lx\n", iismod);
	260
	261	switch (params_format(params)) {
	262	case SNDRV_PCM_FORMAT_S8:
	263	break;
	264	case SNDRV_PCM_FORMAT_S16_LE:
	265	iismod \|= S3C2410_IISMOD_16BIT;
	266	break;
	267	}
	268
	269	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	270	DBG("hw_params w: IISMOD: %lx\n", iismod);
	271	return 0;
	272	}
	273
	274	static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
	275	{
	276	int ret = 0;
	277
9bf8e7dd	278	DBG("Entered %s\n", __func__);
c1422a66 BD	279
	280	switch (cmd) {
	281	case SNDRV_PCM_TRIGGER_START:
	282	case SNDRV_PCM_TRIGGER_RESUME:
	283	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	284	if (!s3c24xx_snd_is_clkmaster()) {
	285	ret = s3c24xx_snd_lrsync();
	286	if (ret)
	287	goto exit_err;
	288	}
	289
	290	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	291	s3c24xx_snd_rxctrl(1);
	292	else
	293	s3c24xx_snd_txctrl(1);
	294	break;
	295	case SNDRV_PCM_TRIGGER_STOP:
	296	case SNDRV_PCM_TRIGGER_SUSPEND:
	297	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	298	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	299	s3c24xx_snd_rxctrl(0);
	300	else
	301	s3c24xx_snd_txctrl(0);
	302	break;
	303	default:
	304	ret = -EINVAL;
	305	break;
	306	}
	307
	308	exit_err:
	309	return ret;
	310	}
	311
	312	/*
	313	* Set S3C24xx Clock source
	314	*/
	315	static int s3c24xx_i2s_set_sysclk(struct snd_soc_cpu_dai *cpu_dai,
	316	int clk_id, unsigned int freq, int dir)
	317	{
	318	u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	319
9bf8e7dd	320	DBG("Entered %s\n", __func__);
c1422a66 BD	321
	322	iismod &= ~S3C2440_IISMOD_MPLL;
	323
	324	switch (clk_id) {
	325	case S3C24XX_CLKSRC_PCLK:
	326	break;
	327	case S3C24XX_CLKSRC_MPLL:
	328	iismod \|= S3C2440_IISMOD_MPLL;
	329	break;
	330	default:
	331	return -EINVAL;
	332	}
	333
	334	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	335	return 0;
	336	}
	337
	338	/*
	339	* Set S3C24xx Clock dividers
	340	*/
	341	static int s3c24xx_i2s_set_clkdiv(struct snd_soc_cpu_dai *cpu_dai,
	342	int div_id, int div)
	343	{
	344	u32 reg;
	345
9bf8e7dd	346	DBG("Entered %s\n", __func__);
c1422a66 BD	347
c1422a66 BD	348	switch (div_id) {
82fb159a	349	case S3C24XX_DIV_BCLK:
c1422a66 BD	350	reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
	351	writel(reg \| div, s3c24xx_i2s.regs + S3C2410_IISMOD);
	352	break;
82fb159a	353	case S3C24XX_DIV_MCLK:
c1422a66 BD	354	reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
	355	writel(reg \| div, s3c24xx_i2s.regs + S3C2410_IISMOD);
	356	break;
	357	case S3C24XX_DIV_PRESCALER:
	358	writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
	359	reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	360	writel(reg \| S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
	361	break;
	362	default:
	363	return -EINVAL;
	364	}
	365
	366	return 0;
	367	}
	368
	369	/*
	370	* To avoid duplicating clock code, allow machine driver to
	371	* get the clockrate from here.
	372	*/
	373	u32 s3c24xx_i2s_get_clockrate(void)
	374	{
	375	return clk_get_rate(s3c24xx_i2s.iis_clk);
	376	}
	377	EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
	378
	379	static int s3c24xx_i2s_probe(struct platform_device *pdev)
	380	{
9bf8e7dd	381	DBG("Entered %s\n", __func__);
c1422a66 BD	382
	383	s3c24xx_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
	384	if (s3c24xx_i2s.regs == NULL)
	385	return -ENXIO;
	386
0fe564a5	387	s3c24xx_i2s.iis_clk = clk_get(&pdev->dev, "iis");
c1422a66 BD	388	if (s3c24xx_i2s.iis_clk == NULL) {
c1422a66 BD	389	DBG("failed to get iis_clock\n");
8642a4ba	390	iounmap(s3c24xx_i2s.regs);
c1422a66 BD	391	return -ENODEV;
	392	}
	393	clk_enable(s3c24xx_i2s.iis_clk);
	394
	395	/* Configure the I2S pins in correct mode */
	396	s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
	397	s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
	398	s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
	399	s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
	400	s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
	401
	402	writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
	403
	404	s3c24xx_snd_txctrl(0);
	405	s3c24xx_snd_rxctrl(0);
	406
	407	return 0;
	408	}
	409
5cd919a2	410	#ifdef CONFIG_PM
d8ed061a	411	static int s3c24xx_i2s_suspend(struct platform_device *pdev,
5cd919a2 GG	412	struct snd_soc_cpu_dai *cpu_dai)
5cd919a2 GG	413	{
40920307 TN	414	DBG("Entered %s\n", __func__);
40920307 TN	415
5cd919a2 GG	416	s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	417	s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	418	s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	419	s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);
	420
	421	clk_disable(s3c24xx_i2s.iis_clk);
	422
	423	return 0;
	424	}
	425
d8ed061a	426	static int s3c24xx_i2s_resume(struct platform_device *pdev,
5cd919a2 GG	427	struct snd_soc_cpu_dai *cpu_dai)
5cd919a2 GG	428	{
40920307	429	DBG("Entered %s\n", __func__);
5cd919a2 GG	430	clk_enable(s3c24xx_i2s.iis_clk);
	431
	432	writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	433	writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	434	writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	435	writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);
	436
	437	return 0;
	438	}
	439	#else
	440	#define s3c24xx_i2s_suspend NULL
	441	#define s3c24xx_i2s_resume NULL
	442	#endif
	443
	444
c1422a66 BD	445	#define S3C24XX_I2S_RATES \
	446	(SNDRV_PCM_RATE_8000 \| SNDRV_PCM_RATE_11025 \| SNDRV_PCM_RATE_16000 \| \
	447	SNDRV_PCM_RATE_22050 \| SNDRV_PCM_RATE_32000 \| SNDRV_PCM_RATE_44100 \| \
	448	SNDRV_PCM_RATE_48000 \| SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	449
	450	struct snd_soc_cpu_dai s3c24xx_i2s_dai = {
	451	.name = "s3c24xx-i2s",
	452	.id = 0,
	453	.type = SND_SOC_DAI_I2S,
	454	.probe = s3c24xx_i2s_probe,
5cd919a2 GG	455	.suspend = s3c24xx_i2s_suspend,
5cd919a2 GG	456	.resume = s3c24xx_i2s_resume,
c1422a66 BD	457	.playback = {
	458	.channels_min = 2,
	459	.channels_max = 2,
	460	.rates = S3C24XX_I2S_RATES,
	461	.formats = SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE,},
	462	.capture = {
	463	.channels_min = 2,
	464	.channels_max = 2,
	465	.rates = S3C24XX_I2S_RATES,
	466	.formats = SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE,},
	467	.ops = {
	468	.trigger = s3c24xx_i2s_trigger,
	469	.hw_params = s3c24xx_i2s_hw_params,},
	470	.dai_ops = {
	471	.set_fmt = s3c24xx_i2s_set_fmt,
	472	.set_clkdiv = s3c24xx_i2s_set_clkdiv,
	473	.set_sysclk = s3c24xx_i2s_set_sysclk,
	474	},
	475	};
	476	EXPORT_SYMBOL_GPL(s3c24xx_i2s_dai);
	477
	478	/* Module information */
	479	MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
	480	MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
	481	MODULE_LICENSE("GPL");