Commit | Line | Data |
---|---|---|
5033f43c | 1 | /* sound/soc/samsung/ac97.c |
fc93ea2f JB |
2 | * |
3 | * ALSA SoC Audio Layer - S3C AC97 Controller driver | |
4 | * Evolved from s3c2443-ac97.c | |
5 | * | |
6 | * Copyright (c) 2010 Samsung Electronics Co. Ltd | |
df8ad335 | 7 | * Author: Jaswinder Singh <jassisinghbrar@gmail.com> |
fc93ea2f JB |
8 | * Credits: Graeme Gregory, Sean Choi |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
fc93ea2f JB |
15 | #include <linux/io.h> |
16 | #include <linux/delay.h> | |
17 | #include <linux/clk.h> | |
da155d5b | 18 | #include <linux/module.h> |
fc93ea2f JB |
19 | |
20 | #include <sound/soc.h> | |
21 | ||
fc93ea2f | 22 | #include <mach/dma.h> |
5d229ce5 | 23 | #include "regs-ac97.h" |
436d42c6 | 24 | #include <linux/platform_data/asoc-s3c.h> |
fc93ea2f | 25 | |
4b640cf3 | 26 | #include "dma.h" |
fc93ea2f JB |
27 | |
28 | #define AC_CMD_ADDR(x) (x << 16) | |
29 | #define AC_CMD_DATA(x) (x & 0xffff) | |
30 | ||
4f644ea7 SY |
31 | #define S3C_AC97_DAI_PCM 0 |
32 | #define S3C_AC97_DAI_MIC 1 | |
33 | ||
fc93ea2f | 34 | struct s3c_ac97_info { |
fc93ea2f JB |
35 | struct clk *ac97_clk; |
36 | void __iomem *regs; | |
37 | struct mutex lock; | |
38 | struct completion done; | |
39 | }; | |
40 | static struct s3c_ac97_info s3c_ac97; | |
41 | ||
42 | static struct s3c2410_dma_client s3c_dma_client_out = { | |
43 | .name = "AC97 PCMOut" | |
44 | }; | |
45 | ||
46 | static struct s3c2410_dma_client s3c_dma_client_in = { | |
47 | .name = "AC97 PCMIn" | |
48 | }; | |
49 | ||
50 | static struct s3c2410_dma_client s3c_dma_client_micin = { | |
51 | .name = "AC97 MicIn" | |
52 | }; | |
53 | ||
54 | static struct s3c_dma_params s3c_ac97_pcm_out = { | |
55 | .client = &s3c_dma_client_out, | |
56 | .dma_size = 4, | |
57 | }; | |
58 | ||
59 | static struct s3c_dma_params s3c_ac97_pcm_in = { | |
60 | .client = &s3c_dma_client_in, | |
61 | .dma_size = 4, | |
62 | }; | |
63 | ||
64 | static struct s3c_dma_params s3c_ac97_mic_in = { | |
65 | .client = &s3c_dma_client_micin, | |
66 | .dma_size = 4, | |
67 | }; | |
68 | ||
69 | static void s3c_ac97_activate(struct snd_ac97 *ac97) | |
70 | { | |
71 | u32 ac_glbctrl, stat; | |
72 | ||
73 | stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7; | |
74 | if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE) | |
75 | return; /* Return if already active */ | |
76 | ||
77 | INIT_COMPLETION(s3c_ac97.done); | |
78 | ||
79 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
80 | ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON; | |
81 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
82 | msleep(1); | |
83 | ||
84 | ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE; | |
85 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
86 | msleep(1); | |
87 | ||
88 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
89 | ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE; | |
90 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
91 | ||
92 | if (!wait_for_completion_timeout(&s3c_ac97.done, HZ)) | |
4a6f998e | 93 | pr_err("AC97: Unable to activate!"); |
fc93ea2f JB |
94 | } |
95 | ||
96 | static unsigned short s3c_ac97_read(struct snd_ac97 *ac97, | |
97 | unsigned short reg) | |
98 | { | |
99 | u32 ac_glbctrl, ac_codec_cmd; | |
100 | u32 stat, addr, data; | |
101 | ||
102 | mutex_lock(&s3c_ac97.lock); | |
103 | ||
104 | s3c_ac97_activate(ac97); | |
105 | ||
106 | INIT_COMPLETION(s3c_ac97.done); | |
107 | ||
108 | ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD); | |
109 | ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg); | |
110 | writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD); | |
111 | ||
112 | udelay(50); | |
113 | ||
114 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
115 | ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE; | |
116 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
117 | ||
118 | if (!wait_for_completion_timeout(&s3c_ac97.done, HZ)) | |
4a6f998e | 119 | pr_err("AC97: Unable to read!"); |
fc93ea2f JB |
120 | |
121 | stat = readl(s3c_ac97.regs + S3C_AC97_STAT); | |
122 | addr = (stat >> 16) & 0x7f; | |
123 | data = (stat & 0xffff); | |
124 | ||
125 | if (addr != reg) | |
99ce3a3f | 126 | pr_err("ac97: req addr = %02x, rep addr = %02x\n", |
4a6f998e | 127 | reg, addr); |
fc93ea2f JB |
128 | |
129 | mutex_unlock(&s3c_ac97.lock); | |
130 | ||
131 | return (unsigned short)data; | |
132 | } | |
133 | ||
134 | static void s3c_ac97_write(struct snd_ac97 *ac97, unsigned short reg, | |
135 | unsigned short val) | |
136 | { | |
137 | u32 ac_glbctrl, ac_codec_cmd; | |
138 | ||
139 | mutex_lock(&s3c_ac97.lock); | |
140 | ||
141 | s3c_ac97_activate(ac97); | |
142 | ||
143 | INIT_COMPLETION(s3c_ac97.done); | |
144 | ||
145 | ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD); | |
146 | ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val); | |
147 | writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD); | |
148 | ||
149 | udelay(50); | |
150 | ||
151 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
152 | ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE; | |
153 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
154 | ||
155 | if (!wait_for_completion_timeout(&s3c_ac97.done, HZ)) | |
4a6f998e | 156 | pr_err("AC97: Unable to write!"); |
fc93ea2f JB |
157 | |
158 | ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD); | |
159 | ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ; | |
160 | writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD); | |
161 | ||
162 | mutex_unlock(&s3c_ac97.lock); | |
163 | } | |
164 | ||
165 | static void s3c_ac97_cold_reset(struct snd_ac97 *ac97) | |
166 | { | |
8d85d741 | 167 | pr_debug("AC97: Cold reset\n"); |
fc93ea2f JB |
168 | writel(S3C_AC97_GLBCTRL_COLDRESET, |
169 | s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
170 | msleep(1); | |
171 | ||
172 | writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
173 | msleep(1); | |
174 | } | |
175 | ||
176 | static void s3c_ac97_warm_reset(struct snd_ac97 *ac97) | |
177 | { | |
178 | u32 stat; | |
179 | ||
180 | stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7; | |
181 | if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE) | |
182 | return; /* Return if already active */ | |
183 | ||
8d85d741 MB |
184 | pr_debug("AC97: Warm reset\n"); |
185 | ||
fc93ea2f JB |
186 | writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL); |
187 | msleep(1); | |
188 | ||
189 | writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
190 | msleep(1); | |
191 | ||
192 | s3c_ac97_activate(ac97); | |
193 | } | |
194 | ||
195 | static irqreturn_t s3c_ac97_irq(int irq, void *dev_id) | |
196 | { | |
197 | u32 ac_glbctrl, ac_glbstat; | |
198 | ||
199 | ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT); | |
200 | ||
201 | if (ac_glbstat & S3C_AC97_GLBSTAT_CODECREADY) { | |
202 | ||
203 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
204 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE; | |
205 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
206 | ||
207 | complete(&s3c_ac97.done); | |
208 | } | |
209 | ||
210 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
211 | ac_glbctrl |= (1<<30); /* Clear interrupt */ | |
212 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
213 | ||
214 | return IRQ_HANDLED; | |
215 | } | |
216 | ||
b047e1cc | 217 | static struct snd_ac97_bus_ops s3c_ac97_ops = { |
fc93ea2f JB |
218 | .read = s3c_ac97_read, |
219 | .write = s3c_ac97_write, | |
220 | .warm_reset = s3c_ac97_warm_reset, | |
221 | .reset = s3c_ac97_cold_reset, | |
222 | }; | |
fc93ea2f JB |
223 | |
224 | static int s3c_ac97_hw_params(struct snd_pcm_substream *substream, | |
225 | struct snd_pcm_hw_params *params, | |
226 | struct snd_soc_dai *dai) | |
227 | { | |
228 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 229 | struct snd_soc_dai *cpu_dai = rtd->cpu_dai; |
5f712b2b | 230 | struct s3c_dma_params *dma_data; |
fc93ea2f JB |
231 | |
232 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
5f712b2b | 233 | dma_data = &s3c_ac97_pcm_out; |
fc93ea2f | 234 | else |
5f712b2b DM |
235 | dma_data = &s3c_ac97_pcm_in; |
236 | ||
237 | snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data); | |
fc93ea2f JB |
238 | |
239 | return 0; | |
240 | } | |
241 | ||
242 | static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd, | |
243 | struct snd_soc_dai *dai) | |
244 | { | |
245 | u32 ac_glbctrl; | |
246 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
5f712b2b | 247 | struct s3c_dma_params *dma_data = |
f0fba2ad | 248 | snd_soc_dai_get_dma_data(rtd->cpu_dai, substream); |
fc93ea2f JB |
249 | |
250 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
251 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
252 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK; | |
253 | else | |
254 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK; | |
255 | ||
256 | switch (cmd) { | |
257 | case SNDRV_PCM_TRIGGER_START: | |
258 | case SNDRV_PCM_TRIGGER_RESUME: | |
259 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
260 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
261 | ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA; | |
262 | else | |
263 | ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA; | |
264 | break; | |
265 | ||
266 | case SNDRV_PCM_TRIGGER_STOP: | |
267 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
268 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
269 | break; | |
270 | } | |
271 | ||
272 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
273 | ||
344b4c48 BK |
274 | if (!dma_data->ops) |
275 | dma_data->ops = samsung_dma_get_ops(); | |
276 | ||
277 | dma_data->ops->started(dma_data->channel); | |
fc93ea2f JB |
278 | |
279 | return 0; | |
280 | } | |
281 | ||
282 | static int s3c_ac97_hw_mic_params(struct snd_pcm_substream *substream, | |
283 | struct snd_pcm_hw_params *params, | |
284 | struct snd_soc_dai *dai) | |
285 | { | |
286 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 287 | struct snd_soc_dai *cpu_dai = rtd->cpu_dai; |
fc93ea2f JB |
288 | |
289 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
290 | return -ENODEV; | |
291 | else | |
5f712b2b | 292 | snd_soc_dai_set_dma_data(cpu_dai, substream, &s3c_ac97_mic_in); |
fc93ea2f JB |
293 | |
294 | return 0; | |
295 | } | |
296 | ||
297 | static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream, | |
298 | int cmd, struct snd_soc_dai *dai) | |
299 | { | |
300 | u32 ac_glbctrl; | |
301 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
5f712b2b | 302 | struct s3c_dma_params *dma_data = |
f0fba2ad | 303 | snd_soc_dai_get_dma_data(rtd->cpu_dai, substream); |
fc93ea2f JB |
304 | |
305 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
306 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK; | |
307 | ||
308 | switch (cmd) { | |
309 | case SNDRV_PCM_TRIGGER_START: | |
310 | case SNDRV_PCM_TRIGGER_RESUME: | |
311 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
312 | ac_glbctrl |= S3C_AC97_GLBCTRL_MICINTM_DMA; | |
313 | break; | |
314 | ||
315 | case SNDRV_PCM_TRIGGER_STOP: | |
316 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
317 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
318 | break; | |
319 | } | |
320 | ||
321 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); | |
322 | ||
344b4c48 BK |
323 | if (!dma_data->ops) |
324 | dma_data->ops = samsung_dma_get_ops(); | |
325 | ||
326 | dma_data->ops->started(dma_data->channel); | |
fc93ea2f JB |
327 | |
328 | return 0; | |
329 | } | |
330 | ||
85e7652d | 331 | static const struct snd_soc_dai_ops s3c_ac97_dai_ops = { |
fc93ea2f JB |
332 | .hw_params = s3c_ac97_hw_params, |
333 | .trigger = s3c_ac97_trigger, | |
334 | }; | |
335 | ||
85e7652d | 336 | static const struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = { |
fc93ea2f JB |
337 | .hw_params = s3c_ac97_hw_mic_params, |
338 | .trigger = s3c_ac97_mic_trigger, | |
339 | }; | |
340 | ||
f0fba2ad | 341 | static struct snd_soc_dai_driver s3c_ac97_dai[] = { |
fc93ea2f | 342 | [S3C_AC97_DAI_PCM] = { |
99ce3a3f | 343 | .name = "samsung-ac97", |
fc93ea2f JB |
344 | .ac97_control = 1, |
345 | .playback = { | |
346 | .stream_name = "AC97 Playback", | |
347 | .channels_min = 2, | |
348 | .channels_max = 2, | |
349 | .rates = SNDRV_PCM_RATE_8000_48000, | |
350 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
351 | .capture = { | |
352 | .stream_name = "AC97 Capture", | |
353 | .channels_min = 2, | |
354 | .channels_max = 2, | |
355 | .rates = SNDRV_PCM_RATE_8000_48000, | |
356 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
357 | .ops = &s3c_ac97_dai_ops, | |
358 | }, | |
359 | [S3C_AC97_DAI_MIC] = { | |
99ce3a3f | 360 | .name = "samsung-ac97-mic", |
fc93ea2f JB |
361 | .ac97_control = 1, |
362 | .capture = { | |
363 | .stream_name = "AC97 Mic Capture", | |
364 | .channels_min = 1, | |
365 | .channels_max = 1, | |
366 | .rates = SNDRV_PCM_RATE_8000_48000, | |
367 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
368 | .ops = &s3c_ac97_mic_dai_ops, | |
369 | }, | |
370 | }; | |
fc93ea2f | 371 | |
6d717f3e KM |
372 | static const struct snd_soc_component_driver s3c_ac97_component = { |
373 | .name = "s3c-ac97", | |
374 | }; | |
375 | ||
fdca21ad | 376 | static int s3c_ac97_probe(struct platform_device *pdev) |
fc93ea2f JB |
377 | { |
378 | struct resource *mem_res, *dmatx_res, *dmarx_res, *dmamic_res, *irq_res; | |
379 | struct s3c_audio_pdata *ac97_pdata; | |
380 | int ret; | |
381 | ||
382 | ac97_pdata = pdev->dev.platform_data; | |
383 | if (!ac97_pdata || !ac97_pdata->cfg_gpio) { | |
384 | dev_err(&pdev->dev, "cfg_gpio callback not provided!\n"); | |
385 | return -EINVAL; | |
386 | } | |
387 | ||
388 | /* Check for availability of necessary resource */ | |
389 | dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
390 | if (!dmatx_res) { | |
391 | dev_err(&pdev->dev, "Unable to get AC97-TX dma resource\n"); | |
392 | return -ENXIO; | |
393 | } | |
394 | ||
395 | dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
396 | if (!dmarx_res) { | |
397 | dev_err(&pdev->dev, "Unable to get AC97-RX dma resource\n"); | |
398 | return -ENXIO; | |
399 | } | |
400 | ||
401 | dmamic_res = platform_get_resource(pdev, IORESOURCE_DMA, 2); | |
402 | if (!dmamic_res) { | |
403 | dev_err(&pdev->dev, "Unable to get AC97-MIC dma resource\n"); | |
404 | return -ENXIO; | |
405 | } | |
406 | ||
fc93ea2f JB |
407 | irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
408 | if (!irq_res) { | |
409 | dev_err(&pdev->dev, "AC97 IRQ not provided!\n"); | |
410 | return -ENXIO; | |
411 | } | |
412 | ||
64efc5a0 | 413 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
25fd0bfd MB |
414 | s3c_ac97.regs = devm_ioremap_resource(&pdev->dev, mem_res); |
415 | if (IS_ERR(s3c_ac97.regs)) | |
416 | return PTR_ERR(s3c_ac97.regs); | |
fc93ea2f JB |
417 | |
418 | s3c_ac97_pcm_out.channel = dmatx_res->start; | |
419 | s3c_ac97_pcm_out.dma_addr = mem_res->start + S3C_AC97_PCM_DATA; | |
420 | s3c_ac97_pcm_in.channel = dmarx_res->start; | |
421 | s3c_ac97_pcm_in.dma_addr = mem_res->start + S3C_AC97_PCM_DATA; | |
422 | s3c_ac97_mic_in.channel = dmamic_res->start; | |
423 | s3c_ac97_mic_in.dma_addr = mem_res->start + S3C_AC97_MIC_DATA; | |
424 | ||
425 | init_completion(&s3c_ac97.done); | |
426 | mutex_init(&s3c_ac97.lock); | |
427 | ||
5d45ee3c | 428 | s3c_ac97.ac97_clk = devm_clk_get(&pdev->dev, "ac97"); |
fc93ea2f | 429 | if (IS_ERR(s3c_ac97.ac97_clk)) { |
99ce3a3f | 430 | dev_err(&pdev->dev, "ac97 failed to get ac97_clock\n"); |
fc93ea2f JB |
431 | ret = -ENODEV; |
432 | goto err2; | |
433 | } | |
54f174ab | 434 | clk_prepare_enable(s3c_ac97.ac97_clk); |
fc93ea2f JB |
435 | |
436 | if (ac97_pdata->cfg_gpio(pdev)) { | |
437 | dev_err(&pdev->dev, "Unable to configure gpio\n"); | |
438 | ret = -EINVAL; | |
439 | goto err3; | |
440 | } | |
441 | ||
442 | ret = request_irq(irq_res->start, s3c_ac97_irq, | |
88e24c3a | 443 | 0, "AC97", NULL); |
fc93ea2f | 444 | if (ret < 0) { |
99ce3a3f | 445 | dev_err(&pdev->dev, "ac97: interrupt request failed.\n"); |
fc93ea2f JB |
446 | goto err4; |
447 | } | |
448 | ||
b047e1cc MB |
449 | ret = snd_soc_set_ac97_ops(&s3c_ac97_ops); |
450 | if (ret != 0) { | |
451 | dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret); | |
452 | goto err4; | |
453 | } | |
454 | ||
6d717f3e KM |
455 | ret = snd_soc_register_component(&pdev->dev, &s3c_ac97_component, |
456 | s3c_ac97_dai, ARRAY_SIZE(s3c_ac97_dai)); | |
fc93ea2f JB |
457 | if (ret) |
458 | goto err5; | |
459 | ||
85ff3c29 | 460 | ret = samsung_asoc_dma_platform_register(&pdev->dev); |
a08485d8 PV |
461 | if (ret) { |
462 | dev_err(&pdev->dev, "failed to get register DMA: %d\n", ret); | |
463 | goto err6; | |
464 | } | |
fc93ea2f | 465 | |
a08485d8 PV |
466 | return 0; |
467 | err6: | |
6d717f3e | 468 | snd_soc_unregister_component(&pdev->dev); |
fc93ea2f JB |
469 | err5: |
470 | free_irq(irq_res->start, NULL); | |
471 | err4: | |
472 | err3: | |
54f174ab | 473 | clk_disable_unprepare(s3c_ac97.ac97_clk); |
fc93ea2f | 474 | err2: |
b047e1cc | 475 | snd_soc_set_ac97_ops(NULL); |
fc93ea2f JB |
476 | return ret; |
477 | } | |
478 | ||
fdca21ad | 479 | static int s3c_ac97_remove(struct platform_device *pdev) |
fc93ea2f | 480 | { |
25fd0bfd | 481 | struct resource *irq_res; |
fc93ea2f | 482 | |
85ff3c29 | 483 | samsung_asoc_dma_platform_unregister(&pdev->dev); |
6d717f3e | 484 | snd_soc_unregister_component(&pdev->dev); |
fc93ea2f JB |
485 | |
486 | irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
487 | if (irq_res) | |
488 | free_irq(irq_res->start, NULL); | |
489 | ||
54f174ab | 490 | clk_disable_unprepare(s3c_ac97.ac97_clk); |
b047e1cc | 491 | snd_soc_set_ac97_ops(NULL); |
fc93ea2f | 492 | |
fc93ea2f JB |
493 | return 0; |
494 | } | |
495 | ||
496 | static struct platform_driver s3c_ac97_driver = { | |
497 | .probe = s3c_ac97_probe, | |
fdca21ad | 498 | .remove = s3c_ac97_remove, |
fc93ea2f | 499 | .driver = { |
e6104673 | 500 | .name = "samsung-ac97", |
fc93ea2f JB |
501 | .owner = THIS_MODULE, |
502 | }, | |
503 | }; | |
504 | ||
e00c3f55 | 505 | module_platform_driver(s3c_ac97_driver); |
fc93ea2f | 506 | |
df8ad335 | 507 | MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>"); |
fc93ea2f JB |
508 | MODULE_DESCRIPTION("AC97 driver for the Samsung SoC"); |
509 | MODULE_LICENSE("GPL"); | |
e6104673 | 510 | MODULE_ALIAS("platform:samsung-ac97"); |