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ASoC: samsung: i2s: Add clk provider DT binding documentation
[deliverable/linux.git] / sound / soc / samsung / i2s.c
CommitLineData
5033f43c 1/* sound/soc/samsung/i2s.c
1c7ac018
JB		 2 *
3 * ALSA SoC Audio Layer - Samsung I2S Controller driver
4 *
5 * Copyright (c) 2010 Samsung Electronics Co. Ltd.
df8ad335 6 * Jaswinder Singh <jassisinghbrar@gmail.com>
1c7ac018
JB		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/delay.h>
14#include <linux/slab.h>
15#include <linux/clk.h>
16#include <linux/io.h>
da155d5b 17#include <linux/module.h>
40476f61
PV		 18#include <linux/of.h>
19#include <linux/of_gpio.h>
c5cf4dbc 20#include <linux/pm_runtime.h>
1c7ac018 21
1c7ac018 22#include <sound/soc.h>
0378b6ac 23#include <sound/pcm_params.h>
1c7ac018 24
436d42c6 25#include <linux/platform_data/asoc-s3c.h>
1c7ac018
JB		 26
27#include "dma.h"
61100f40 28#include "idma.h"
1c7ac018 29#include "i2s.h"
172a453d 30#include "i2s-regs.h"
1c7ac018
JB		 31
32#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
33
7c62eebb
PV		 34enum samsung_dai_type {
35 TYPE_PRI,
36 TYPE_SEC,
37};
38
a5a56871
PV		 39struct samsung_i2s_variant_regs {
40 unsigned int bfs_off;
41 unsigned int rfs_off;
42 unsigned int sdf_off;
43 unsigned int txr_off;
44 unsigned int rclksrc_off;
45 unsigned int mss_off;
46 unsigned int cdclkcon_off;
47 unsigned int lrp_off;
48 unsigned int bfs_mask;
49 unsigned int rfs_mask;
50 unsigned int ftx0cnt_off;
51};
52
40476f61
PV		 53struct samsung_i2s_dai_data {
54 int dai_type;
7da493e9 55 u32 quirks;
a5a56871 56 const struct samsung_i2s_variant_regs *i2s_variant_regs;
40476f61
PV		 57};
58
1c7ac018
JB		 59struct i2s_dai {
60 /* Platform device for this DAI */
61 struct platform_device *pdev;
af1cf5cf 62 /* Memory mapped SFR region */
1c7ac018 63 void __iomem *addr;
1c7ac018
JB		 64 /* Rate of RCLK source clock */
65 unsigned long rclk_srcrate;
66 /* Frame Clock */
67 unsigned frmclk;
68 /*
69 * Specifically requested RCLK,BCLK by MACHINE Driver.
70 * 0 indicates CPU driver is free to choose any value.
71 */
72 unsigned rfs, bfs;
73 /* I2S Controller's core clock */
74 struct clk *clk;
75 /* Clock for generating I2S signals */
76 struct clk *op_clk;
1c7ac018
JB		 77 /* Pointer to the Primary_Fifo if this is Sec_Fifo, NULL otherwise */
78 struct i2s_dai *pri_dai;
79 /* Pointer to the Secondary_Fifo if it has one, NULL otherwise */
80 struct i2s_dai *sec_dai;
81#define DAI_OPENED (1 << 0) /* Dai is opened */
82#define DAI_MANAGER (1 << 1) /* Dai is the manager */
83 unsigned mode;
b97c60ab
SN		 84 /* CDCLK pin direction: 0 - input, 1 - output */
85 unsigned int cdclk_out:1;
1c7ac018
JB		 86 /* Driver for this DAI */
87 struct snd_soc_dai_driver i2s_dai_drv;
88 /* DMA parameters */
89 struct s3c_dma_params dma_playback;
90 struct s3c_dma_params dma_capture;
61100f40 91 struct s3c_dma_params idma_playback;
1c7ac018
JB		 92 u32 quirks;
93 u32 suspend_i2smod;
94 u32 suspend_i2scon;
95 u32 suspend_i2spsr;
a5a56871 96 const struct samsung_i2s_variant_regs *variant_regs;
f3670536
SN		 97
98 /* Spinlock protecting access to the device's registers */
99 spinlock_t spinlock;
100 spinlock_t *lock;
1c7ac018
JB		 101};
102
103/* Lock for cross i/f checks */
104static DEFINE_SPINLOCK(lock);
105
106/* If this is the 'overlay' stereo DAI */
107static inline bool is_secondary(struct i2s_dai *i2s)
108{
109 return i2s->pri_dai ? true : false;
110}
111
112/* If operating in SoC-Slave mode */
113static inline bool is_slave(struct i2s_dai *i2s)
114{
a5a56871
PV		 115 u32 mod = readl(i2s->addr + I2SMOD);
116 return (mod & (1 << i2s->variant_regs->mss_off)) ? true : false;
1c7ac018
JB		 117}
118
119/* If this interface of the controller is transmitting data */
120static inline bool tx_active(struct i2s_dai *i2s)
121{
122 u32 active;
123
124 if (!i2s)
125 return false;
126
33195500 127 active = readl(i2s->addr + I2SCON);
1c7ac018
JB		 128
129 if (is_secondary(i2s))
130 active &= CON_TXSDMA_ACTIVE;
131 else
132 active &= CON_TXDMA_ACTIVE;
133
134 return active ? true : false;
135}
136
dcd60fc3
SN		 137/* Return pointer to the other DAI */
138static inline struct i2s_dai *get_other_dai(struct i2s_dai *i2s)
139{
140 return i2s->pri_dai ? : i2s->sec_dai;
141}
142
1c7ac018
JB		 143/* If the other interface of the controller is transmitting data */
144static inline bool other_tx_active(struct i2s_dai *i2s)
145{
dcd60fc3 146 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 147
148 return tx_active(other);
149}
150
151/* If any interface of the controller is transmitting data */
152static inline bool any_tx_active(struct i2s_dai *i2s)
153{
154 return tx_active(i2s) || other_tx_active(i2s);
155}
156
157/* If this interface of the controller is receiving data */
158static inline bool rx_active(struct i2s_dai *i2s)
159{
160 u32 active;
161
162 if (!i2s)
163 return false;
164
33195500 165 active = readl(i2s->addr + I2SCON) & CON_RXDMA_ACTIVE;
1c7ac018
JB		 166
167 return active ? true : false;
168}
169
170/* If the other interface of the controller is receiving data */
171static inline bool other_rx_active(struct i2s_dai *i2s)
172{
dcd60fc3 173 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 174
175 return rx_active(other);
176}
177
178/* If any interface of the controller is receiving data */
179static inline bool any_rx_active(struct i2s_dai *i2s)
180{
181 return rx_active(i2s) || other_rx_active(i2s);
182}
183
184/* If the other DAI is transmitting or receiving data */
185static inline bool other_active(struct i2s_dai *i2s)
186{
187 return other_rx_active(i2s) || other_tx_active(i2s);
188}
189
190/* If this DAI is transmitting or receiving data */
191static inline bool this_active(struct i2s_dai *i2s)
192{
193 return tx_active(i2s) || rx_active(i2s);
194}
195
196/* If the controller is active anyway */
197static inline bool any_active(struct i2s_dai *i2s)
198{
199 return this_active(i2s) || other_active(i2s);
200}
201
202static inline struct i2s_dai *to_info(struct snd_soc_dai *dai)
203{
204 return snd_soc_dai_get_drvdata(dai);
205}
206
207static inline bool is_opened(struct i2s_dai *i2s)
208{
209 if (i2s && (i2s->mode & DAI_OPENED))
210 return true;
211 else
212 return false;
213}
214
215static inline bool is_manager(struct i2s_dai *i2s)
216{
217 if (is_opened(i2s) && (i2s->mode & DAI_MANAGER))
218 return true;
219 else
220 return false;
221}
222
223/* Read RCLK of I2S (in multiples of LRCLK) */
224static inline unsigned get_rfs(struct i2s_dai *i2s)
225{
4ca0c0d4 226 u32 rfs;
a5a56871
PV		 227 rfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->rfs_off;
228 rfs &= i2s->variant_regs->rfs_mask;
1c7ac018
JB		 229
230 switch (rfs) {
a5a56871
PV		 231 case 7: return 192;
232 case 6: return 96;
233 case 5: return 128;
234 case 4: return 64;
1c7ac018
JB		 235 case 3: return 768;
236 case 2: return 384;
237 case 1: return 512;
238 default: return 256;
239 }
240}
241
242/* Write RCLK of I2S (in multiples of LRCLK) */
243static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
244{
245 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871 246 int rfs_shift = i2s->variant_regs->rfs_off;
1c7ac018 247
a5a56871 248 mod &= ~(i2s->variant_regs->rfs_mask << rfs_shift);
1c7ac018
JB		 249
250 switch (rfs) {
a5a56871
PV		 251 case 192:
252 mod |= (EXYNOS7_MOD_RCLK_192FS << rfs_shift);
253 break;
254 case 96:
255 mod |= (EXYNOS7_MOD_RCLK_96FS << rfs_shift);
256 break;
257 case 128:
258 mod |= (EXYNOS7_MOD_RCLK_128FS << rfs_shift);
259 break;
260 case 64:
261 mod |= (EXYNOS7_MOD_RCLK_64FS << rfs_shift);
262 break;
1c7ac018 263 case 768:
b60be4aa 264 mod |= (MOD_RCLK_768FS << rfs_shift);
1c7ac018
JB		 265 break;
266 case 512:
b60be4aa 267 mod |= (MOD_RCLK_512FS << rfs_shift);
1c7ac018
JB		 268 break;
269 case 384:
b60be4aa 270 mod |= (MOD_RCLK_384FS << rfs_shift);
1c7ac018
JB		 271 break;
272 default:
b60be4aa 273 mod |= (MOD_RCLK_256FS << rfs_shift);
1c7ac018
JB		 274 break;
275 }
276
277 writel(mod, i2s->addr + I2SMOD);
278}
279
280/* Read Bit-Clock of I2S (in multiples of LRCLK) */
281static inline unsigned get_bfs(struct i2s_dai *i2s)
282{
4ca0c0d4 283 u32 bfs;
a5a56871
PV		 284 bfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->bfs_off;
285 bfs &= i2s->variant_regs->bfs_mask;
1c7ac018
JB		 286
287 switch (bfs) {
4ca0c0d4
PV		 288 case 8: return 256;
289 case 7: return 192;
290 case 6: return 128;
291 case 5: return 96;
292 case 4: return 64;
1c7ac018
JB		 293 case 3: return 24;
294 case 2: return 16;
295 case 1: return 48;
296 default: return 32;
297 }
298}
299
300/* Write Bit-Clock of I2S (in multiples of LRCLK) */
301static inline void set_bfs(struct i2s_dai *i2s, unsigned bfs)
302{
303 u32 mod = readl(i2s->addr + I2SMOD);
4ca0c0d4 304 int tdm = i2s->quirks & QUIRK_SUPPORTS_TDM;
a5a56871 305 int bfs_shift = i2s->variant_regs->bfs_off;
4ca0c0d4
PV		 306
307 /* Non-TDM I2S controllers do not support BCLK > 48 * FS */
308 if (!tdm && bfs > 48) {
309 dev_err(&i2s->pdev->dev, "Unsupported BCLK divider\n");
310 return;
311 }
1c7ac018 312
a5a56871
PV		 313 mod &= ~(i2s->variant_regs->bfs_mask << bfs_shift);
314
1c7ac018
JB		 315 switch (bfs) {
316 case 48:
b60be4aa 317 mod |= (MOD_BCLK_48FS << bfs_shift);
1c7ac018
JB		 318 break;
319 case 32:
b60be4aa 320 mod |= (MOD_BCLK_32FS << bfs_shift);
1c7ac018
JB		 321 break;
322 case 24:
b60be4aa 323 mod |= (MOD_BCLK_24FS << bfs_shift);
1c7ac018
JB		 324 break;
325 case 16:
b60be4aa 326 mod |= (MOD_BCLK_16FS << bfs_shift);
1c7ac018 327 break;
4ca0c0d4
PV		 328 case 64:
329 mod |= (EXYNOS5420_MOD_BCLK_64FS << bfs_shift);
330 break;
331 case 96:
332 mod |= (EXYNOS5420_MOD_BCLK_96FS << bfs_shift);
333 break;
334 case 128:
335 mod |= (EXYNOS5420_MOD_BCLK_128FS << bfs_shift);
336 break;
337 case 192:
338 mod |= (EXYNOS5420_MOD_BCLK_192FS << bfs_shift);
339 break;
340 case 256:
341 mod |= (EXYNOS5420_MOD_BCLK_256FS << bfs_shift);
1c7ac018
JB		 342 break;
343 default:
344 dev_err(&i2s->pdev->dev, "Wrong BCLK Divider!\n");
345 return;
346 }
347
348 writel(mod, i2s->addr + I2SMOD);
349}
350
351/* Sample-Size */
352static inline int get_blc(struct i2s_dai *i2s)
353{
354 int blc = readl(i2s->addr + I2SMOD);
355
356 blc = (blc >> 13) & 0x3;
357
358 switch (blc) {
359 case 2: return 24;
360 case 1: return 8;
361 default: return 16;
362 }
363}
364
365/* TX Channel Control */
366static void i2s_txctrl(struct i2s_dai *i2s, int on)
367{
368 void __iomem *addr = i2s->addr;
a5a56871 369 int txr_off = i2s->variant_regs->txr_off;
1c7ac018 370 u32 con = readl(addr + I2SCON);
a5a56871 371 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
1c7ac018
JB		 372
373 if (on) {
374 con |= CON_ACTIVE;
375 con &= ~CON_TXCH_PAUSE;
376
377 if (is_secondary(i2s)) {
378 con |= CON_TXSDMA_ACTIVE;
379 con &= ~CON_TXSDMA_PAUSE;
380 } else {
381 con |= CON_TXDMA_ACTIVE;
382 con &= ~CON_TXDMA_PAUSE;
383 }
384
385 if (any_rx_active(i2s))
a5a56871 386 mod |= 2 << txr_off;
1c7ac018 387 else
a5a56871 388 mod |= 0 << txr_off;
1c7ac018
JB		 389 } else {
390 if (is_secondary(i2s)) {
391 con |= CON_TXSDMA_PAUSE;
392 con &= ~CON_TXSDMA_ACTIVE;
393 } else {
394 con |= CON_TXDMA_PAUSE;
395 con &= ~CON_TXDMA_ACTIVE;
396 }
397
398 if (other_tx_active(i2s)) {
399 writel(con, addr + I2SCON);
400 return;
401 }
402
403 con |= CON_TXCH_PAUSE;
404
405 if (any_rx_active(i2s))
a5a56871 406 mod |= 1 << txr_off;
1c7ac018
JB		 407 else
408 con &= ~CON_ACTIVE;
409 }
410
411 writel(mod, addr + I2SMOD);
412 writel(con, addr + I2SCON);
413}
414
415/* RX Channel Control */
416static void i2s_rxctrl(struct i2s_dai *i2s, int on)
417{
418 void __iomem *addr = i2s->addr;
a5a56871 419 int txr_off = i2s->variant_regs->txr_off;
1c7ac018 420 u32 con = readl(addr + I2SCON);
a5a56871 421 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
1c7ac018
JB		 422
423 if (on) {
424 con |= CON_RXDMA_ACTIVE | CON_ACTIVE;
425 con &= ~(CON_RXDMA_PAUSE | CON_RXCH_PAUSE);
426
427 if (any_tx_active(i2s))
a5a56871 428 mod |= 2 << txr_off;
1c7ac018 429 else
a5a56871 430 mod |= 1 << txr_off;
1c7ac018
JB		 431 } else {
432 con |= CON_RXDMA_PAUSE | CON_RXCH_PAUSE;
433 con &= ~CON_RXDMA_ACTIVE;
434
435 if (any_tx_active(i2s))
a5a56871 436 mod |= 0 << txr_off;
1c7ac018
JB		 437 else
438 con &= ~CON_ACTIVE;
439 }
440
441 writel(mod, addr + I2SMOD);
442 writel(con, addr + I2SCON);
443}
444
445/* Flush FIFO of an interface */
446static inline void i2s_fifo(struct i2s_dai *i2s, u32 flush)
447{
448 void __iomem *fic;
449 u32 val;
450
451 if (!i2s)
452 return;
453
454 if (is_secondary(i2s))
455 fic = i2s->addr + I2SFICS;
456 else
457 fic = i2s->addr + I2SFIC;
458
459 /* Flush the FIFO */
460 writel(readl(fic) | flush, fic);
461
462 /* Be patient */
463 val = msecs_to_loops(1) / 1000; /* 1 usec */
464 while (--val)
465 cpu_relax();
466
467 writel(readl(fic) & ~flush, fic);
468}
469
470static int i2s_set_sysclk(struct snd_soc_dai *dai,
471 int clk_id, unsigned int rfs, int dir)
472{
473 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 474 struct i2s_dai *other = get_other_dai(i2s);
a5a56871
PV		 475 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
476 unsigned int cdcon_mask = 1 << i2s_regs->cdclkcon_off;
477 unsigned int rsrc_mask = 1 << i2s_regs->rclksrc_off;
ce8bcdbb
SN		 478 u32 mod, mask, val = 0;
479
480 spin_lock(i2s->lock);
481 mod = readl(i2s->addr + I2SMOD);
482 spin_unlock(i2s->lock);
1c7ac018
JB		 483
484 switch (clk_id) {
c86d50f9 485 case SAMSUNG_I2S_OPCLK:
ce8bcdbb
SN		 486 mask = MOD_OPCLK_MASK;
487 val = dir;
c86d50f9 488 break;
1c7ac018 489 case SAMSUNG_I2S_CDCLK:
ce8bcdbb 490 mask = 1 << i2s_regs->cdclkcon_off;
1c7ac018
JB		 491 /* Shouldn't matter in GATING(CLOCK_IN) mode */
492 if (dir == SND_SOC_CLOCK_IN)
493 rfs = 0;
494
133c2681 495 if ((rfs && other && other->rfs && (other->rfs != rfs)) ||
1c7ac018
JB		 496 (any_active(i2s) &&
497 (((dir == SND_SOC_CLOCK_IN)
a5a56871 498 && !(mod & cdcon_mask)) ||
1c7ac018 499 ((dir == SND_SOC_CLOCK_OUT)
a5a56871 500 && (mod & cdcon_mask))))) {
1c7ac018
JB		 501 dev_err(&i2s->pdev->dev,
502 "%s:%d Other DAI busy\n", __func__, __LINE__);
503 return -EAGAIN;
504 }
505
506 if (dir == SND_SOC_CLOCK_IN)
ce8bcdbb 507 val = 1 << i2s_regs->cdclkcon_off;
1c7ac018
JB		 508
509 i2s->rfs = rfs;
510 break;
511
512 case SAMSUNG_I2S_RCLKSRC_0: /* clock corrsponding to IISMOD[10] := 0 */
513 case SAMSUNG_I2S_RCLKSRC_1: /* clock corrsponding to IISMOD[10] := 1 */
ce8bcdbb
SN		 514 mask = 1 << i2s_regs->rclksrc_off;
515
1c7ac018
JB		 516 if ((i2s->quirks & QUIRK_NO_MUXPSR)
517 || (clk_id == SAMSUNG_I2S_RCLKSRC_0))
518 clk_id = 0;
519 else
520 clk_id = 1;
521
522 if (!any_active(i2s)) {
a6aba536 523 if (i2s->op_clk && !IS_ERR(i2s->op_clk)) {
a5a56871
PV		 524 if ((clk_id && !(mod & rsrc_mask)) ||
525 (!clk_id && (mod & rsrc_mask))) {
98614cf6 526 clk_disable_unprepare(i2s->op_clk);
1c7ac018
JB		 527 clk_put(i2s->op_clk);
528 } else {
6ce534aa
JB		 529 i2s->rclk_srcrate =
530 clk_get_rate(i2s->op_clk);
1c7ac018
JB		 531 return 0;
532 }
533 }
534
1974a042
PV		 535 if (clk_id)
536 i2s->op_clk = clk_get(&i2s->pdev->dev,
537 "i2s_opclk1");
538 else
539 i2s->op_clk = clk_get(&i2s->pdev->dev,
540 "i2s_opclk0");
a6aba536
SN		 541
542 if (WARN_ON(IS_ERR(i2s->op_clk)))
543 return PTR_ERR(i2s->op_clk);
544
98614cf6 545 clk_prepare_enable(i2s->op_clk);
1c7ac018
JB		 546 i2s->rclk_srcrate = clk_get_rate(i2s->op_clk);
547
548 /* Over-ride the other's */
549 if (other) {
550 other->op_clk = i2s->op_clk;
551 other->rclk_srcrate = i2s->rclk_srcrate;
552 }
a5a56871
PV		 553 } else if ((!clk_id && (mod & rsrc_mask))
554 || (clk_id && !(mod & rsrc_mask))) {
1c7ac018
JB		 555 dev_err(&i2s->pdev->dev,
556 "%s:%d Other DAI busy\n", __func__, __LINE__);
557 return -EAGAIN;
558 } else {
559 /* Call can't be on the active DAI */
560 i2s->op_clk = other->op_clk;
561 i2s->rclk_srcrate = other->rclk_srcrate;
562 return 0;
563 }
564
ce8bcdbb
SN		 565 if (clk_id == 1)
566 val = 1 << i2s_regs->rclksrc_off;
b2de1d20 567 break;
1c7ac018
JB		 568 default:
569 dev_err(&i2s->pdev->dev, "We don't serve that!\n");
570 return -EINVAL;
571 }
572
ce8bcdbb
SN		 573 spin_lock(i2s->lock);
574 mod = readl(i2s->addr + I2SMOD);
575 mod = (mod & ~mask) | val;
1c7ac018 576 writel(mod, i2s->addr + I2SMOD);
ce8bcdbb 577 spin_unlock(i2s->lock);
1c7ac018
JB		 578
579 return 0;
580}
581
582static int i2s_set_fmt(struct snd_soc_dai *dai,
583 unsigned int fmt)
584{
585 struct i2s_dai *i2s = to_info(dai);
a5a56871 586 int lrp_shift, sdf_shift, sdf_mask, lrp_rlow, mod_slave;
ce8bcdbb 587 u32 mod, tmp = 0;
1c7ac018 588
a5a56871
PV		 589 lrp_shift = i2s->variant_regs->lrp_off;
590 sdf_shift = i2s->variant_regs->sdf_off;
591 mod_slave = 1 << i2s->variant_regs->mss_off;
4ca0c0d4 592
b60be4aa
PV		 593 sdf_mask = MOD_SDF_MASK << sdf_shift;
594 lrp_rlow = MOD_LR_RLOW << lrp_shift;
595
1c7ac018
JB		 596 /* Format is priority */
597 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
598 case SND_SOC_DAIFMT_RIGHT_J:
b60be4aa
PV		 599 tmp |= lrp_rlow;
600 tmp |= (MOD_SDF_MSB << sdf_shift);
1c7ac018
JB		 601 break;
602 case SND_SOC_DAIFMT_LEFT_J:
b60be4aa
PV		 603 tmp |= lrp_rlow;
604 tmp |= (MOD_SDF_LSB << sdf_shift);
1c7ac018
JB		 605 break;
606 case SND_SOC_DAIFMT_I2S:
b60be4aa 607 tmp |= (MOD_SDF_IIS << sdf_shift);
1c7ac018
JB		 608 break;
609 default:
610 dev_err(&i2s->pdev->dev, "Format not supported\n");
611 return -EINVAL;
612 }
613
614 /*
615 * INV flag is relative to the FORMAT flag - if set it simply
616 * flips the polarity specified by the Standard
617 */
618 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
619 case SND_SOC_DAIFMT_NB_NF:
620 break;
621 case SND_SOC_DAIFMT_NB_IF:
b60be4aa
PV		 622 if (tmp & lrp_rlow)
623 tmp &= ~lrp_rlow;
1c7ac018 624 else
b60be4aa 625 tmp |= lrp_rlow;
1c7ac018
JB		 626 break;
627 default:
628 dev_err(&i2s->pdev->dev, "Polarity not supported\n");
629 return -EINVAL;
630 }
631
632 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
633 case SND_SOC_DAIFMT_CBM_CFM:
a5a56871 634 tmp |= mod_slave;
1c7ac018
JB		 635 break;
636 case SND_SOC_DAIFMT_CBS_CFS:
637 /* Set default source clock in Master mode */
638 if (i2s->rclk_srcrate == 0)
639 i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0,
640 0, SND_SOC_CLOCK_IN);
641 break;
642 default:
643 dev_err(&i2s->pdev->dev, "master/slave format not supported\n");
644 return -EINVAL;
645 }
646
ce8bcdbb
SN		 647 spin_lock(i2s->lock);
648 mod = readl(i2s->addr + I2SMOD);
b60be4aa
PV		 649 /*
650 * Don't change the I2S mode if any controller is active on this
651 * channel.
652 */
1c7ac018 653 if (any_active(i2s) &&
a5a56871 654 ((mod & (sdf_mask | lrp_rlow | mod_slave)) != tmp)) {
ce8bcdbb 655 spin_unlock(i2s->lock);
1c7ac018
JB		 656 dev_err(&i2s->pdev->dev,
657 "%s:%d Other DAI busy\n", __func__, __LINE__);
658 return -EAGAIN;
659 }
660
a5a56871 661 mod &= ~(sdf_mask | lrp_rlow | mod_slave);
1c7ac018
JB		 662 mod |= tmp;
663 writel(mod, i2s->addr + I2SMOD);
ce8bcdbb 664 spin_unlock(i2s->lock);
1c7ac018
JB		 665
666 return 0;
667}
668
669static int i2s_hw_params(struct snd_pcm_substream *substream,
670 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
671{
672 struct i2s_dai *i2s = to_info(dai);
ce8bcdbb 673 u32 mod, mask = 0, val = 0;
1c7ac018
JB		 674
675 if (!is_secondary(i2s))
ce8bcdbb 676 mask |= (MOD_DC2_EN | MOD_DC1_EN);
1c7ac018
JB		 677
678 switch (params_channels(params)) {
679 case 6:
ce8bcdbb 680 val |= MOD_DC2_EN;
1c7ac018 681 case 4:
ce8bcdbb 682 val |= MOD_DC1_EN;
1c7ac018
JB		 683 break;
684 case 2:
588fb705
SP		 685 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
686 i2s->dma_playback.dma_size = 4;
687 else
688 i2s->dma_capture.dma_size = 4;
689 break;
690 case 1:
691 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
692 i2s->dma_playback.dma_size = 2;
693 else
694 i2s->dma_capture.dma_size = 2;
695
1c7ac018
JB		 696 break;
697 default:
698 dev_err(&i2s->pdev->dev, "%d channels not supported\n",
699 params_channels(params));
700 return -EINVAL;
701 }
702
703 if (is_secondary(i2s))
ce8bcdbb 704 mask |= MOD_BLCS_MASK;
1c7ac018 705 else
ce8bcdbb 706 mask |= MOD_BLCP_MASK;
1c7ac018
JB		 707
708 if (is_manager(i2s))
ce8bcdbb 709 mask |= MOD_BLC_MASK;
1c7ac018 710
88ce1465
TB		 711 switch (params_width(params)) {
712 case 8:
1c7ac018 713 if (is_secondary(i2s))
ce8bcdbb 714 val |= MOD_BLCS_8BIT;
1c7ac018 715 else
ce8bcdbb 716 val |= MOD_BLCP_8BIT;
1c7ac018 717 if (is_manager(i2s))
ce8bcdbb 718 val |= MOD_BLC_8BIT;
1c7ac018 719 break;
88ce1465 720 case 16:
1c7ac018 721 if (is_secondary(i2s))
ce8bcdbb 722 val |= MOD_BLCS_16BIT;
1c7ac018 723 else
ce8bcdbb 724 val |= MOD_BLCP_16BIT;
1c7ac018 725 if (is_manager(i2s))
ce8bcdbb 726 val |= MOD_BLC_16BIT;
1c7ac018 727 break;
88ce1465 728 case 24:
1c7ac018 729 if (is_secondary(i2s))
ce8bcdbb 730 val |= MOD_BLCS_24BIT;
1c7ac018 731 else
ce8bcdbb 732 val |= MOD_BLCP_24BIT;
1c7ac018 733 if (is_manager(i2s))
ce8bcdbb 734 val |= MOD_BLC_24BIT;
1c7ac018
JB		 735 break;
736 default:
737 dev_err(&i2s->pdev->dev, "Format(%d) not supported\n",
738 params_format(params));
739 return -EINVAL;
740 }
ce8bcdbb
SN		 741
742 spin_lock(i2s->lock);
743 mod = readl(i2s->addr + I2SMOD);
744 mod = (mod & ~mask) | val;
1c7ac018 745 writel(mod, i2s->addr + I2SMOD);
ce8bcdbb 746 spin_unlock(i2s->lock);
1c7ac018 747
d37bdf73
MB		 748 samsung_asoc_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture);
749
1c7ac018
JB		 750 i2s->frmclk = params_rate(params);
751
752 return 0;
753}
754
755/* We set constraints on the substream acc to the version of I2S */
756static int i2s_startup(struct snd_pcm_substream *substream,
757 struct snd_soc_dai *dai)
758{
759 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 760 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 761 unsigned long flags;
762
763 spin_lock_irqsave(&lock, flags);
764
765 i2s->mode |= DAI_OPENED;
766
767 if (is_manager(other))
768 i2s->mode &= ~DAI_MANAGER;
769 else
770 i2s->mode |= DAI_MANAGER;
771
2d77828d
PV		 772 if (!any_active(i2s) && (i2s->quirks & QUIRK_NEED_RSTCLR))
773 writel(CON_RSTCLR, i2s->addr + I2SCON);
774
1c7ac018
JB		 775 spin_unlock_irqrestore(&lock, flags);
776
b97c60ab
SN		 777 if (!is_opened(other) && i2s->cdclk_out)
778 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
779 0, SND_SOC_CLOCK_OUT);
1c7ac018
JB		 780 return 0;
781}
782
783static void i2s_shutdown(struct snd_pcm_substream *substream,
784 struct snd_soc_dai *dai)
785{
786 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 787 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018 788 unsigned long flags;
a5a56871 789 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
1c7ac018
JB		 790
791 spin_lock_irqsave(&lock, flags);
792
793 i2s->mode &= ~DAI_OPENED;
794 i2s->mode &= ~DAI_MANAGER;
795
b97c60ab 796 if (is_opened(other)) {
1c7ac018 797 other->mode |= DAI_MANAGER;
b97c60ab
SN		 798 } else {
799 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871 800 i2s->cdclk_out = !(mod & (1 << i2s_regs->cdclkcon_off));
133c2681
CK		 801 if (other)
802 other->cdclk_out = i2s->cdclk_out;
b97c60ab 803 }
1c7ac018
JB		 804 /* Reset any constraint on RFS and BFS */
805 i2s->rfs = 0;
806 i2s->bfs = 0;
807
808 spin_unlock_irqrestore(&lock, flags);
809
810 /* Gate CDCLK by default */
811 if (!is_opened(other))
812 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
813 0, SND_SOC_CLOCK_IN);
814}
815
816static int config_setup(struct i2s_dai *i2s)
817{
dcd60fc3 818 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 819 unsigned rfs, bfs, blc;
820 u32 psr;
821
822 blc = get_blc(i2s);
823
824 bfs = i2s->bfs;
825
826 if (!bfs && other)
827 bfs = other->bfs;
828
829 /* Select least possible multiple(2) if no constraint set */
830 if (!bfs)
831 bfs = blc * 2;
832
833 rfs = i2s->rfs;
834
835 if (!rfs && other)
836 rfs = other->rfs;
837
838 if ((rfs == 256 || rfs == 512) && (blc == 24)) {
839 dev_err(&i2s->pdev->dev,
840 "%d-RFS not supported for 24-blc\n", rfs);
841 return -EINVAL;
842 }
843
844 if (!rfs) {
845 if (bfs == 16 || bfs == 32)
846 rfs = 256;
847 else
848 rfs = 384;
849 }
850
851 /* If already setup and running */
852 if (any_active(i2s) && (get_rfs(i2s) != rfs || get_bfs(i2s) != bfs)) {
853 dev_err(&i2s->pdev->dev,
854 "%s:%d Other DAI busy\n", __func__, __LINE__);
855 return -EAGAIN;
856 }
857
1c7ac018
JB		 858 set_bfs(i2s, bfs);
859 set_rfs(i2s, rfs);
860
77010010
PV		 861 /* Don't bother with PSR in Slave mode */
862 if (is_slave(i2s))
863 return 0;
864
1c7ac018
JB		 865 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) {
866 psr = i2s->rclk_srcrate / i2s->frmclk / rfs;
867 writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR);
868 dev_dbg(&i2s->pdev->dev,
869 "RCLK_SRC=%luHz PSR=%u, RCLK=%dfs, BCLK=%dfs\n",
870 i2s->rclk_srcrate, psr, rfs, bfs);
871 }
872
873 return 0;
874}
875
876static int i2s_trigger(struct snd_pcm_substream *substream,
877 int cmd, struct snd_soc_dai *dai)
878{
879 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
880 struct snd_soc_pcm_runtime *rtd = substream->private_data;
881 struct i2s_dai *i2s = to_info(rtd->cpu_dai);
882 unsigned long flags;
883
884 switch (cmd) {
885 case SNDRV_PCM_TRIGGER_START:
886 case SNDRV_PCM_TRIGGER_RESUME:
887 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
f3670536 888 spin_lock_irqsave(i2s->lock, flags);
1c7ac018 889
1c7ac018 890 if (config_setup(i2s)) {
f3670536 891 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 892 return -EINVAL;
893 }
894
895 if (capture)
896 i2s_rxctrl(i2s, 1);
897 else
898 i2s_txctrl(i2s, 1);
899
f3670536 900 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 901 break;
902 case SNDRV_PCM_TRIGGER_STOP:
903 case SNDRV_PCM_TRIGGER_SUSPEND:
904 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
f3670536 905 spin_lock_irqsave(i2s->lock, flags);
1c7ac018 906
c90887fe 907 if (capture) {
1c7ac018 908 i2s_rxctrl(i2s, 0);
775bc971 909 i2s_fifo(i2s, FIC_RXFLUSH);
c90887fe
JB		 910 } else {
911 i2s_txctrl(i2s, 0);
775bc971 912 i2s_fifo(i2s, FIC_TXFLUSH);
c90887fe 913 }
775bc971 914
f3670536 915 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 916 break;
917 }
918
919 return 0;
920}
921
922static int i2s_set_clkdiv(struct snd_soc_dai *dai,
923 int div_id, int div)
924{
925 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 926 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 927
928 switch (div_id) {
929 case SAMSUNG_I2S_DIV_BCLK:
930 if ((any_active(i2s) && div && (get_bfs(i2s) != div))
931 || (other && other->bfs && (other->bfs != div))) {
932 dev_err(&i2s->pdev->dev,
933 "%s:%d Other DAI busy\n", __func__, __LINE__);
934 return -EAGAIN;
935 }
936 i2s->bfs = div;
937 break;
938 default:
939 dev_err(&i2s->pdev->dev,
940 "Invalid clock divider(%d)\n", div_id);
941 return -EINVAL;
942 }
943
944 return 0;
945}
946
947static snd_pcm_sframes_t
948i2s_delay(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
949{
950 struct i2s_dai *i2s = to_info(dai);
951 u32 reg = readl(i2s->addr + I2SFIC);
952 snd_pcm_sframes_t delay;
a5a56871 953 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
1c7ac018
JB		 954
955 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
956 delay = FIC_RXCOUNT(reg);
957 else if (is_secondary(i2s))
958 delay = FICS_TXCOUNT(readl(i2s->addr + I2SFICS));
959 else
a5a56871 960 delay = (reg >> i2s_regs->ftx0cnt_off) & 0x7f;
1c7ac018
JB		 961
962 return delay;
963}
964
965#ifdef CONFIG_PM
966static int i2s_suspend(struct snd_soc_dai *dai)
967{
968 struct i2s_dai *i2s = to_info(dai);
969
d3d4e524
SN		 970 i2s->suspend_i2smod = readl(i2s->addr + I2SMOD);
971 i2s->suspend_i2scon = readl(i2s->addr + I2SCON);
972 i2s->suspend_i2spsr = readl(i2s->addr + I2SPSR);
1c7ac018
JB		 973
974 return 0;
975}
976
977static int i2s_resume(struct snd_soc_dai *dai)
978{
979 struct i2s_dai *i2s = to_info(dai);
980
d3d4e524
SN		 981 writel(i2s->suspend_i2scon, i2s->addr + I2SCON);
982 writel(i2s->suspend_i2smod, i2s->addr + I2SMOD);
983 writel(i2s->suspend_i2spsr, i2s->addr + I2SPSR);
1c7ac018
JB		 984
985 return 0;
986}
987#else
988#define i2s_suspend NULL
989#define i2s_resume NULL
990#endif
991
992static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
993{
994 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 995 struct i2s_dai *other = get_other_dai(i2s);
ce8bcdbb 996 unsigned long flags;
1c7ac018 997
0ec2ba80 998 if (is_secondary(i2s)) { /* If this is probe on the secondary DAI */
3688569e
MB		 999 samsung_asoc_init_dma_data(dai, &other->sec_dai->dma_playback,
1000 NULL);
872c26bd
SN		 1001 } else {
1002 samsung_asoc_init_dma_data(dai, &i2s->dma_playback,
1003 &i2s->dma_capture);
511e3033 1004
872c26bd
SN		 1005 if (i2s->quirks & QUIRK_NEED_RSTCLR)
1006 writel(CON_RSTCLR, i2s->addr + I2SCON);
1c7ac018 1007
872c26bd
SN		 1008 if (i2s->quirks & QUIRK_SUPPORTS_IDMA)
1009 idma_reg_addr_init(i2s->addr,
61100f40 1010 i2s->sec_dai->idma_playback.dma_addr);
872c26bd 1011 }
61100f40 1012
1c7ac018
JB		 1013 /* Reset any constraint on RFS and BFS */
1014 i2s->rfs = 0;
1015 i2s->bfs = 0;
d66eac3e 1016 i2s->rclk_srcrate = 0;
ce8bcdbb
SN		 1017
1018 spin_lock_irqsave(i2s->lock, flags);
1c7ac018
JB		 1019 i2s_txctrl(i2s, 0);
1020 i2s_rxctrl(i2s, 0);
1021 i2s_fifo(i2s, FIC_TXFLUSH);
1022 i2s_fifo(other, FIC_TXFLUSH);
1023 i2s_fifo(i2s, FIC_RXFLUSH);
ce8bcdbb 1024 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 1025
1026 /* Gate CDCLK by default */
1027 if (!is_opened(other))
1028 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
1029 0, SND_SOC_CLOCK_IN);
1030
1031 return 0;
1032}
1033
1034static int samsung_i2s_dai_remove(struct snd_soc_dai *dai)
1035{
1036 struct i2s_dai *i2s = snd_soc_dai_get_drvdata(dai);
1c7ac018 1037
c92f1d0e 1038 if (!is_secondary(i2s)) {
ce8bcdbb
SN		 1039 if (i2s->quirks & QUIRK_NEED_RSTCLR) {
1040 spin_lock(i2s->lock);
1c7ac018 1041 writel(0, i2s->addr + I2SCON);
ce8bcdbb
SN		 1042 spin_unlock(i2s->lock);
1043 }
1c7ac018
JB		 1044 }
1045
1c7ac018
JB		 1046 return 0;
1047}
1048
85e7652d 1049static const struct snd_soc_dai_ops samsung_i2s_dai_ops = {
1c7ac018
JB		 1050 .trigger = i2s_trigger,
1051 .hw_params = i2s_hw_params,
1052 .set_fmt = i2s_set_fmt,
1053 .set_clkdiv = i2s_set_clkdiv,
1054 .set_sysclk = i2s_set_sysclk,
1055 .startup = i2s_startup,
1056 .shutdown = i2s_shutdown,
1057 .delay = i2s_delay,
1058};
1059
4b828535
KM		 1060static const struct snd_soc_component_driver samsung_i2s_component = {
1061 .name = "samsung-i2s",
1062};
1063
1c7ac018
JB		 1064#define SAMSUNG_I2S_RATES SNDRV_PCM_RATE_8000_96000
1065
1066#define SAMSUNG_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1067 SNDRV_PCM_FMTBIT_S16_LE | \
1068 SNDRV_PCM_FMTBIT_S24_LE)
1069
fdca21ad 1070static struct i2s_dai *i2s_alloc_dai(struct platform_device *pdev, bool sec)
1c7ac018
JB		 1071{
1072 struct i2s_dai *i2s;
c6f9b1eb 1073 int ret;
1c7ac018 1074
b960ce74 1075 i2s = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dai), GFP_KERNEL);
1c7ac018
JB		 1076 if (i2s == NULL)
1077 return NULL;
1078
1079 i2s->pdev = pdev;
1080 i2s->pri_dai = NULL;
1081 i2s->sec_dai = NULL;
1082 i2s->i2s_dai_drv.symmetric_rates = 1;
1083 i2s->i2s_dai_drv.probe = samsung_i2s_dai_probe;
1084 i2s->i2s_dai_drv.remove = samsung_i2s_dai_remove;
1085 i2s->i2s_dai_drv.ops = &samsung_i2s_dai_ops;
1086 i2s->i2s_dai_drv.suspend = i2s_suspend;
1087 i2s->i2s_dai_drv.resume = i2s_resume;
a0ff6ea2 1088 i2s->i2s_dai_drv.playback.channels_min = 1;
1c7ac018
JB		 1089 i2s->i2s_dai_drv.playback.channels_max = 2;
1090 i2s->i2s_dai_drv.playback.rates = SAMSUNG_I2S_RATES;
1091 i2s->i2s_dai_drv.playback.formats = SAMSUNG_I2S_FMTS;
1092
1093 if (!sec) {
588fb705 1094 i2s->i2s_dai_drv.capture.channels_min = 1;
1c7ac018
JB		 1095 i2s->i2s_dai_drv.capture.channels_max = 2;
1096 i2s->i2s_dai_drv.capture.rates = SAMSUNG_I2S_RATES;
1097 i2s->i2s_dai_drv.capture.formats = SAMSUNG_I2S_FMTS;
c6f9b1eb 1098 dev_set_drvdata(&i2s->pdev->dev, i2s);
1c7ac018 1099 } else { /* Create a new platform_device for Secondary */
c6f9b1eb 1100 i2s->pdev = platform_device_alloc("samsung-i2s-sec", -1);
29ca9c73 1101 if (!i2s->pdev)
1c7ac018 1102 return NULL;
1c7ac018 1103
2f6f0ffb
MB		 1104 i2s->pdev->dev.parent = &pdev->dev;
1105
c6f9b1eb
P		 1106 platform_set_drvdata(i2s->pdev, i2s);
1107 ret = platform_device_add(i2s->pdev);
1108 if (ret < 0)
1109 return NULL;
1110 }
1c7ac018
JB		 1111
1112 return i2s;
1113}
1114
40476f61
PV		 1115static const struct of_device_id exynos_i2s_match[];
1116
7da493e9
PV		 1117static inline const struct samsung_i2s_dai_data *samsung_i2s_get_driver_data(
1118 struct platform_device *pdev)
7c62eebb 1119{
9cf24747 1120 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
40476f61
PV		 1121 const struct of_device_id *match;
1122 match = of_match_node(exynos_i2s_match, pdev->dev.of_node);
9cf24747
SN		 1123 return match ? match->data : NULL;
1124 } else {
7da493e9
PV		 1125 return (struct samsung_i2s_dai_data *)
1126 platform_get_device_id(pdev)->driver_data;
9cf24747 1127 }
7c62eebb
PV		 1128}
1129
641d334b 1130#ifdef CONFIG_PM
5b1d3c34
C		 1131static int i2s_runtime_suspend(struct device *dev)
1132{
1133 struct i2s_dai *i2s = dev_get_drvdata(dev);
1134
1135 clk_disable_unprepare(i2s->clk);
1136
1137 return 0;
1138}
1139
1140static int i2s_runtime_resume(struct device *dev)
1141{
1142 struct i2s_dai *i2s = dev_get_drvdata(dev);
1143
1144 clk_prepare_enable(i2s->clk);
1145
1146 return 0;
1147}
641d334b 1148#endif /* CONFIG_PM */
5b1d3c34 1149
fdca21ad 1150static int samsung_i2s_probe(struct platform_device *pdev)
1c7ac018 1151{
1c7ac018 1152 struct i2s_dai *pri_dai, *sec_dai = NULL;
40476f61
PV		 1153 struct s3c_audio_pdata *i2s_pdata = pdev->dev.platform_data;
1154 struct samsung_i2s *i2s_cfg = NULL;
1c7ac018 1155 struct resource *res;
40476f61
PV		 1156 u32 regs_base, quirks = 0, idma_addr = 0;
1157 struct device_node *np = pdev->dev.of_node;
7da493e9 1158 const struct samsung_i2s_dai_data *i2s_dai_data;
c92f1d0e 1159 int ret;
1c7ac018
JB		 1160
1161 /* Call during Seconday interface registration */
7da493e9 1162 i2s_dai_data = samsung_i2s_get_driver_data(pdev);
7c62eebb 1163
7da493e9 1164 if (i2s_dai_data->dai_type == TYPE_SEC) {
1c7ac018 1165 sec_dai = dev_get_drvdata(&pdev->dev);
a9b977ec
P		 1166 if (!sec_dai) {
1167 dev_err(&pdev->dev, "Unable to get drvdata\n");
1168 return -EFAULT;
1169 }
53f7faa1 1170 ret = devm_snd_soc_register_component(&sec_dai->pdev->dev,
d644a115
MB		 1171 &samsung_i2s_component,
1172 &sec_dai->i2s_dai_drv, 1);
53f7faa1
SN		 1173 if (ret != 0)
1174 return ret;
1175
1176 return samsung_asoc_dma_platform_register(&pdev->dev);
1c7ac018
JB		 1177 }
1178
40476f61
PV		 1179 pri_dai = i2s_alloc_dai(pdev, false);
1180 if (!pri_dai) {
1181 dev_err(&pdev->dev, "Unable to alloc I2S_pri\n");
1182 return -ENOMEM;
1c7ac018
JB		 1183 }
1184
f3670536
SN		 1185 spin_lock_init(&pri_dai->spinlock);
1186 pri_dai->lock = &pri_dai->spinlock;
1187
40476f61
PV		 1188 if (!np) {
1189 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1190 if (!res) {
1191 dev_err(&pdev->dev,
1192 "Unable to get I2S-TX dma resource\n");
1193 return -ENXIO;
1194 }
1195 pri_dai->dma_playback.channel = res->start;
1c7ac018 1196
40476f61
PV		 1197 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1198 if (!res) {
1199 dev_err(&pdev->dev,
1200 "Unable to get I2S-RX dma resource\n");
1201 return -ENXIO;
1202 }
1203 pri_dai->dma_capture.channel = res->start;
1c7ac018 1204
40476f61
PV		 1205 if (i2s_pdata == NULL) {
1206 dev_err(&pdev->dev, "Can't work without s3c_audio_pdata\n");
1207 return -EINVAL;
1208 }
1209
1210 if (&i2s_pdata->type)
1211 i2s_cfg = &i2s_pdata->type.i2s;
1212
1213 if (i2s_cfg) {
1214 quirks = i2s_cfg->quirks;
1215 idma_addr = i2s_cfg->idma_addr;
1216 }
1217 } else {
7da493e9 1218 quirks = i2s_dai_data->quirks;
40476f61
PV		 1219 if (of_property_read_u32(np, "samsung,idma-addr",
1220 &idma_addr)) {
b0759736
PV		 1221 if (quirks & QUIRK_SUPPORTS_IDMA) {
1222 dev_info(&pdev->dev, "idma address is not"\
40476f61 1223 "specified");
40476f61
PV		 1224 }
1225 }
1226 }
1c7ac018
JB		 1227
1228 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
af1cf5cf
SN		 1229 pri_dai->addr = devm_ioremap_resource(&pdev->dev, res);
1230 if (IS_ERR(pri_dai->addr))
1231 return PTR_ERR(pri_dai->addr);
1c7ac018 1232
1c7ac018
JB		 1233 regs_base = res->start;
1234
0ec2ba80
SN		 1235 pri_dai->clk = devm_clk_get(&pdev->dev, "iis");
1236 if (IS_ERR(pri_dai->clk)) {
1237 dev_err(&pdev->dev, "Failed to get iis clock\n");
1238 return PTR_ERR(pri_dai->clk);
1239 }
c92f1d0e
SN		 1240
1241 ret = clk_prepare_enable(pri_dai->clk);
1242 if (ret != 0) {
1243 dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
1244 return ret;
1245 }
1c7ac018
JB		 1246 pri_dai->dma_playback.dma_addr = regs_base + I2STXD;
1247 pri_dai->dma_capture.dma_addr = regs_base + I2SRXD;
40476f61 1248 pri_dai->dma_playback.ch_name = "tx";
40476f61 1249 pri_dai->dma_capture.ch_name = "rx";
1c7ac018
JB		 1250 pri_dai->dma_playback.dma_size = 4;
1251 pri_dai->dma_capture.dma_size = 4;
1c7ac018 1252 pri_dai->quirks = quirks;
a5a56871 1253 pri_dai->variant_regs = i2s_dai_data->i2s_variant_regs;
1c7ac018
JB		 1254
1255 if (quirks & QUIRK_PRI_6CHAN)
1256 pri_dai->i2s_dai_drv.playback.channels_max = 6;
1257
1258 if (quirks & QUIRK_SEC_DAI) {
1259 sec_dai = i2s_alloc_dai(pdev, true);
1260 if (!sec_dai) {
1261 dev_err(&pdev->dev, "Unable to alloc I2S_sec\n");
af1cf5cf 1262 return -ENOMEM;
1c7ac018 1263 }
7e5d8706 1264
f3670536 1265 sec_dai->lock = &pri_dai->spinlock;
7e5d8706 1266 sec_dai->variant_regs = pri_dai->variant_regs;
1c7ac018 1267 sec_dai->dma_playback.dma_addr = regs_base + I2STXDS;
40476f61
PV		 1268 sec_dai->dma_playback.ch_name = "tx-sec";
1269
1270 if (!np) {
1271 res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
1272 if (res)
1273 sec_dai->dma_playback.channel = res->start;
1274 }
1275
1c7ac018 1276 sec_dai->dma_playback.dma_size = 4;
af1cf5cf 1277 sec_dai->addr = pri_dai->addr;
0ec2ba80 1278 sec_dai->clk = pri_dai->clk;
1c7ac018 1279 sec_dai->quirks = quirks;
40476f61 1280 sec_dai->idma_playback.dma_addr = idma_addr;
1c7ac018
JB		 1281 sec_dai->pri_dai = pri_dai;
1282 pri_dai->sec_dai = sec_dai;
1283 }
1284
0429ffef
MB		 1285 if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
1286 dev_err(&pdev->dev, "Unable to configure gpio\n");
af1cf5cf 1287 return -EINVAL;
1c7ac018
JB		 1288 }
1289
d644a115
MB		 1290 devm_snd_soc_register_component(&pri_dai->pdev->dev,
1291 &samsung_i2s_component,
1292 &pri_dai->i2s_dai_drv, 1);
1c7ac018 1293
c5cf4dbc
MB		 1294 pm_runtime_enable(&pdev->dev);
1295
53f7faa1
SN		 1296 ret = samsung_asoc_dma_platform_register(&pdev->dev);
1297 if (ret != 0)
1298 return ret;
a08485d8 1299
1c7ac018 1300 return 0;
1c7ac018
JB		 1301}
1302
fdca21ad 1303static int samsung_i2s_remove(struct platform_device *pdev)
1c7ac018
JB		 1304{
1305 struct i2s_dai *i2s, *other;
1306
1307 i2s = dev_get_drvdata(&pdev->dev);
dcd60fc3 1308 other = get_other_dai(i2s);
1c7ac018
JB		 1309
1310 if (other) {
1311 other->pri_dai = NULL;
1312 other->sec_dai = NULL;
1313 } else {
c5cf4dbc 1314 pm_runtime_disable(&pdev->dev);
1c7ac018
JB		 1315 }
1316
c92f1d0e
SN		 1317 if (!is_secondary(i2s))
1318 clk_disable_unprepare(i2s->clk);
1319
1c7ac018
JB		 1320 i2s->pri_dai = NULL;
1321 i2s->sec_dai = NULL;
1322
1c7ac018
JB		 1323 return 0;
1324}
1325
a5a56871
PV		 1326static const struct samsung_i2s_variant_regs i2sv3_regs = {
1327 .bfs_off = 1,
1328 .rfs_off = 3,
1329 .sdf_off = 5,
1330 .txr_off = 8,
1331 .rclksrc_off = 10,
1332 .mss_off = 11,
1333 .cdclkcon_off = 12,
1334 .lrp_off = 7,
1335 .bfs_mask = 0x3,
1336 .rfs_mask = 0x3,
1337 .ftx0cnt_off = 8,
1338};
1339
1340static const struct samsung_i2s_variant_regs i2sv6_regs = {
1341 .bfs_off = 0,
1342 .rfs_off = 4,
1343 .sdf_off = 6,
1344 .txr_off = 8,
1345 .rclksrc_off = 10,
1346 .mss_off = 11,
1347 .cdclkcon_off = 12,
1348 .lrp_off = 15,
1349 .bfs_mask = 0xf,
1350 .rfs_mask = 0x3,
1351 .ftx0cnt_off = 8,
1352};
1353
1354static const struct samsung_i2s_variant_regs i2sv7_regs = {
1355 .bfs_off = 0,
1356 .rfs_off = 4,
1357 .sdf_off = 7,
1358 .txr_off = 9,
1359 .rclksrc_off = 11,
1360 .mss_off = 12,
1361 .cdclkcon_off = 22,
1362 .lrp_off = 15,
1363 .bfs_mask = 0xf,
1364 .rfs_mask = 0x7,
1365 .ftx0cnt_off = 0,
1366};
1367
1368static const struct samsung_i2s_variant_regs i2sv5_i2s1_regs = {
1369 .bfs_off = 0,
1370 .rfs_off = 3,
1371 .sdf_off = 6,
1372 .txr_off = 8,
1373 .rclksrc_off = 10,
1374 .mss_off = 11,
1375 .cdclkcon_off = 12,
1376 .lrp_off = 15,
1377 .bfs_mask = 0x7,
1378 .rfs_mask = 0x7,
1379 .ftx0cnt_off = 8,
1380};
1381
7da493e9
PV		 1382static const struct samsung_i2s_dai_data i2sv3_dai_type = {
1383 .dai_type = TYPE_PRI,
1384 .quirks = QUIRK_NO_MUXPSR,
a5a56871 1385 .i2s_variant_regs = &i2sv3_regs,
7da493e9
PV		 1386};
1387
1388static const struct samsung_i2s_dai_data i2sv5_dai_type = {
1389 .dai_type = TYPE_PRI,
b0759736
PV		 1390 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1391 QUIRK_SUPPORTS_IDMA,
a5a56871 1392 .i2s_variant_regs = &i2sv3_regs,
7da493e9
PV		 1393};
1394
4ca0c0d4
PV		 1395static const struct samsung_i2s_dai_data i2sv6_dai_type = {
1396 .dai_type = TYPE_PRI,
1397 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
b0759736 1398 QUIRK_SUPPORTS_TDM | QUIRK_SUPPORTS_IDMA,
a5a56871
PV		 1399 .i2s_variant_regs = &i2sv6_regs,
1400};
1401
1402static const struct samsung_i2s_dai_data i2sv7_dai_type = {
1403 .dai_type = TYPE_PRI,
1404 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1405 QUIRK_SUPPORTS_TDM,
1406 .i2s_variant_regs = &i2sv7_regs,
1407};
1408
1409static const struct samsung_i2s_dai_data i2sv5_dai_type_i2s1 = {
1410 .dai_type = TYPE_PRI,
1411 .quirks = QUIRK_PRI_6CHAN | QUIRK_NEED_RSTCLR,
1412 .i2s_variant_regs = &i2sv5_i2s1_regs,
4ca0c0d4
PV		 1413};
1414
7da493e9
PV		 1415static const struct samsung_i2s_dai_data samsung_dai_type_pri = {
1416 .dai_type = TYPE_PRI,
1417};
1418
1419static const struct samsung_i2s_dai_data samsung_dai_type_sec = {
1420 .dai_type = TYPE_SEC,
1421};
1422
7c62eebb
PV		 1423static struct platform_device_id samsung_i2s_driver_ids[] = {
1424 {
1425 .name = "samsung-i2s",
3f024980 1426 .driver_data = (kernel_ulong_t)&i2sv3_dai_type,
7c62eebb
PV		 1427 }, {
1428 .name = "samsung-i2s-sec",
7da493e9 1429 .driver_data = (kernel_ulong_t)&samsung_dai_type_sec,
3f024980
MB		 1430 }, {
1431 .name = "samsung-i2sv4",
1432 .driver_data = (kernel_ulong_t)&i2sv5_dai_type,
7c62eebb
PV		 1433 },
1434 {},
1435};
2af19558 1436MODULE_DEVICE_TABLE(platform, samsung_i2s_driver_ids);
7c62eebb 1437
40476f61 1438#ifdef CONFIG_OF
40476f61 1439static const struct of_device_id exynos_i2s_match[] = {
7da493e9
PV		 1440 {
1441 .compatible = "samsung,s3c6410-i2s",
1442 .data = &i2sv3_dai_type,
1443 }, {
1444 .compatible = "samsung,s5pv210-i2s",
1445 .data = &i2sv5_dai_type,
4ca0c0d4
PV		 1446 }, {
1447 .compatible = "samsung,exynos5420-i2s",
1448 .data = &i2sv6_dai_type,
a5a56871
PV		 1449 }, {
1450 .compatible = "samsung,exynos7-i2s",
1451 .data = &i2sv7_dai_type,
1452 }, {
1453 .compatible = "samsung,exynos7-i2s1",
1454 .data = &i2sv5_dai_type_i2s1,
40476f61
PV		 1455 },
1456 {},
1457};
1458MODULE_DEVICE_TABLE(of, exynos_i2s_match);
1459#endif
1460
5b1d3c34
C		 1461static const struct dev_pm_ops samsung_i2s_pm = {
1462 SET_RUNTIME_PM_OPS(i2s_runtime_suspend,
1463 i2s_runtime_resume, NULL)
1464};
1465
1c7ac018
JB		 1466static struct platform_driver samsung_i2s_driver = {
1467 .probe = samsung_i2s_probe,
fdca21ad 1468 .remove = samsung_i2s_remove,
7c62eebb 1469 .id_table = samsung_i2s_driver_ids,
1c7ac018
JB		 1470 .driver = {
1471 .name = "samsung-i2s",
40476f61 1472 .of_match_table = of_match_ptr(exynos_i2s_match),
5b1d3c34 1473 .pm = &samsung_i2s_pm,
1c7ac018
JB		 1474 },
1475};
1476
e00c3f55 1477module_platform_driver(samsung_i2s_driver);
1c7ac018
JB		 1478
1479/* Module information */
df8ad335 1480MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
1c7ac018
JB		 1481MODULE_DESCRIPTION("Samsung I2S Interface");
1482MODULE_ALIAS("platform:samsung-i2s");
1483MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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