projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: samsung: i2s: Move clk_get() to platform driver probe()
[deliverable/linux.git] / sound / soc / samsung / i2s.c
CommitLineData
5033f43c 1/* sound/soc/samsung/i2s.c
1c7ac018
JB		 2 *
3 * ALSA SoC Audio Layer - Samsung I2S Controller driver
4 *
5 * Copyright (c) 2010 Samsung Electronics Co. Ltd.
df8ad335 6 * Jaswinder Singh <jassisinghbrar@gmail.com>
1c7ac018
JB		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/delay.h>
14#include <linux/slab.h>
15#include <linux/clk.h>
16#include <linux/io.h>
da155d5b 17#include <linux/module.h>
40476f61
PV		 18#include <linux/of.h>
19#include <linux/of_gpio.h>
c5cf4dbc 20#include <linux/pm_runtime.h>
1c7ac018 21
1c7ac018 22#include <sound/soc.h>
0378b6ac 23#include <sound/pcm_params.h>
1c7ac018 24
436d42c6 25#include <linux/platform_data/asoc-s3c.h>
1c7ac018
JB		 26
27#include "dma.h"
61100f40 28#include "idma.h"
1c7ac018 29#include "i2s.h"
172a453d 30#include "i2s-regs.h"
1c7ac018
JB		 31
32#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
33
7c62eebb
PV		 34enum samsung_dai_type {
35 TYPE_PRI,
36 TYPE_SEC,
37};
38
a5a56871
PV		 39struct samsung_i2s_variant_regs {
40 unsigned int bfs_off;
41 unsigned int rfs_off;
42 unsigned int sdf_off;
43 unsigned int txr_off;
44 unsigned int rclksrc_off;
45 unsigned int mss_off;
46 unsigned int cdclkcon_off;
47 unsigned int lrp_off;
48 unsigned int bfs_mask;
49 unsigned int rfs_mask;
50 unsigned int ftx0cnt_off;
51};
52
40476f61
PV		 53struct samsung_i2s_dai_data {
54 int dai_type;
7da493e9 55 u32 quirks;
a5a56871 56 const struct samsung_i2s_variant_regs *i2s_variant_regs;
40476f61
PV		 57};
58
1c7ac018
JB		 59struct i2s_dai {
60 /* Platform device for this DAI */
61 struct platform_device *pdev;
af1cf5cf 62 /* Memory mapped SFR region */
1c7ac018 63 void __iomem *addr;
1c7ac018
JB		 64 /* Rate of RCLK source clock */
65 unsigned long rclk_srcrate;
66 /* Frame Clock */
67 unsigned frmclk;
68 /*
69 * Specifically requested RCLK,BCLK by MACHINE Driver.
70 * 0 indicates CPU driver is free to choose any value.
71 */
72 unsigned rfs, bfs;
73 /* I2S Controller's core clock */
74 struct clk *clk;
75 /* Clock for generating I2S signals */
76 struct clk *op_clk;
1c7ac018
JB		 77 /* Pointer to the Primary_Fifo if this is Sec_Fifo, NULL otherwise */
78 struct i2s_dai *pri_dai;
79 /* Pointer to the Secondary_Fifo if it has one, NULL otherwise */
80 struct i2s_dai *sec_dai;
81#define DAI_OPENED (1 << 0) /* Dai is opened */
82#define DAI_MANAGER (1 << 1) /* Dai is the manager */
83 unsigned mode;
b97c60ab
SN		 84 /* CDCLK pin direction: 0 - input, 1 - output */
85 unsigned int cdclk_out:1;
1c7ac018
JB		 86 /* Driver for this DAI */
87 struct snd_soc_dai_driver i2s_dai_drv;
88 /* DMA parameters */
89 struct s3c_dma_params dma_playback;
90 struct s3c_dma_params dma_capture;
61100f40 91 struct s3c_dma_params idma_playback;
1c7ac018
JB		 92 u32 quirks;
93 u32 suspend_i2smod;
94 u32 suspend_i2scon;
95 u32 suspend_i2spsr;
a5a56871 96 const struct samsung_i2s_variant_regs *variant_regs;
1c7ac018
JB		 97};
98
99/* Lock for cross i/f checks */
100static DEFINE_SPINLOCK(lock);
101
102/* If this is the 'overlay' stereo DAI */
103static inline bool is_secondary(struct i2s_dai *i2s)
104{
105 return i2s->pri_dai ? true : false;
106}
107
108/* If operating in SoC-Slave mode */
109static inline bool is_slave(struct i2s_dai *i2s)
110{
a5a56871
PV		 111 u32 mod = readl(i2s->addr + I2SMOD);
112 return (mod & (1 << i2s->variant_regs->mss_off)) ? true : false;
1c7ac018
JB		 113}
114
115/* If this interface of the controller is transmitting data */
116static inline bool tx_active(struct i2s_dai *i2s)
117{
118 u32 active;
119
120 if (!i2s)
121 return false;
122
33195500 123 active = readl(i2s->addr + I2SCON);
1c7ac018
JB		 124
125 if (is_secondary(i2s))
126 active &= CON_TXSDMA_ACTIVE;
127 else
128 active &= CON_TXDMA_ACTIVE;
129
130 return active ? true : false;
131}
132
133/* If the other interface of the controller is transmitting data */
134static inline bool other_tx_active(struct i2s_dai *i2s)
135{
136 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
137
138 return tx_active(other);
139}
140
141/* If any interface of the controller is transmitting data */
142static inline bool any_tx_active(struct i2s_dai *i2s)
143{
144 return tx_active(i2s) || other_tx_active(i2s);
145}
146
147/* If this interface of the controller is receiving data */
148static inline bool rx_active(struct i2s_dai *i2s)
149{
150 u32 active;
151
152 if (!i2s)
153 return false;
154
33195500 155 active = readl(i2s->addr + I2SCON) & CON_RXDMA_ACTIVE;
1c7ac018
JB		 156
157 return active ? true : false;
158}
159
160/* If the other interface of the controller is receiving data */
161static inline bool other_rx_active(struct i2s_dai *i2s)
162{
163 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
164
165 return rx_active(other);
166}
167
168/* If any interface of the controller is receiving data */
169static inline bool any_rx_active(struct i2s_dai *i2s)
170{
171 return rx_active(i2s) || other_rx_active(i2s);
172}
173
174/* If the other DAI is transmitting or receiving data */
175static inline bool other_active(struct i2s_dai *i2s)
176{
177 return other_rx_active(i2s) || other_tx_active(i2s);
178}
179
180/* If this DAI is transmitting or receiving data */
181static inline bool this_active(struct i2s_dai *i2s)
182{
183 return tx_active(i2s) || rx_active(i2s);
184}
185
186/* If the controller is active anyway */
187static inline bool any_active(struct i2s_dai *i2s)
188{
189 return this_active(i2s) || other_active(i2s);
190}
191
192static inline struct i2s_dai *to_info(struct snd_soc_dai *dai)
193{
194 return snd_soc_dai_get_drvdata(dai);
195}
196
197static inline bool is_opened(struct i2s_dai *i2s)
198{
199 if (i2s && (i2s->mode & DAI_OPENED))
200 return true;
201 else
202 return false;
203}
204
205static inline bool is_manager(struct i2s_dai *i2s)
206{
207 if (is_opened(i2s) && (i2s->mode & DAI_MANAGER))
208 return true;
209 else
210 return false;
211}
212
213/* Read RCLK of I2S (in multiples of LRCLK) */
214static inline unsigned get_rfs(struct i2s_dai *i2s)
215{
4ca0c0d4 216 u32 rfs;
a5a56871
PV		 217 rfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->rfs_off;
218 rfs &= i2s->variant_regs->rfs_mask;
1c7ac018
JB		 219
220 switch (rfs) {
a5a56871
PV		 221 case 7: return 192;
222 case 6: return 96;
223 case 5: return 128;
224 case 4: return 64;
1c7ac018
JB		 225 case 3: return 768;
226 case 2: return 384;
227 case 1: return 512;
228 default: return 256;
229 }
230}
231
232/* Write RCLK of I2S (in multiples of LRCLK) */
233static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
234{
235 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871 236 int rfs_shift = i2s->variant_regs->rfs_off;
1c7ac018 237
a5a56871 238 mod &= ~(i2s->variant_regs->rfs_mask << rfs_shift);
1c7ac018
JB		 239
240 switch (rfs) {
a5a56871
PV		 241 case 192:
242 mod |= (EXYNOS7_MOD_RCLK_192FS << rfs_shift);
243 break;
244 case 96:
245 mod |= (EXYNOS7_MOD_RCLK_96FS << rfs_shift);
246 break;
247 case 128:
248 mod |= (EXYNOS7_MOD_RCLK_128FS << rfs_shift);
249 break;
250 case 64:
251 mod |= (EXYNOS7_MOD_RCLK_64FS << rfs_shift);
252 break;
1c7ac018 253 case 768:
b60be4aa 254 mod |= (MOD_RCLK_768FS << rfs_shift);
1c7ac018
JB		 255 break;
256 case 512:
b60be4aa 257 mod |= (MOD_RCLK_512FS << rfs_shift);
1c7ac018
JB		 258 break;
259 case 384:
b60be4aa 260 mod |= (MOD_RCLK_384FS << rfs_shift);
1c7ac018
JB		 261 break;
262 default:
b60be4aa 263 mod |= (MOD_RCLK_256FS << rfs_shift);
1c7ac018
JB		 264 break;
265 }
266
267 writel(mod, i2s->addr + I2SMOD);
268}
269
270/* Read Bit-Clock of I2S (in multiples of LRCLK) */
271static inline unsigned get_bfs(struct i2s_dai *i2s)
272{
4ca0c0d4 273 u32 bfs;
a5a56871
PV		 274 bfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->bfs_off;
275 bfs &= i2s->variant_regs->bfs_mask;
1c7ac018
JB		 276
277 switch (bfs) {
4ca0c0d4
PV		 278 case 8: return 256;
279 case 7: return 192;
280 case 6: return 128;
281 case 5: return 96;
282 case 4: return 64;
1c7ac018
JB		 283 case 3: return 24;
284 case 2: return 16;
285 case 1: return 48;
286 default: return 32;
287 }
288}
289
290/* Write Bit-Clock of I2S (in multiples of LRCLK) */
291static inline void set_bfs(struct i2s_dai *i2s, unsigned bfs)
292{
293 u32 mod = readl(i2s->addr + I2SMOD);
4ca0c0d4 294 int tdm = i2s->quirks & QUIRK_SUPPORTS_TDM;
a5a56871 295 int bfs_shift = i2s->variant_regs->bfs_off;
4ca0c0d4
PV		 296
297 /* Non-TDM I2S controllers do not support BCLK > 48 * FS */
298 if (!tdm && bfs > 48) {
299 dev_err(&i2s->pdev->dev, "Unsupported BCLK divider\n");
300 return;
301 }
1c7ac018 302
a5a56871
PV		 303 mod &= ~(i2s->variant_regs->bfs_mask << bfs_shift);
304
1c7ac018
JB		 305 switch (bfs) {
306 case 48:
b60be4aa 307 mod |= (MOD_BCLK_48FS << bfs_shift);
1c7ac018
JB		 308 break;
309 case 32:
b60be4aa 310 mod |= (MOD_BCLK_32FS << bfs_shift);
1c7ac018
JB		 311 break;
312 case 24:
b60be4aa 313 mod |= (MOD_BCLK_24FS << bfs_shift);
1c7ac018
JB		 314 break;
315 case 16:
b60be4aa 316 mod |= (MOD_BCLK_16FS << bfs_shift);
1c7ac018 317 break;
4ca0c0d4
PV		 318 case 64:
319 mod |= (EXYNOS5420_MOD_BCLK_64FS << bfs_shift);
320 break;
321 case 96:
322 mod |= (EXYNOS5420_MOD_BCLK_96FS << bfs_shift);
323 break;
324 case 128:
325 mod |= (EXYNOS5420_MOD_BCLK_128FS << bfs_shift);
326 break;
327 case 192:
328 mod |= (EXYNOS5420_MOD_BCLK_192FS << bfs_shift);
329 break;
330 case 256:
331 mod |= (EXYNOS5420_MOD_BCLK_256FS << bfs_shift);
1c7ac018
JB		 332 break;
333 default:
334 dev_err(&i2s->pdev->dev, "Wrong BCLK Divider!\n");
335 return;
336 }
337
338 writel(mod, i2s->addr + I2SMOD);
339}
340
341/* Sample-Size */
342static inline int get_blc(struct i2s_dai *i2s)
343{
344 int blc = readl(i2s->addr + I2SMOD);
345
346 blc = (blc >> 13) & 0x3;
347
348 switch (blc) {
349 case 2: return 24;
350 case 1: return 8;
351 default: return 16;
352 }
353}
354
355/* TX Channel Control */
356static void i2s_txctrl(struct i2s_dai *i2s, int on)
357{
358 void __iomem *addr = i2s->addr;
a5a56871 359 int txr_off = i2s->variant_regs->txr_off;
1c7ac018 360 u32 con = readl(addr + I2SCON);
a5a56871 361 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
1c7ac018
JB		 362
363 if (on) {
364 con |= CON_ACTIVE;
365 con &= ~CON_TXCH_PAUSE;
366
367 if (is_secondary(i2s)) {
368 con |= CON_TXSDMA_ACTIVE;
369 con &= ~CON_TXSDMA_PAUSE;
370 } else {
371 con |= CON_TXDMA_ACTIVE;
372 con &= ~CON_TXDMA_PAUSE;
373 }
374
375 if (any_rx_active(i2s))
a5a56871 376 mod |= 2 << txr_off;
1c7ac018 377 else
a5a56871 378 mod |= 0 << txr_off;
1c7ac018
JB		 379 } else {
380 if (is_secondary(i2s)) {
381 con |= CON_TXSDMA_PAUSE;
382 con &= ~CON_TXSDMA_ACTIVE;
383 } else {
384 con |= CON_TXDMA_PAUSE;
385 con &= ~CON_TXDMA_ACTIVE;
386 }
387
388 if (other_tx_active(i2s)) {
389 writel(con, addr + I2SCON);
390 return;
391 }
392
393 con |= CON_TXCH_PAUSE;
394
395 if (any_rx_active(i2s))
a5a56871 396 mod |= 1 << txr_off;
1c7ac018
JB		 397 else
398 con &= ~CON_ACTIVE;
399 }
400
401 writel(mod, addr + I2SMOD);
402 writel(con, addr + I2SCON);
403}
404
405/* RX Channel Control */
406static void i2s_rxctrl(struct i2s_dai *i2s, int on)
407{
408 void __iomem *addr = i2s->addr;
a5a56871 409 int txr_off = i2s->variant_regs->txr_off;
1c7ac018 410 u32 con = readl(addr + I2SCON);
a5a56871 411 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
1c7ac018
JB		 412
413 if (on) {
414 con |= CON_RXDMA_ACTIVE | CON_ACTIVE;
415 con &= ~(CON_RXDMA_PAUSE | CON_RXCH_PAUSE);
416
417 if (any_tx_active(i2s))
a5a56871 418 mod |= 2 << txr_off;
1c7ac018 419 else
a5a56871 420 mod |= 1 << txr_off;
1c7ac018
JB		 421 } else {
422 con |= CON_RXDMA_PAUSE | CON_RXCH_PAUSE;
423 con &= ~CON_RXDMA_ACTIVE;
424
425 if (any_tx_active(i2s))
a5a56871 426 mod |= 0 << txr_off;
1c7ac018
JB		 427 else
428 con &= ~CON_ACTIVE;
429 }
430
431 writel(mod, addr + I2SMOD);
432 writel(con, addr + I2SCON);
433}
434
435/* Flush FIFO of an interface */
436static inline void i2s_fifo(struct i2s_dai *i2s, u32 flush)
437{
438 void __iomem *fic;
439 u32 val;
440
441 if (!i2s)
442 return;
443
444 if (is_secondary(i2s))
445 fic = i2s->addr + I2SFICS;
446 else
447 fic = i2s->addr + I2SFIC;
448
449 /* Flush the FIFO */
450 writel(readl(fic) | flush, fic);
451
452 /* Be patient */
453 val = msecs_to_loops(1) / 1000; /* 1 usec */
454 while (--val)
455 cpu_relax();
456
457 writel(readl(fic) & ~flush, fic);
458}
459
460static int i2s_set_sysclk(struct snd_soc_dai *dai,
461 int clk_id, unsigned int rfs, int dir)
462{
463 struct i2s_dai *i2s = to_info(dai);
464 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
465 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871
PV		 466 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
467 unsigned int cdcon_mask = 1 << i2s_regs->cdclkcon_off;
468 unsigned int rsrc_mask = 1 << i2s_regs->rclksrc_off;
1c7ac018
JB		 469
470 switch (clk_id) {
c86d50f9
SN		 471 case SAMSUNG_I2S_OPCLK:
472 mod &= ~MOD_OPCLK_MASK;
473 mod |= dir;
474 break;
1c7ac018
JB		 475 case SAMSUNG_I2S_CDCLK:
476 /* Shouldn't matter in GATING(CLOCK_IN) mode */
477 if (dir == SND_SOC_CLOCK_IN)
478 rfs = 0;
479
133c2681 480 if ((rfs && other && other->rfs && (other->rfs != rfs)) ||
1c7ac018
JB		 481 (any_active(i2s) &&
482 (((dir == SND_SOC_CLOCK_IN)
a5a56871 483 && !(mod & cdcon_mask)) ||
1c7ac018 484 ((dir == SND_SOC_CLOCK_OUT)
a5a56871 485 && (mod & cdcon_mask))))) {
1c7ac018
JB		 486 dev_err(&i2s->pdev->dev,
487 "%s:%d Other DAI busy\n", __func__, __LINE__);
488 return -EAGAIN;
489 }
490
491 if (dir == SND_SOC_CLOCK_IN)
a5a56871 492 mod |= 1 << i2s_regs->cdclkcon_off;
1c7ac018 493 else
b2de1d20 494 mod &= ~(1 << i2s_regs->cdclkcon_off);
1c7ac018
JB		 495
496 i2s->rfs = rfs;
497 break;
498
499 case SAMSUNG_I2S_RCLKSRC_0: /* clock corrsponding to IISMOD[10] := 0 */
500 case SAMSUNG_I2S_RCLKSRC_1: /* clock corrsponding to IISMOD[10] := 1 */
501 if ((i2s->quirks & QUIRK_NO_MUXPSR)
502 || (clk_id == SAMSUNG_I2S_RCLKSRC_0))
503 clk_id = 0;
504 else
505 clk_id = 1;
506
507 if (!any_active(i2s)) {
a6aba536 508 if (i2s->op_clk && !IS_ERR(i2s->op_clk)) {
a5a56871
PV		 509 if ((clk_id && !(mod & rsrc_mask)) ||
510 (!clk_id && (mod & rsrc_mask))) {
98614cf6 511 clk_disable_unprepare(i2s->op_clk);
1c7ac018
JB		 512 clk_put(i2s->op_clk);
513 } else {
6ce534aa
JB		 514 i2s->rclk_srcrate =
515 clk_get_rate(i2s->op_clk);
1c7ac018
JB		 516 return 0;
517 }
518 }
519
1974a042
PV		 520 if (clk_id)
521 i2s->op_clk = clk_get(&i2s->pdev->dev,
522 "i2s_opclk1");
523 else
524 i2s->op_clk = clk_get(&i2s->pdev->dev,
525 "i2s_opclk0");
a6aba536
SN		 526
527 if (WARN_ON(IS_ERR(i2s->op_clk)))
528 return PTR_ERR(i2s->op_clk);
529
98614cf6 530 clk_prepare_enable(i2s->op_clk);
1c7ac018
JB		 531 i2s->rclk_srcrate = clk_get_rate(i2s->op_clk);
532
533 /* Over-ride the other's */
534 if (other) {
535 other->op_clk = i2s->op_clk;
536 other->rclk_srcrate = i2s->rclk_srcrate;
537 }
a5a56871
PV		 538 } else if ((!clk_id && (mod & rsrc_mask))
539 || (clk_id && !(mod & rsrc_mask))) {
1c7ac018
JB		 540 dev_err(&i2s->pdev->dev,
541 "%s:%d Other DAI busy\n", __func__, __LINE__);
542 return -EAGAIN;
543 } else {
544 /* Call can't be on the active DAI */
545 i2s->op_clk = other->op_clk;
546 i2s->rclk_srcrate = other->rclk_srcrate;
547 return 0;
548 }
549
550 if (clk_id == 0)
b2de1d20 551 mod &= ~(1 << i2s_regs->rclksrc_off);
1c7ac018 552 else
a5a56871 553 mod |= 1 << i2s_regs->rclksrc_off;
1c7ac018 554
b2de1d20 555 break;
1c7ac018
JB		 556 default:
557 dev_err(&i2s->pdev->dev, "We don't serve that!\n");
558 return -EINVAL;
559 }
560
561 writel(mod, i2s->addr + I2SMOD);
562
563 return 0;
564}
565
566static int i2s_set_fmt(struct snd_soc_dai *dai,
567 unsigned int fmt)
568{
569 struct i2s_dai *i2s = to_info(dai);
570 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871 571 int lrp_shift, sdf_shift, sdf_mask, lrp_rlow, mod_slave;
1c7ac018
JB		 572 u32 tmp = 0;
573
a5a56871
PV		 574 lrp_shift = i2s->variant_regs->lrp_off;
575 sdf_shift = i2s->variant_regs->sdf_off;
576 mod_slave = 1 << i2s->variant_regs->mss_off;
4ca0c0d4 577
b60be4aa
PV		 578 sdf_mask = MOD_SDF_MASK << sdf_shift;
579 lrp_rlow = MOD_LR_RLOW << lrp_shift;
580
1c7ac018
JB		 581 /* Format is priority */
582 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
583 case SND_SOC_DAIFMT_RIGHT_J:
b60be4aa
PV		 584 tmp |= lrp_rlow;
585 tmp |= (MOD_SDF_MSB << sdf_shift);
1c7ac018
JB		 586 break;
587 case SND_SOC_DAIFMT_LEFT_J:
b60be4aa
PV		 588 tmp |= lrp_rlow;
589 tmp |= (MOD_SDF_LSB << sdf_shift);
1c7ac018
JB		 590 break;
591 case SND_SOC_DAIFMT_I2S:
b60be4aa 592 tmp |= (MOD_SDF_IIS << sdf_shift);
1c7ac018
JB		 593 break;
594 default:
595 dev_err(&i2s->pdev->dev, "Format not supported\n");
596 return -EINVAL;
597 }
598
599 /*
600 * INV flag is relative to the FORMAT flag - if set it simply
601 * flips the polarity specified by the Standard
602 */
603 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
604 case SND_SOC_DAIFMT_NB_NF:
605 break;
606 case SND_SOC_DAIFMT_NB_IF:
b60be4aa
PV		 607 if (tmp & lrp_rlow)
608 tmp &= ~lrp_rlow;
1c7ac018 609 else
b60be4aa 610 tmp |= lrp_rlow;
1c7ac018
JB		 611 break;
612 default:
613 dev_err(&i2s->pdev->dev, "Polarity not supported\n");
614 return -EINVAL;
615 }
616
617 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
618 case SND_SOC_DAIFMT_CBM_CFM:
a5a56871 619 tmp |= mod_slave;
1c7ac018
JB		 620 break;
621 case SND_SOC_DAIFMT_CBS_CFS:
622 /* Set default source clock in Master mode */
623 if (i2s->rclk_srcrate == 0)
624 i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0,
625 0, SND_SOC_CLOCK_IN);
626 break;
627 default:
628 dev_err(&i2s->pdev->dev, "master/slave format not supported\n");
629 return -EINVAL;
630 }
631
b60be4aa
PV		 632 /*
633 * Don't change the I2S mode if any controller is active on this
634 * channel.
635 */
1c7ac018 636 if (any_active(i2s) &&
a5a56871 637 ((mod & (sdf_mask | lrp_rlow | mod_slave)) != tmp)) {
1c7ac018
JB		 638 dev_err(&i2s->pdev->dev,
639 "%s:%d Other DAI busy\n", __func__, __LINE__);
640 return -EAGAIN;
641 }
642
a5a56871 643 mod &= ~(sdf_mask | lrp_rlow | mod_slave);
1c7ac018
JB		 644 mod |= tmp;
645 writel(mod, i2s->addr + I2SMOD);
646
647 return 0;
648}
649
650static int i2s_hw_params(struct snd_pcm_substream *substream,
651 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
652{
653 struct i2s_dai *i2s = to_info(dai);
654 u32 mod = readl(i2s->addr + I2SMOD);
655
656 if (!is_secondary(i2s))
657 mod &= ~(MOD_DC2_EN | MOD_DC1_EN);
658
659 switch (params_channels(params)) {
660 case 6:
661 mod |= MOD_DC2_EN;
662 case 4:
663 mod |= MOD_DC1_EN;
664 break;
665 case 2:
588fb705
SP		 666 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
667 i2s->dma_playback.dma_size = 4;
668 else
669 i2s->dma_capture.dma_size = 4;
670 break;
671 case 1:
672 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
673 i2s->dma_playback.dma_size = 2;
674 else
675 i2s->dma_capture.dma_size = 2;
676
1c7ac018
JB		 677 break;
678 default:
679 dev_err(&i2s->pdev->dev, "%d channels not supported\n",
680 params_channels(params));
681 return -EINVAL;
682 }
683
684 if (is_secondary(i2s))
685 mod &= ~MOD_BLCS_MASK;
686 else
687 mod &= ~MOD_BLCP_MASK;
688
689 if (is_manager(i2s))
690 mod &= ~MOD_BLC_MASK;
691
88ce1465
TB		 692 switch (params_width(params)) {
693 case 8:
1c7ac018
JB		 694 if (is_secondary(i2s))
695 mod |= MOD_BLCS_8BIT;
696 else
697 mod |= MOD_BLCP_8BIT;
698 if (is_manager(i2s))
699 mod |= MOD_BLC_8BIT;
700 break;
88ce1465 701 case 16:
1c7ac018
JB		 702 if (is_secondary(i2s))
703 mod |= MOD_BLCS_16BIT;
704 else
705 mod |= MOD_BLCP_16BIT;
706 if (is_manager(i2s))
707 mod |= MOD_BLC_16BIT;
708 break;
88ce1465 709 case 24:
1c7ac018
JB		 710 if (is_secondary(i2s))
711 mod |= MOD_BLCS_24BIT;
712 else
713 mod |= MOD_BLCP_24BIT;
714 if (is_manager(i2s))
715 mod |= MOD_BLC_24BIT;
716 break;
717 default:
718 dev_err(&i2s->pdev->dev, "Format(%d) not supported\n",
719 params_format(params));
720 return -EINVAL;
721 }
722 writel(mod, i2s->addr + I2SMOD);
723
d37bdf73
MB		 724 samsung_asoc_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture);
725
1c7ac018
JB		 726 i2s->frmclk = params_rate(params);
727
728 return 0;
729}
730
731/* We set constraints on the substream acc to the version of I2S */
732static int i2s_startup(struct snd_pcm_substream *substream,
733 struct snd_soc_dai *dai)
734{
735 struct i2s_dai *i2s = to_info(dai);
736 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
737 unsigned long flags;
738
739 spin_lock_irqsave(&lock, flags);
740
741 i2s->mode |= DAI_OPENED;
742
743 if (is_manager(other))
744 i2s->mode &= ~DAI_MANAGER;
745 else
746 i2s->mode |= DAI_MANAGER;
747
2d77828d
PV		 748 if (!any_active(i2s) && (i2s->quirks & QUIRK_NEED_RSTCLR))
749 writel(CON_RSTCLR, i2s->addr + I2SCON);
750
1c7ac018
JB		 751 spin_unlock_irqrestore(&lock, flags);
752
b97c60ab
SN		 753 if (!is_opened(other) && i2s->cdclk_out)
754 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
755 0, SND_SOC_CLOCK_OUT);
1c7ac018
JB		 756 return 0;
757}
758
759static void i2s_shutdown(struct snd_pcm_substream *substream,
760 struct snd_soc_dai *dai)
761{
762 struct i2s_dai *i2s = to_info(dai);
763 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
764 unsigned long flags;
a5a56871 765 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
1c7ac018
JB		 766
767 spin_lock_irqsave(&lock, flags);
768
769 i2s->mode &= ~DAI_OPENED;
770 i2s->mode &= ~DAI_MANAGER;
771
b97c60ab 772 if (is_opened(other)) {
1c7ac018 773 other->mode |= DAI_MANAGER;
b97c60ab
SN		 774 } else {
775 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871 776 i2s->cdclk_out = !(mod & (1 << i2s_regs->cdclkcon_off));
133c2681
CK		 777 if (other)
778 other->cdclk_out = i2s->cdclk_out;
b97c60ab 779 }
1c7ac018
JB		 780 /* Reset any constraint on RFS and BFS */
781 i2s->rfs = 0;
782 i2s->bfs = 0;
783
784 spin_unlock_irqrestore(&lock, flags);
785
786 /* Gate CDCLK by default */
787 if (!is_opened(other))
788 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
789 0, SND_SOC_CLOCK_IN);
790}
791
792static int config_setup(struct i2s_dai *i2s)
793{
794 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
795 unsigned rfs, bfs, blc;
796 u32 psr;
797
798 blc = get_blc(i2s);
799
800 bfs = i2s->bfs;
801
802 if (!bfs && other)
803 bfs = other->bfs;
804
805 /* Select least possible multiple(2) if no constraint set */
806 if (!bfs)
807 bfs = blc * 2;
808
809 rfs = i2s->rfs;
810
811 if (!rfs && other)
812 rfs = other->rfs;
813
814 if ((rfs == 256 || rfs == 512) && (blc == 24)) {
815 dev_err(&i2s->pdev->dev,
816 "%d-RFS not supported for 24-blc\n", rfs);
817 return -EINVAL;
818 }
819
820 if (!rfs) {
821 if (bfs == 16 || bfs == 32)
822 rfs = 256;
823 else
824 rfs = 384;
825 }
826
827 /* If already setup and running */
828 if (any_active(i2s) && (get_rfs(i2s) != rfs || get_bfs(i2s) != bfs)) {
829 dev_err(&i2s->pdev->dev,
830 "%s:%d Other DAI busy\n", __func__, __LINE__);
831 return -EAGAIN;
832 }
833
1c7ac018
JB		 834 set_bfs(i2s, bfs);
835 set_rfs(i2s, rfs);
836
77010010
PV		 837 /* Don't bother with PSR in Slave mode */
838 if (is_slave(i2s))
839 return 0;
840
1c7ac018
JB		 841 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) {
842 psr = i2s->rclk_srcrate / i2s->frmclk / rfs;
843 writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR);
844 dev_dbg(&i2s->pdev->dev,
845 "RCLK_SRC=%luHz PSR=%u, RCLK=%dfs, BCLK=%dfs\n",
846 i2s->rclk_srcrate, psr, rfs, bfs);
847 }
848
849 return 0;
850}
851
852static int i2s_trigger(struct snd_pcm_substream *substream,
853 int cmd, struct snd_soc_dai *dai)
854{
855 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
856 struct snd_soc_pcm_runtime *rtd = substream->private_data;
857 struct i2s_dai *i2s = to_info(rtd->cpu_dai);
858 unsigned long flags;
859
860 switch (cmd) {
861 case SNDRV_PCM_TRIGGER_START:
862 case SNDRV_PCM_TRIGGER_RESUME:
863 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
864 local_irq_save(flags);
865
1c7ac018
JB		 866 if (config_setup(i2s)) {
867 local_irq_restore(flags);
868 return -EINVAL;
869 }
870
871 if (capture)
872 i2s_rxctrl(i2s, 1);
873 else
874 i2s_txctrl(i2s, 1);
875
876 local_irq_restore(flags);
877 break;
878 case SNDRV_PCM_TRIGGER_STOP:
879 case SNDRV_PCM_TRIGGER_SUSPEND:
880 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
881 local_irq_save(flags);
882
c90887fe 883 if (capture) {
1c7ac018 884 i2s_rxctrl(i2s, 0);
775bc971 885 i2s_fifo(i2s, FIC_RXFLUSH);
c90887fe
JB		 886 } else {
887 i2s_txctrl(i2s, 0);
775bc971 888 i2s_fifo(i2s, FIC_TXFLUSH);
c90887fe 889 }
775bc971 890
1c7ac018
JB		 891 local_irq_restore(flags);
892 break;
893 }
894
895 return 0;
896}
897
898static int i2s_set_clkdiv(struct snd_soc_dai *dai,
899 int div_id, int div)
900{
901 struct i2s_dai *i2s = to_info(dai);
902 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
903
904 switch (div_id) {
905 case SAMSUNG_I2S_DIV_BCLK:
906 if ((any_active(i2s) && div && (get_bfs(i2s) != div))
907 || (other && other->bfs && (other->bfs != div))) {
908 dev_err(&i2s->pdev->dev,
909 "%s:%d Other DAI busy\n", __func__, __LINE__);
910 return -EAGAIN;
911 }
912 i2s->bfs = div;
913 break;
914 default:
915 dev_err(&i2s->pdev->dev,
916 "Invalid clock divider(%d)\n", div_id);
917 return -EINVAL;
918 }
919
920 return 0;
921}
922
923static snd_pcm_sframes_t
924i2s_delay(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
925{
926 struct i2s_dai *i2s = to_info(dai);
927 u32 reg = readl(i2s->addr + I2SFIC);
928 snd_pcm_sframes_t delay;
a5a56871 929 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
1c7ac018
JB		 930
931 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
932 delay = FIC_RXCOUNT(reg);
933 else if (is_secondary(i2s))
934 delay = FICS_TXCOUNT(readl(i2s->addr + I2SFICS));
935 else
a5a56871 936 delay = (reg >> i2s_regs->ftx0cnt_off) & 0x7f;
1c7ac018
JB		 937
938 return delay;
939}
940
941#ifdef CONFIG_PM
942static int i2s_suspend(struct snd_soc_dai *dai)
943{
944 struct i2s_dai *i2s = to_info(dai);
945
d3d4e524
SN		 946 i2s->suspend_i2smod = readl(i2s->addr + I2SMOD);
947 i2s->suspend_i2scon = readl(i2s->addr + I2SCON);
948 i2s->suspend_i2spsr = readl(i2s->addr + I2SPSR);
1c7ac018
JB		 949
950 return 0;
951}
952
953static int i2s_resume(struct snd_soc_dai *dai)
954{
955 struct i2s_dai *i2s = to_info(dai);
956
d3d4e524
SN		 957 writel(i2s->suspend_i2scon, i2s->addr + I2SCON);
958 writel(i2s->suspend_i2smod, i2s->addr + I2SMOD);
959 writel(i2s->suspend_i2spsr, i2s->addr + I2SPSR);
1c7ac018
JB		 960
961 return 0;
962}
963#else
964#define i2s_suspend NULL
965#define i2s_resume NULL
966#endif
967
968static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
969{
970 struct i2s_dai *i2s = to_info(dai);
971 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
ba56447c 972 int ret;
1c7ac018 973
0ec2ba80 974 if (is_secondary(i2s)) { /* If this is probe on the secondary DAI */
3688569e
MB		 975 samsung_asoc_init_dma_data(dai, &other->sec_dai->dma_playback,
976 NULL);
1c7ac018 977 goto probe_exit;
3688569e 978 }
1c7ac018 979
ba56447c
MB		 980 ret = clk_prepare_enable(i2s->clk);
981 if (ret != 0) {
982 dev_err(&i2s->pdev->dev, "failed to enable clock: %d\n", ret);
983 return ret;
1c7ac018 984 }
1c7ac018 985
3688569e 986 samsung_asoc_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture);
511e3033 987
1c7ac018
JB		 988 if (i2s->quirks & QUIRK_NEED_RSTCLR)
989 writel(CON_RSTCLR, i2s->addr + I2SCON);
990
b0759736 991 if (i2s->quirks & QUIRK_SUPPORTS_IDMA)
9b8f5695 992 idma_reg_addr_init(i2s->addr,
61100f40
SK		 993 i2s->sec_dai->idma_playback.dma_addr);
994
1c7ac018
JB		 995probe_exit:
996 /* Reset any constraint on RFS and BFS */
997 i2s->rfs = 0;
998 i2s->bfs = 0;
d66eac3e 999 i2s->rclk_srcrate = 0;
1c7ac018
JB		 1000 i2s_txctrl(i2s, 0);
1001 i2s_rxctrl(i2s, 0);
1002 i2s_fifo(i2s, FIC_TXFLUSH);
1003 i2s_fifo(other, FIC_TXFLUSH);
1004 i2s_fifo(i2s, FIC_RXFLUSH);
1005
1006 /* Gate CDCLK by default */
1007 if (!is_opened(other))
1008 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
1009 0, SND_SOC_CLOCK_IN);
1010
1011 return 0;
1012}
1013
1014static int samsung_i2s_dai_remove(struct snd_soc_dai *dai)
1015{
1016 struct i2s_dai *i2s = snd_soc_dai_get_drvdata(dai);
1017 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
1018
1019 if (!other || !other->clk) {
1020
1021 if (i2s->quirks & QUIRK_NEED_RSTCLR)
1022 writel(0, i2s->addr + I2SCON);
1023
98614cf6 1024 clk_disable_unprepare(i2s->clk);
1c7ac018
JB		 1025 }
1026
1027 i2s->clk = NULL;
1028
1029 return 0;
1030}
1031
85e7652d 1032static const struct snd_soc_dai_ops samsung_i2s_dai_ops = {
1c7ac018
JB		 1033 .trigger = i2s_trigger,
1034 .hw_params = i2s_hw_params,
1035 .set_fmt = i2s_set_fmt,
1036 .set_clkdiv = i2s_set_clkdiv,
1037 .set_sysclk = i2s_set_sysclk,
1038 .startup = i2s_startup,
1039 .shutdown = i2s_shutdown,
1040 .delay = i2s_delay,
1041};
1042
4b828535
KM		 1043static const struct snd_soc_component_driver samsung_i2s_component = {
1044 .name = "samsung-i2s",
1045};
1046
1c7ac018
JB		 1047#define SAMSUNG_I2S_RATES SNDRV_PCM_RATE_8000_96000
1048
1049#define SAMSUNG_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1050 SNDRV_PCM_FMTBIT_S16_LE | \
1051 SNDRV_PCM_FMTBIT_S24_LE)
1052
fdca21ad 1053static struct i2s_dai *i2s_alloc_dai(struct platform_device *pdev, bool sec)
1c7ac018
JB		 1054{
1055 struct i2s_dai *i2s;
c6f9b1eb 1056 int ret;
1c7ac018 1057
b960ce74 1058 i2s = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dai), GFP_KERNEL);
1c7ac018
JB		 1059 if (i2s == NULL)
1060 return NULL;
1061
1062 i2s->pdev = pdev;
1063 i2s->pri_dai = NULL;
1064 i2s->sec_dai = NULL;
1065 i2s->i2s_dai_drv.symmetric_rates = 1;
1066 i2s->i2s_dai_drv.probe = samsung_i2s_dai_probe;
1067 i2s->i2s_dai_drv.remove = samsung_i2s_dai_remove;
1068 i2s->i2s_dai_drv.ops = &samsung_i2s_dai_ops;
1069 i2s->i2s_dai_drv.suspend = i2s_suspend;
1070 i2s->i2s_dai_drv.resume = i2s_resume;
a0ff6ea2 1071 i2s->i2s_dai_drv.playback.channels_min = 1;
1c7ac018
JB		 1072 i2s->i2s_dai_drv.playback.channels_max = 2;
1073 i2s->i2s_dai_drv.playback.rates = SAMSUNG_I2S_RATES;
1074 i2s->i2s_dai_drv.playback.formats = SAMSUNG_I2S_FMTS;
1075
1076 if (!sec) {
588fb705 1077 i2s->i2s_dai_drv.capture.channels_min = 1;
1c7ac018
JB		 1078 i2s->i2s_dai_drv.capture.channels_max = 2;
1079 i2s->i2s_dai_drv.capture.rates = SAMSUNG_I2S_RATES;
1080 i2s->i2s_dai_drv.capture.formats = SAMSUNG_I2S_FMTS;
c6f9b1eb 1081 dev_set_drvdata(&i2s->pdev->dev, i2s);
1c7ac018 1082 } else { /* Create a new platform_device for Secondary */
c6f9b1eb 1083 i2s->pdev = platform_device_alloc("samsung-i2s-sec", -1);
29ca9c73 1084 if (!i2s->pdev)
1c7ac018 1085 return NULL;
1c7ac018 1086
2f6f0ffb
MB		 1087 i2s->pdev->dev.parent = &pdev->dev;
1088
c6f9b1eb
P		 1089 platform_set_drvdata(i2s->pdev, i2s);
1090 ret = platform_device_add(i2s->pdev);
1091 if (ret < 0)
1092 return NULL;
1093 }
1c7ac018
JB		 1094
1095 return i2s;
1096}
1097
40476f61
PV		 1098static const struct of_device_id exynos_i2s_match[];
1099
7da493e9
PV		 1100static inline const struct samsung_i2s_dai_data *samsung_i2s_get_driver_data(
1101 struct platform_device *pdev)
7c62eebb 1102{
9cf24747 1103 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
40476f61
PV		 1104 const struct of_device_id *match;
1105 match = of_match_node(exynos_i2s_match, pdev->dev.of_node);
9cf24747
SN		 1106 return match ? match->data : NULL;
1107 } else {
7da493e9
PV		 1108 return (struct samsung_i2s_dai_data *)
1109 platform_get_device_id(pdev)->driver_data;
9cf24747 1110 }
7c62eebb
PV		 1111}
1112
641d334b 1113#ifdef CONFIG_PM
5b1d3c34
C		 1114static int i2s_runtime_suspend(struct device *dev)
1115{
1116 struct i2s_dai *i2s = dev_get_drvdata(dev);
1117
1118 clk_disable_unprepare(i2s->clk);
1119
1120 return 0;
1121}
1122
1123static int i2s_runtime_resume(struct device *dev)
1124{
1125 struct i2s_dai *i2s = dev_get_drvdata(dev);
1126
1127 clk_prepare_enable(i2s->clk);
1128
1129 return 0;
1130}
641d334b 1131#endif /* CONFIG_PM */
5b1d3c34 1132
fdca21ad 1133static int samsung_i2s_probe(struct platform_device *pdev)
1c7ac018 1134{
1c7ac018 1135 struct i2s_dai *pri_dai, *sec_dai = NULL;
40476f61
PV		 1136 struct s3c_audio_pdata *i2s_pdata = pdev->dev.platform_data;
1137 struct samsung_i2s *i2s_cfg = NULL;
1c7ac018 1138 struct resource *res;
40476f61
PV		 1139 u32 regs_base, quirks = 0, idma_addr = 0;
1140 struct device_node *np = pdev->dev.of_node;
7da493e9 1141 const struct samsung_i2s_dai_data *i2s_dai_data;
1c7ac018
JB		 1142
1143 /* Call during Seconday interface registration */
7da493e9 1144 i2s_dai_data = samsung_i2s_get_driver_data(pdev);
7c62eebb 1145
7da493e9 1146 if (i2s_dai_data->dai_type == TYPE_SEC) {
1c7ac018 1147 sec_dai = dev_get_drvdata(&pdev->dev);
a9b977ec
P		 1148 if (!sec_dai) {
1149 dev_err(&pdev->dev, "Unable to get drvdata\n");
1150 return -EFAULT;
1151 }
53f7faa1 1152 ret = devm_snd_soc_register_component(&sec_dai->pdev->dev,
d644a115
MB		 1153 &samsung_i2s_component,
1154 &sec_dai->i2s_dai_drv, 1);
53f7faa1
SN		 1155 if (ret != 0)
1156 return ret;
1157
1158 return samsung_asoc_dma_platform_register(&pdev->dev);
1c7ac018
JB		 1159 }
1160
40476f61
PV		 1161 pri_dai = i2s_alloc_dai(pdev, false);
1162 if (!pri_dai) {
1163 dev_err(&pdev->dev, "Unable to alloc I2S_pri\n");
1164 return -ENOMEM;
1c7ac018
JB		 1165 }
1166
40476f61
PV		 1167 if (!np) {
1168 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1169 if (!res) {
1170 dev_err(&pdev->dev,
1171 "Unable to get I2S-TX dma resource\n");
1172 return -ENXIO;
1173 }
1174 pri_dai->dma_playback.channel = res->start;
1c7ac018 1175
40476f61
PV		 1176 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1177 if (!res) {
1178 dev_err(&pdev->dev,
1179 "Unable to get I2S-RX dma resource\n");
1180 return -ENXIO;
1181 }
1182 pri_dai->dma_capture.channel = res->start;
1c7ac018 1183
40476f61
PV		 1184 if (i2s_pdata == NULL) {
1185 dev_err(&pdev->dev, "Can't work without s3c_audio_pdata\n");
1186 return -EINVAL;
1187 }
1188
1189 if (&i2s_pdata->type)
1190 i2s_cfg = &i2s_pdata->type.i2s;
1191
1192 if (i2s_cfg) {
1193 quirks = i2s_cfg->quirks;
1194 idma_addr = i2s_cfg->idma_addr;
1195 }
1196 } else {
7da493e9 1197 quirks = i2s_dai_data->quirks;
40476f61
PV		 1198 if (of_property_read_u32(np, "samsung,idma-addr",
1199 &idma_addr)) {
b0759736
PV		 1200 if (quirks & QUIRK_SUPPORTS_IDMA) {
1201 dev_info(&pdev->dev, "idma address is not"\
40476f61 1202 "specified");
40476f61
PV		 1203 }
1204 }
1205 }
1c7ac018
JB		 1206
1207 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
af1cf5cf
SN		 1208 pri_dai->addr = devm_ioremap_resource(&pdev->dev, res);
1209 if (IS_ERR(pri_dai->addr))
1210 return PTR_ERR(pri_dai->addr);
1c7ac018 1211
1c7ac018
JB		 1212 regs_base = res->start;
1213
0ec2ba80
SN		 1214 pri_dai->clk = devm_clk_get(&pdev->dev, "iis");
1215 if (IS_ERR(pri_dai->clk)) {
1216 dev_err(&pdev->dev, "Failed to get iis clock\n");
1217 return PTR_ERR(pri_dai->clk);
1218 }
1c7ac018
JB		 1219 pri_dai->dma_playback.dma_addr = regs_base + I2STXD;
1220 pri_dai->dma_capture.dma_addr = regs_base + I2SRXD;
40476f61 1221 pri_dai->dma_playback.ch_name = "tx";
40476f61 1222 pri_dai->dma_capture.ch_name = "rx";
1c7ac018
JB		 1223 pri_dai->dma_playback.dma_size = 4;
1224 pri_dai->dma_capture.dma_size = 4;
1c7ac018 1225 pri_dai->quirks = quirks;
a5a56871 1226 pri_dai->variant_regs = i2s_dai_data->i2s_variant_regs;
1c7ac018
JB		 1227
1228 if (quirks & QUIRK_PRI_6CHAN)
1229 pri_dai->i2s_dai_drv.playback.channels_max = 6;
1230
1231 if (quirks & QUIRK_SEC_DAI) {
1232 sec_dai = i2s_alloc_dai(pdev, true);
1233 if (!sec_dai) {
1234 dev_err(&pdev->dev, "Unable to alloc I2S_sec\n");
af1cf5cf 1235 return -ENOMEM;
1c7ac018 1236 }
7e5d8706
SN		 1237
1238 sec_dai->variant_regs = pri_dai->variant_regs;
1c7ac018 1239 sec_dai->dma_playback.dma_addr = regs_base + I2STXDS;
40476f61
PV		 1240 sec_dai->dma_playback.ch_name = "tx-sec";
1241
1242 if (!np) {
1243 res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
1244 if (res)
1245 sec_dai->dma_playback.channel = res->start;
1246 }
1247
1c7ac018 1248 sec_dai->dma_playback.dma_size = 4;
af1cf5cf 1249 sec_dai->addr = pri_dai->addr;
0ec2ba80 1250 sec_dai->clk = pri_dai->clk;
1c7ac018 1251 sec_dai->quirks = quirks;
40476f61 1252 sec_dai->idma_playback.dma_addr = idma_addr;
1c7ac018
JB		 1253 sec_dai->pri_dai = pri_dai;
1254 pri_dai->sec_dai = sec_dai;
1255 }
1256
0429ffef
MB		 1257 if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
1258 dev_err(&pdev->dev, "Unable to configure gpio\n");
af1cf5cf 1259 return -EINVAL;
1c7ac018
JB		 1260 }
1261
d644a115
MB		 1262 devm_snd_soc_register_component(&pri_dai->pdev->dev,
1263 &samsung_i2s_component,
1264 &pri_dai->i2s_dai_drv, 1);
1c7ac018 1265
c5cf4dbc
MB		 1266 pm_runtime_enable(&pdev->dev);
1267
53f7faa1
SN		 1268 ret = samsung_asoc_dma_platform_register(&pdev->dev);
1269 if (ret != 0)
1270 return ret;
a08485d8 1271
1c7ac018 1272 return 0;
1c7ac018
JB		 1273}
1274
fdca21ad 1275static int samsung_i2s_remove(struct platform_device *pdev)
1c7ac018
JB		 1276{
1277 struct i2s_dai *i2s, *other;
1278
1279 i2s = dev_get_drvdata(&pdev->dev);
1280 other = i2s->pri_dai ? : i2s->sec_dai;
1281
1282 if (other) {
1283 other->pri_dai = NULL;
1284 other->sec_dai = NULL;
1285 } else {
c5cf4dbc 1286 pm_runtime_disable(&pdev->dev);
1c7ac018
JB		 1287 }
1288
1289 i2s->pri_dai = NULL;
1290 i2s->sec_dai = NULL;
1291
1c7ac018
JB		 1292 return 0;
1293}
1294
a5a56871
PV		 1295static const struct samsung_i2s_variant_regs i2sv3_regs = {
1296 .bfs_off = 1,
1297 .rfs_off = 3,
1298 .sdf_off = 5,
1299 .txr_off = 8,
1300 .rclksrc_off = 10,
1301 .mss_off = 11,
1302 .cdclkcon_off = 12,
1303 .lrp_off = 7,
1304 .bfs_mask = 0x3,
1305 .rfs_mask = 0x3,
1306 .ftx0cnt_off = 8,
1307};
1308
1309static const struct samsung_i2s_variant_regs i2sv6_regs = {
1310 .bfs_off = 0,
1311 .rfs_off = 4,
1312 .sdf_off = 6,
1313 .txr_off = 8,
1314 .rclksrc_off = 10,
1315 .mss_off = 11,
1316 .cdclkcon_off = 12,
1317 .lrp_off = 15,
1318 .bfs_mask = 0xf,
1319 .rfs_mask = 0x3,
1320 .ftx0cnt_off = 8,
1321};
1322
1323static const struct samsung_i2s_variant_regs i2sv7_regs = {
1324 .bfs_off = 0,
1325 .rfs_off = 4,
1326 .sdf_off = 7,
1327 .txr_off = 9,
1328 .rclksrc_off = 11,
1329 .mss_off = 12,
1330 .cdclkcon_off = 22,
1331 .lrp_off = 15,
1332 .bfs_mask = 0xf,
1333 .rfs_mask = 0x7,
1334 .ftx0cnt_off = 0,
1335};
1336
1337static const struct samsung_i2s_variant_regs i2sv5_i2s1_regs = {
1338 .bfs_off = 0,
1339 .rfs_off = 3,
1340 .sdf_off = 6,
1341 .txr_off = 8,
1342 .rclksrc_off = 10,
1343 .mss_off = 11,
1344 .cdclkcon_off = 12,
1345 .lrp_off = 15,
1346 .bfs_mask = 0x7,
1347 .rfs_mask = 0x7,
1348 .ftx0cnt_off = 8,
1349};
1350
7da493e9
PV		 1351static const struct samsung_i2s_dai_data i2sv3_dai_type = {
1352 .dai_type = TYPE_PRI,
1353 .quirks = QUIRK_NO_MUXPSR,
a5a56871 1354 .i2s_variant_regs = &i2sv3_regs,
7da493e9
PV		 1355};
1356
1357static const struct samsung_i2s_dai_data i2sv5_dai_type = {
1358 .dai_type = TYPE_PRI,
b0759736
PV		 1359 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1360 QUIRK_SUPPORTS_IDMA,
a5a56871 1361 .i2s_variant_regs = &i2sv3_regs,
7da493e9
PV		 1362};
1363
4ca0c0d4
PV		 1364static const struct samsung_i2s_dai_data i2sv6_dai_type = {
1365 .dai_type = TYPE_PRI,
1366 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
b0759736 1367 QUIRK_SUPPORTS_TDM | QUIRK_SUPPORTS_IDMA,
a5a56871
PV		 1368 .i2s_variant_regs = &i2sv6_regs,
1369};
1370
1371static const struct samsung_i2s_dai_data i2sv7_dai_type = {
1372 .dai_type = TYPE_PRI,
1373 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1374 QUIRK_SUPPORTS_TDM,
1375 .i2s_variant_regs = &i2sv7_regs,
1376};
1377
1378static const struct samsung_i2s_dai_data i2sv5_dai_type_i2s1 = {
1379 .dai_type = TYPE_PRI,
1380 .quirks = QUIRK_PRI_6CHAN | QUIRK_NEED_RSTCLR,
1381 .i2s_variant_regs = &i2sv5_i2s1_regs,
4ca0c0d4
PV		 1382};
1383
7da493e9
PV		 1384static const struct samsung_i2s_dai_data samsung_dai_type_pri = {
1385 .dai_type = TYPE_PRI,
1386};
1387
1388static const struct samsung_i2s_dai_data samsung_dai_type_sec = {
1389 .dai_type = TYPE_SEC,
1390};
1391
7c62eebb
PV		 1392static struct platform_device_id samsung_i2s_driver_ids[] = {
1393 {
1394 .name = "samsung-i2s",
3f024980 1395 .driver_data = (kernel_ulong_t)&i2sv3_dai_type,
7c62eebb
PV		 1396 }, {
1397 .name = "samsung-i2s-sec",
7da493e9 1398 .driver_data = (kernel_ulong_t)&samsung_dai_type_sec,
3f024980
MB		 1399 }, {
1400 .name = "samsung-i2sv4",
1401 .driver_data = (kernel_ulong_t)&i2sv5_dai_type,
7c62eebb
PV		 1402 },
1403 {},
1404};
2af19558 1405MODULE_DEVICE_TABLE(platform, samsung_i2s_driver_ids);
7c62eebb 1406
40476f61 1407#ifdef CONFIG_OF
40476f61 1408static const struct of_device_id exynos_i2s_match[] = {
7da493e9
PV		 1409 {
1410 .compatible = "samsung,s3c6410-i2s",
1411 .data = &i2sv3_dai_type,
1412 }, {
1413 .compatible = "samsung,s5pv210-i2s",
1414 .data = &i2sv5_dai_type,
4ca0c0d4
PV		 1415 }, {
1416 .compatible = "samsung,exynos5420-i2s",
1417 .data = &i2sv6_dai_type,
a5a56871
PV		 1418 }, {
1419 .compatible = "samsung,exynos7-i2s",
1420 .data = &i2sv7_dai_type,
1421 }, {
1422 .compatible = "samsung,exynos7-i2s1",
1423 .data = &i2sv5_dai_type_i2s1,
40476f61
PV		 1424 },
1425 {},
1426};
1427MODULE_DEVICE_TABLE(of, exynos_i2s_match);
1428#endif
1429
5b1d3c34
C		 1430static const struct dev_pm_ops samsung_i2s_pm = {
1431 SET_RUNTIME_PM_OPS(i2s_runtime_suspend,
1432 i2s_runtime_resume, NULL)
1433};
1434
1c7ac018
JB		 1435static struct platform_driver samsung_i2s_driver = {
1436 .probe = samsung_i2s_probe,
fdca21ad 1437 .remove = samsung_i2s_remove,
7c62eebb 1438 .id_table = samsung_i2s_driver_ids,
1c7ac018
JB		 1439 .driver = {
1440 .name = "samsung-i2s",
40476f61 1441 .of_match_table = of_match_ptr(exynos_i2s_match),
5b1d3c34 1442 .pm = &samsung_i2s_pm,
1c7ac018
JB		 1443 },
1444};
1445
e00c3f55 1446module_platform_driver(samsung_i2s_driver);
1c7ac018
JB		 1447
1448/* Module information */
df8ad335 1449MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
1c7ac018
JB		 1450MODULE_DESCRIPTION("Samsung I2S Interface");
1451MODULE_ALIAS("platform:samsung-i2s");
1452MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.281857 seconds and 5 git commands to generate.