projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: samsung: i2s: Add return value checks in probe()
[deliverable/linux.git] / sound / soc / samsung / i2s.c
CommitLineData
5033f43c 1/* sound/soc/samsung/i2s.c
1c7ac018
JB		 2 *
3 * ALSA SoC Audio Layer - Samsung I2S Controller driver
4 *
5 * Copyright (c) 2010 Samsung Electronics Co. Ltd.
df8ad335 6 * Jaswinder Singh <jassisinghbrar@gmail.com>
1c7ac018
JB		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/delay.h>
14#include <linux/slab.h>
15#include <linux/clk.h>
16#include <linux/io.h>
da155d5b 17#include <linux/module.h>
40476f61
PV		 18#include <linux/of.h>
19#include <linux/of_gpio.h>
c5cf4dbc 20#include <linux/pm_runtime.h>
1c7ac018 21
1c7ac018 22#include <sound/soc.h>
0378b6ac 23#include <sound/pcm_params.h>
1c7ac018 24
436d42c6 25#include <linux/platform_data/asoc-s3c.h>
1c7ac018
JB		 26
27#include "dma.h"
61100f40 28#include "idma.h"
1c7ac018 29#include "i2s.h"
172a453d 30#include "i2s-regs.h"
1c7ac018
JB		 31
32#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
33
7c62eebb
PV		 34enum samsung_dai_type {
35 TYPE_PRI,
36 TYPE_SEC,
37};
38
a5a56871
PV		 39struct samsung_i2s_variant_regs {
40 unsigned int bfs_off;
41 unsigned int rfs_off;
42 unsigned int sdf_off;
43 unsigned int txr_off;
44 unsigned int rclksrc_off;
45 unsigned int mss_off;
46 unsigned int cdclkcon_off;
47 unsigned int lrp_off;
48 unsigned int bfs_mask;
49 unsigned int rfs_mask;
50 unsigned int ftx0cnt_off;
51};
52
40476f61
PV		 53struct samsung_i2s_dai_data {
54 int dai_type;
7da493e9 55 u32 quirks;
a5a56871 56 const struct samsung_i2s_variant_regs *i2s_variant_regs;
40476f61
PV		 57};
58
1c7ac018
JB		 59struct i2s_dai {
60 /* Platform device for this DAI */
61 struct platform_device *pdev;
62 /* IOREMAP'd SFRs */
63 void __iomem *addr;
64 /* Physical base address of SFRs */
65 u32 base;
66 /* Rate of RCLK source clock */
67 unsigned long rclk_srcrate;
68 /* Frame Clock */
69 unsigned frmclk;
70 /*
71 * Specifically requested RCLK,BCLK by MACHINE Driver.
72 * 0 indicates CPU driver is free to choose any value.
73 */
74 unsigned rfs, bfs;
75 /* I2S Controller's core clock */
76 struct clk *clk;
77 /* Clock for generating I2S signals */
78 struct clk *op_clk;
1c7ac018
JB		 79 /* Pointer to the Primary_Fifo if this is Sec_Fifo, NULL otherwise */
80 struct i2s_dai *pri_dai;
81 /* Pointer to the Secondary_Fifo if it has one, NULL otherwise */
82 struct i2s_dai *sec_dai;
83#define DAI_OPENED (1 << 0) /* Dai is opened */
84#define DAI_MANAGER (1 << 1) /* Dai is the manager */
85 unsigned mode;
b97c60ab
SN		 86 /* CDCLK pin direction: 0 - input, 1 - output */
87 unsigned int cdclk_out:1;
1c7ac018
JB		 88 /* Driver for this DAI */
89 struct snd_soc_dai_driver i2s_dai_drv;
90 /* DMA parameters */
91 struct s3c_dma_params dma_playback;
92 struct s3c_dma_params dma_capture;
61100f40 93 struct s3c_dma_params idma_playback;
1c7ac018
JB		 94 u32 quirks;
95 u32 suspend_i2smod;
96 u32 suspend_i2scon;
97 u32 suspend_i2spsr;
a5a56871 98 const struct samsung_i2s_variant_regs *variant_regs;
1c7ac018
JB		 99};
100
101/* Lock for cross i/f checks */
102static DEFINE_SPINLOCK(lock);
103
104/* If this is the 'overlay' stereo DAI */
105static inline bool is_secondary(struct i2s_dai *i2s)
106{
107 return i2s->pri_dai ? true : false;
108}
109
110/* If operating in SoC-Slave mode */
111static inline bool is_slave(struct i2s_dai *i2s)
112{
a5a56871
PV		 113 u32 mod = readl(i2s->addr + I2SMOD);
114 return (mod & (1 << i2s->variant_regs->mss_off)) ? true : false;
1c7ac018
JB		 115}
116
117/* If this interface of the controller is transmitting data */
118static inline bool tx_active(struct i2s_dai *i2s)
119{
120 u32 active;
121
122 if (!i2s)
123 return false;
124
33195500 125 active = readl(i2s->addr + I2SCON);
1c7ac018
JB		 126
127 if (is_secondary(i2s))
128 active &= CON_TXSDMA_ACTIVE;
129 else
130 active &= CON_TXDMA_ACTIVE;
131
132 return active ? true : false;
133}
134
135/* If the other interface of the controller is transmitting data */
136static inline bool other_tx_active(struct i2s_dai *i2s)
137{
138 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
139
140 return tx_active(other);
141}
142
143/* If any interface of the controller is transmitting data */
144static inline bool any_tx_active(struct i2s_dai *i2s)
145{
146 return tx_active(i2s) || other_tx_active(i2s);
147}
148
149/* If this interface of the controller is receiving data */
150static inline bool rx_active(struct i2s_dai *i2s)
151{
152 u32 active;
153
154 if (!i2s)
155 return false;
156
33195500 157 active = readl(i2s->addr + I2SCON) & CON_RXDMA_ACTIVE;
1c7ac018
JB		 158
159 return active ? true : false;
160}
161
162/* If the other interface of the controller is receiving data */
163static inline bool other_rx_active(struct i2s_dai *i2s)
164{
165 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
166
167 return rx_active(other);
168}
169
170/* If any interface of the controller is receiving data */
171static inline bool any_rx_active(struct i2s_dai *i2s)
172{
173 return rx_active(i2s) || other_rx_active(i2s);
174}
175
176/* If the other DAI is transmitting or receiving data */
177static inline bool other_active(struct i2s_dai *i2s)
178{
179 return other_rx_active(i2s) || other_tx_active(i2s);
180}
181
182/* If this DAI is transmitting or receiving data */
183static inline bool this_active(struct i2s_dai *i2s)
184{
185 return tx_active(i2s) || rx_active(i2s);
186}
187
188/* If the controller is active anyway */
189static inline bool any_active(struct i2s_dai *i2s)
190{
191 return this_active(i2s) || other_active(i2s);
192}
193
194static inline struct i2s_dai *to_info(struct snd_soc_dai *dai)
195{
196 return snd_soc_dai_get_drvdata(dai);
197}
198
199static inline bool is_opened(struct i2s_dai *i2s)
200{
201 if (i2s && (i2s->mode & DAI_OPENED))
202 return true;
203 else
204 return false;
205}
206
207static inline bool is_manager(struct i2s_dai *i2s)
208{
209 if (is_opened(i2s) && (i2s->mode & DAI_MANAGER))
210 return true;
211 else
212 return false;
213}
214
215/* Read RCLK of I2S (in multiples of LRCLK) */
216static inline unsigned get_rfs(struct i2s_dai *i2s)
217{
4ca0c0d4 218 u32 rfs;
a5a56871
PV		 219 rfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->rfs_off;
220 rfs &= i2s->variant_regs->rfs_mask;
1c7ac018
JB		 221
222 switch (rfs) {
a5a56871
PV		 223 case 7: return 192;
224 case 6: return 96;
225 case 5: return 128;
226 case 4: return 64;
1c7ac018
JB		 227 case 3: return 768;
228 case 2: return 384;
229 case 1: return 512;
230 default: return 256;
231 }
232}
233
234/* Write RCLK of I2S (in multiples of LRCLK) */
235static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
236{
237 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871 238 int rfs_shift = i2s->variant_regs->rfs_off;
1c7ac018 239
a5a56871 240 mod &= ~(i2s->variant_regs->rfs_mask << rfs_shift);
1c7ac018
JB		 241
242 switch (rfs) {
a5a56871
PV		 243 case 192:
244 mod |= (EXYNOS7_MOD_RCLK_192FS << rfs_shift);
245 break;
246 case 96:
247 mod |= (EXYNOS7_MOD_RCLK_96FS << rfs_shift);
248 break;
249 case 128:
250 mod |= (EXYNOS7_MOD_RCLK_128FS << rfs_shift);
251 break;
252 case 64:
253 mod |= (EXYNOS7_MOD_RCLK_64FS << rfs_shift);
254 break;
1c7ac018 255 case 768:
b60be4aa 256 mod |= (MOD_RCLK_768FS << rfs_shift);
1c7ac018
JB		 257 break;
258 case 512:
b60be4aa 259 mod |= (MOD_RCLK_512FS << rfs_shift);
1c7ac018
JB		 260 break;
261 case 384:
b60be4aa 262 mod |= (MOD_RCLK_384FS << rfs_shift);
1c7ac018
JB		 263 break;
264 default:
b60be4aa 265 mod |= (MOD_RCLK_256FS << rfs_shift);
1c7ac018
JB		 266 break;
267 }
268
269 writel(mod, i2s->addr + I2SMOD);
270}
271
272/* Read Bit-Clock of I2S (in multiples of LRCLK) */
273static inline unsigned get_bfs(struct i2s_dai *i2s)
274{
4ca0c0d4 275 u32 bfs;
a5a56871
PV		 276 bfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->bfs_off;
277 bfs &= i2s->variant_regs->bfs_mask;
1c7ac018
JB		 278
279 switch (bfs) {
4ca0c0d4
PV		 280 case 8: return 256;
281 case 7: return 192;
282 case 6: return 128;
283 case 5: return 96;
284 case 4: return 64;
1c7ac018
JB		 285 case 3: return 24;
286 case 2: return 16;
287 case 1: return 48;
288 default: return 32;
289 }
290}
291
292/* Write Bit-Clock of I2S (in multiples of LRCLK) */
293static inline void set_bfs(struct i2s_dai *i2s, unsigned bfs)
294{
295 u32 mod = readl(i2s->addr + I2SMOD);
4ca0c0d4 296 int tdm = i2s->quirks & QUIRK_SUPPORTS_TDM;
a5a56871 297 int bfs_shift = i2s->variant_regs->bfs_off;
4ca0c0d4
PV		 298
299 /* Non-TDM I2S controllers do not support BCLK > 48 * FS */
300 if (!tdm && bfs > 48) {
301 dev_err(&i2s->pdev->dev, "Unsupported BCLK divider\n");
302 return;
303 }
1c7ac018 304
a5a56871
PV		 305 mod &= ~(i2s->variant_regs->bfs_mask << bfs_shift);
306
1c7ac018
JB		 307 switch (bfs) {
308 case 48:
b60be4aa 309 mod |= (MOD_BCLK_48FS << bfs_shift);
1c7ac018
JB		 310 break;
311 case 32:
b60be4aa 312 mod |= (MOD_BCLK_32FS << bfs_shift);
1c7ac018
JB		 313 break;
314 case 24:
b60be4aa 315 mod |= (MOD_BCLK_24FS << bfs_shift);
1c7ac018
JB		 316 break;
317 case 16:
b60be4aa 318 mod |= (MOD_BCLK_16FS << bfs_shift);
1c7ac018 319 break;
4ca0c0d4
PV		 320 case 64:
321 mod |= (EXYNOS5420_MOD_BCLK_64FS << bfs_shift);
322 break;
323 case 96:
324 mod |= (EXYNOS5420_MOD_BCLK_96FS << bfs_shift);
325 break;
326 case 128:
327 mod |= (EXYNOS5420_MOD_BCLK_128FS << bfs_shift);
328 break;
329 case 192:
330 mod |= (EXYNOS5420_MOD_BCLK_192FS << bfs_shift);
331 break;
332 case 256:
333 mod |= (EXYNOS5420_MOD_BCLK_256FS << bfs_shift);
1c7ac018
JB		 334 break;
335 default:
336 dev_err(&i2s->pdev->dev, "Wrong BCLK Divider!\n");
337 return;
338 }
339
340 writel(mod, i2s->addr + I2SMOD);
341}
342
343/* Sample-Size */
344static inline int get_blc(struct i2s_dai *i2s)
345{
346 int blc = readl(i2s->addr + I2SMOD);
347
348 blc = (blc >> 13) & 0x3;
349
350 switch (blc) {
351 case 2: return 24;
352 case 1: return 8;
353 default: return 16;
354 }
355}
356
357/* TX Channel Control */
358static void i2s_txctrl(struct i2s_dai *i2s, int on)
359{
360 void __iomem *addr = i2s->addr;
a5a56871 361 int txr_off = i2s->variant_regs->txr_off;
1c7ac018 362 u32 con = readl(addr + I2SCON);
a5a56871 363 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
1c7ac018
JB		 364
365 if (on) {
366 con |= CON_ACTIVE;
367 con &= ~CON_TXCH_PAUSE;
368
369 if (is_secondary(i2s)) {
370 con |= CON_TXSDMA_ACTIVE;
371 con &= ~CON_TXSDMA_PAUSE;
372 } else {
373 con |= CON_TXDMA_ACTIVE;
374 con &= ~CON_TXDMA_PAUSE;
375 }
376
377 if (any_rx_active(i2s))
a5a56871 378 mod |= 2 << txr_off;
1c7ac018 379 else
a5a56871 380 mod |= 0 << txr_off;
1c7ac018
JB		 381 } else {
382 if (is_secondary(i2s)) {
383 con |= CON_TXSDMA_PAUSE;
384 con &= ~CON_TXSDMA_ACTIVE;
385 } else {
386 con |= CON_TXDMA_PAUSE;
387 con &= ~CON_TXDMA_ACTIVE;
388 }
389
390 if (other_tx_active(i2s)) {
391 writel(con, addr + I2SCON);
392 return;
393 }
394
395 con |= CON_TXCH_PAUSE;
396
397 if (any_rx_active(i2s))
a5a56871 398 mod |= 1 << txr_off;
1c7ac018
JB		 399 else
400 con &= ~CON_ACTIVE;
401 }
402
403 writel(mod, addr + I2SMOD);
404 writel(con, addr + I2SCON);
405}
406
407/* RX Channel Control */
408static void i2s_rxctrl(struct i2s_dai *i2s, int on)
409{
410 void __iomem *addr = i2s->addr;
a5a56871 411 int txr_off = i2s->variant_regs->txr_off;
1c7ac018 412 u32 con = readl(addr + I2SCON);
a5a56871 413 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
1c7ac018
JB		 414
415 if (on) {
416 con |= CON_RXDMA_ACTIVE | CON_ACTIVE;
417 con &= ~(CON_RXDMA_PAUSE | CON_RXCH_PAUSE);
418
419 if (any_tx_active(i2s))
a5a56871 420 mod |= 2 << txr_off;
1c7ac018 421 else
a5a56871 422 mod |= 1 << txr_off;
1c7ac018
JB		 423 } else {
424 con |= CON_RXDMA_PAUSE | CON_RXCH_PAUSE;
425 con &= ~CON_RXDMA_ACTIVE;
426
427 if (any_tx_active(i2s))
a5a56871 428 mod |= 0 << txr_off;
1c7ac018
JB		 429 else
430 con &= ~CON_ACTIVE;
431 }
432
433 writel(mod, addr + I2SMOD);
434 writel(con, addr + I2SCON);
435}
436
437/* Flush FIFO of an interface */
438static inline void i2s_fifo(struct i2s_dai *i2s, u32 flush)
439{
440 void __iomem *fic;
441 u32 val;
442
443 if (!i2s)
444 return;
445
446 if (is_secondary(i2s))
447 fic = i2s->addr + I2SFICS;
448 else
449 fic = i2s->addr + I2SFIC;
450
451 /* Flush the FIFO */
452 writel(readl(fic) | flush, fic);
453
454 /* Be patient */
455 val = msecs_to_loops(1) / 1000; /* 1 usec */
456 while (--val)
457 cpu_relax();
458
459 writel(readl(fic) & ~flush, fic);
460}
461
462static int i2s_set_sysclk(struct snd_soc_dai *dai,
463 int clk_id, unsigned int rfs, int dir)
464{
465 struct i2s_dai *i2s = to_info(dai);
466 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
467 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871
PV		 468 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
469 unsigned int cdcon_mask = 1 << i2s_regs->cdclkcon_off;
470 unsigned int rsrc_mask = 1 << i2s_regs->rclksrc_off;
1c7ac018
JB		 471
472 switch (clk_id) {
c86d50f9
SN		 473 case SAMSUNG_I2S_OPCLK:
474 mod &= ~MOD_OPCLK_MASK;
475 mod |= dir;
476 break;
1c7ac018
JB		 477 case SAMSUNG_I2S_CDCLK:
478 /* Shouldn't matter in GATING(CLOCK_IN) mode */
479 if (dir == SND_SOC_CLOCK_IN)
480 rfs = 0;
481
133c2681 482 if ((rfs && other && other->rfs && (other->rfs != rfs)) ||
1c7ac018
JB		 483 (any_active(i2s) &&
484 (((dir == SND_SOC_CLOCK_IN)
a5a56871 485 && !(mod & cdcon_mask)) ||
1c7ac018 486 ((dir == SND_SOC_CLOCK_OUT)
a5a56871 487 && (mod & cdcon_mask))))) {
1c7ac018
JB		 488 dev_err(&i2s->pdev->dev,
489 "%s:%d Other DAI busy\n", __func__, __LINE__);
490 return -EAGAIN;
491 }
492
493 if (dir == SND_SOC_CLOCK_IN)
a5a56871 494 mod |= 1 << i2s_regs->cdclkcon_off;
1c7ac018 495 else
b2de1d20 496 mod &= ~(1 << i2s_regs->cdclkcon_off);
1c7ac018
JB		 497
498 i2s->rfs = rfs;
499 break;
500
501 case SAMSUNG_I2S_RCLKSRC_0: /* clock corrsponding to IISMOD[10] := 0 */
502 case SAMSUNG_I2S_RCLKSRC_1: /* clock corrsponding to IISMOD[10] := 1 */
503 if ((i2s->quirks & QUIRK_NO_MUXPSR)
504 || (clk_id == SAMSUNG_I2S_RCLKSRC_0))
505 clk_id = 0;
506 else
507 clk_id = 1;
508
509 if (!any_active(i2s)) {
a6aba536 510 if (i2s->op_clk && !IS_ERR(i2s->op_clk)) {
a5a56871
PV		 511 if ((clk_id && !(mod & rsrc_mask)) ||
512 (!clk_id && (mod & rsrc_mask))) {
98614cf6 513 clk_disable_unprepare(i2s->op_clk);
1c7ac018
JB		 514 clk_put(i2s->op_clk);
515 } else {
6ce534aa
JB		 516 i2s->rclk_srcrate =
517 clk_get_rate(i2s->op_clk);
1c7ac018
JB		 518 return 0;
519 }
520 }
521
1974a042
PV		 522 if (clk_id)
523 i2s->op_clk = clk_get(&i2s->pdev->dev,
524 "i2s_opclk1");
525 else
526 i2s->op_clk = clk_get(&i2s->pdev->dev,
527 "i2s_opclk0");
a6aba536
SN		 528
529 if (WARN_ON(IS_ERR(i2s->op_clk)))
530 return PTR_ERR(i2s->op_clk);
531
98614cf6 532 clk_prepare_enable(i2s->op_clk);
1c7ac018
JB		 533 i2s->rclk_srcrate = clk_get_rate(i2s->op_clk);
534
535 /* Over-ride the other's */
536 if (other) {
537 other->op_clk = i2s->op_clk;
538 other->rclk_srcrate = i2s->rclk_srcrate;
539 }
a5a56871
PV		 540 } else if ((!clk_id && (mod & rsrc_mask))
541 || (clk_id && !(mod & rsrc_mask))) {
1c7ac018
JB		 542 dev_err(&i2s->pdev->dev,
543 "%s:%d Other DAI busy\n", __func__, __LINE__);
544 return -EAGAIN;
545 } else {
546 /* Call can't be on the active DAI */
547 i2s->op_clk = other->op_clk;
548 i2s->rclk_srcrate = other->rclk_srcrate;
549 return 0;
550 }
551
552 if (clk_id == 0)
b2de1d20 553 mod &= ~(1 << i2s_regs->rclksrc_off);
1c7ac018 554 else
a5a56871 555 mod |= 1 << i2s_regs->rclksrc_off;
1c7ac018 556
b2de1d20 557 break;
1c7ac018
JB		 558 default:
559 dev_err(&i2s->pdev->dev, "We don't serve that!\n");
560 return -EINVAL;
561 }
562
563 writel(mod, i2s->addr + I2SMOD);
564
565 return 0;
566}
567
568static int i2s_set_fmt(struct snd_soc_dai *dai,
569 unsigned int fmt)
570{
571 struct i2s_dai *i2s = to_info(dai);
572 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871 573 int lrp_shift, sdf_shift, sdf_mask, lrp_rlow, mod_slave;
1c7ac018
JB		 574 u32 tmp = 0;
575
a5a56871
PV		 576 lrp_shift = i2s->variant_regs->lrp_off;
577 sdf_shift = i2s->variant_regs->sdf_off;
578 mod_slave = 1 << i2s->variant_regs->mss_off;
4ca0c0d4 579
b60be4aa
PV		 580 sdf_mask = MOD_SDF_MASK << sdf_shift;
581 lrp_rlow = MOD_LR_RLOW << lrp_shift;
582
1c7ac018
JB		 583 /* Format is priority */
584 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
585 case SND_SOC_DAIFMT_RIGHT_J:
b60be4aa
PV		 586 tmp |= lrp_rlow;
587 tmp |= (MOD_SDF_MSB << sdf_shift);
1c7ac018
JB		 588 break;
589 case SND_SOC_DAIFMT_LEFT_J:
b60be4aa
PV		 590 tmp |= lrp_rlow;
591 tmp |= (MOD_SDF_LSB << sdf_shift);
1c7ac018
JB		 592 break;
593 case SND_SOC_DAIFMT_I2S:
b60be4aa 594 tmp |= (MOD_SDF_IIS << sdf_shift);
1c7ac018
JB		 595 break;
596 default:
597 dev_err(&i2s->pdev->dev, "Format not supported\n");
598 return -EINVAL;
599 }
600
601 /*
602 * INV flag is relative to the FORMAT flag - if set it simply
603 * flips the polarity specified by the Standard
604 */
605 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
606 case SND_SOC_DAIFMT_NB_NF:
607 break;
608 case SND_SOC_DAIFMT_NB_IF:
b60be4aa
PV		 609 if (tmp & lrp_rlow)
610 tmp &= ~lrp_rlow;
1c7ac018 611 else
b60be4aa 612 tmp |= lrp_rlow;
1c7ac018
JB		 613 break;
614 default:
615 dev_err(&i2s->pdev->dev, "Polarity not supported\n");
616 return -EINVAL;
617 }
618
619 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
620 case SND_SOC_DAIFMT_CBM_CFM:
a5a56871 621 tmp |= mod_slave;
1c7ac018
JB		 622 break;
623 case SND_SOC_DAIFMT_CBS_CFS:
624 /* Set default source clock in Master mode */
625 if (i2s->rclk_srcrate == 0)
626 i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0,
627 0, SND_SOC_CLOCK_IN);
628 break;
629 default:
630 dev_err(&i2s->pdev->dev, "master/slave format not supported\n");
631 return -EINVAL;
632 }
633
b60be4aa
PV		 634 /*
635 * Don't change the I2S mode if any controller is active on this
636 * channel.
637 */
1c7ac018 638 if (any_active(i2s) &&
a5a56871 639 ((mod & (sdf_mask | lrp_rlow | mod_slave)) != tmp)) {
1c7ac018
JB		 640 dev_err(&i2s->pdev->dev,
641 "%s:%d Other DAI busy\n", __func__, __LINE__);
642 return -EAGAIN;
643 }
644
a5a56871 645 mod &= ~(sdf_mask | lrp_rlow | mod_slave);
1c7ac018
JB		 646 mod |= tmp;
647 writel(mod, i2s->addr + I2SMOD);
648
649 return 0;
650}
651
652static int i2s_hw_params(struct snd_pcm_substream *substream,
653 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
654{
655 struct i2s_dai *i2s = to_info(dai);
656 u32 mod = readl(i2s->addr + I2SMOD);
657
658 if (!is_secondary(i2s))
659 mod &= ~(MOD_DC2_EN | MOD_DC1_EN);
660
661 switch (params_channels(params)) {
662 case 6:
663 mod |= MOD_DC2_EN;
664 case 4:
665 mod |= MOD_DC1_EN;
666 break;
667 case 2:
588fb705
SP		 668 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
669 i2s->dma_playback.dma_size = 4;
670 else
671 i2s->dma_capture.dma_size = 4;
672 break;
673 case 1:
674 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
675 i2s->dma_playback.dma_size = 2;
676 else
677 i2s->dma_capture.dma_size = 2;
678
1c7ac018
JB		 679 break;
680 default:
681 dev_err(&i2s->pdev->dev, "%d channels not supported\n",
682 params_channels(params));
683 return -EINVAL;
684 }
685
686 if (is_secondary(i2s))
687 mod &= ~MOD_BLCS_MASK;
688 else
689 mod &= ~MOD_BLCP_MASK;
690
691 if (is_manager(i2s))
692 mod &= ~MOD_BLC_MASK;
693
88ce1465
TB		 694 switch (params_width(params)) {
695 case 8:
1c7ac018
JB		 696 if (is_secondary(i2s))
697 mod |= MOD_BLCS_8BIT;
698 else
699 mod |= MOD_BLCP_8BIT;
700 if (is_manager(i2s))
701 mod |= MOD_BLC_8BIT;
702 break;
88ce1465 703 case 16:
1c7ac018
JB		 704 if (is_secondary(i2s))
705 mod |= MOD_BLCS_16BIT;
706 else
707 mod |= MOD_BLCP_16BIT;
708 if (is_manager(i2s))
709 mod |= MOD_BLC_16BIT;
710 break;
88ce1465 711 case 24:
1c7ac018
JB		 712 if (is_secondary(i2s))
713 mod |= MOD_BLCS_24BIT;
714 else
715 mod |= MOD_BLCP_24BIT;
716 if (is_manager(i2s))
717 mod |= MOD_BLC_24BIT;
718 break;
719 default:
720 dev_err(&i2s->pdev->dev, "Format(%d) not supported\n",
721 params_format(params));
722 return -EINVAL;
723 }
724 writel(mod, i2s->addr + I2SMOD);
725
d37bdf73
MB		 726 samsung_asoc_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture);
727
1c7ac018
JB		 728 i2s->frmclk = params_rate(params);
729
730 return 0;
731}
732
733/* We set constraints on the substream acc to the version of I2S */
734static int i2s_startup(struct snd_pcm_substream *substream,
735 struct snd_soc_dai *dai)
736{
737 struct i2s_dai *i2s = to_info(dai);
738 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
739 unsigned long flags;
740
741 spin_lock_irqsave(&lock, flags);
742
743 i2s->mode |= DAI_OPENED;
744
745 if (is_manager(other))
746 i2s->mode &= ~DAI_MANAGER;
747 else
748 i2s->mode |= DAI_MANAGER;
749
2d77828d
PV		 750 if (!any_active(i2s) && (i2s->quirks & QUIRK_NEED_RSTCLR))
751 writel(CON_RSTCLR, i2s->addr + I2SCON);
752
1c7ac018
JB		 753 spin_unlock_irqrestore(&lock, flags);
754
b97c60ab
SN		 755 if (!is_opened(other) && i2s->cdclk_out)
756 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
757 0, SND_SOC_CLOCK_OUT);
1c7ac018
JB		 758 return 0;
759}
760
761static void i2s_shutdown(struct snd_pcm_substream *substream,
762 struct snd_soc_dai *dai)
763{
764 struct i2s_dai *i2s = to_info(dai);
765 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
766 unsigned long flags;
a5a56871 767 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
1c7ac018
JB		 768
769 spin_lock_irqsave(&lock, flags);
770
771 i2s->mode &= ~DAI_OPENED;
772 i2s->mode &= ~DAI_MANAGER;
773
b97c60ab 774 if (is_opened(other)) {
1c7ac018 775 other->mode |= DAI_MANAGER;
b97c60ab
SN		 776 } else {
777 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871 778 i2s->cdclk_out = !(mod & (1 << i2s_regs->cdclkcon_off));
133c2681
CK		 779 if (other)
780 other->cdclk_out = i2s->cdclk_out;
b97c60ab 781 }
1c7ac018
JB		 782 /* Reset any constraint on RFS and BFS */
783 i2s->rfs = 0;
784 i2s->bfs = 0;
785
786 spin_unlock_irqrestore(&lock, flags);
787
788 /* Gate CDCLK by default */
789 if (!is_opened(other))
790 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
791 0, SND_SOC_CLOCK_IN);
792}
793
794static int config_setup(struct i2s_dai *i2s)
795{
796 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
797 unsigned rfs, bfs, blc;
798 u32 psr;
799
800 blc = get_blc(i2s);
801
802 bfs = i2s->bfs;
803
804 if (!bfs && other)
805 bfs = other->bfs;
806
807 /* Select least possible multiple(2) if no constraint set */
808 if (!bfs)
809 bfs = blc * 2;
810
811 rfs = i2s->rfs;
812
813 if (!rfs && other)
814 rfs = other->rfs;
815
816 if ((rfs == 256 || rfs == 512) && (blc == 24)) {
817 dev_err(&i2s->pdev->dev,
818 "%d-RFS not supported for 24-blc\n", rfs);
819 return -EINVAL;
820 }
821
822 if (!rfs) {
823 if (bfs == 16 || bfs == 32)
824 rfs = 256;
825 else
826 rfs = 384;
827 }
828
829 /* If already setup and running */
830 if (any_active(i2s) && (get_rfs(i2s) != rfs || get_bfs(i2s) != bfs)) {
831 dev_err(&i2s->pdev->dev,
832 "%s:%d Other DAI busy\n", __func__, __LINE__);
833 return -EAGAIN;
834 }
835
1c7ac018
JB		 836 set_bfs(i2s, bfs);
837 set_rfs(i2s, rfs);
838
77010010
PV		 839 /* Don't bother with PSR in Slave mode */
840 if (is_slave(i2s))
841 return 0;
842
1c7ac018
JB		 843 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) {
844 psr = i2s->rclk_srcrate / i2s->frmclk / rfs;
845 writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR);
846 dev_dbg(&i2s->pdev->dev,
847 "RCLK_SRC=%luHz PSR=%u, RCLK=%dfs, BCLK=%dfs\n",
848 i2s->rclk_srcrate, psr, rfs, bfs);
849 }
850
851 return 0;
852}
853
854static int i2s_trigger(struct snd_pcm_substream *substream,
855 int cmd, struct snd_soc_dai *dai)
856{
857 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
858 struct snd_soc_pcm_runtime *rtd = substream->private_data;
859 struct i2s_dai *i2s = to_info(rtd->cpu_dai);
860 unsigned long flags;
861
862 switch (cmd) {
863 case SNDRV_PCM_TRIGGER_START:
864 case SNDRV_PCM_TRIGGER_RESUME:
865 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
866 local_irq_save(flags);
867
1c7ac018
JB		 868 if (config_setup(i2s)) {
869 local_irq_restore(flags);
870 return -EINVAL;
871 }
872
873 if (capture)
874 i2s_rxctrl(i2s, 1);
875 else
876 i2s_txctrl(i2s, 1);
877
878 local_irq_restore(flags);
879 break;
880 case SNDRV_PCM_TRIGGER_STOP:
881 case SNDRV_PCM_TRIGGER_SUSPEND:
882 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
883 local_irq_save(flags);
884
c90887fe 885 if (capture) {
1c7ac018 886 i2s_rxctrl(i2s, 0);
775bc971 887 i2s_fifo(i2s, FIC_RXFLUSH);
c90887fe
JB		 888 } else {
889 i2s_txctrl(i2s, 0);
775bc971 890 i2s_fifo(i2s, FIC_TXFLUSH);
c90887fe 891 }
775bc971 892
1c7ac018
JB		 893 local_irq_restore(flags);
894 break;
895 }
896
897 return 0;
898}
899
900static int i2s_set_clkdiv(struct snd_soc_dai *dai,
901 int div_id, int div)
902{
903 struct i2s_dai *i2s = to_info(dai);
904 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
905
906 switch (div_id) {
907 case SAMSUNG_I2S_DIV_BCLK:
908 if ((any_active(i2s) && div && (get_bfs(i2s) != div))
909 || (other && other->bfs && (other->bfs != div))) {
910 dev_err(&i2s->pdev->dev,
911 "%s:%d Other DAI busy\n", __func__, __LINE__);
912 return -EAGAIN;
913 }
914 i2s->bfs = div;
915 break;
916 default:
917 dev_err(&i2s->pdev->dev,
918 "Invalid clock divider(%d)\n", div_id);
919 return -EINVAL;
920 }
921
922 return 0;
923}
924
925static snd_pcm_sframes_t
926i2s_delay(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
927{
928 struct i2s_dai *i2s = to_info(dai);
929 u32 reg = readl(i2s->addr + I2SFIC);
930 snd_pcm_sframes_t delay;
a5a56871 931 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
1c7ac018
JB		 932
933 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
934 delay = FIC_RXCOUNT(reg);
935 else if (is_secondary(i2s))
936 delay = FICS_TXCOUNT(readl(i2s->addr + I2SFICS));
937 else
a5a56871 938 delay = (reg >> i2s_regs->ftx0cnt_off) & 0x7f;
1c7ac018
JB		 939
940 return delay;
941}
942
943#ifdef CONFIG_PM
944static int i2s_suspend(struct snd_soc_dai *dai)
945{
946 struct i2s_dai *i2s = to_info(dai);
947
d3d4e524
SN		 948 i2s->suspend_i2smod = readl(i2s->addr + I2SMOD);
949 i2s->suspend_i2scon = readl(i2s->addr + I2SCON);
950 i2s->suspend_i2spsr = readl(i2s->addr + I2SPSR);
1c7ac018
JB		 951
952 return 0;
953}
954
955static int i2s_resume(struct snd_soc_dai *dai)
956{
957 struct i2s_dai *i2s = to_info(dai);
958
d3d4e524
SN		 959 writel(i2s->suspend_i2scon, i2s->addr + I2SCON);
960 writel(i2s->suspend_i2smod, i2s->addr + I2SMOD);
961 writel(i2s->suspend_i2spsr, i2s->addr + I2SPSR);
1c7ac018
JB		 962
963 return 0;
964}
965#else
966#define i2s_suspend NULL
967#define i2s_resume NULL
968#endif
969
970static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
971{
972 struct i2s_dai *i2s = to_info(dai);
973 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
ba56447c 974 int ret;
1c7ac018 975
3688569e
MB		 976 if (other && other->clk) { /* If this is probe on secondary */
977 samsung_asoc_init_dma_data(dai, &other->sec_dai->dma_playback,
978 NULL);
1c7ac018 979 goto probe_exit;
3688569e 980 }
1c7ac018
JB		 981
982 i2s->addr = ioremap(i2s->base, 0x100);
983 if (i2s->addr == NULL) {
984 dev_err(&i2s->pdev->dev, "cannot ioremap registers\n");
985 return -ENXIO;
986 }
987
988 i2s->clk = clk_get(&i2s->pdev->dev, "iis");
989 if (IS_ERR(i2s->clk)) {
990 dev_err(&i2s->pdev->dev, "failed to get i2s_clock\n");
991 iounmap(i2s->addr);
ba56447c
MB		 992 return PTR_ERR(i2s->clk);
993 }
994
995 ret = clk_prepare_enable(i2s->clk);
996 if (ret != 0) {
997 dev_err(&i2s->pdev->dev, "failed to enable clock: %d\n", ret);
998 return ret;
1c7ac018 999 }
1c7ac018 1000
3688569e 1001 samsung_asoc_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture);
511e3033 1002
1c7ac018
JB		 1003 if (other) {
1004 other->addr = i2s->addr;
1005 other->clk = i2s->clk;
1006 }
1007
1008 if (i2s->quirks & QUIRK_NEED_RSTCLR)
1009 writel(CON_RSTCLR, i2s->addr + I2SCON);
1010
b0759736 1011 if (i2s->quirks & QUIRK_SUPPORTS_IDMA)
9b8f5695 1012 idma_reg_addr_init(i2s->addr,
61100f40
SK		 1013 i2s->sec_dai->idma_playback.dma_addr);
1014
1c7ac018
JB		 1015probe_exit:
1016 /* Reset any constraint on RFS and BFS */
1017 i2s->rfs = 0;
1018 i2s->bfs = 0;
d66eac3e 1019 i2s->rclk_srcrate = 0;
1c7ac018
JB		 1020 i2s_txctrl(i2s, 0);
1021 i2s_rxctrl(i2s, 0);
1022 i2s_fifo(i2s, FIC_TXFLUSH);
1023 i2s_fifo(other, FIC_TXFLUSH);
1024 i2s_fifo(i2s, FIC_RXFLUSH);
1025
1026 /* Gate CDCLK by default */
1027 if (!is_opened(other))
1028 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
1029 0, SND_SOC_CLOCK_IN);
1030
1031 return 0;
1032}
1033
1034static int samsung_i2s_dai_remove(struct snd_soc_dai *dai)
1035{
1036 struct i2s_dai *i2s = snd_soc_dai_get_drvdata(dai);
1037 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
1038
1039 if (!other || !other->clk) {
1040
1041 if (i2s->quirks & QUIRK_NEED_RSTCLR)
1042 writel(0, i2s->addr + I2SCON);
1043
98614cf6 1044 clk_disable_unprepare(i2s->clk);
1c7ac018
JB		 1045 clk_put(i2s->clk);
1046
1047 iounmap(i2s->addr);
1048 }
1049
1050 i2s->clk = NULL;
1051
1052 return 0;
1053}
1054
85e7652d 1055static const struct snd_soc_dai_ops samsung_i2s_dai_ops = {
1c7ac018
JB		 1056 .trigger = i2s_trigger,
1057 .hw_params = i2s_hw_params,
1058 .set_fmt = i2s_set_fmt,
1059 .set_clkdiv = i2s_set_clkdiv,
1060 .set_sysclk = i2s_set_sysclk,
1061 .startup = i2s_startup,
1062 .shutdown = i2s_shutdown,
1063 .delay = i2s_delay,
1064};
1065
4b828535
KM		 1066static const struct snd_soc_component_driver samsung_i2s_component = {
1067 .name = "samsung-i2s",
1068};
1069
1c7ac018
JB		 1070#define SAMSUNG_I2S_RATES SNDRV_PCM_RATE_8000_96000
1071
1072#define SAMSUNG_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1073 SNDRV_PCM_FMTBIT_S16_LE | \
1074 SNDRV_PCM_FMTBIT_S24_LE)
1075
fdca21ad 1076static struct i2s_dai *i2s_alloc_dai(struct platform_device *pdev, bool sec)
1c7ac018
JB		 1077{
1078 struct i2s_dai *i2s;
c6f9b1eb 1079 int ret;
1c7ac018 1080
b960ce74 1081 i2s = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dai), GFP_KERNEL);
1c7ac018
JB		 1082 if (i2s == NULL)
1083 return NULL;
1084
1085 i2s->pdev = pdev;
1086 i2s->pri_dai = NULL;
1087 i2s->sec_dai = NULL;
1088 i2s->i2s_dai_drv.symmetric_rates = 1;
1089 i2s->i2s_dai_drv.probe = samsung_i2s_dai_probe;
1090 i2s->i2s_dai_drv.remove = samsung_i2s_dai_remove;
1091 i2s->i2s_dai_drv.ops = &samsung_i2s_dai_ops;
1092 i2s->i2s_dai_drv.suspend = i2s_suspend;
1093 i2s->i2s_dai_drv.resume = i2s_resume;
a0ff6ea2 1094 i2s->i2s_dai_drv.playback.channels_min = 1;
1c7ac018
JB		 1095 i2s->i2s_dai_drv.playback.channels_max = 2;
1096 i2s->i2s_dai_drv.playback.rates = SAMSUNG_I2S_RATES;
1097 i2s->i2s_dai_drv.playback.formats = SAMSUNG_I2S_FMTS;
1098
1099 if (!sec) {
588fb705 1100 i2s->i2s_dai_drv.capture.channels_min = 1;
1c7ac018
JB		 1101 i2s->i2s_dai_drv.capture.channels_max = 2;
1102 i2s->i2s_dai_drv.capture.rates = SAMSUNG_I2S_RATES;
1103 i2s->i2s_dai_drv.capture.formats = SAMSUNG_I2S_FMTS;
c6f9b1eb 1104 dev_set_drvdata(&i2s->pdev->dev, i2s);
1c7ac018 1105 } else { /* Create a new platform_device for Secondary */
c6f9b1eb 1106 i2s->pdev = platform_device_alloc("samsung-i2s-sec", -1);
29ca9c73 1107 if (!i2s->pdev)
1c7ac018 1108 return NULL;
1c7ac018 1109
2f6f0ffb
MB		 1110 i2s->pdev->dev.parent = &pdev->dev;
1111
c6f9b1eb
P		 1112 platform_set_drvdata(i2s->pdev, i2s);
1113 ret = platform_device_add(i2s->pdev);
1114 if (ret < 0)
1115 return NULL;
1116 }
1c7ac018
JB		 1117
1118 return i2s;
1119}
1120
40476f61
PV		 1121static const struct of_device_id exynos_i2s_match[];
1122
7da493e9
PV		 1123static inline const struct samsung_i2s_dai_data *samsung_i2s_get_driver_data(
1124 struct platform_device *pdev)
7c62eebb 1125{
9cf24747 1126 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
40476f61
PV		 1127 const struct of_device_id *match;
1128 match = of_match_node(exynos_i2s_match, pdev->dev.of_node);
9cf24747
SN		 1129 return match ? match->data : NULL;
1130 } else {
7da493e9
PV		 1131 return (struct samsung_i2s_dai_data *)
1132 platform_get_device_id(pdev)->driver_data;
9cf24747 1133 }
7c62eebb
PV		 1134}
1135
641d334b 1136#ifdef CONFIG_PM
5b1d3c34
C		 1137static int i2s_runtime_suspend(struct device *dev)
1138{
1139 struct i2s_dai *i2s = dev_get_drvdata(dev);
1140
1141 clk_disable_unprepare(i2s->clk);
1142
1143 return 0;
1144}
1145
1146static int i2s_runtime_resume(struct device *dev)
1147{
1148 struct i2s_dai *i2s = dev_get_drvdata(dev);
1149
1150 clk_prepare_enable(i2s->clk);
1151
1152 return 0;
1153}
641d334b 1154#endif /* CONFIG_PM */
5b1d3c34 1155
fdca21ad 1156static int samsung_i2s_probe(struct platform_device *pdev)
1c7ac018 1157{
1c7ac018 1158 struct i2s_dai *pri_dai, *sec_dai = NULL;
40476f61
PV		 1159 struct s3c_audio_pdata *i2s_pdata = pdev->dev.platform_data;
1160 struct samsung_i2s *i2s_cfg = NULL;
1c7ac018 1161 struct resource *res;
40476f61
PV		 1162 u32 regs_base, quirks = 0, idma_addr = 0;
1163 struct device_node *np = pdev->dev.of_node;
7da493e9 1164 const struct samsung_i2s_dai_data *i2s_dai_data;
1c7ac018
JB		 1165 int ret = 0;
1166
1167 /* Call during Seconday interface registration */
7da493e9 1168 i2s_dai_data = samsung_i2s_get_driver_data(pdev);
7c62eebb 1169
7da493e9 1170 if (i2s_dai_data->dai_type == TYPE_SEC) {
1c7ac018 1171 sec_dai = dev_get_drvdata(&pdev->dev);
a9b977ec
P		 1172 if (!sec_dai) {
1173 dev_err(&pdev->dev, "Unable to get drvdata\n");
1174 return -EFAULT;
1175 }
53f7faa1 1176 ret = devm_snd_soc_register_component(&sec_dai->pdev->dev,
d644a115
MB		 1177 &samsung_i2s_component,
1178 &sec_dai->i2s_dai_drv, 1);
53f7faa1
SN		 1179 if (ret != 0)
1180 return ret;
1181
1182 return samsung_asoc_dma_platform_register(&pdev->dev);
1c7ac018
JB		 1183 }
1184
40476f61
PV		 1185 pri_dai = i2s_alloc_dai(pdev, false);
1186 if (!pri_dai) {
1187 dev_err(&pdev->dev, "Unable to alloc I2S_pri\n");
1188 return -ENOMEM;
1c7ac018
JB		 1189 }
1190
40476f61
PV		 1191 if (!np) {
1192 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1193 if (!res) {
1194 dev_err(&pdev->dev,
1195 "Unable to get I2S-TX dma resource\n");
1196 return -ENXIO;
1197 }
1198 pri_dai->dma_playback.channel = res->start;
1c7ac018 1199
40476f61
PV		 1200 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1201 if (!res) {
1202 dev_err(&pdev->dev,
1203 "Unable to get I2S-RX dma resource\n");
1204 return -ENXIO;
1205 }
1206 pri_dai->dma_capture.channel = res->start;
1c7ac018 1207
40476f61
PV		 1208 if (i2s_pdata == NULL) {
1209 dev_err(&pdev->dev, "Can't work without s3c_audio_pdata\n");
1210 return -EINVAL;
1211 }
1212
1213 if (&i2s_pdata->type)
1214 i2s_cfg = &i2s_pdata->type.i2s;
1215
1216 if (i2s_cfg) {
1217 quirks = i2s_cfg->quirks;
1218 idma_addr = i2s_cfg->idma_addr;
1219 }
1220 } else {
7da493e9 1221 quirks = i2s_dai_data->quirks;
40476f61
PV		 1222 if (of_property_read_u32(np, "samsung,idma-addr",
1223 &idma_addr)) {
b0759736
PV		 1224 if (quirks & QUIRK_SUPPORTS_IDMA) {
1225 dev_info(&pdev->dev, "idma address is not"\
40476f61 1226 "specified");
40476f61
PV		 1227 }
1228 }
1229 }
1c7ac018
JB		 1230
1231 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1232 if (!res) {
1233 dev_err(&pdev->dev, "Unable to get I2S SFR address\n");
1234 return -ENXIO;
1235 }
1236
1237 if (!request_mem_region(res->start, resource_size(res),
1238 "samsung-i2s")) {
1239 dev_err(&pdev->dev, "Unable to request SFR region\n");
1240 return -EBUSY;
1241 }
1242 regs_base = res->start;
1243
1c7ac018
JB		 1244 pri_dai->dma_playback.dma_addr = regs_base + I2STXD;
1245 pri_dai->dma_capture.dma_addr = regs_base + I2SRXD;
40476f61 1246 pri_dai->dma_playback.ch_name = "tx";
40476f61 1247 pri_dai->dma_capture.ch_name = "rx";
1c7ac018
JB		 1248 pri_dai->dma_playback.dma_size = 4;
1249 pri_dai->dma_capture.dma_size = 4;
1250 pri_dai->base = regs_base;
1251 pri_dai->quirks = quirks;
a5a56871 1252 pri_dai->variant_regs = i2s_dai_data->i2s_variant_regs;
1c7ac018
JB		 1253
1254 if (quirks & QUIRK_PRI_6CHAN)
1255 pri_dai->i2s_dai_drv.playback.channels_max = 6;
1256
1257 if (quirks & QUIRK_SEC_DAI) {
1258 sec_dai = i2s_alloc_dai(pdev, true);
1259 if (!sec_dai) {
1260 dev_err(&pdev->dev, "Unable to alloc I2S_sec\n");
1261 ret = -ENOMEM;
b960ce74 1262 goto err;
1c7ac018 1263 }
7e5d8706
SN		 1264
1265 sec_dai->variant_regs = pri_dai->variant_regs;
1c7ac018 1266 sec_dai->dma_playback.dma_addr = regs_base + I2STXDS;
40476f61
PV		 1267 sec_dai->dma_playback.ch_name = "tx-sec";
1268
1269 if (!np) {
1270 res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
1271 if (res)
1272 sec_dai->dma_playback.channel = res->start;
1273 }
1274
1c7ac018
JB		 1275 sec_dai->dma_playback.dma_size = 4;
1276 sec_dai->base = regs_base;
1277 sec_dai->quirks = quirks;
40476f61 1278 sec_dai->idma_playback.dma_addr = idma_addr;
1c7ac018
JB		 1279 sec_dai->pri_dai = pri_dai;
1280 pri_dai->sec_dai = sec_dai;
1281 }
1282
0429ffef
MB		 1283 if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
1284 dev_err(&pdev->dev, "Unable to configure gpio\n");
1285 ret = -EINVAL;
1286 goto err;
1c7ac018
JB		 1287 }
1288
d644a115
MB		 1289 devm_snd_soc_register_component(&pri_dai->pdev->dev,
1290 &samsung_i2s_component,
1291 &pri_dai->i2s_dai_drv, 1);
1c7ac018 1292
c5cf4dbc
MB		 1293 pm_runtime_enable(&pdev->dev);
1294
53f7faa1
SN		 1295 ret = samsung_asoc_dma_platform_register(&pdev->dev);
1296 if (ret != 0)
1297 return ret;
a08485d8 1298
1c7ac018 1299 return 0;
b960ce74 1300err:
57e33781
SK		 1301 if (res)
1302 release_mem_region(regs_base, resource_size(res));
1c7ac018
JB		 1303
1304 return ret;
1305}
1306
fdca21ad 1307static int samsung_i2s_remove(struct platform_device *pdev)
1c7ac018
JB		 1308{
1309 struct i2s_dai *i2s, *other;
c5cf4dbc 1310 struct resource *res;
1c7ac018
JB		 1311
1312 i2s = dev_get_drvdata(&pdev->dev);
1313 other = i2s->pri_dai ? : i2s->sec_dai;
1314
1315 if (other) {
1316 other->pri_dai = NULL;
1317 other->sec_dai = NULL;
1318 } else {
c5cf4dbc 1319 pm_runtime_disable(&pdev->dev);
1c7ac018
JB		 1320 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1321 if (res)
1322 release_mem_region(res->start, resource_size(res));
1323 }
1324
1325 i2s->pri_dai = NULL;
1326 i2s->sec_dai = NULL;
1327
1c7ac018
JB		 1328 return 0;
1329}
1330
a5a56871
PV		 1331static const struct samsung_i2s_variant_regs i2sv3_regs = {
1332 .bfs_off = 1,
1333 .rfs_off = 3,
1334 .sdf_off = 5,
1335 .txr_off = 8,
1336 .rclksrc_off = 10,
1337 .mss_off = 11,
1338 .cdclkcon_off = 12,
1339 .lrp_off = 7,
1340 .bfs_mask = 0x3,
1341 .rfs_mask = 0x3,
1342 .ftx0cnt_off = 8,
1343};
1344
1345static const struct samsung_i2s_variant_regs i2sv6_regs = {
1346 .bfs_off = 0,
1347 .rfs_off = 4,
1348 .sdf_off = 6,
1349 .txr_off = 8,
1350 .rclksrc_off = 10,
1351 .mss_off = 11,
1352 .cdclkcon_off = 12,
1353 .lrp_off = 15,
1354 .bfs_mask = 0xf,
1355 .rfs_mask = 0x3,
1356 .ftx0cnt_off = 8,
1357};
1358
1359static const struct samsung_i2s_variant_regs i2sv7_regs = {
1360 .bfs_off = 0,
1361 .rfs_off = 4,
1362 .sdf_off = 7,
1363 .txr_off = 9,
1364 .rclksrc_off = 11,
1365 .mss_off = 12,
1366 .cdclkcon_off = 22,
1367 .lrp_off = 15,
1368 .bfs_mask = 0xf,
1369 .rfs_mask = 0x7,
1370 .ftx0cnt_off = 0,
1371};
1372
1373static const struct samsung_i2s_variant_regs i2sv5_i2s1_regs = {
1374 .bfs_off = 0,
1375 .rfs_off = 3,
1376 .sdf_off = 6,
1377 .txr_off = 8,
1378 .rclksrc_off = 10,
1379 .mss_off = 11,
1380 .cdclkcon_off = 12,
1381 .lrp_off = 15,
1382 .bfs_mask = 0x7,
1383 .rfs_mask = 0x7,
1384 .ftx0cnt_off = 8,
1385};
1386
7da493e9
PV		 1387static const struct samsung_i2s_dai_data i2sv3_dai_type = {
1388 .dai_type = TYPE_PRI,
1389 .quirks = QUIRK_NO_MUXPSR,
a5a56871 1390 .i2s_variant_regs = &i2sv3_regs,
7da493e9
PV		 1391};
1392
1393static const struct samsung_i2s_dai_data i2sv5_dai_type = {
1394 .dai_type = TYPE_PRI,
b0759736
PV		 1395 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1396 QUIRK_SUPPORTS_IDMA,
a5a56871 1397 .i2s_variant_regs = &i2sv3_regs,
7da493e9
PV		 1398};
1399
4ca0c0d4
PV		 1400static const struct samsung_i2s_dai_data i2sv6_dai_type = {
1401 .dai_type = TYPE_PRI,
1402 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
b0759736 1403 QUIRK_SUPPORTS_TDM | QUIRK_SUPPORTS_IDMA,
a5a56871
PV		 1404 .i2s_variant_regs = &i2sv6_regs,
1405};
1406
1407static const struct samsung_i2s_dai_data i2sv7_dai_type = {
1408 .dai_type = TYPE_PRI,
1409 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1410 QUIRK_SUPPORTS_TDM,
1411 .i2s_variant_regs = &i2sv7_regs,
1412};
1413
1414static const struct samsung_i2s_dai_data i2sv5_dai_type_i2s1 = {
1415 .dai_type = TYPE_PRI,
1416 .quirks = QUIRK_PRI_6CHAN | QUIRK_NEED_RSTCLR,
1417 .i2s_variant_regs = &i2sv5_i2s1_regs,
4ca0c0d4
PV		 1418};
1419
7da493e9
PV		 1420static const struct samsung_i2s_dai_data samsung_dai_type_pri = {
1421 .dai_type = TYPE_PRI,
1422};
1423
1424static const struct samsung_i2s_dai_data samsung_dai_type_sec = {
1425 .dai_type = TYPE_SEC,
1426};
1427
7c62eebb
PV		 1428static struct platform_device_id samsung_i2s_driver_ids[] = {
1429 {
1430 .name = "samsung-i2s",
3f024980 1431 .driver_data = (kernel_ulong_t)&i2sv3_dai_type,
7c62eebb
PV		 1432 }, {
1433 .name = "samsung-i2s-sec",
7da493e9 1434 .driver_data = (kernel_ulong_t)&samsung_dai_type_sec,
3f024980
MB		 1435 }, {
1436 .name = "samsung-i2sv4",
1437 .driver_data = (kernel_ulong_t)&i2sv5_dai_type,
7c62eebb
PV		 1438 },
1439 {},
1440};
2af19558 1441MODULE_DEVICE_TABLE(platform, samsung_i2s_driver_ids);
7c62eebb 1442
40476f61 1443#ifdef CONFIG_OF
40476f61 1444static const struct of_device_id exynos_i2s_match[] = {
7da493e9
PV		 1445 {
1446 .compatible = "samsung,s3c6410-i2s",
1447 .data = &i2sv3_dai_type,
1448 }, {
1449 .compatible = "samsung,s5pv210-i2s",
1450 .data = &i2sv5_dai_type,
4ca0c0d4
PV		 1451 }, {
1452 .compatible = "samsung,exynos5420-i2s",
1453 .data = &i2sv6_dai_type,
a5a56871
PV		 1454 }, {
1455 .compatible = "samsung,exynos7-i2s",
1456 .data = &i2sv7_dai_type,
1457 }, {
1458 .compatible = "samsung,exynos7-i2s1",
1459 .data = &i2sv5_dai_type_i2s1,
40476f61
PV		 1460 },
1461 {},
1462};
1463MODULE_DEVICE_TABLE(of, exynos_i2s_match);
1464#endif
1465
5b1d3c34
C		 1466static const struct dev_pm_ops samsung_i2s_pm = {
1467 SET_RUNTIME_PM_OPS(i2s_runtime_suspend,
1468 i2s_runtime_resume, NULL)
1469};
1470
1c7ac018
JB		 1471static struct platform_driver samsung_i2s_driver = {
1472 .probe = samsung_i2s_probe,
fdca21ad 1473 .remove = samsung_i2s_remove,
7c62eebb 1474 .id_table = samsung_i2s_driver_ids,
1c7ac018
JB		 1475 .driver = {
1476 .name = "samsung-i2s",
40476f61 1477 .of_match_table = of_match_ptr(exynos_i2s_match),
5b1d3c34 1478 .pm = &samsung_i2s_pm,
1c7ac018
JB		 1479 },
1480};
1481
e00c3f55 1482module_platform_driver(samsung_i2s_driver);
1c7ac018
JB		 1483
1484/* Module information */
df8ad335 1485MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
1c7ac018
JB		 1486MODULE_DESCRIPTION("Samsung I2S Interface");
1487MODULE_ALIAS("platform:samsung-i2s");
1488MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.298942 seconds and 5 git commands to generate.