Commit | Line | Data |
---|---|---|
5033f43c | 1 | /* sound/soc/samsung/i2s.c |
1c7ac018 JB |
2 | * |
3 | * ALSA SoC Audio Layer - Samsung I2S Controller driver | |
4 | * | |
5 | * Copyright (c) 2010 Samsung Electronics Co. Ltd. | |
df8ad335 | 6 | * Jaswinder Singh <jassisinghbrar@gmail.com> |
1c7ac018 JB |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
074b89bb | 13 | #include <dt-bindings/sound/samsung-i2s.h> |
1c7ac018 JB |
14 | #include <linux/delay.h> |
15 | #include <linux/slab.h> | |
16 | #include <linux/clk.h> | |
074b89bb | 17 | #include <linux/clk-provider.h> |
1c7ac018 | 18 | #include <linux/io.h> |
da155d5b | 19 | #include <linux/module.h> |
40476f61 | 20 | #include <linux/of.h> |
2f7b5d14 | 21 | #include <linux/of_device.h> |
40476f61 | 22 | #include <linux/of_gpio.h> |
c5cf4dbc | 23 | #include <linux/pm_runtime.h> |
1c7ac018 | 24 | |
1c7ac018 | 25 | #include <sound/soc.h> |
0378b6ac | 26 | #include <sound/pcm_params.h> |
1c7ac018 | 27 | |
436d42c6 | 28 | #include <linux/platform_data/asoc-s3c.h> |
1c7ac018 JB |
29 | |
30 | #include "dma.h" | |
61100f40 | 31 | #include "idma.h" |
1c7ac018 | 32 | #include "i2s.h" |
172a453d | 33 | #include "i2s-regs.h" |
1c7ac018 JB |
34 | |
35 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | |
36 | ||
7c62eebb PV |
37 | enum samsung_dai_type { |
38 | TYPE_PRI, | |
39 | TYPE_SEC, | |
40 | }; | |
41 | ||
a5a56871 PV |
42 | struct samsung_i2s_variant_regs { |
43 | unsigned int bfs_off; | |
44 | unsigned int rfs_off; | |
45 | unsigned int sdf_off; | |
46 | unsigned int txr_off; | |
47 | unsigned int rclksrc_off; | |
48 | unsigned int mss_off; | |
49 | unsigned int cdclkcon_off; | |
50 | unsigned int lrp_off; | |
51 | unsigned int bfs_mask; | |
52 | unsigned int rfs_mask; | |
53 | unsigned int ftx0cnt_off; | |
54 | }; | |
55 | ||
40476f61 PV |
56 | struct samsung_i2s_dai_data { |
57 | int dai_type; | |
7da493e9 | 58 | u32 quirks; |
a5a56871 | 59 | const struct samsung_i2s_variant_regs *i2s_variant_regs; |
40476f61 PV |
60 | }; |
61 | ||
1c7ac018 JB |
62 | struct i2s_dai { |
63 | /* Platform device for this DAI */ | |
64 | struct platform_device *pdev; | |
af1cf5cf | 65 | /* Memory mapped SFR region */ |
1c7ac018 | 66 | void __iomem *addr; |
1c7ac018 JB |
67 | /* Rate of RCLK source clock */ |
68 | unsigned long rclk_srcrate; | |
69 | /* Frame Clock */ | |
70 | unsigned frmclk; | |
71 | /* | |
72 | * Specifically requested RCLK,BCLK by MACHINE Driver. | |
73 | * 0 indicates CPU driver is free to choose any value. | |
74 | */ | |
75 | unsigned rfs, bfs; | |
76 | /* I2S Controller's core clock */ | |
77 | struct clk *clk; | |
78 | /* Clock for generating I2S signals */ | |
79 | struct clk *op_clk; | |
1c7ac018 JB |
80 | /* Pointer to the Primary_Fifo if this is Sec_Fifo, NULL otherwise */ |
81 | struct i2s_dai *pri_dai; | |
82 | /* Pointer to the Secondary_Fifo if it has one, NULL otherwise */ | |
83 | struct i2s_dai *sec_dai; | |
84 | #define DAI_OPENED (1 << 0) /* Dai is opened */ | |
85 | #define DAI_MANAGER (1 << 1) /* Dai is the manager */ | |
86 | unsigned mode; | |
87 | /* Driver for this DAI */ | |
88 | struct snd_soc_dai_driver i2s_dai_drv; | |
89 | /* DMA parameters */ | |
69e7a69a SN |
90 | struct snd_dmaengine_dai_dma_data dma_playback; |
91 | struct snd_dmaengine_dai_dma_data dma_capture; | |
92 | struct snd_dmaengine_dai_dma_data idma_playback; | |
9bdca822 | 93 | dma_filter_fn filter; |
1c7ac018 JB |
94 | u32 quirks; |
95 | u32 suspend_i2smod; | |
96 | u32 suspend_i2scon; | |
97 | u32 suspend_i2spsr; | |
a5a56871 | 98 | const struct samsung_i2s_variant_regs *variant_regs; |
f3670536 SN |
99 | |
100 | /* Spinlock protecting access to the device's registers */ | |
101 | spinlock_t spinlock; | |
102 | spinlock_t *lock; | |
074b89bb SN |
103 | |
104 | /* Below fields are only valid if this is the primary FIFO */ | |
105 | struct clk *clk_table[3]; | |
106 | struct clk_onecell_data clk_data; | |
1c7ac018 JB |
107 | }; |
108 | ||
109 | /* Lock for cross i/f checks */ | |
110 | static DEFINE_SPINLOCK(lock); | |
111 | ||
112 | /* If this is the 'overlay' stereo DAI */ | |
113 | static inline bool is_secondary(struct i2s_dai *i2s) | |
114 | { | |
115 | return i2s->pri_dai ? true : false; | |
116 | } | |
117 | ||
118 | /* If operating in SoC-Slave mode */ | |
119 | static inline bool is_slave(struct i2s_dai *i2s) | |
120 | { | |
a5a56871 PV |
121 | u32 mod = readl(i2s->addr + I2SMOD); |
122 | return (mod & (1 << i2s->variant_regs->mss_off)) ? true : false; | |
1c7ac018 JB |
123 | } |
124 | ||
125 | /* If this interface of the controller is transmitting data */ | |
126 | static inline bool tx_active(struct i2s_dai *i2s) | |
127 | { | |
128 | u32 active; | |
129 | ||
130 | if (!i2s) | |
131 | return false; | |
132 | ||
33195500 | 133 | active = readl(i2s->addr + I2SCON); |
1c7ac018 JB |
134 | |
135 | if (is_secondary(i2s)) | |
136 | active &= CON_TXSDMA_ACTIVE; | |
137 | else | |
138 | active &= CON_TXDMA_ACTIVE; | |
139 | ||
140 | return active ? true : false; | |
141 | } | |
142 | ||
dcd60fc3 SN |
143 | /* Return pointer to the other DAI */ |
144 | static inline struct i2s_dai *get_other_dai(struct i2s_dai *i2s) | |
145 | { | |
146 | return i2s->pri_dai ? : i2s->sec_dai; | |
147 | } | |
148 | ||
1c7ac018 JB |
149 | /* If the other interface of the controller is transmitting data */ |
150 | static inline bool other_tx_active(struct i2s_dai *i2s) | |
151 | { | |
dcd60fc3 | 152 | struct i2s_dai *other = get_other_dai(i2s); |
1c7ac018 JB |
153 | |
154 | return tx_active(other); | |
155 | } | |
156 | ||
157 | /* If any interface of the controller is transmitting data */ | |
158 | static inline bool any_tx_active(struct i2s_dai *i2s) | |
159 | { | |
160 | return tx_active(i2s) || other_tx_active(i2s); | |
161 | } | |
162 | ||
163 | /* If this interface of the controller is receiving data */ | |
164 | static inline bool rx_active(struct i2s_dai *i2s) | |
165 | { | |
166 | u32 active; | |
167 | ||
168 | if (!i2s) | |
169 | return false; | |
170 | ||
33195500 | 171 | active = readl(i2s->addr + I2SCON) & CON_RXDMA_ACTIVE; |
1c7ac018 JB |
172 | |
173 | return active ? true : false; | |
174 | } | |
175 | ||
176 | /* If the other interface of the controller is receiving data */ | |
177 | static inline bool other_rx_active(struct i2s_dai *i2s) | |
178 | { | |
dcd60fc3 | 179 | struct i2s_dai *other = get_other_dai(i2s); |
1c7ac018 JB |
180 | |
181 | return rx_active(other); | |
182 | } | |
183 | ||
184 | /* If any interface of the controller is receiving data */ | |
185 | static inline bool any_rx_active(struct i2s_dai *i2s) | |
186 | { | |
187 | return rx_active(i2s) || other_rx_active(i2s); | |
188 | } | |
189 | ||
190 | /* If the other DAI is transmitting or receiving data */ | |
191 | static inline bool other_active(struct i2s_dai *i2s) | |
192 | { | |
193 | return other_rx_active(i2s) || other_tx_active(i2s); | |
194 | } | |
195 | ||
196 | /* If this DAI is transmitting or receiving data */ | |
197 | static inline bool this_active(struct i2s_dai *i2s) | |
198 | { | |
199 | return tx_active(i2s) || rx_active(i2s); | |
200 | } | |
201 | ||
202 | /* If the controller is active anyway */ | |
203 | static inline bool any_active(struct i2s_dai *i2s) | |
204 | { | |
205 | return this_active(i2s) || other_active(i2s); | |
206 | } | |
207 | ||
208 | static inline struct i2s_dai *to_info(struct snd_soc_dai *dai) | |
209 | { | |
210 | return snd_soc_dai_get_drvdata(dai); | |
211 | } | |
212 | ||
213 | static inline bool is_opened(struct i2s_dai *i2s) | |
214 | { | |
215 | if (i2s && (i2s->mode & DAI_OPENED)) | |
216 | return true; | |
217 | else | |
218 | return false; | |
219 | } | |
220 | ||
221 | static inline bool is_manager(struct i2s_dai *i2s) | |
222 | { | |
223 | if (is_opened(i2s) && (i2s->mode & DAI_MANAGER)) | |
224 | return true; | |
225 | else | |
226 | return false; | |
227 | } | |
228 | ||
229 | /* Read RCLK of I2S (in multiples of LRCLK) */ | |
230 | static inline unsigned get_rfs(struct i2s_dai *i2s) | |
231 | { | |
4ca0c0d4 | 232 | u32 rfs; |
a5a56871 PV |
233 | rfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->rfs_off; |
234 | rfs &= i2s->variant_regs->rfs_mask; | |
1c7ac018 JB |
235 | |
236 | switch (rfs) { | |
a5a56871 PV |
237 | case 7: return 192; |
238 | case 6: return 96; | |
239 | case 5: return 128; | |
240 | case 4: return 64; | |
1c7ac018 JB |
241 | case 3: return 768; |
242 | case 2: return 384; | |
243 | case 1: return 512; | |
244 | default: return 256; | |
245 | } | |
246 | } | |
247 | ||
248 | /* Write RCLK of I2S (in multiples of LRCLK) */ | |
249 | static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs) | |
250 | { | |
251 | u32 mod = readl(i2s->addr + I2SMOD); | |
a5a56871 | 252 | int rfs_shift = i2s->variant_regs->rfs_off; |
1c7ac018 | 253 | |
a5a56871 | 254 | mod &= ~(i2s->variant_regs->rfs_mask << rfs_shift); |
1c7ac018 JB |
255 | |
256 | switch (rfs) { | |
a5a56871 PV |
257 | case 192: |
258 | mod |= (EXYNOS7_MOD_RCLK_192FS << rfs_shift); | |
259 | break; | |
260 | case 96: | |
261 | mod |= (EXYNOS7_MOD_RCLK_96FS << rfs_shift); | |
262 | break; | |
263 | case 128: | |
264 | mod |= (EXYNOS7_MOD_RCLK_128FS << rfs_shift); | |
265 | break; | |
266 | case 64: | |
267 | mod |= (EXYNOS7_MOD_RCLK_64FS << rfs_shift); | |
268 | break; | |
1c7ac018 | 269 | case 768: |
b60be4aa | 270 | mod |= (MOD_RCLK_768FS << rfs_shift); |
1c7ac018 JB |
271 | break; |
272 | case 512: | |
b60be4aa | 273 | mod |= (MOD_RCLK_512FS << rfs_shift); |
1c7ac018 JB |
274 | break; |
275 | case 384: | |
b60be4aa | 276 | mod |= (MOD_RCLK_384FS << rfs_shift); |
1c7ac018 JB |
277 | break; |
278 | default: | |
b60be4aa | 279 | mod |= (MOD_RCLK_256FS << rfs_shift); |
1c7ac018 JB |
280 | break; |
281 | } | |
282 | ||
283 | writel(mod, i2s->addr + I2SMOD); | |
284 | } | |
285 | ||
286 | /* Read Bit-Clock of I2S (in multiples of LRCLK) */ | |
287 | static inline unsigned get_bfs(struct i2s_dai *i2s) | |
288 | { | |
4ca0c0d4 | 289 | u32 bfs; |
a5a56871 PV |
290 | bfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->bfs_off; |
291 | bfs &= i2s->variant_regs->bfs_mask; | |
1c7ac018 JB |
292 | |
293 | switch (bfs) { | |
4ca0c0d4 PV |
294 | case 8: return 256; |
295 | case 7: return 192; | |
296 | case 6: return 128; | |
297 | case 5: return 96; | |
298 | case 4: return 64; | |
1c7ac018 JB |
299 | case 3: return 24; |
300 | case 2: return 16; | |
301 | case 1: return 48; | |
302 | default: return 32; | |
303 | } | |
304 | } | |
305 | ||
306 | /* Write Bit-Clock of I2S (in multiples of LRCLK) */ | |
307 | static inline void set_bfs(struct i2s_dai *i2s, unsigned bfs) | |
308 | { | |
309 | u32 mod = readl(i2s->addr + I2SMOD); | |
4ca0c0d4 | 310 | int tdm = i2s->quirks & QUIRK_SUPPORTS_TDM; |
a5a56871 | 311 | int bfs_shift = i2s->variant_regs->bfs_off; |
4ca0c0d4 PV |
312 | |
313 | /* Non-TDM I2S controllers do not support BCLK > 48 * FS */ | |
314 | if (!tdm && bfs > 48) { | |
315 | dev_err(&i2s->pdev->dev, "Unsupported BCLK divider\n"); | |
316 | return; | |
317 | } | |
1c7ac018 | 318 | |
a5a56871 PV |
319 | mod &= ~(i2s->variant_regs->bfs_mask << bfs_shift); |
320 | ||
1c7ac018 JB |
321 | switch (bfs) { |
322 | case 48: | |
b60be4aa | 323 | mod |= (MOD_BCLK_48FS << bfs_shift); |
1c7ac018 JB |
324 | break; |
325 | case 32: | |
b60be4aa | 326 | mod |= (MOD_BCLK_32FS << bfs_shift); |
1c7ac018 JB |
327 | break; |
328 | case 24: | |
b60be4aa | 329 | mod |= (MOD_BCLK_24FS << bfs_shift); |
1c7ac018 JB |
330 | break; |
331 | case 16: | |
b60be4aa | 332 | mod |= (MOD_BCLK_16FS << bfs_shift); |
1c7ac018 | 333 | break; |
4ca0c0d4 PV |
334 | case 64: |
335 | mod |= (EXYNOS5420_MOD_BCLK_64FS << bfs_shift); | |
336 | break; | |
337 | case 96: | |
338 | mod |= (EXYNOS5420_MOD_BCLK_96FS << bfs_shift); | |
339 | break; | |
340 | case 128: | |
341 | mod |= (EXYNOS5420_MOD_BCLK_128FS << bfs_shift); | |
342 | break; | |
343 | case 192: | |
344 | mod |= (EXYNOS5420_MOD_BCLK_192FS << bfs_shift); | |
345 | break; | |
346 | case 256: | |
347 | mod |= (EXYNOS5420_MOD_BCLK_256FS << bfs_shift); | |
1c7ac018 JB |
348 | break; |
349 | default: | |
350 | dev_err(&i2s->pdev->dev, "Wrong BCLK Divider!\n"); | |
351 | return; | |
352 | } | |
353 | ||
354 | writel(mod, i2s->addr + I2SMOD); | |
355 | } | |
356 | ||
357 | /* Sample-Size */ | |
358 | static inline int get_blc(struct i2s_dai *i2s) | |
359 | { | |
360 | int blc = readl(i2s->addr + I2SMOD); | |
361 | ||
362 | blc = (blc >> 13) & 0x3; | |
363 | ||
364 | switch (blc) { | |
365 | case 2: return 24; | |
366 | case 1: return 8; | |
367 | default: return 16; | |
368 | } | |
369 | } | |
370 | ||
371 | /* TX Channel Control */ | |
372 | static void i2s_txctrl(struct i2s_dai *i2s, int on) | |
373 | { | |
374 | void __iomem *addr = i2s->addr; | |
a5a56871 | 375 | int txr_off = i2s->variant_regs->txr_off; |
1c7ac018 | 376 | u32 con = readl(addr + I2SCON); |
a5a56871 | 377 | u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off); |
1c7ac018 JB |
378 | |
379 | if (on) { | |
380 | con |= CON_ACTIVE; | |
381 | con &= ~CON_TXCH_PAUSE; | |
382 | ||
383 | if (is_secondary(i2s)) { | |
384 | con |= CON_TXSDMA_ACTIVE; | |
385 | con &= ~CON_TXSDMA_PAUSE; | |
386 | } else { | |
387 | con |= CON_TXDMA_ACTIVE; | |
388 | con &= ~CON_TXDMA_PAUSE; | |
389 | } | |
390 | ||
391 | if (any_rx_active(i2s)) | |
a5a56871 | 392 | mod |= 2 << txr_off; |
1c7ac018 | 393 | else |
a5a56871 | 394 | mod |= 0 << txr_off; |
1c7ac018 JB |
395 | } else { |
396 | if (is_secondary(i2s)) { | |
397 | con |= CON_TXSDMA_PAUSE; | |
398 | con &= ~CON_TXSDMA_ACTIVE; | |
399 | } else { | |
400 | con |= CON_TXDMA_PAUSE; | |
401 | con &= ~CON_TXDMA_ACTIVE; | |
402 | } | |
403 | ||
404 | if (other_tx_active(i2s)) { | |
405 | writel(con, addr + I2SCON); | |
406 | return; | |
407 | } | |
408 | ||
409 | con |= CON_TXCH_PAUSE; | |
410 | ||
411 | if (any_rx_active(i2s)) | |
a5a56871 | 412 | mod |= 1 << txr_off; |
1c7ac018 JB |
413 | else |
414 | con &= ~CON_ACTIVE; | |
415 | } | |
416 | ||
417 | writel(mod, addr + I2SMOD); | |
418 | writel(con, addr + I2SCON); | |
419 | } | |
420 | ||
421 | /* RX Channel Control */ | |
422 | static void i2s_rxctrl(struct i2s_dai *i2s, int on) | |
423 | { | |
424 | void __iomem *addr = i2s->addr; | |
a5a56871 | 425 | int txr_off = i2s->variant_regs->txr_off; |
1c7ac018 | 426 | u32 con = readl(addr + I2SCON); |
a5a56871 | 427 | u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off); |
1c7ac018 JB |
428 | |
429 | if (on) { | |
430 | con |= CON_RXDMA_ACTIVE | CON_ACTIVE; | |
431 | con &= ~(CON_RXDMA_PAUSE | CON_RXCH_PAUSE); | |
432 | ||
433 | if (any_tx_active(i2s)) | |
a5a56871 | 434 | mod |= 2 << txr_off; |
1c7ac018 | 435 | else |
a5a56871 | 436 | mod |= 1 << txr_off; |
1c7ac018 JB |
437 | } else { |
438 | con |= CON_RXDMA_PAUSE | CON_RXCH_PAUSE; | |
439 | con &= ~CON_RXDMA_ACTIVE; | |
440 | ||
441 | if (any_tx_active(i2s)) | |
a5a56871 | 442 | mod |= 0 << txr_off; |
1c7ac018 JB |
443 | else |
444 | con &= ~CON_ACTIVE; | |
445 | } | |
446 | ||
447 | writel(mod, addr + I2SMOD); | |
448 | writel(con, addr + I2SCON); | |
449 | } | |
450 | ||
451 | /* Flush FIFO of an interface */ | |
452 | static inline void i2s_fifo(struct i2s_dai *i2s, u32 flush) | |
453 | { | |
454 | void __iomem *fic; | |
455 | u32 val; | |
456 | ||
457 | if (!i2s) | |
458 | return; | |
459 | ||
460 | if (is_secondary(i2s)) | |
461 | fic = i2s->addr + I2SFICS; | |
462 | else | |
463 | fic = i2s->addr + I2SFIC; | |
464 | ||
465 | /* Flush the FIFO */ | |
466 | writel(readl(fic) | flush, fic); | |
467 | ||
468 | /* Be patient */ | |
469 | val = msecs_to_loops(1) / 1000; /* 1 usec */ | |
470 | while (--val) | |
471 | cpu_relax(); | |
472 | ||
473 | writel(readl(fic) & ~flush, fic); | |
474 | } | |
475 | ||
476 | static int i2s_set_sysclk(struct snd_soc_dai *dai, | |
477 | int clk_id, unsigned int rfs, int dir) | |
478 | { | |
479 | struct i2s_dai *i2s = to_info(dai); | |
dcd60fc3 | 480 | struct i2s_dai *other = get_other_dai(i2s); |
a5a56871 PV |
481 | const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs; |
482 | unsigned int cdcon_mask = 1 << i2s_regs->cdclkcon_off; | |
483 | unsigned int rsrc_mask = 1 << i2s_regs->rclksrc_off; | |
ce8bcdbb | 484 | u32 mod, mask, val = 0; |
316fa9e0 | 485 | unsigned long flags; |
ce8bcdbb | 486 | |
316fa9e0 | 487 | spin_lock_irqsave(i2s->lock, flags); |
ce8bcdbb | 488 | mod = readl(i2s->addr + I2SMOD); |
316fa9e0 | 489 | spin_unlock_irqrestore(i2s->lock, flags); |
1c7ac018 JB |
490 | |
491 | switch (clk_id) { | |
c86d50f9 | 492 | case SAMSUNG_I2S_OPCLK: |
ce8bcdbb SN |
493 | mask = MOD_OPCLK_MASK; |
494 | val = dir; | |
c86d50f9 | 495 | break; |
1c7ac018 | 496 | case SAMSUNG_I2S_CDCLK: |
ce8bcdbb | 497 | mask = 1 << i2s_regs->cdclkcon_off; |
1c7ac018 JB |
498 | /* Shouldn't matter in GATING(CLOCK_IN) mode */ |
499 | if (dir == SND_SOC_CLOCK_IN) | |
500 | rfs = 0; | |
501 | ||
133c2681 | 502 | if ((rfs && other && other->rfs && (other->rfs != rfs)) || |
1c7ac018 JB |
503 | (any_active(i2s) && |
504 | (((dir == SND_SOC_CLOCK_IN) | |
a5a56871 | 505 | && !(mod & cdcon_mask)) || |
1c7ac018 | 506 | ((dir == SND_SOC_CLOCK_OUT) |
a5a56871 | 507 | && (mod & cdcon_mask))))) { |
1c7ac018 JB |
508 | dev_err(&i2s->pdev->dev, |
509 | "%s:%d Other DAI busy\n", __func__, __LINE__); | |
510 | return -EAGAIN; | |
511 | } | |
512 | ||
513 | if (dir == SND_SOC_CLOCK_IN) | |
ce8bcdbb | 514 | val = 1 << i2s_regs->cdclkcon_off; |
1c7ac018 JB |
515 | |
516 | i2s->rfs = rfs; | |
517 | break; | |
518 | ||
519 | case SAMSUNG_I2S_RCLKSRC_0: /* clock corrsponding to IISMOD[10] := 0 */ | |
520 | case SAMSUNG_I2S_RCLKSRC_1: /* clock corrsponding to IISMOD[10] := 1 */ | |
ce8bcdbb SN |
521 | mask = 1 << i2s_regs->rclksrc_off; |
522 | ||
1c7ac018 JB |
523 | if ((i2s->quirks & QUIRK_NO_MUXPSR) |
524 | || (clk_id == SAMSUNG_I2S_RCLKSRC_0)) | |
525 | clk_id = 0; | |
526 | else | |
527 | clk_id = 1; | |
528 | ||
529 | if (!any_active(i2s)) { | |
a6aba536 | 530 | if (i2s->op_clk && !IS_ERR(i2s->op_clk)) { |
a5a56871 PV |
531 | if ((clk_id && !(mod & rsrc_mask)) || |
532 | (!clk_id && (mod & rsrc_mask))) { | |
98614cf6 | 533 | clk_disable_unprepare(i2s->op_clk); |
1c7ac018 JB |
534 | clk_put(i2s->op_clk); |
535 | } else { | |
6ce534aa JB |
536 | i2s->rclk_srcrate = |
537 | clk_get_rate(i2s->op_clk); | |
1c7ac018 JB |
538 | return 0; |
539 | } | |
540 | } | |
541 | ||
1974a042 PV |
542 | if (clk_id) |
543 | i2s->op_clk = clk_get(&i2s->pdev->dev, | |
544 | "i2s_opclk1"); | |
545 | else | |
546 | i2s->op_clk = clk_get(&i2s->pdev->dev, | |
547 | "i2s_opclk0"); | |
a6aba536 SN |
548 | |
549 | if (WARN_ON(IS_ERR(i2s->op_clk))) | |
550 | return PTR_ERR(i2s->op_clk); | |
551 | ||
98614cf6 | 552 | clk_prepare_enable(i2s->op_clk); |
1c7ac018 JB |
553 | i2s->rclk_srcrate = clk_get_rate(i2s->op_clk); |
554 | ||
555 | /* Over-ride the other's */ | |
556 | if (other) { | |
557 | other->op_clk = i2s->op_clk; | |
558 | other->rclk_srcrate = i2s->rclk_srcrate; | |
559 | } | |
a5a56871 PV |
560 | } else if ((!clk_id && (mod & rsrc_mask)) |
561 | || (clk_id && !(mod & rsrc_mask))) { | |
1c7ac018 JB |
562 | dev_err(&i2s->pdev->dev, |
563 | "%s:%d Other DAI busy\n", __func__, __LINE__); | |
564 | return -EAGAIN; | |
565 | } else { | |
566 | /* Call can't be on the active DAI */ | |
567 | i2s->op_clk = other->op_clk; | |
568 | i2s->rclk_srcrate = other->rclk_srcrate; | |
569 | return 0; | |
570 | } | |
571 | ||
ce8bcdbb SN |
572 | if (clk_id == 1) |
573 | val = 1 << i2s_regs->rclksrc_off; | |
b2de1d20 | 574 | break; |
1c7ac018 JB |
575 | default: |
576 | dev_err(&i2s->pdev->dev, "We don't serve that!\n"); | |
577 | return -EINVAL; | |
578 | } | |
579 | ||
316fa9e0 | 580 | spin_lock_irqsave(i2s->lock, flags); |
ce8bcdbb SN |
581 | mod = readl(i2s->addr + I2SMOD); |
582 | mod = (mod & ~mask) | val; | |
1c7ac018 | 583 | writel(mod, i2s->addr + I2SMOD); |
316fa9e0 | 584 | spin_unlock_irqrestore(i2s->lock, flags); |
1c7ac018 JB |
585 | |
586 | return 0; | |
587 | } | |
588 | ||
589 | static int i2s_set_fmt(struct snd_soc_dai *dai, | |
590 | unsigned int fmt) | |
591 | { | |
592 | struct i2s_dai *i2s = to_info(dai); | |
a5a56871 | 593 | int lrp_shift, sdf_shift, sdf_mask, lrp_rlow, mod_slave; |
ce8bcdbb | 594 | u32 mod, tmp = 0; |
316fa9e0 | 595 | unsigned long flags; |
1c7ac018 | 596 | |
a5a56871 PV |
597 | lrp_shift = i2s->variant_regs->lrp_off; |
598 | sdf_shift = i2s->variant_regs->sdf_off; | |
599 | mod_slave = 1 << i2s->variant_regs->mss_off; | |
4ca0c0d4 | 600 | |
b60be4aa PV |
601 | sdf_mask = MOD_SDF_MASK << sdf_shift; |
602 | lrp_rlow = MOD_LR_RLOW << lrp_shift; | |
603 | ||
1c7ac018 JB |
604 | /* Format is priority */ |
605 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
606 | case SND_SOC_DAIFMT_RIGHT_J: | |
b60be4aa PV |
607 | tmp |= lrp_rlow; |
608 | tmp |= (MOD_SDF_MSB << sdf_shift); | |
1c7ac018 JB |
609 | break; |
610 | case SND_SOC_DAIFMT_LEFT_J: | |
b60be4aa PV |
611 | tmp |= lrp_rlow; |
612 | tmp |= (MOD_SDF_LSB << sdf_shift); | |
1c7ac018 JB |
613 | break; |
614 | case SND_SOC_DAIFMT_I2S: | |
b60be4aa | 615 | tmp |= (MOD_SDF_IIS << sdf_shift); |
1c7ac018 JB |
616 | break; |
617 | default: | |
618 | dev_err(&i2s->pdev->dev, "Format not supported\n"); | |
619 | return -EINVAL; | |
620 | } | |
621 | ||
622 | /* | |
623 | * INV flag is relative to the FORMAT flag - if set it simply | |
624 | * flips the polarity specified by the Standard | |
625 | */ | |
626 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
627 | case SND_SOC_DAIFMT_NB_NF: | |
628 | break; | |
629 | case SND_SOC_DAIFMT_NB_IF: | |
b60be4aa PV |
630 | if (tmp & lrp_rlow) |
631 | tmp &= ~lrp_rlow; | |
1c7ac018 | 632 | else |
b60be4aa | 633 | tmp |= lrp_rlow; |
1c7ac018 JB |
634 | break; |
635 | default: | |
636 | dev_err(&i2s->pdev->dev, "Polarity not supported\n"); | |
637 | return -EINVAL; | |
638 | } | |
639 | ||
640 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
641 | case SND_SOC_DAIFMT_CBM_CFM: | |
a5a56871 | 642 | tmp |= mod_slave; |
1c7ac018 JB |
643 | break; |
644 | case SND_SOC_DAIFMT_CBS_CFS: | |
645 | /* Set default source clock in Master mode */ | |
646 | if (i2s->rclk_srcrate == 0) | |
647 | i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0, | |
648 | 0, SND_SOC_CLOCK_IN); | |
649 | break; | |
650 | default: | |
651 | dev_err(&i2s->pdev->dev, "master/slave format not supported\n"); | |
652 | return -EINVAL; | |
653 | } | |
654 | ||
316fa9e0 | 655 | spin_lock_irqsave(i2s->lock, flags); |
ce8bcdbb | 656 | mod = readl(i2s->addr + I2SMOD); |
b60be4aa PV |
657 | /* |
658 | * Don't change the I2S mode if any controller is active on this | |
659 | * channel. | |
660 | */ | |
1c7ac018 | 661 | if (any_active(i2s) && |
a5a56871 | 662 | ((mod & (sdf_mask | lrp_rlow | mod_slave)) != tmp)) { |
316fa9e0 | 663 | spin_unlock_irqrestore(i2s->lock, flags); |
1c7ac018 JB |
664 | dev_err(&i2s->pdev->dev, |
665 | "%s:%d Other DAI busy\n", __func__, __LINE__); | |
666 | return -EAGAIN; | |
667 | } | |
668 | ||
a5a56871 | 669 | mod &= ~(sdf_mask | lrp_rlow | mod_slave); |
1c7ac018 JB |
670 | mod |= tmp; |
671 | writel(mod, i2s->addr + I2SMOD); | |
316fa9e0 | 672 | spin_unlock_irqrestore(i2s->lock, flags); |
1c7ac018 JB |
673 | |
674 | return 0; | |
675 | } | |
676 | ||
677 | static int i2s_hw_params(struct snd_pcm_substream *substream, | |
678 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
679 | { | |
680 | struct i2s_dai *i2s = to_info(dai); | |
ce8bcdbb | 681 | u32 mod, mask = 0, val = 0; |
316fa9e0 | 682 | unsigned long flags; |
1c7ac018 JB |
683 | |
684 | if (!is_secondary(i2s)) | |
ce8bcdbb | 685 | mask |= (MOD_DC2_EN | MOD_DC1_EN); |
1c7ac018 JB |
686 | |
687 | switch (params_channels(params)) { | |
688 | case 6: | |
ce8bcdbb | 689 | val |= MOD_DC2_EN; |
1c7ac018 | 690 | case 4: |
ce8bcdbb | 691 | val |= MOD_DC1_EN; |
1c7ac018 JB |
692 | break; |
693 | case 2: | |
588fb705 | 694 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
69e7a69a | 695 | i2s->dma_playback.addr_width = 4; |
588fb705 | 696 | else |
69e7a69a | 697 | i2s->dma_capture.addr_width = 4; |
588fb705 SP |
698 | break; |
699 | case 1: | |
700 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
69e7a69a | 701 | i2s->dma_playback.addr_width = 2; |
588fb705 | 702 | else |
69e7a69a | 703 | i2s->dma_capture.addr_width = 2; |
588fb705 | 704 | |
1c7ac018 JB |
705 | break; |
706 | default: | |
707 | dev_err(&i2s->pdev->dev, "%d channels not supported\n", | |
708 | params_channels(params)); | |
709 | return -EINVAL; | |
710 | } | |
711 | ||
712 | if (is_secondary(i2s)) | |
ce8bcdbb | 713 | mask |= MOD_BLCS_MASK; |
1c7ac018 | 714 | else |
ce8bcdbb | 715 | mask |= MOD_BLCP_MASK; |
1c7ac018 JB |
716 | |
717 | if (is_manager(i2s)) | |
ce8bcdbb | 718 | mask |= MOD_BLC_MASK; |
1c7ac018 | 719 | |
88ce1465 TB |
720 | switch (params_width(params)) { |
721 | case 8: | |
1c7ac018 | 722 | if (is_secondary(i2s)) |
ce8bcdbb | 723 | val |= MOD_BLCS_8BIT; |
1c7ac018 | 724 | else |
ce8bcdbb | 725 | val |= MOD_BLCP_8BIT; |
1c7ac018 | 726 | if (is_manager(i2s)) |
ce8bcdbb | 727 | val |= MOD_BLC_8BIT; |
1c7ac018 | 728 | break; |
88ce1465 | 729 | case 16: |
1c7ac018 | 730 | if (is_secondary(i2s)) |
ce8bcdbb | 731 | val |= MOD_BLCS_16BIT; |
1c7ac018 | 732 | else |
ce8bcdbb | 733 | val |= MOD_BLCP_16BIT; |
1c7ac018 | 734 | if (is_manager(i2s)) |
ce8bcdbb | 735 | val |= MOD_BLC_16BIT; |
1c7ac018 | 736 | break; |
88ce1465 | 737 | case 24: |
1c7ac018 | 738 | if (is_secondary(i2s)) |
ce8bcdbb | 739 | val |= MOD_BLCS_24BIT; |
1c7ac018 | 740 | else |
ce8bcdbb | 741 | val |= MOD_BLCP_24BIT; |
1c7ac018 | 742 | if (is_manager(i2s)) |
ce8bcdbb | 743 | val |= MOD_BLC_24BIT; |
1c7ac018 JB |
744 | break; |
745 | default: | |
746 | dev_err(&i2s->pdev->dev, "Format(%d) not supported\n", | |
747 | params_format(params)); | |
748 | return -EINVAL; | |
749 | } | |
ce8bcdbb | 750 | |
316fa9e0 | 751 | spin_lock_irqsave(i2s->lock, flags); |
ce8bcdbb SN |
752 | mod = readl(i2s->addr + I2SMOD); |
753 | mod = (mod & ~mask) | val; | |
1c7ac018 | 754 | writel(mod, i2s->addr + I2SMOD); |
316fa9e0 | 755 | spin_unlock_irqrestore(i2s->lock, flags); |
1c7ac018 | 756 | |
69e7a69a | 757 | snd_soc_dai_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture); |
d37bdf73 | 758 | |
1c7ac018 JB |
759 | i2s->frmclk = params_rate(params); |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
764 | /* We set constraints on the substream acc to the version of I2S */ | |
765 | static int i2s_startup(struct snd_pcm_substream *substream, | |
766 | struct snd_soc_dai *dai) | |
767 | { | |
768 | struct i2s_dai *i2s = to_info(dai); | |
dcd60fc3 | 769 | struct i2s_dai *other = get_other_dai(i2s); |
1c7ac018 JB |
770 | unsigned long flags; |
771 | ||
772 | spin_lock_irqsave(&lock, flags); | |
773 | ||
774 | i2s->mode |= DAI_OPENED; | |
775 | ||
776 | if (is_manager(other)) | |
777 | i2s->mode &= ~DAI_MANAGER; | |
778 | else | |
779 | i2s->mode |= DAI_MANAGER; | |
780 | ||
2d77828d PV |
781 | if (!any_active(i2s) && (i2s->quirks & QUIRK_NEED_RSTCLR)) |
782 | writel(CON_RSTCLR, i2s->addr + I2SCON); | |
783 | ||
1c7ac018 JB |
784 | spin_unlock_irqrestore(&lock, flags); |
785 | ||
786 | return 0; | |
787 | } | |
788 | ||
789 | static void i2s_shutdown(struct snd_pcm_substream *substream, | |
790 | struct snd_soc_dai *dai) | |
791 | { | |
792 | struct i2s_dai *i2s = to_info(dai); | |
dcd60fc3 | 793 | struct i2s_dai *other = get_other_dai(i2s); |
1c7ac018 JB |
794 | unsigned long flags; |
795 | ||
796 | spin_lock_irqsave(&lock, flags); | |
797 | ||
798 | i2s->mode &= ~DAI_OPENED; | |
799 | i2s->mode &= ~DAI_MANAGER; | |
800 | ||
074b89bb | 801 | if (is_opened(other)) |
1c7ac018 | 802 | other->mode |= DAI_MANAGER; |
074b89bb | 803 | |
1c7ac018 JB |
804 | /* Reset any constraint on RFS and BFS */ |
805 | i2s->rfs = 0; | |
806 | i2s->bfs = 0; | |
807 | ||
808 | spin_unlock_irqrestore(&lock, flags); | |
1c7ac018 JB |
809 | } |
810 | ||
811 | static int config_setup(struct i2s_dai *i2s) | |
812 | { | |
dcd60fc3 | 813 | struct i2s_dai *other = get_other_dai(i2s); |
1c7ac018 JB |
814 | unsigned rfs, bfs, blc; |
815 | u32 psr; | |
816 | ||
817 | blc = get_blc(i2s); | |
818 | ||
819 | bfs = i2s->bfs; | |
820 | ||
821 | if (!bfs && other) | |
822 | bfs = other->bfs; | |
823 | ||
824 | /* Select least possible multiple(2) if no constraint set */ | |
825 | if (!bfs) | |
826 | bfs = blc * 2; | |
827 | ||
828 | rfs = i2s->rfs; | |
829 | ||
830 | if (!rfs && other) | |
831 | rfs = other->rfs; | |
832 | ||
833 | if ((rfs == 256 || rfs == 512) && (blc == 24)) { | |
834 | dev_err(&i2s->pdev->dev, | |
835 | "%d-RFS not supported for 24-blc\n", rfs); | |
836 | return -EINVAL; | |
837 | } | |
838 | ||
839 | if (!rfs) { | |
840 | if (bfs == 16 || bfs == 32) | |
841 | rfs = 256; | |
842 | else | |
843 | rfs = 384; | |
844 | } | |
845 | ||
846 | /* If already setup and running */ | |
847 | if (any_active(i2s) && (get_rfs(i2s) != rfs || get_bfs(i2s) != bfs)) { | |
848 | dev_err(&i2s->pdev->dev, | |
849 | "%s:%d Other DAI busy\n", __func__, __LINE__); | |
850 | return -EAGAIN; | |
851 | } | |
852 | ||
1c7ac018 JB |
853 | set_bfs(i2s, bfs); |
854 | set_rfs(i2s, rfs); | |
855 | ||
77010010 PV |
856 | /* Don't bother with PSR in Slave mode */ |
857 | if (is_slave(i2s)) | |
858 | return 0; | |
859 | ||
1c7ac018 JB |
860 | if (!(i2s->quirks & QUIRK_NO_MUXPSR)) { |
861 | psr = i2s->rclk_srcrate / i2s->frmclk / rfs; | |
862 | writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR); | |
863 | dev_dbg(&i2s->pdev->dev, | |
864 | "RCLK_SRC=%luHz PSR=%u, RCLK=%dfs, BCLK=%dfs\n", | |
865 | i2s->rclk_srcrate, psr, rfs, bfs); | |
866 | } | |
867 | ||
868 | return 0; | |
869 | } | |
870 | ||
871 | static int i2s_trigger(struct snd_pcm_substream *substream, | |
872 | int cmd, struct snd_soc_dai *dai) | |
873 | { | |
874 | int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE); | |
875 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
876 | struct i2s_dai *i2s = to_info(rtd->cpu_dai); | |
877 | unsigned long flags; | |
878 | ||
879 | switch (cmd) { | |
880 | case SNDRV_PCM_TRIGGER_START: | |
881 | case SNDRV_PCM_TRIGGER_RESUME: | |
882 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
f3670536 | 883 | spin_lock_irqsave(i2s->lock, flags); |
1c7ac018 | 884 | |
1c7ac018 | 885 | if (config_setup(i2s)) { |
f3670536 | 886 | spin_unlock_irqrestore(i2s->lock, flags); |
1c7ac018 JB |
887 | return -EINVAL; |
888 | } | |
889 | ||
890 | if (capture) | |
891 | i2s_rxctrl(i2s, 1); | |
892 | else | |
893 | i2s_txctrl(i2s, 1); | |
894 | ||
f3670536 | 895 | spin_unlock_irqrestore(i2s->lock, flags); |
1c7ac018 JB |
896 | break; |
897 | case SNDRV_PCM_TRIGGER_STOP: | |
898 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
899 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
f3670536 | 900 | spin_lock_irqsave(i2s->lock, flags); |
1c7ac018 | 901 | |
c90887fe | 902 | if (capture) { |
1c7ac018 | 903 | i2s_rxctrl(i2s, 0); |
775bc971 | 904 | i2s_fifo(i2s, FIC_RXFLUSH); |
c90887fe JB |
905 | } else { |
906 | i2s_txctrl(i2s, 0); | |
775bc971 | 907 | i2s_fifo(i2s, FIC_TXFLUSH); |
c90887fe | 908 | } |
775bc971 | 909 | |
f3670536 | 910 | spin_unlock_irqrestore(i2s->lock, flags); |
1c7ac018 JB |
911 | break; |
912 | } | |
913 | ||
914 | return 0; | |
915 | } | |
916 | ||
917 | static int i2s_set_clkdiv(struct snd_soc_dai *dai, | |
918 | int div_id, int div) | |
919 | { | |
920 | struct i2s_dai *i2s = to_info(dai); | |
dcd60fc3 | 921 | struct i2s_dai *other = get_other_dai(i2s); |
1c7ac018 JB |
922 | |
923 | switch (div_id) { | |
924 | case SAMSUNG_I2S_DIV_BCLK: | |
925 | if ((any_active(i2s) && div && (get_bfs(i2s) != div)) | |
926 | || (other && other->bfs && (other->bfs != div))) { | |
927 | dev_err(&i2s->pdev->dev, | |
928 | "%s:%d Other DAI busy\n", __func__, __LINE__); | |
929 | return -EAGAIN; | |
930 | } | |
931 | i2s->bfs = div; | |
932 | break; | |
933 | default: | |
934 | dev_err(&i2s->pdev->dev, | |
935 | "Invalid clock divider(%d)\n", div_id); | |
936 | return -EINVAL; | |
937 | } | |
938 | ||
939 | return 0; | |
940 | } | |
941 | ||
942 | static snd_pcm_sframes_t | |
943 | i2s_delay(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) | |
944 | { | |
945 | struct i2s_dai *i2s = to_info(dai); | |
946 | u32 reg = readl(i2s->addr + I2SFIC); | |
947 | snd_pcm_sframes_t delay; | |
a5a56871 | 948 | const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs; |
1c7ac018 JB |
949 | |
950 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
951 | delay = FIC_RXCOUNT(reg); | |
952 | else if (is_secondary(i2s)) | |
953 | delay = FICS_TXCOUNT(readl(i2s->addr + I2SFICS)); | |
954 | else | |
a5a56871 | 955 | delay = (reg >> i2s_regs->ftx0cnt_off) & 0x7f; |
1c7ac018 JB |
956 | |
957 | return delay; | |
958 | } | |
959 | ||
960 | #ifdef CONFIG_PM | |
961 | static int i2s_suspend(struct snd_soc_dai *dai) | |
962 | { | |
963 | struct i2s_dai *i2s = to_info(dai); | |
964 | ||
d3d4e524 SN |
965 | i2s->suspend_i2smod = readl(i2s->addr + I2SMOD); |
966 | i2s->suspend_i2scon = readl(i2s->addr + I2SCON); | |
967 | i2s->suspend_i2spsr = readl(i2s->addr + I2SPSR); | |
1c7ac018 JB |
968 | |
969 | return 0; | |
970 | } | |
971 | ||
972 | static int i2s_resume(struct snd_soc_dai *dai) | |
973 | { | |
974 | struct i2s_dai *i2s = to_info(dai); | |
975 | ||
d3d4e524 SN |
976 | writel(i2s->suspend_i2scon, i2s->addr + I2SCON); |
977 | writel(i2s->suspend_i2smod, i2s->addr + I2SMOD); | |
978 | writel(i2s->suspend_i2spsr, i2s->addr + I2SPSR); | |
1c7ac018 JB |
979 | |
980 | return 0; | |
981 | } | |
982 | #else | |
983 | #define i2s_suspend NULL | |
984 | #define i2s_resume NULL | |
985 | #endif | |
986 | ||
987 | static int samsung_i2s_dai_probe(struct snd_soc_dai *dai) | |
988 | { | |
989 | struct i2s_dai *i2s = to_info(dai); | |
dcd60fc3 | 990 | struct i2s_dai *other = get_other_dai(i2s); |
ce8bcdbb | 991 | unsigned long flags; |
1c7ac018 | 992 | |
0ec2ba80 | 993 | if (is_secondary(i2s)) { /* If this is probe on the secondary DAI */ |
69e7a69a | 994 | snd_soc_dai_init_dma_data(dai, &other->sec_dai->dma_playback, |
3688569e | 995 | NULL); |
872c26bd | 996 | } else { |
69e7a69a | 997 | snd_soc_dai_init_dma_data(dai, &i2s->dma_playback, |
872c26bd | 998 | &i2s->dma_capture); |
511e3033 | 999 | |
872c26bd SN |
1000 | if (i2s->quirks & QUIRK_NEED_RSTCLR) |
1001 | writel(CON_RSTCLR, i2s->addr + I2SCON); | |
1c7ac018 | 1002 | |
872c26bd SN |
1003 | if (i2s->quirks & QUIRK_SUPPORTS_IDMA) |
1004 | idma_reg_addr_init(i2s->addr, | |
69e7a69a | 1005 | i2s->sec_dai->idma_playback.addr); |
872c26bd | 1006 | } |
61100f40 | 1007 | |
1c7ac018 JB |
1008 | /* Reset any constraint on RFS and BFS */ |
1009 | i2s->rfs = 0; | |
1010 | i2s->bfs = 0; | |
d66eac3e | 1011 | i2s->rclk_srcrate = 0; |
ce8bcdbb SN |
1012 | |
1013 | spin_lock_irqsave(i2s->lock, flags); | |
1c7ac018 JB |
1014 | i2s_txctrl(i2s, 0); |
1015 | i2s_rxctrl(i2s, 0); | |
1016 | i2s_fifo(i2s, FIC_TXFLUSH); | |
1017 | i2s_fifo(other, FIC_TXFLUSH); | |
1018 | i2s_fifo(i2s, FIC_RXFLUSH); | |
ce8bcdbb | 1019 | spin_unlock_irqrestore(i2s->lock, flags); |
1c7ac018 JB |
1020 | |
1021 | /* Gate CDCLK by default */ | |
1022 | if (!is_opened(other)) | |
1023 | i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK, | |
1024 | 0, SND_SOC_CLOCK_IN); | |
1025 | ||
1026 | return 0; | |
1027 | } | |
1028 | ||
1029 | static int samsung_i2s_dai_remove(struct snd_soc_dai *dai) | |
1030 | { | |
1031 | struct i2s_dai *i2s = snd_soc_dai_get_drvdata(dai); | |
1c7ac018 | 1032 | |
c92f1d0e | 1033 | if (!is_secondary(i2s)) { |
ce8bcdbb SN |
1034 | if (i2s->quirks & QUIRK_NEED_RSTCLR) { |
1035 | spin_lock(i2s->lock); | |
1c7ac018 | 1036 | writel(0, i2s->addr + I2SCON); |
ce8bcdbb SN |
1037 | spin_unlock(i2s->lock); |
1038 | } | |
1c7ac018 JB |
1039 | } |
1040 | ||
1c7ac018 JB |
1041 | return 0; |
1042 | } | |
1043 | ||
85e7652d | 1044 | static const struct snd_soc_dai_ops samsung_i2s_dai_ops = { |
1c7ac018 JB |
1045 | .trigger = i2s_trigger, |
1046 | .hw_params = i2s_hw_params, | |
1047 | .set_fmt = i2s_set_fmt, | |
1048 | .set_clkdiv = i2s_set_clkdiv, | |
1049 | .set_sysclk = i2s_set_sysclk, | |
1050 | .startup = i2s_startup, | |
1051 | .shutdown = i2s_shutdown, | |
1052 | .delay = i2s_delay, | |
1053 | }; | |
1054 | ||
4b828535 KM |
1055 | static const struct snd_soc_component_driver samsung_i2s_component = { |
1056 | .name = "samsung-i2s", | |
1057 | }; | |
1058 | ||
1c7ac018 JB |
1059 | #define SAMSUNG_I2S_RATES SNDRV_PCM_RATE_8000_96000 |
1060 | ||
1061 | #define SAMSUNG_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \ | |
1062 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
1063 | SNDRV_PCM_FMTBIT_S24_LE) | |
1064 | ||
fdca21ad | 1065 | static struct i2s_dai *i2s_alloc_dai(struct platform_device *pdev, bool sec) |
1c7ac018 JB |
1066 | { |
1067 | struct i2s_dai *i2s; | |
c6f9b1eb | 1068 | int ret; |
1c7ac018 | 1069 | |
b960ce74 | 1070 | i2s = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dai), GFP_KERNEL); |
1c7ac018 JB |
1071 | if (i2s == NULL) |
1072 | return NULL; | |
1073 | ||
1074 | i2s->pdev = pdev; | |
1075 | i2s->pri_dai = NULL; | |
1076 | i2s->sec_dai = NULL; | |
1077 | i2s->i2s_dai_drv.symmetric_rates = 1; | |
1078 | i2s->i2s_dai_drv.probe = samsung_i2s_dai_probe; | |
1079 | i2s->i2s_dai_drv.remove = samsung_i2s_dai_remove; | |
1080 | i2s->i2s_dai_drv.ops = &samsung_i2s_dai_ops; | |
1081 | i2s->i2s_dai_drv.suspend = i2s_suspend; | |
1082 | i2s->i2s_dai_drv.resume = i2s_resume; | |
a0ff6ea2 | 1083 | i2s->i2s_dai_drv.playback.channels_min = 1; |
1c7ac018 JB |
1084 | i2s->i2s_dai_drv.playback.channels_max = 2; |
1085 | i2s->i2s_dai_drv.playback.rates = SAMSUNG_I2S_RATES; | |
1086 | i2s->i2s_dai_drv.playback.formats = SAMSUNG_I2S_FMTS; | |
1087 | ||
1088 | if (!sec) { | |
588fb705 | 1089 | i2s->i2s_dai_drv.capture.channels_min = 1; |
1c7ac018 JB |
1090 | i2s->i2s_dai_drv.capture.channels_max = 2; |
1091 | i2s->i2s_dai_drv.capture.rates = SAMSUNG_I2S_RATES; | |
1092 | i2s->i2s_dai_drv.capture.formats = SAMSUNG_I2S_FMTS; | |
c6f9b1eb | 1093 | dev_set_drvdata(&i2s->pdev->dev, i2s); |
1c7ac018 | 1094 | } else { /* Create a new platform_device for Secondary */ |
c6f9b1eb | 1095 | i2s->pdev = platform_device_alloc("samsung-i2s-sec", -1); |
29ca9c73 | 1096 | if (!i2s->pdev) |
1c7ac018 | 1097 | return NULL; |
1c7ac018 | 1098 | |
2f6f0ffb MB |
1099 | i2s->pdev->dev.parent = &pdev->dev; |
1100 | ||
c6f9b1eb P |
1101 | platform_set_drvdata(i2s->pdev, i2s); |
1102 | ret = platform_device_add(i2s->pdev); | |
1103 | if (ret < 0) | |
1104 | return NULL; | |
1105 | } | |
1c7ac018 JB |
1106 | |
1107 | return i2s; | |
1108 | } | |
1109 | ||
2b960386 SN |
1110 | static void i2s_free_sec_dai(struct i2s_dai *i2s) |
1111 | { | |
1112 | platform_device_del(i2s->pdev); | |
1113 | } | |
1114 | ||
641d334b | 1115 | #ifdef CONFIG_PM |
5b1d3c34 C |
1116 | static int i2s_runtime_suspend(struct device *dev) |
1117 | { | |
1118 | struct i2s_dai *i2s = dev_get_drvdata(dev); | |
1119 | ||
1120 | clk_disable_unprepare(i2s->clk); | |
1121 | ||
1122 | return 0; | |
1123 | } | |
1124 | ||
1125 | static int i2s_runtime_resume(struct device *dev) | |
1126 | { | |
1127 | struct i2s_dai *i2s = dev_get_drvdata(dev); | |
1128 | ||
1129 | clk_prepare_enable(i2s->clk); | |
1130 | ||
1131 | return 0; | |
1132 | } | |
641d334b | 1133 | #endif /* CONFIG_PM */ |
5b1d3c34 | 1134 | |
074b89bb SN |
1135 | static void i2s_unregister_clocks(struct i2s_dai *i2s) |
1136 | { | |
1137 | int i; | |
1138 | ||
1139 | for (i = 0; i < i2s->clk_data.clk_num; i++) { | |
1140 | if (!IS_ERR(i2s->clk_table[i])) | |
1141 | clk_unregister(i2s->clk_table[i]); | |
1142 | } | |
1143 | } | |
1144 | ||
1145 | static void i2s_unregister_clock_provider(struct platform_device *pdev) | |
1146 | { | |
1147 | struct i2s_dai *i2s = dev_get_drvdata(&pdev->dev); | |
1148 | ||
1149 | of_clk_del_provider(pdev->dev.of_node); | |
1150 | i2s_unregister_clocks(i2s); | |
1151 | } | |
1152 | ||
1153 | static int i2s_register_clock_provider(struct platform_device *pdev) | |
1154 | { | |
1155 | struct device *dev = &pdev->dev; | |
1156 | struct i2s_dai *i2s = dev_get_drvdata(dev); | |
1157 | const char *clk_name[2] = { "i2s_opclk0", "i2s_opclk1" }; | |
1158 | const char *p_names[2] = { NULL }; | |
1159 | const struct samsung_i2s_variant_regs *reg_info = i2s->variant_regs; | |
1160 | struct clk *rclksrc; | |
1161 | int ret, i; | |
1162 | ||
1163 | /* Register the clock provider only if it's expected in the DTB */ | |
1164 | if (!of_find_property(dev->of_node, "#clock-cells", NULL)) | |
1165 | return 0; | |
1166 | ||
1167 | /* Get the RCLKSRC mux clock parent clock names */ | |
1168 | for (i = 0; i < ARRAY_SIZE(p_names); i++) { | |
1169 | rclksrc = clk_get(dev, clk_name[i]); | |
1170 | if (IS_ERR(rclksrc)) | |
1171 | continue; | |
1172 | p_names[i] = __clk_get_name(rclksrc); | |
1173 | clk_put(rclksrc); | |
1174 | } | |
1175 | ||
1176 | if (!(i2s->quirks & QUIRK_NO_MUXPSR)) { | |
1177 | /* Activate the prescaler */ | |
1178 | u32 val = readl(i2s->addr + I2SPSR); | |
1179 | writel(val | PSR_PSREN, i2s->addr + I2SPSR); | |
1180 | ||
1181 | i2s->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(NULL, | |
1182 | "i2s_rclksrc", p_names, ARRAY_SIZE(p_names), | |
1183 | CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, | |
1184 | i2s->addr + I2SMOD, reg_info->rclksrc_off, | |
1185 | 1, 0, i2s->lock); | |
1186 | ||
1187 | i2s->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(NULL, | |
1188 | "i2s_presc", "i2s_rclksrc", | |
1189 | CLK_SET_RATE_PARENT, | |
1190 | i2s->addr + I2SPSR, 8, 6, 0, i2s->lock); | |
1191 | ||
1192 | p_names[0] = "i2s_presc"; | |
1193 | i2s->clk_data.clk_num = 2; | |
1194 | } | |
1195 | of_property_read_string_index(dev->of_node, | |
1196 | "clock-output-names", 0, &clk_name[0]); | |
1197 | ||
1198 | i2s->clk_table[CLK_I2S_CDCLK] = clk_register_gate(NULL, clk_name[0], | |
1199 | p_names[0], CLK_SET_RATE_PARENT, | |
1200 | i2s->addr + I2SMOD, reg_info->cdclkcon_off, | |
1201 | CLK_GATE_SET_TO_DISABLE, i2s->lock); | |
1202 | ||
1203 | i2s->clk_data.clk_num += 1; | |
1204 | i2s->clk_data.clks = i2s->clk_table; | |
1205 | ||
1206 | ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, | |
1207 | &i2s->clk_data); | |
1208 | if (ret < 0) { | |
1209 | dev_err(dev, "failed to add clock provider: %d\n", ret); | |
1210 | i2s_unregister_clocks(i2s); | |
1211 | } | |
1212 | ||
1213 | return ret; | |
1214 | } | |
1215 | ||
fdca21ad | 1216 | static int samsung_i2s_probe(struct platform_device *pdev) |
1c7ac018 | 1217 | { |
1c7ac018 | 1218 | struct i2s_dai *pri_dai, *sec_dai = NULL; |
40476f61 PV |
1219 | struct s3c_audio_pdata *i2s_pdata = pdev->dev.platform_data; |
1220 | struct samsung_i2s *i2s_cfg = NULL; | |
1c7ac018 | 1221 | struct resource *res; |
40476f61 PV |
1222 | u32 regs_base, quirks = 0, idma_addr = 0; |
1223 | struct device_node *np = pdev->dev.of_node; | |
7da493e9 | 1224 | const struct samsung_i2s_dai_data *i2s_dai_data; |
c92f1d0e | 1225 | int ret; |
1c7ac018 | 1226 | |
2f7b5d14 SN |
1227 | if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) |
1228 | i2s_dai_data = of_device_get_match_data(&pdev->dev); | |
1229 | else | |
1230 | i2s_dai_data = (struct samsung_i2s_dai_data *) | |
1231 | platform_get_device_id(pdev)->driver_data; | |
7c62eebb | 1232 | |
2f7b5d14 | 1233 | /* Call during the secondary interface registration */ |
7da493e9 | 1234 | if (i2s_dai_data->dai_type == TYPE_SEC) { |
1c7ac018 | 1235 | sec_dai = dev_get_drvdata(&pdev->dev); |
a9b977ec P |
1236 | if (!sec_dai) { |
1237 | dev_err(&pdev->dev, "Unable to get drvdata\n"); | |
1238 | return -EFAULT; | |
1239 | } | |
53f7faa1 | 1240 | ret = devm_snd_soc_register_component(&sec_dai->pdev->dev, |
d644a115 MB |
1241 | &samsung_i2s_component, |
1242 | &sec_dai->i2s_dai_drv, 1); | |
53f7faa1 SN |
1243 | if (ret != 0) |
1244 | return ret; | |
1245 | ||
9bdca822 | 1246 | return samsung_asoc_dma_platform_register(&pdev->dev, |
42a74e77 | 1247 | sec_dai->filter, "tx-sec", NULL); |
1c7ac018 JB |
1248 | } |
1249 | ||
40476f61 PV |
1250 | pri_dai = i2s_alloc_dai(pdev, false); |
1251 | if (!pri_dai) { | |
1252 | dev_err(&pdev->dev, "Unable to alloc I2S_pri\n"); | |
1253 | return -ENOMEM; | |
1c7ac018 JB |
1254 | } |
1255 | ||
f3670536 SN |
1256 | spin_lock_init(&pri_dai->spinlock); |
1257 | pri_dai->lock = &pri_dai->spinlock; | |
1258 | ||
40476f61 | 1259 | if (!np) { |
40476f61 PV |
1260 | if (i2s_pdata == NULL) { |
1261 | dev_err(&pdev->dev, "Can't work without s3c_audio_pdata\n"); | |
1262 | return -EINVAL; | |
1263 | } | |
1264 | ||
69e7a69a SN |
1265 | pri_dai->dma_playback.filter_data = i2s_pdata->dma_playback; |
1266 | pri_dai->dma_capture.filter_data = i2s_pdata->dma_capture; | |
9bdca822 | 1267 | pri_dai->filter = i2s_pdata->dma_filter; |
b9a1a743 | 1268 | |
40476f61 PV |
1269 | if (&i2s_pdata->type) |
1270 | i2s_cfg = &i2s_pdata->type.i2s; | |
1271 | ||
1272 | if (i2s_cfg) { | |
1273 | quirks = i2s_cfg->quirks; | |
1274 | idma_addr = i2s_cfg->idma_addr; | |
1275 | } | |
1276 | } else { | |
7da493e9 | 1277 | quirks = i2s_dai_data->quirks; |
40476f61 PV |
1278 | if (of_property_read_u32(np, "samsung,idma-addr", |
1279 | &idma_addr)) { | |
b0759736 PV |
1280 | if (quirks & QUIRK_SUPPORTS_IDMA) { |
1281 | dev_info(&pdev->dev, "idma address is not"\ | |
40476f61 | 1282 | "specified"); |
40476f61 PV |
1283 | } |
1284 | } | |
1285 | } | |
1c7ac018 JB |
1286 | |
1287 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
af1cf5cf SN |
1288 | pri_dai->addr = devm_ioremap_resource(&pdev->dev, res); |
1289 | if (IS_ERR(pri_dai->addr)) | |
1290 | return PTR_ERR(pri_dai->addr); | |
1c7ac018 | 1291 | |
1c7ac018 JB |
1292 | regs_base = res->start; |
1293 | ||
0ec2ba80 SN |
1294 | pri_dai->clk = devm_clk_get(&pdev->dev, "iis"); |
1295 | if (IS_ERR(pri_dai->clk)) { | |
1296 | dev_err(&pdev->dev, "Failed to get iis clock\n"); | |
1297 | return PTR_ERR(pri_dai->clk); | |
1298 | } | |
c92f1d0e SN |
1299 | |
1300 | ret = clk_prepare_enable(pri_dai->clk); | |
1301 | if (ret != 0) { | |
1302 | dev_err(&pdev->dev, "failed to enable clock: %d\n", ret); | |
1303 | return ret; | |
1304 | } | |
69e7a69a SN |
1305 | pri_dai->dma_playback.addr = regs_base + I2STXD; |
1306 | pri_dai->dma_capture.addr = regs_base + I2SRXD; | |
1307 | pri_dai->dma_playback.chan_name = "tx"; | |
1308 | pri_dai->dma_capture.chan_name = "rx"; | |
1309 | pri_dai->dma_playback.addr_width = 4; | |
1310 | pri_dai->dma_capture.addr_width = 4; | |
1c7ac018 | 1311 | pri_dai->quirks = quirks; |
a5a56871 | 1312 | pri_dai->variant_regs = i2s_dai_data->i2s_variant_regs; |
1c7ac018 JB |
1313 | |
1314 | if (quirks & QUIRK_PRI_6CHAN) | |
1315 | pri_dai->i2s_dai_drv.playback.channels_max = 6; | |
1316 | ||
1317 | if (quirks & QUIRK_SEC_DAI) { | |
1318 | sec_dai = i2s_alloc_dai(pdev, true); | |
1319 | if (!sec_dai) { | |
1320 | dev_err(&pdev->dev, "Unable to alloc I2S_sec\n"); | |
af1cf5cf | 1321 | return -ENOMEM; |
1c7ac018 | 1322 | } |
7e5d8706 | 1323 | |
f3670536 | 1324 | sec_dai->lock = &pri_dai->spinlock; |
7e5d8706 | 1325 | sec_dai->variant_regs = pri_dai->variant_regs; |
69e7a69a SN |
1326 | sec_dai->dma_playback.addr = regs_base + I2STXDS; |
1327 | sec_dai->dma_playback.chan_name = "tx-sec"; | |
40476f61 | 1328 | |
9bdca822 | 1329 | if (!np) { |
69e7a69a | 1330 | sec_dai->dma_playback.filter_data = i2s_pdata->dma_play_sec; |
9bdca822 AB |
1331 | sec_dai->filter = i2s_pdata->dma_filter; |
1332 | } | |
40476f61 | 1333 | |
69e7a69a | 1334 | sec_dai->dma_playback.addr_width = 4; |
af1cf5cf | 1335 | sec_dai->addr = pri_dai->addr; |
0ec2ba80 | 1336 | sec_dai->clk = pri_dai->clk; |
1c7ac018 | 1337 | sec_dai->quirks = quirks; |
69e7a69a | 1338 | sec_dai->idma_playback.addr = idma_addr; |
1c7ac018 JB |
1339 | sec_dai->pri_dai = pri_dai; |
1340 | pri_dai->sec_dai = sec_dai; | |
1341 | } | |
1342 | ||
0429ffef MB |
1343 | if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) { |
1344 | dev_err(&pdev->dev, "Unable to configure gpio\n"); | |
af1cf5cf | 1345 | return -EINVAL; |
1c7ac018 JB |
1346 | } |
1347 | ||
2b960386 | 1348 | ret = devm_snd_soc_register_component(&pri_dai->pdev->dev, |
d644a115 MB |
1349 | &samsung_i2s_component, |
1350 | &pri_dai->i2s_dai_drv, 1); | |
2b960386 SN |
1351 | if (ret < 0) |
1352 | goto err_free_dai; | |
1353 | ||
42a74e77 SN |
1354 | ret = samsung_asoc_dma_platform_register(&pdev->dev, pri_dai->filter, |
1355 | NULL, NULL); | |
2b960386 SN |
1356 | if (ret < 0) |
1357 | goto err_free_dai; | |
1c7ac018 | 1358 | |
c5cf4dbc MB |
1359 | pm_runtime_enable(&pdev->dev); |
1360 | ||
2b960386 SN |
1361 | ret = i2s_register_clock_provider(pdev); |
1362 | if (!ret) | |
1363 | return 0; | |
a08485d8 | 1364 | |
2b960386 SN |
1365 | pm_runtime_disable(&pdev->dev); |
1366 | err_free_dai: | |
1367 | if (sec_dai) | |
1368 | i2s_free_sec_dai(sec_dai); | |
1369 | return ret; | |
1c7ac018 JB |
1370 | } |
1371 | ||
fdca21ad | 1372 | static int samsung_i2s_remove(struct platform_device *pdev) |
1c7ac018 JB |
1373 | { |
1374 | struct i2s_dai *i2s, *other; | |
1375 | ||
1376 | i2s = dev_get_drvdata(&pdev->dev); | |
dcd60fc3 | 1377 | other = get_other_dai(i2s); |
1c7ac018 JB |
1378 | |
1379 | if (other) { | |
1380 | other->pri_dai = NULL; | |
1381 | other->sec_dai = NULL; | |
1382 | } else { | |
c5cf4dbc | 1383 | pm_runtime_disable(&pdev->dev); |
1c7ac018 JB |
1384 | } |
1385 | ||
074b89bb SN |
1386 | if (!is_secondary(i2s)) { |
1387 | i2s_unregister_clock_provider(pdev); | |
c92f1d0e | 1388 | clk_disable_unprepare(i2s->clk); |
074b89bb | 1389 | } |
c92f1d0e | 1390 | |
1c7ac018 JB |
1391 | i2s->pri_dai = NULL; |
1392 | i2s->sec_dai = NULL; | |
1393 | ||
1c7ac018 JB |
1394 | return 0; |
1395 | } | |
1396 | ||
a5a56871 PV |
1397 | static const struct samsung_i2s_variant_regs i2sv3_regs = { |
1398 | .bfs_off = 1, | |
1399 | .rfs_off = 3, | |
1400 | .sdf_off = 5, | |
1401 | .txr_off = 8, | |
1402 | .rclksrc_off = 10, | |
1403 | .mss_off = 11, | |
1404 | .cdclkcon_off = 12, | |
1405 | .lrp_off = 7, | |
1406 | .bfs_mask = 0x3, | |
1407 | .rfs_mask = 0x3, | |
1408 | .ftx0cnt_off = 8, | |
1409 | }; | |
1410 | ||
1411 | static const struct samsung_i2s_variant_regs i2sv6_regs = { | |
1412 | .bfs_off = 0, | |
1413 | .rfs_off = 4, | |
1414 | .sdf_off = 6, | |
1415 | .txr_off = 8, | |
1416 | .rclksrc_off = 10, | |
1417 | .mss_off = 11, | |
1418 | .cdclkcon_off = 12, | |
1419 | .lrp_off = 15, | |
1420 | .bfs_mask = 0xf, | |
1421 | .rfs_mask = 0x3, | |
1422 | .ftx0cnt_off = 8, | |
1423 | }; | |
1424 | ||
1425 | static const struct samsung_i2s_variant_regs i2sv7_regs = { | |
1426 | .bfs_off = 0, | |
1427 | .rfs_off = 4, | |
1428 | .sdf_off = 7, | |
1429 | .txr_off = 9, | |
1430 | .rclksrc_off = 11, | |
1431 | .mss_off = 12, | |
1432 | .cdclkcon_off = 22, | |
1433 | .lrp_off = 15, | |
1434 | .bfs_mask = 0xf, | |
1435 | .rfs_mask = 0x7, | |
1436 | .ftx0cnt_off = 0, | |
1437 | }; | |
1438 | ||
1439 | static const struct samsung_i2s_variant_regs i2sv5_i2s1_regs = { | |
1440 | .bfs_off = 0, | |
1441 | .rfs_off = 3, | |
1442 | .sdf_off = 6, | |
1443 | .txr_off = 8, | |
1444 | .rclksrc_off = 10, | |
1445 | .mss_off = 11, | |
1446 | .cdclkcon_off = 12, | |
1447 | .lrp_off = 15, | |
1448 | .bfs_mask = 0x7, | |
1449 | .rfs_mask = 0x7, | |
1450 | .ftx0cnt_off = 8, | |
1451 | }; | |
1452 | ||
7da493e9 PV |
1453 | static const struct samsung_i2s_dai_data i2sv3_dai_type = { |
1454 | .dai_type = TYPE_PRI, | |
1455 | .quirks = QUIRK_NO_MUXPSR, | |
a5a56871 | 1456 | .i2s_variant_regs = &i2sv3_regs, |
7da493e9 PV |
1457 | }; |
1458 | ||
1459 | static const struct samsung_i2s_dai_data i2sv5_dai_type = { | |
1460 | .dai_type = TYPE_PRI, | |
b0759736 PV |
1461 | .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR | |
1462 | QUIRK_SUPPORTS_IDMA, | |
a5a56871 | 1463 | .i2s_variant_regs = &i2sv3_regs, |
7da493e9 PV |
1464 | }; |
1465 | ||
4ca0c0d4 PV |
1466 | static const struct samsung_i2s_dai_data i2sv6_dai_type = { |
1467 | .dai_type = TYPE_PRI, | |
1468 | .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR | | |
b0759736 | 1469 | QUIRK_SUPPORTS_TDM | QUIRK_SUPPORTS_IDMA, |
a5a56871 PV |
1470 | .i2s_variant_regs = &i2sv6_regs, |
1471 | }; | |
1472 | ||
1473 | static const struct samsung_i2s_dai_data i2sv7_dai_type = { | |
1474 | .dai_type = TYPE_PRI, | |
1475 | .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR | | |
1476 | QUIRK_SUPPORTS_TDM, | |
1477 | .i2s_variant_regs = &i2sv7_regs, | |
1478 | }; | |
1479 | ||
1480 | static const struct samsung_i2s_dai_data i2sv5_dai_type_i2s1 = { | |
1481 | .dai_type = TYPE_PRI, | |
1482 | .quirks = QUIRK_PRI_6CHAN | QUIRK_NEED_RSTCLR, | |
1483 | .i2s_variant_regs = &i2sv5_i2s1_regs, | |
4ca0c0d4 PV |
1484 | }; |
1485 | ||
7da493e9 PV |
1486 | static const struct samsung_i2s_dai_data samsung_dai_type_sec = { |
1487 | .dai_type = TYPE_SEC, | |
1488 | }; | |
1489 | ||
eb8ca0fa | 1490 | static const struct platform_device_id samsung_i2s_driver_ids[] = { |
7c62eebb PV |
1491 | { |
1492 | .name = "samsung-i2s", | |
3f024980 | 1493 | .driver_data = (kernel_ulong_t)&i2sv3_dai_type, |
7c62eebb PV |
1494 | }, { |
1495 | .name = "samsung-i2s-sec", | |
7da493e9 | 1496 | .driver_data = (kernel_ulong_t)&samsung_dai_type_sec, |
7c62eebb PV |
1497 | }, |
1498 | {}, | |
1499 | }; | |
2af19558 | 1500 | MODULE_DEVICE_TABLE(platform, samsung_i2s_driver_ids); |
7c62eebb | 1501 | |
40476f61 | 1502 | #ifdef CONFIG_OF |
40476f61 | 1503 | static const struct of_device_id exynos_i2s_match[] = { |
7da493e9 PV |
1504 | { |
1505 | .compatible = "samsung,s3c6410-i2s", | |
1506 | .data = &i2sv3_dai_type, | |
1507 | }, { | |
1508 | .compatible = "samsung,s5pv210-i2s", | |
1509 | .data = &i2sv5_dai_type, | |
4ca0c0d4 PV |
1510 | }, { |
1511 | .compatible = "samsung,exynos5420-i2s", | |
1512 | .data = &i2sv6_dai_type, | |
a5a56871 PV |
1513 | }, { |
1514 | .compatible = "samsung,exynos7-i2s", | |
1515 | .data = &i2sv7_dai_type, | |
1516 | }, { | |
1517 | .compatible = "samsung,exynos7-i2s1", | |
1518 | .data = &i2sv5_dai_type_i2s1, | |
40476f61 PV |
1519 | }, |
1520 | {}, | |
1521 | }; | |
1522 | MODULE_DEVICE_TABLE(of, exynos_i2s_match); | |
1523 | #endif | |
1524 | ||
5b1d3c34 C |
1525 | static const struct dev_pm_ops samsung_i2s_pm = { |
1526 | SET_RUNTIME_PM_OPS(i2s_runtime_suspend, | |
1527 | i2s_runtime_resume, NULL) | |
1528 | }; | |
1529 | ||
1c7ac018 JB |
1530 | static struct platform_driver samsung_i2s_driver = { |
1531 | .probe = samsung_i2s_probe, | |
fdca21ad | 1532 | .remove = samsung_i2s_remove, |
7c62eebb | 1533 | .id_table = samsung_i2s_driver_ids, |
1c7ac018 JB |
1534 | .driver = { |
1535 | .name = "samsung-i2s", | |
40476f61 | 1536 | .of_match_table = of_match_ptr(exynos_i2s_match), |
5b1d3c34 | 1537 | .pm = &samsung_i2s_pm, |
1c7ac018 JB |
1538 | }, |
1539 | }; | |
1540 | ||
e00c3f55 | 1541 | module_platform_driver(samsung_i2s_driver); |
1c7ac018 JB |
1542 | |
1543 | /* Module information */ | |
df8ad335 | 1544 | MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>"); |
1c7ac018 JB |
1545 | MODULE_DESCRIPTION("Samsung I2S Interface"); |
1546 | MODULE_ALIAS("platform:samsung-i2s"); | |
1547 | MODULE_LICENSE("GPL"); |