projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: samsung: Fix error handling for clock lookup
[deliverable/linux.git] / sound / soc / samsung / i2s.c
CommitLineData
5033f43c 1/* sound/soc/samsung/i2s.c
1c7ac018
JB		 2 *
3 * ALSA SoC Audio Layer - Samsung I2S Controller driver
4 *
5 * Copyright (c) 2010 Samsung Electronics Co. Ltd.
df8ad335 6 * Jaswinder Singh <jassisinghbrar@gmail.com>
1c7ac018
JB		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/delay.h>
14#include <linux/slab.h>
15#include <linux/clk.h>
16#include <linux/io.h>
da155d5b 17#include <linux/module.h>
40476f61
PV		 18#include <linux/of.h>
19#include <linux/of_gpio.h>
c5cf4dbc 20#include <linux/pm_runtime.h>
1c7ac018 21
1c7ac018 22#include <sound/soc.h>
0378b6ac 23#include <sound/pcm_params.h>
1c7ac018 24
436d42c6 25#include <linux/platform_data/asoc-s3c.h>
1c7ac018
JB		 26
27#include "dma.h"
61100f40 28#include "idma.h"
1c7ac018 29#include "i2s.h"
172a453d 30#include "i2s-regs.h"
1c7ac018
JB		 31
32#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
33
7c62eebb
PV		 34enum samsung_dai_type {
35 TYPE_PRI,
36 TYPE_SEC,
37};
38
a5a56871
PV		 39struct samsung_i2s_variant_regs {
40 unsigned int bfs_off;
41 unsigned int rfs_off;
42 unsigned int sdf_off;
43 unsigned int txr_off;
44 unsigned int rclksrc_off;
45 unsigned int mss_off;
46 unsigned int cdclkcon_off;
47 unsigned int lrp_off;
48 unsigned int bfs_mask;
49 unsigned int rfs_mask;
50 unsigned int ftx0cnt_off;
51};
52
40476f61
PV		 53struct samsung_i2s_dai_data {
54 int dai_type;
7da493e9 55 u32 quirks;
a5a56871 56 const struct samsung_i2s_variant_regs *i2s_variant_regs;
40476f61
PV		 57};
58
1c7ac018
JB		 59struct i2s_dai {
60 /* Platform device for this DAI */
61 struct platform_device *pdev;
62 /* IOREMAP'd SFRs */
63 void __iomem *addr;
64 /* Physical base address of SFRs */
65 u32 base;
66 /* Rate of RCLK source clock */
67 unsigned long rclk_srcrate;
68 /* Frame Clock */
69 unsigned frmclk;
70 /*
71 * Specifically requested RCLK,BCLK by MACHINE Driver.
72 * 0 indicates CPU driver is free to choose any value.
73 */
74 unsigned rfs, bfs;
75 /* I2S Controller's core clock */
76 struct clk *clk;
77 /* Clock for generating I2S signals */
78 struct clk *op_clk;
1c7ac018
JB		 79 /* Pointer to the Primary_Fifo if this is Sec_Fifo, NULL otherwise */
80 struct i2s_dai *pri_dai;
81 /* Pointer to the Secondary_Fifo if it has one, NULL otherwise */
82 struct i2s_dai *sec_dai;
83#define DAI_OPENED (1 << 0) /* Dai is opened */
84#define DAI_MANAGER (1 << 1) /* Dai is the manager */
85 unsigned mode;
b97c60ab
SN		 86 /* CDCLK pin direction: 0 - input, 1 - output */
87 unsigned int cdclk_out:1;
1c7ac018
JB		 88 /* Driver for this DAI */
89 struct snd_soc_dai_driver i2s_dai_drv;
90 /* DMA parameters */
91 struct s3c_dma_params dma_playback;
92 struct s3c_dma_params dma_capture;
61100f40 93 struct s3c_dma_params idma_playback;
1c7ac018
JB		 94 u32 quirks;
95 u32 suspend_i2smod;
96 u32 suspend_i2scon;
97 u32 suspend_i2spsr;
40476f61 98 unsigned long gpios[7]; /* i2s gpio line numbers */
a5a56871 99 const struct samsung_i2s_variant_regs *variant_regs;
1c7ac018
JB		 100};
101
102/* Lock for cross i/f checks */
103static DEFINE_SPINLOCK(lock);
104
105/* If this is the 'overlay' stereo DAI */
106static inline bool is_secondary(struct i2s_dai *i2s)
107{
108 return i2s->pri_dai ? true : false;
109}
110
111/* If operating in SoC-Slave mode */
112static inline bool is_slave(struct i2s_dai *i2s)
113{
a5a56871
PV		 114 u32 mod = readl(i2s->addr + I2SMOD);
115 return (mod & (1 << i2s->variant_regs->mss_off)) ? true : false;
1c7ac018
JB		 116}
117
118/* If this interface of the controller is transmitting data */
119static inline bool tx_active(struct i2s_dai *i2s)
120{
121 u32 active;
122
123 if (!i2s)
124 return false;
125
33195500 126 active = readl(i2s->addr + I2SCON);
1c7ac018
JB		 127
128 if (is_secondary(i2s))
129 active &= CON_TXSDMA_ACTIVE;
130 else
131 active &= CON_TXDMA_ACTIVE;
132
133 return active ? true : false;
134}
135
136/* If the other interface of the controller is transmitting data */
137static inline bool other_tx_active(struct i2s_dai *i2s)
138{
139 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
140
141 return tx_active(other);
142}
143
144/* If any interface of the controller is transmitting data */
145static inline bool any_tx_active(struct i2s_dai *i2s)
146{
147 return tx_active(i2s) || other_tx_active(i2s);
148}
149
150/* If this interface of the controller is receiving data */
151static inline bool rx_active(struct i2s_dai *i2s)
152{
153 u32 active;
154
155 if (!i2s)
156 return false;
157
33195500 158 active = readl(i2s->addr + I2SCON) & CON_RXDMA_ACTIVE;
1c7ac018
JB		 159
160 return active ? true : false;
161}
162
163/* If the other interface of the controller is receiving data */
164static inline bool other_rx_active(struct i2s_dai *i2s)
165{
166 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
167
168 return rx_active(other);
169}
170
171/* If any interface of the controller is receiving data */
172static inline bool any_rx_active(struct i2s_dai *i2s)
173{
174 return rx_active(i2s) || other_rx_active(i2s);
175}
176
177/* If the other DAI is transmitting or receiving data */
178static inline bool other_active(struct i2s_dai *i2s)
179{
180 return other_rx_active(i2s) || other_tx_active(i2s);
181}
182
183/* If this DAI is transmitting or receiving data */
184static inline bool this_active(struct i2s_dai *i2s)
185{
186 return tx_active(i2s) || rx_active(i2s);
187}
188
189/* If the controller is active anyway */
190static inline bool any_active(struct i2s_dai *i2s)
191{
192 return this_active(i2s) || other_active(i2s);
193}
194
195static inline struct i2s_dai *to_info(struct snd_soc_dai *dai)
196{
197 return snd_soc_dai_get_drvdata(dai);
198}
199
200static inline bool is_opened(struct i2s_dai *i2s)
201{
202 if (i2s && (i2s->mode & DAI_OPENED))
203 return true;
204 else
205 return false;
206}
207
208static inline bool is_manager(struct i2s_dai *i2s)
209{
210 if (is_opened(i2s) && (i2s->mode & DAI_MANAGER))
211 return true;
212 else
213 return false;
214}
215
216/* Read RCLK of I2S (in multiples of LRCLK) */
217static inline unsigned get_rfs(struct i2s_dai *i2s)
218{
4ca0c0d4 219 u32 rfs;
a5a56871
PV		 220 rfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->rfs_off;
221 rfs &= i2s->variant_regs->rfs_mask;
1c7ac018
JB		 222
223 switch (rfs) {
a5a56871
PV		 224 case 7: return 192;
225 case 6: return 96;
226 case 5: return 128;
227 case 4: return 64;
1c7ac018
JB		 228 case 3: return 768;
229 case 2: return 384;
230 case 1: return 512;
231 default: return 256;
232 }
233}
234
235/* Write RCLK of I2S (in multiples of LRCLK) */
236static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
237{
238 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871 239 int rfs_shift = i2s->variant_regs->rfs_off;
1c7ac018 240
a5a56871 241 mod &= ~(i2s->variant_regs->rfs_mask << rfs_shift);
1c7ac018
JB		 242
243 switch (rfs) {
a5a56871
PV		 244 case 192:
245 mod |= (EXYNOS7_MOD_RCLK_192FS << rfs_shift);
246 break;
247 case 96:
248 mod |= (EXYNOS7_MOD_RCLK_96FS << rfs_shift);
249 break;
250 case 128:
251 mod |= (EXYNOS7_MOD_RCLK_128FS << rfs_shift);
252 break;
253 case 64:
254 mod |= (EXYNOS7_MOD_RCLK_64FS << rfs_shift);
255 break;
1c7ac018 256 case 768:
b60be4aa 257 mod |= (MOD_RCLK_768FS << rfs_shift);
1c7ac018
JB		 258 break;
259 case 512:
b60be4aa 260 mod |= (MOD_RCLK_512FS << rfs_shift);
1c7ac018
JB		 261 break;
262 case 384:
b60be4aa 263 mod |= (MOD_RCLK_384FS << rfs_shift);
1c7ac018
JB		 264 break;
265 default:
b60be4aa 266 mod |= (MOD_RCLK_256FS << rfs_shift);
1c7ac018
JB		 267 break;
268 }
269
270 writel(mod, i2s->addr + I2SMOD);
271}
272
273/* Read Bit-Clock of I2S (in multiples of LRCLK) */
274static inline unsigned get_bfs(struct i2s_dai *i2s)
275{
4ca0c0d4 276 u32 bfs;
a5a56871
PV		 277 bfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->bfs_off;
278 bfs &= i2s->variant_regs->bfs_mask;
1c7ac018
JB		 279
280 switch (bfs) {
4ca0c0d4
PV		 281 case 8: return 256;
282 case 7: return 192;
283 case 6: return 128;
284 case 5: return 96;
285 case 4: return 64;
1c7ac018
JB		 286 case 3: return 24;
287 case 2: return 16;
288 case 1: return 48;
289 default: return 32;
290 }
291}
292
293/* Write Bit-Clock of I2S (in multiples of LRCLK) */
294static inline void set_bfs(struct i2s_dai *i2s, unsigned bfs)
295{
296 u32 mod = readl(i2s->addr + I2SMOD);
4ca0c0d4 297 int tdm = i2s->quirks & QUIRK_SUPPORTS_TDM;
a5a56871 298 int bfs_shift = i2s->variant_regs->bfs_off;
4ca0c0d4
PV		 299
300 /* Non-TDM I2S controllers do not support BCLK > 48 * FS */
301 if (!tdm && bfs > 48) {
302 dev_err(&i2s->pdev->dev, "Unsupported BCLK divider\n");
303 return;
304 }
1c7ac018 305
a5a56871
PV		 306 mod &= ~(i2s->variant_regs->bfs_mask << bfs_shift);
307
1c7ac018
JB		 308 switch (bfs) {
309 case 48:
b60be4aa 310 mod |= (MOD_BCLK_48FS << bfs_shift);
1c7ac018
JB		 311 break;
312 case 32:
b60be4aa 313 mod |= (MOD_BCLK_32FS << bfs_shift);
1c7ac018
JB		 314 break;
315 case 24:
b60be4aa 316 mod |= (MOD_BCLK_24FS << bfs_shift);
1c7ac018
JB		 317 break;
318 case 16:
b60be4aa 319 mod |= (MOD_BCLK_16FS << bfs_shift);
1c7ac018 320 break;
4ca0c0d4
PV		 321 case 64:
322 mod |= (EXYNOS5420_MOD_BCLK_64FS << bfs_shift);
323 break;
324 case 96:
325 mod |= (EXYNOS5420_MOD_BCLK_96FS << bfs_shift);
326 break;
327 case 128:
328 mod |= (EXYNOS5420_MOD_BCLK_128FS << bfs_shift);
329 break;
330 case 192:
331 mod |= (EXYNOS5420_MOD_BCLK_192FS << bfs_shift);
332 break;
333 case 256:
334 mod |= (EXYNOS5420_MOD_BCLK_256FS << bfs_shift);
1c7ac018
JB		 335 break;
336 default:
337 dev_err(&i2s->pdev->dev, "Wrong BCLK Divider!\n");
338 return;
339 }
340
341 writel(mod, i2s->addr + I2SMOD);
342}
343
344/* Sample-Size */
345static inline int get_blc(struct i2s_dai *i2s)
346{
347 int blc = readl(i2s->addr + I2SMOD);
348
349 blc = (blc >> 13) & 0x3;
350
351 switch (blc) {
352 case 2: return 24;
353 case 1: return 8;
354 default: return 16;
355 }
356}
357
358/* TX Channel Control */
359static void i2s_txctrl(struct i2s_dai *i2s, int on)
360{
361 void __iomem *addr = i2s->addr;
a5a56871 362 int txr_off = i2s->variant_regs->txr_off;
1c7ac018 363 u32 con = readl(addr + I2SCON);
a5a56871 364 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
1c7ac018
JB		 365
366 if (on) {
367 con |= CON_ACTIVE;
368 con &= ~CON_TXCH_PAUSE;
369
370 if (is_secondary(i2s)) {
371 con |= CON_TXSDMA_ACTIVE;
372 con &= ~CON_TXSDMA_PAUSE;
373 } else {
374 con |= CON_TXDMA_ACTIVE;
375 con &= ~CON_TXDMA_PAUSE;
376 }
377
378 if (any_rx_active(i2s))
a5a56871 379 mod |= 2 << txr_off;
1c7ac018 380 else
a5a56871 381 mod |= 0 << txr_off;
1c7ac018
JB		 382 } else {
383 if (is_secondary(i2s)) {
384 con |= CON_TXSDMA_PAUSE;
385 con &= ~CON_TXSDMA_ACTIVE;
386 } else {
387 con |= CON_TXDMA_PAUSE;
388 con &= ~CON_TXDMA_ACTIVE;
389 }
390
391 if (other_tx_active(i2s)) {
392 writel(con, addr + I2SCON);
393 return;
394 }
395
396 con |= CON_TXCH_PAUSE;
397
398 if (any_rx_active(i2s))
a5a56871 399 mod |= 1 << txr_off;
1c7ac018
JB		 400 else
401 con &= ~CON_ACTIVE;
402 }
403
404 writel(mod, addr + I2SMOD);
405 writel(con, addr + I2SCON);
406}
407
408/* RX Channel Control */
409static void i2s_rxctrl(struct i2s_dai *i2s, int on)
410{
411 void __iomem *addr = i2s->addr;
a5a56871 412 int txr_off = i2s->variant_regs->txr_off;
1c7ac018 413 u32 con = readl(addr + I2SCON);
a5a56871 414 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
1c7ac018
JB		 415
416 if (on) {
417 con |= CON_RXDMA_ACTIVE | CON_ACTIVE;
418 con &= ~(CON_RXDMA_PAUSE | CON_RXCH_PAUSE);
419
420 if (any_tx_active(i2s))
a5a56871 421 mod |= 2 << txr_off;
1c7ac018 422 else
a5a56871 423 mod |= 1 << txr_off;
1c7ac018
JB		 424 } else {
425 con |= CON_RXDMA_PAUSE | CON_RXCH_PAUSE;
426 con &= ~CON_RXDMA_ACTIVE;
427
428 if (any_tx_active(i2s))
a5a56871 429 mod |= 0 << txr_off;
1c7ac018
JB		 430 else
431 con &= ~CON_ACTIVE;
432 }
433
434 writel(mod, addr + I2SMOD);
435 writel(con, addr + I2SCON);
436}
437
438/* Flush FIFO of an interface */
439static inline void i2s_fifo(struct i2s_dai *i2s, u32 flush)
440{
441 void __iomem *fic;
442 u32 val;
443
444 if (!i2s)
445 return;
446
447 if (is_secondary(i2s))
448 fic = i2s->addr + I2SFICS;
449 else
450 fic = i2s->addr + I2SFIC;
451
452 /* Flush the FIFO */
453 writel(readl(fic) | flush, fic);
454
455 /* Be patient */
456 val = msecs_to_loops(1) / 1000; /* 1 usec */
457 while (--val)
458 cpu_relax();
459
460 writel(readl(fic) & ~flush, fic);
461}
462
463static int i2s_set_sysclk(struct snd_soc_dai *dai,
464 int clk_id, unsigned int rfs, int dir)
465{
466 struct i2s_dai *i2s = to_info(dai);
467 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
468 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871
PV		 469 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
470 unsigned int cdcon_mask = 1 << i2s_regs->cdclkcon_off;
471 unsigned int rsrc_mask = 1 << i2s_regs->rclksrc_off;
1c7ac018
JB		 472
473 switch (clk_id) {
c86d50f9
SN		 474 case SAMSUNG_I2S_OPCLK:
475 mod &= ~MOD_OPCLK_MASK;
476 mod |= dir;
477 break;
1c7ac018
JB		 478 case SAMSUNG_I2S_CDCLK:
479 /* Shouldn't matter in GATING(CLOCK_IN) mode */
480 if (dir == SND_SOC_CLOCK_IN)
481 rfs = 0;
482
133c2681 483 if ((rfs && other && other->rfs && (other->rfs != rfs)) ||
1c7ac018
JB		 484 (any_active(i2s) &&
485 (((dir == SND_SOC_CLOCK_IN)
a5a56871 486 && !(mod & cdcon_mask)) ||
1c7ac018 487 ((dir == SND_SOC_CLOCK_OUT)
a5a56871 488 && (mod & cdcon_mask))))) {
1c7ac018
JB		 489 dev_err(&i2s->pdev->dev,
490 "%s:%d Other DAI busy\n", __func__, __LINE__);
491 return -EAGAIN;
492 }
493
494 if (dir == SND_SOC_CLOCK_IN)
a5a56871 495 mod |= 1 << i2s_regs->cdclkcon_off;
1c7ac018 496 else
b2de1d20 497 mod &= ~(1 << i2s_regs->cdclkcon_off);
1c7ac018
JB		 498
499 i2s->rfs = rfs;
500 break;
501
502 case SAMSUNG_I2S_RCLKSRC_0: /* clock corrsponding to IISMOD[10] := 0 */
503 case SAMSUNG_I2S_RCLKSRC_1: /* clock corrsponding to IISMOD[10] := 1 */
504 if ((i2s->quirks & QUIRK_NO_MUXPSR)
505 || (clk_id == SAMSUNG_I2S_RCLKSRC_0))
506 clk_id = 0;
507 else
508 clk_id = 1;
509
510 if (!any_active(i2s)) {
a6aba536 511 if (i2s->op_clk && !IS_ERR(i2s->op_clk)) {
a5a56871
PV		 512 if ((clk_id && !(mod & rsrc_mask)) ||
513 (!clk_id && (mod & rsrc_mask))) {
98614cf6 514 clk_disable_unprepare(i2s->op_clk);
1c7ac018
JB		 515 clk_put(i2s->op_clk);
516 } else {
6ce534aa
JB		 517 i2s->rclk_srcrate =
518 clk_get_rate(i2s->op_clk);
1c7ac018
JB		 519 return 0;
520 }
521 }
522
1974a042
PV		 523 if (clk_id)
524 i2s->op_clk = clk_get(&i2s->pdev->dev,
525 "i2s_opclk1");
526 else
527 i2s->op_clk = clk_get(&i2s->pdev->dev,
528 "i2s_opclk0");
a6aba536
SN		 529
530 if (WARN_ON(IS_ERR(i2s->op_clk)))
531 return PTR_ERR(i2s->op_clk);
532
98614cf6 533 clk_prepare_enable(i2s->op_clk);
1c7ac018
JB		 534 i2s->rclk_srcrate = clk_get_rate(i2s->op_clk);
535
536 /* Over-ride the other's */
537 if (other) {
538 other->op_clk = i2s->op_clk;
539 other->rclk_srcrate = i2s->rclk_srcrate;
540 }
a5a56871
PV		 541 } else if ((!clk_id && (mod & rsrc_mask))
542 || (clk_id && !(mod & rsrc_mask))) {
1c7ac018
JB		 543 dev_err(&i2s->pdev->dev,
544 "%s:%d Other DAI busy\n", __func__, __LINE__);
545 return -EAGAIN;
546 } else {
547 /* Call can't be on the active DAI */
548 i2s->op_clk = other->op_clk;
549 i2s->rclk_srcrate = other->rclk_srcrate;
550 return 0;
551 }
552
553 if (clk_id == 0)
b2de1d20 554 mod &= ~(1 << i2s_regs->rclksrc_off);
1c7ac018 555 else
a5a56871 556 mod |= 1 << i2s_regs->rclksrc_off;
1c7ac018 557
b2de1d20 558 break;
1c7ac018
JB		 559 default:
560 dev_err(&i2s->pdev->dev, "We don't serve that!\n");
561 return -EINVAL;
562 }
563
564 writel(mod, i2s->addr + I2SMOD);
565
566 return 0;
567}
568
569static int i2s_set_fmt(struct snd_soc_dai *dai,
570 unsigned int fmt)
571{
572 struct i2s_dai *i2s = to_info(dai);
573 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871 574 int lrp_shift, sdf_shift, sdf_mask, lrp_rlow, mod_slave;
1c7ac018
JB		 575 u32 tmp = 0;
576
a5a56871
PV		 577 lrp_shift = i2s->variant_regs->lrp_off;
578 sdf_shift = i2s->variant_regs->sdf_off;
579 mod_slave = 1 << i2s->variant_regs->mss_off;
4ca0c0d4 580
b60be4aa
PV		 581 sdf_mask = MOD_SDF_MASK << sdf_shift;
582 lrp_rlow = MOD_LR_RLOW << lrp_shift;
583
1c7ac018
JB		 584 /* Format is priority */
585 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
586 case SND_SOC_DAIFMT_RIGHT_J:
b60be4aa
PV		 587 tmp |= lrp_rlow;
588 tmp |= (MOD_SDF_MSB << sdf_shift);
1c7ac018
JB		 589 break;
590 case SND_SOC_DAIFMT_LEFT_J:
b60be4aa
PV		 591 tmp |= lrp_rlow;
592 tmp |= (MOD_SDF_LSB << sdf_shift);
1c7ac018
JB		 593 break;
594 case SND_SOC_DAIFMT_I2S:
b60be4aa 595 tmp |= (MOD_SDF_IIS << sdf_shift);
1c7ac018
JB		 596 break;
597 default:
598 dev_err(&i2s->pdev->dev, "Format not supported\n");
599 return -EINVAL;
600 }
601
602 /*
603 * INV flag is relative to the FORMAT flag - if set it simply
604 * flips the polarity specified by the Standard
605 */
606 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
607 case SND_SOC_DAIFMT_NB_NF:
608 break;
609 case SND_SOC_DAIFMT_NB_IF:
b60be4aa
PV		 610 if (tmp & lrp_rlow)
611 tmp &= ~lrp_rlow;
1c7ac018 612 else
b60be4aa 613 tmp |= lrp_rlow;
1c7ac018
JB		 614 break;
615 default:
616 dev_err(&i2s->pdev->dev, "Polarity not supported\n");
617 return -EINVAL;
618 }
619
620 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
621 case SND_SOC_DAIFMT_CBM_CFM:
a5a56871 622 tmp |= mod_slave;
1c7ac018
JB		 623 break;
624 case SND_SOC_DAIFMT_CBS_CFS:
625 /* Set default source clock in Master mode */
626 if (i2s->rclk_srcrate == 0)
627 i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0,
628 0, SND_SOC_CLOCK_IN);
629 break;
630 default:
631 dev_err(&i2s->pdev->dev, "master/slave format not supported\n");
632 return -EINVAL;
633 }
634
b60be4aa
PV		 635 /*
636 * Don't change the I2S mode if any controller is active on this
637 * channel.
638 */
1c7ac018 639 if (any_active(i2s) &&
a5a56871 640 ((mod & (sdf_mask | lrp_rlow | mod_slave)) != tmp)) {
1c7ac018
JB		 641 dev_err(&i2s->pdev->dev,
642 "%s:%d Other DAI busy\n", __func__, __LINE__);
643 return -EAGAIN;
644 }
645
a5a56871 646 mod &= ~(sdf_mask | lrp_rlow | mod_slave);
1c7ac018
JB		 647 mod |= tmp;
648 writel(mod, i2s->addr + I2SMOD);
649
650 return 0;
651}
652
653static int i2s_hw_params(struct snd_pcm_substream *substream,
654 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
655{
656 struct i2s_dai *i2s = to_info(dai);
657 u32 mod = readl(i2s->addr + I2SMOD);
658
659 if (!is_secondary(i2s))
660 mod &= ~(MOD_DC2_EN | MOD_DC1_EN);
661
662 switch (params_channels(params)) {
663 case 6:
664 mod |= MOD_DC2_EN;
665 case 4:
666 mod |= MOD_DC1_EN;
667 break;
668 case 2:
588fb705
SP		 669 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
670 i2s->dma_playback.dma_size = 4;
671 else
672 i2s->dma_capture.dma_size = 4;
673 break;
674 case 1:
675 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
676 i2s->dma_playback.dma_size = 2;
677 else
678 i2s->dma_capture.dma_size = 2;
679
1c7ac018
JB		 680 break;
681 default:
682 dev_err(&i2s->pdev->dev, "%d channels not supported\n",
683 params_channels(params));
684 return -EINVAL;
685 }
686
687 if (is_secondary(i2s))
688 mod &= ~MOD_BLCS_MASK;
689 else
690 mod &= ~MOD_BLCP_MASK;
691
692 if (is_manager(i2s))
693 mod &= ~MOD_BLC_MASK;
694
88ce1465
TB		 695 switch (params_width(params)) {
696 case 8:
1c7ac018
JB		 697 if (is_secondary(i2s))
698 mod |= MOD_BLCS_8BIT;
699 else
700 mod |= MOD_BLCP_8BIT;
701 if (is_manager(i2s))
702 mod |= MOD_BLC_8BIT;
703 break;
88ce1465 704 case 16:
1c7ac018
JB		 705 if (is_secondary(i2s))
706 mod |= MOD_BLCS_16BIT;
707 else
708 mod |= MOD_BLCP_16BIT;
709 if (is_manager(i2s))
710 mod |= MOD_BLC_16BIT;
711 break;
88ce1465 712 case 24:
1c7ac018
JB		 713 if (is_secondary(i2s))
714 mod |= MOD_BLCS_24BIT;
715 else
716 mod |= MOD_BLCP_24BIT;
717 if (is_manager(i2s))
718 mod |= MOD_BLC_24BIT;
719 break;
720 default:
721 dev_err(&i2s->pdev->dev, "Format(%d) not supported\n",
722 params_format(params));
723 return -EINVAL;
724 }
725 writel(mod, i2s->addr + I2SMOD);
726
d37bdf73
MB		 727 samsung_asoc_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture);
728
1c7ac018
JB		 729 i2s->frmclk = params_rate(params);
730
731 return 0;
732}
733
734/* We set constraints on the substream acc to the version of I2S */
735static int i2s_startup(struct snd_pcm_substream *substream,
736 struct snd_soc_dai *dai)
737{
738 struct i2s_dai *i2s = to_info(dai);
739 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
740 unsigned long flags;
741
742 spin_lock_irqsave(&lock, flags);
743
744 i2s->mode |= DAI_OPENED;
745
746 if (is_manager(other))
747 i2s->mode &= ~DAI_MANAGER;
748 else
749 i2s->mode |= DAI_MANAGER;
750
2d77828d
PV		 751 if (!any_active(i2s) && (i2s->quirks & QUIRK_NEED_RSTCLR))
752 writel(CON_RSTCLR, i2s->addr + I2SCON);
753
1c7ac018
JB		 754 spin_unlock_irqrestore(&lock, flags);
755
b97c60ab
SN		 756 if (!is_opened(other) && i2s->cdclk_out)
757 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
758 0, SND_SOC_CLOCK_OUT);
1c7ac018
JB		 759 return 0;
760}
761
762static void i2s_shutdown(struct snd_pcm_substream *substream,
763 struct snd_soc_dai *dai)
764{
765 struct i2s_dai *i2s = to_info(dai);
766 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
767 unsigned long flags;
a5a56871 768 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
1c7ac018
JB		 769
770 spin_lock_irqsave(&lock, flags);
771
772 i2s->mode &= ~DAI_OPENED;
773 i2s->mode &= ~DAI_MANAGER;
774
b97c60ab 775 if (is_opened(other)) {
1c7ac018 776 other->mode |= DAI_MANAGER;
b97c60ab
SN		 777 } else {
778 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871 779 i2s->cdclk_out = !(mod & (1 << i2s_regs->cdclkcon_off));
133c2681
CK		 780 if (other)
781 other->cdclk_out = i2s->cdclk_out;
b97c60ab 782 }
1c7ac018
JB		 783 /* Reset any constraint on RFS and BFS */
784 i2s->rfs = 0;
785 i2s->bfs = 0;
786
787 spin_unlock_irqrestore(&lock, flags);
788
789 /* Gate CDCLK by default */
790 if (!is_opened(other))
791 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
792 0, SND_SOC_CLOCK_IN);
793}
794
795static int config_setup(struct i2s_dai *i2s)
796{
797 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
798 unsigned rfs, bfs, blc;
799 u32 psr;
800
801 blc = get_blc(i2s);
802
803 bfs = i2s->bfs;
804
805 if (!bfs && other)
806 bfs = other->bfs;
807
808 /* Select least possible multiple(2) if no constraint set */
809 if (!bfs)
810 bfs = blc * 2;
811
812 rfs = i2s->rfs;
813
814 if (!rfs && other)
815 rfs = other->rfs;
816
817 if ((rfs == 256 || rfs == 512) && (blc == 24)) {
818 dev_err(&i2s->pdev->dev,
819 "%d-RFS not supported for 24-blc\n", rfs);
820 return -EINVAL;
821 }
822
823 if (!rfs) {
824 if (bfs == 16 || bfs == 32)
825 rfs = 256;
826 else
827 rfs = 384;
828 }
829
830 /* If already setup and running */
831 if (any_active(i2s) && (get_rfs(i2s) != rfs || get_bfs(i2s) != bfs)) {
832 dev_err(&i2s->pdev->dev,
833 "%s:%d Other DAI busy\n", __func__, __LINE__);
834 return -EAGAIN;
835 }
836
1c7ac018
JB		 837 set_bfs(i2s, bfs);
838 set_rfs(i2s, rfs);
839
77010010
PV		 840 /* Don't bother with PSR in Slave mode */
841 if (is_slave(i2s))
842 return 0;
843
1c7ac018
JB		 844 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) {
845 psr = i2s->rclk_srcrate / i2s->frmclk / rfs;
846 writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR);
847 dev_dbg(&i2s->pdev->dev,
848 "RCLK_SRC=%luHz PSR=%u, RCLK=%dfs, BCLK=%dfs\n",
849 i2s->rclk_srcrate, psr, rfs, bfs);
850 }
851
852 return 0;
853}
854
855static int i2s_trigger(struct snd_pcm_substream *substream,
856 int cmd, struct snd_soc_dai *dai)
857{
858 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
859 struct snd_soc_pcm_runtime *rtd = substream->private_data;
860 struct i2s_dai *i2s = to_info(rtd->cpu_dai);
861 unsigned long flags;
862
863 switch (cmd) {
864 case SNDRV_PCM_TRIGGER_START:
865 case SNDRV_PCM_TRIGGER_RESUME:
866 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
867 local_irq_save(flags);
868
1c7ac018
JB		 869 if (config_setup(i2s)) {
870 local_irq_restore(flags);
871 return -EINVAL;
872 }
873
874 if (capture)
875 i2s_rxctrl(i2s, 1);
876 else
877 i2s_txctrl(i2s, 1);
878
879 local_irq_restore(flags);
880 break;
881 case SNDRV_PCM_TRIGGER_STOP:
882 case SNDRV_PCM_TRIGGER_SUSPEND:
883 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
884 local_irq_save(flags);
885
c90887fe 886 if (capture) {
1c7ac018 887 i2s_rxctrl(i2s, 0);
775bc971 888 i2s_fifo(i2s, FIC_RXFLUSH);
c90887fe
JB		 889 } else {
890 i2s_txctrl(i2s, 0);
775bc971 891 i2s_fifo(i2s, FIC_TXFLUSH);
c90887fe 892 }
775bc971 893
1c7ac018
JB		 894 local_irq_restore(flags);
895 break;
896 }
897
898 return 0;
899}
900
901static int i2s_set_clkdiv(struct snd_soc_dai *dai,
902 int div_id, int div)
903{
904 struct i2s_dai *i2s = to_info(dai);
905 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
906
907 switch (div_id) {
908 case SAMSUNG_I2S_DIV_BCLK:
909 if ((any_active(i2s) && div && (get_bfs(i2s) != div))
910 || (other && other->bfs && (other->bfs != div))) {
911 dev_err(&i2s->pdev->dev,
912 "%s:%d Other DAI busy\n", __func__, __LINE__);
913 return -EAGAIN;
914 }
915 i2s->bfs = div;
916 break;
917 default:
918 dev_err(&i2s->pdev->dev,
919 "Invalid clock divider(%d)\n", div_id);
920 return -EINVAL;
921 }
922
923 return 0;
924}
925
926static snd_pcm_sframes_t
927i2s_delay(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
928{
929 struct i2s_dai *i2s = to_info(dai);
930 u32 reg = readl(i2s->addr + I2SFIC);
931 snd_pcm_sframes_t delay;
a5a56871 932 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
1c7ac018
JB		 933
934 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
935 delay = FIC_RXCOUNT(reg);
936 else if (is_secondary(i2s))
937 delay = FICS_TXCOUNT(readl(i2s->addr + I2SFICS));
938 else
a5a56871 939 delay = (reg >> i2s_regs->ftx0cnt_off) & 0x7f;
1c7ac018
JB		 940
941 return delay;
942}
943
944#ifdef CONFIG_PM
945static int i2s_suspend(struct snd_soc_dai *dai)
946{
947 struct i2s_dai *i2s = to_info(dai);
948
d3d4e524
SN		 949 i2s->suspend_i2smod = readl(i2s->addr + I2SMOD);
950 i2s->suspend_i2scon = readl(i2s->addr + I2SCON);
951 i2s->suspend_i2spsr = readl(i2s->addr + I2SPSR);
1c7ac018
JB		 952
953 return 0;
954}
955
956static int i2s_resume(struct snd_soc_dai *dai)
957{
958 struct i2s_dai *i2s = to_info(dai);
959
d3d4e524
SN		 960 writel(i2s->suspend_i2scon, i2s->addr + I2SCON);
961 writel(i2s->suspend_i2smod, i2s->addr + I2SMOD);
962 writel(i2s->suspend_i2spsr, i2s->addr + I2SPSR);
1c7ac018
JB		 963
964 return 0;
965}
966#else
967#define i2s_suspend NULL
968#define i2s_resume NULL
969#endif
970
971static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
972{
973 struct i2s_dai *i2s = to_info(dai);
974 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
ba56447c 975 int ret;
1c7ac018 976
3688569e
MB		 977 if (other && other->clk) { /* If this is probe on secondary */
978 samsung_asoc_init_dma_data(dai, &other->sec_dai->dma_playback,
979 NULL);
1c7ac018 980 goto probe_exit;
3688569e 981 }
1c7ac018
JB		 982
983 i2s->addr = ioremap(i2s->base, 0x100);
984 if (i2s->addr == NULL) {
985 dev_err(&i2s->pdev->dev, "cannot ioremap registers\n");
986 return -ENXIO;
987 }
988
989 i2s->clk = clk_get(&i2s->pdev->dev, "iis");
990 if (IS_ERR(i2s->clk)) {
991 dev_err(&i2s->pdev->dev, "failed to get i2s_clock\n");
992 iounmap(i2s->addr);
ba56447c
MB		 993 return PTR_ERR(i2s->clk);
994 }
995
996 ret = clk_prepare_enable(i2s->clk);
997 if (ret != 0) {
998 dev_err(&i2s->pdev->dev, "failed to enable clock: %d\n", ret);
999 return ret;
1c7ac018 1000 }
1c7ac018 1001
3688569e 1002 samsung_asoc_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture);
511e3033 1003
1c7ac018
JB		 1004 if (other) {
1005 other->addr = i2s->addr;
1006 other->clk = i2s->clk;
1007 }
1008
1009 if (i2s->quirks & QUIRK_NEED_RSTCLR)
1010 writel(CON_RSTCLR, i2s->addr + I2SCON);
1011
b0759736 1012 if (i2s->quirks & QUIRK_SUPPORTS_IDMA)
9b8f5695 1013 idma_reg_addr_init(i2s->addr,
61100f40
SK		 1014 i2s->sec_dai->idma_playback.dma_addr);
1015
1c7ac018
JB		 1016probe_exit:
1017 /* Reset any constraint on RFS and BFS */
1018 i2s->rfs = 0;
1019 i2s->bfs = 0;
d66eac3e 1020 i2s->rclk_srcrate = 0;
1c7ac018
JB		 1021 i2s_txctrl(i2s, 0);
1022 i2s_rxctrl(i2s, 0);
1023 i2s_fifo(i2s, FIC_TXFLUSH);
1024 i2s_fifo(other, FIC_TXFLUSH);
1025 i2s_fifo(i2s, FIC_RXFLUSH);
1026
1027 /* Gate CDCLK by default */
1028 if (!is_opened(other))
1029 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
1030 0, SND_SOC_CLOCK_IN);
1031
1032 return 0;
1033}
1034
1035static int samsung_i2s_dai_remove(struct snd_soc_dai *dai)
1036{
1037 struct i2s_dai *i2s = snd_soc_dai_get_drvdata(dai);
1038 struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
1039
1040 if (!other || !other->clk) {
1041
1042 if (i2s->quirks & QUIRK_NEED_RSTCLR)
1043 writel(0, i2s->addr + I2SCON);
1044
98614cf6 1045 clk_disable_unprepare(i2s->clk);
1c7ac018
JB		 1046 clk_put(i2s->clk);
1047
1048 iounmap(i2s->addr);
1049 }
1050
1051 i2s->clk = NULL;
1052
1053 return 0;
1054}
1055
85e7652d 1056static const struct snd_soc_dai_ops samsung_i2s_dai_ops = {
1c7ac018
JB		 1057 .trigger = i2s_trigger,
1058 .hw_params = i2s_hw_params,
1059 .set_fmt = i2s_set_fmt,
1060 .set_clkdiv = i2s_set_clkdiv,
1061 .set_sysclk = i2s_set_sysclk,
1062 .startup = i2s_startup,
1063 .shutdown = i2s_shutdown,
1064 .delay = i2s_delay,
1065};
1066
4b828535
KM		 1067static const struct snd_soc_component_driver samsung_i2s_component = {
1068 .name = "samsung-i2s",
1069};
1070
1c7ac018
JB		 1071#define SAMSUNG_I2S_RATES SNDRV_PCM_RATE_8000_96000
1072
1073#define SAMSUNG_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1074 SNDRV_PCM_FMTBIT_S16_LE | \
1075 SNDRV_PCM_FMTBIT_S24_LE)
1076
fdca21ad 1077static struct i2s_dai *i2s_alloc_dai(struct platform_device *pdev, bool sec)
1c7ac018
JB		 1078{
1079 struct i2s_dai *i2s;
c6f9b1eb 1080 int ret;
1c7ac018 1081
b960ce74 1082 i2s = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dai), GFP_KERNEL);
1c7ac018
JB		 1083 if (i2s == NULL)
1084 return NULL;
1085
1086 i2s->pdev = pdev;
1087 i2s->pri_dai = NULL;
1088 i2s->sec_dai = NULL;
1089 i2s->i2s_dai_drv.symmetric_rates = 1;
1090 i2s->i2s_dai_drv.probe = samsung_i2s_dai_probe;
1091 i2s->i2s_dai_drv.remove = samsung_i2s_dai_remove;
1092 i2s->i2s_dai_drv.ops = &samsung_i2s_dai_ops;
1093 i2s->i2s_dai_drv.suspend = i2s_suspend;
1094 i2s->i2s_dai_drv.resume = i2s_resume;
a0ff6ea2 1095 i2s->i2s_dai_drv.playback.channels_min = 1;
1c7ac018
JB		 1096 i2s->i2s_dai_drv.playback.channels_max = 2;
1097 i2s->i2s_dai_drv.playback.rates = SAMSUNG_I2S_RATES;
1098 i2s->i2s_dai_drv.playback.formats = SAMSUNG_I2S_FMTS;
1099
1100 if (!sec) {
588fb705 1101 i2s->i2s_dai_drv.capture.channels_min = 1;
1c7ac018
JB		 1102 i2s->i2s_dai_drv.capture.channels_max = 2;
1103 i2s->i2s_dai_drv.capture.rates = SAMSUNG_I2S_RATES;
1104 i2s->i2s_dai_drv.capture.formats = SAMSUNG_I2S_FMTS;
c6f9b1eb 1105 dev_set_drvdata(&i2s->pdev->dev, i2s);
1c7ac018 1106 } else { /* Create a new platform_device for Secondary */
c6f9b1eb 1107 i2s->pdev = platform_device_alloc("samsung-i2s-sec", -1);
29ca9c73 1108 if (!i2s->pdev)
1c7ac018 1109 return NULL;
1c7ac018 1110
2f6f0ffb
MB		 1111 i2s->pdev->dev.parent = &pdev->dev;
1112
c6f9b1eb
P		 1113 platform_set_drvdata(i2s->pdev, i2s);
1114 ret = platform_device_add(i2s->pdev);
1115 if (ret < 0)
1116 return NULL;
1117 }
1c7ac018
JB		 1118
1119 return i2s;
1120}
1121
40476f61
PV		 1122static const struct of_device_id exynos_i2s_match[];
1123
7da493e9
PV		 1124static inline const struct samsung_i2s_dai_data *samsung_i2s_get_driver_data(
1125 struct platform_device *pdev)
7c62eebb 1126{
40476f61 1127#ifdef CONFIG_OF
40476f61
PV		 1128 if (pdev->dev.of_node) {
1129 const struct of_device_id *match;
1130 match = of_match_node(exynos_i2s_match, pdev->dev.of_node);
7da493e9 1131 return match->data;
40476f61
PV		 1132 } else
1133#endif
7da493e9
PV		 1134 return (struct samsung_i2s_dai_data *)
1135 platform_get_device_id(pdev)->driver_data;
7c62eebb
PV		 1136}
1137
5b1d3c34
C		 1138#ifdef CONFIG_PM_RUNTIME
1139static int i2s_runtime_suspend(struct device *dev)
1140{
1141 struct i2s_dai *i2s = dev_get_drvdata(dev);
1142
1143 clk_disable_unprepare(i2s->clk);
1144
1145 return 0;
1146}
1147
1148static int i2s_runtime_resume(struct device *dev)
1149{
1150 struct i2s_dai *i2s = dev_get_drvdata(dev);
1151
1152 clk_prepare_enable(i2s->clk);
1153
1154 return 0;
1155}
1156#endif /* CONFIG_PM_RUNTIME */
1157
fdca21ad 1158static int samsung_i2s_probe(struct platform_device *pdev)
1c7ac018 1159{
1c7ac018 1160 struct i2s_dai *pri_dai, *sec_dai = NULL;
40476f61
PV		 1161 struct s3c_audio_pdata *i2s_pdata = pdev->dev.platform_data;
1162 struct samsung_i2s *i2s_cfg = NULL;
1c7ac018 1163 struct resource *res;
40476f61
PV		 1164 u32 regs_base, quirks = 0, idma_addr = 0;
1165 struct device_node *np = pdev->dev.of_node;
7da493e9 1166 const struct samsung_i2s_dai_data *i2s_dai_data;
1c7ac018
JB		 1167 int ret = 0;
1168
1169 /* Call during Seconday interface registration */
7da493e9 1170 i2s_dai_data = samsung_i2s_get_driver_data(pdev);
7c62eebb 1171
7da493e9 1172 if (i2s_dai_data->dai_type == TYPE_SEC) {
1c7ac018 1173 sec_dai = dev_get_drvdata(&pdev->dev);
a9b977ec
P		 1174 if (!sec_dai) {
1175 dev_err(&pdev->dev, "Unable to get drvdata\n");
1176 return -EFAULT;
1177 }
d644a115
MB		 1178 devm_snd_soc_register_component(&sec_dai->pdev->dev,
1179 &samsung_i2s_component,
1180 &sec_dai->i2s_dai_drv, 1);
85ff3c29 1181 samsung_asoc_dma_platform_register(&pdev->dev);
1c7ac018
JB		 1182 return 0;
1183 }
1184
40476f61
PV		 1185 pri_dai = i2s_alloc_dai(pdev, false);
1186 if (!pri_dai) {
1187 dev_err(&pdev->dev, "Unable to alloc I2S_pri\n");
1188 return -ENOMEM;
1c7ac018
JB		 1189 }
1190
40476f61
PV		 1191 if (!np) {
1192 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1193 if (!res) {
1194 dev_err(&pdev->dev,
1195 "Unable to get I2S-TX dma resource\n");
1196 return -ENXIO;
1197 }
1198 pri_dai->dma_playback.channel = res->start;
1c7ac018 1199
40476f61
PV		 1200 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1201 if (!res) {
1202 dev_err(&pdev->dev,
1203 "Unable to get I2S-RX dma resource\n");
1204 return -ENXIO;
1205 }
1206 pri_dai->dma_capture.channel = res->start;
1c7ac018 1207
40476f61
PV		 1208 if (i2s_pdata == NULL) {
1209 dev_err(&pdev->dev, "Can't work without s3c_audio_pdata\n");
1210 return -EINVAL;
1211 }
1212
1213 if (&i2s_pdata->type)
1214 i2s_cfg = &i2s_pdata->type.i2s;
1215
1216 if (i2s_cfg) {
1217 quirks = i2s_cfg->quirks;
1218 idma_addr = i2s_cfg->idma_addr;
1219 }
1220 } else {
7da493e9 1221 quirks = i2s_dai_data->quirks;
40476f61
PV		 1222 if (of_property_read_u32(np, "samsung,idma-addr",
1223 &idma_addr)) {
b0759736
PV		 1224 if (quirks & QUIRK_SUPPORTS_IDMA) {
1225 dev_info(&pdev->dev, "idma address is not"\
40476f61 1226 "specified");
40476f61
PV		 1227 }
1228 }
1229 }
1c7ac018
JB		 1230
1231 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1232 if (!res) {
1233 dev_err(&pdev->dev, "Unable to get I2S SFR address\n");
1234 return -ENXIO;
1235 }
1236
1237 if (!request_mem_region(res->start, resource_size(res),
1238 "samsung-i2s")) {
1239 dev_err(&pdev->dev, "Unable to request SFR region\n");
1240 return -EBUSY;
1241 }
1242 regs_base = res->start;
1243
1c7ac018
JB		 1244 pri_dai->dma_playback.dma_addr = regs_base + I2STXD;
1245 pri_dai->dma_capture.dma_addr = regs_base + I2SRXD;
40476f61 1246 pri_dai->dma_playback.ch_name = "tx";
40476f61 1247 pri_dai->dma_capture.ch_name = "rx";
1c7ac018
JB		 1248 pri_dai->dma_playback.dma_size = 4;
1249 pri_dai->dma_capture.dma_size = 4;
1250 pri_dai->base = regs_base;
1251 pri_dai->quirks = quirks;
a5a56871 1252 pri_dai->variant_regs = i2s_dai_data->i2s_variant_regs;
1c7ac018
JB		 1253
1254 if (quirks & QUIRK_PRI_6CHAN)
1255 pri_dai->i2s_dai_drv.playback.channels_max = 6;
1256
1257 if (quirks & QUIRK_SEC_DAI) {
1258 sec_dai = i2s_alloc_dai(pdev, true);
1259 if (!sec_dai) {
1260 dev_err(&pdev->dev, "Unable to alloc I2S_sec\n");
1261 ret = -ENOMEM;
b960ce74 1262 goto err;
1c7ac018
JB		 1263 }
1264 sec_dai->dma_playback.dma_addr = regs_base + I2STXDS;
40476f61
PV		 1265 sec_dai->dma_playback.ch_name = "tx-sec";
1266
1267 if (!np) {
1268 res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
1269 if (res)
1270 sec_dai->dma_playback.channel = res->start;
1271 }
1272
1c7ac018
JB		 1273 sec_dai->dma_playback.dma_size = 4;
1274 sec_dai->base = regs_base;
1275 sec_dai->quirks = quirks;
40476f61 1276 sec_dai->idma_playback.dma_addr = idma_addr;
1c7ac018
JB		 1277 sec_dai->pri_dai = pri_dai;
1278 pri_dai->sec_dai = sec_dai;
1279 }
1280
0429ffef
MB		 1281 if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
1282 dev_err(&pdev->dev, "Unable to configure gpio\n");
1283 ret = -EINVAL;
1284 goto err;
1c7ac018
JB		 1285 }
1286
d644a115
MB		 1287 devm_snd_soc_register_component(&pri_dai->pdev->dev,
1288 &samsung_i2s_component,
1289 &pri_dai->i2s_dai_drv, 1);
1c7ac018 1290
c5cf4dbc
MB		 1291 pm_runtime_enable(&pdev->dev);
1292
85ff3c29 1293 samsung_asoc_dma_platform_register(&pdev->dev);
a08485d8 1294
1c7ac018 1295 return 0;
b960ce74 1296err:
57e33781
SK		 1297 if (res)
1298 release_mem_region(regs_base, resource_size(res));
1c7ac018
JB		 1299
1300 return ret;
1301}
1302
fdca21ad 1303static int samsung_i2s_remove(struct platform_device *pdev)
1c7ac018
JB		 1304{
1305 struct i2s_dai *i2s, *other;
c5cf4dbc 1306 struct resource *res;
1c7ac018
JB		 1307
1308 i2s = dev_get_drvdata(&pdev->dev);
1309 other = i2s->pri_dai ? : i2s->sec_dai;
1310
1311 if (other) {
1312 other->pri_dai = NULL;
1313 other->sec_dai = NULL;
1314 } else {
c5cf4dbc 1315 pm_runtime_disable(&pdev->dev);
1c7ac018
JB		 1316 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1317 if (res)
1318 release_mem_region(res->start, resource_size(res));
1319 }
1320
1321 i2s->pri_dai = NULL;
1322 i2s->sec_dai = NULL;
1323
1c7ac018
JB		 1324 return 0;
1325}
1326
a5a56871
PV		 1327static const struct samsung_i2s_variant_regs i2sv3_regs = {
1328 .bfs_off = 1,
1329 .rfs_off = 3,
1330 .sdf_off = 5,
1331 .txr_off = 8,
1332 .rclksrc_off = 10,
1333 .mss_off = 11,
1334 .cdclkcon_off = 12,
1335 .lrp_off = 7,
1336 .bfs_mask = 0x3,
1337 .rfs_mask = 0x3,
1338 .ftx0cnt_off = 8,
1339};
1340
1341static const struct samsung_i2s_variant_regs i2sv6_regs = {
1342 .bfs_off = 0,
1343 .rfs_off = 4,
1344 .sdf_off = 6,
1345 .txr_off = 8,
1346 .rclksrc_off = 10,
1347 .mss_off = 11,
1348 .cdclkcon_off = 12,
1349 .lrp_off = 15,
1350 .bfs_mask = 0xf,
1351 .rfs_mask = 0x3,
1352 .ftx0cnt_off = 8,
1353};
1354
1355static const struct samsung_i2s_variant_regs i2sv7_regs = {
1356 .bfs_off = 0,
1357 .rfs_off = 4,
1358 .sdf_off = 7,
1359 .txr_off = 9,
1360 .rclksrc_off = 11,
1361 .mss_off = 12,
1362 .cdclkcon_off = 22,
1363 .lrp_off = 15,
1364 .bfs_mask = 0xf,
1365 .rfs_mask = 0x7,
1366 .ftx0cnt_off = 0,
1367};
1368
1369static const struct samsung_i2s_variant_regs i2sv5_i2s1_regs = {
1370 .bfs_off = 0,
1371 .rfs_off = 3,
1372 .sdf_off = 6,
1373 .txr_off = 8,
1374 .rclksrc_off = 10,
1375 .mss_off = 11,
1376 .cdclkcon_off = 12,
1377 .lrp_off = 15,
1378 .bfs_mask = 0x7,
1379 .rfs_mask = 0x7,
1380 .ftx0cnt_off = 8,
1381};
1382
7da493e9
PV		 1383static const struct samsung_i2s_dai_data i2sv3_dai_type = {
1384 .dai_type = TYPE_PRI,
1385 .quirks = QUIRK_NO_MUXPSR,
a5a56871 1386 .i2s_variant_regs = &i2sv3_regs,
7da493e9
PV		 1387};
1388
1389static const struct samsung_i2s_dai_data i2sv5_dai_type = {
1390 .dai_type = TYPE_PRI,
b0759736
PV		 1391 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1392 QUIRK_SUPPORTS_IDMA,
a5a56871 1393 .i2s_variant_regs = &i2sv3_regs,
7da493e9
PV		 1394};
1395
4ca0c0d4
PV		 1396static const struct samsung_i2s_dai_data i2sv6_dai_type = {
1397 .dai_type = TYPE_PRI,
1398 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
b0759736 1399 QUIRK_SUPPORTS_TDM | QUIRK_SUPPORTS_IDMA,
a5a56871
PV		 1400 .i2s_variant_regs = &i2sv6_regs,
1401};
1402
1403static const struct samsung_i2s_dai_data i2sv7_dai_type = {
1404 .dai_type = TYPE_PRI,
1405 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1406 QUIRK_SUPPORTS_TDM,
1407 .i2s_variant_regs = &i2sv7_regs,
1408};
1409
1410static const struct samsung_i2s_dai_data i2sv5_dai_type_i2s1 = {
1411 .dai_type = TYPE_PRI,
1412 .quirks = QUIRK_PRI_6CHAN | QUIRK_NEED_RSTCLR,
1413 .i2s_variant_regs = &i2sv5_i2s1_regs,
4ca0c0d4
PV		 1414};
1415
7da493e9
PV		 1416static const struct samsung_i2s_dai_data samsung_dai_type_pri = {
1417 .dai_type = TYPE_PRI,
1418};
1419
1420static const struct samsung_i2s_dai_data samsung_dai_type_sec = {
1421 .dai_type = TYPE_SEC,
1422};
1423
7c62eebb
PV		 1424static struct platform_device_id samsung_i2s_driver_ids[] = {
1425 {
1426 .name = "samsung-i2s",
7da493e9 1427 .driver_data = (kernel_ulong_t)&samsung_dai_type_pri,
7c62eebb
PV		 1428 }, {
1429 .name = "samsung-i2s-sec",
7da493e9 1430 .driver_data = (kernel_ulong_t)&samsung_dai_type_sec,
7c62eebb
PV		 1431 },
1432 {},
1433};
2af19558 1434MODULE_DEVICE_TABLE(platform, samsung_i2s_driver_ids);
7c62eebb 1435
40476f61 1436#ifdef CONFIG_OF
40476f61 1437static const struct of_device_id exynos_i2s_match[] = {
7da493e9
PV		 1438 {
1439 .compatible = "samsung,s3c6410-i2s",
1440 .data = &i2sv3_dai_type,
1441 }, {
1442 .compatible = "samsung,s5pv210-i2s",
1443 .data = &i2sv5_dai_type,
4ca0c0d4
PV		 1444 }, {
1445 .compatible = "samsung,exynos5420-i2s",
1446 .data = &i2sv6_dai_type,
a5a56871
PV		 1447 }, {
1448 .compatible = "samsung,exynos7-i2s",
1449 .data = &i2sv7_dai_type,
1450 }, {
1451 .compatible = "samsung,exynos7-i2s1",
1452 .data = &i2sv5_dai_type_i2s1,
40476f61
PV		 1453 },
1454 {},
1455};
1456MODULE_DEVICE_TABLE(of, exynos_i2s_match);
1457#endif
1458
5b1d3c34
C		 1459static const struct dev_pm_ops samsung_i2s_pm = {
1460 SET_RUNTIME_PM_OPS(i2s_runtime_suspend,
1461 i2s_runtime_resume, NULL)
1462};
1463
1c7ac018
JB		 1464static struct platform_driver samsung_i2s_driver = {
1465 .probe = samsung_i2s_probe,
fdca21ad 1466 .remove = samsung_i2s_remove,
7c62eebb 1467 .id_table = samsung_i2s_driver_ids,
1c7ac018
JB		 1468 .driver = {
1469 .name = "samsung-i2s",
1470 .owner = THIS_MODULE,
40476f61 1471 .of_match_table = of_match_ptr(exynos_i2s_match),
5b1d3c34 1472 .pm = &samsung_i2s_pm,
1c7ac018
JB		 1473 },
1474};
1475
e00c3f55 1476module_platform_driver(samsung_i2s_driver);
1c7ac018
JB		 1477
1478/* Module information */
df8ad335 1479MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
1c7ac018
JB		 1480MODULE_DESCRIPTION("Samsung I2S Interface");
1481MODULE_ALIAS("platform:samsung-i2s");
1482MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.268628 seconds and 5 git commands to generate.