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f09aecd5 SK |
1 | /* |
2 | * sound/soc/samsung/idma.c | |
3 | * | |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * I2S0's Internal DMA driver | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | */ | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/slab.h> | |
da155d5b | 18 | #include <linux/module.h> |
f09aecd5 SK |
19 | #include <sound/pcm.h> |
20 | #include <sound/pcm_params.h> | |
21 | #include <sound/soc.h> | |
22 | ||
23 | #include "i2s.h" | |
24 | #include "idma.h" | |
25 | #include "dma.h" | |
26 | #include "i2s-regs.h" | |
27 | ||
28 | #define ST_RUNNING (1<<0) | |
29 | #define ST_OPENED (1<<1) | |
30 | ||
31 | static const struct snd_pcm_hardware idma_hardware = { | |
32 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
33 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
34 | SNDRV_PCM_INFO_MMAP | | |
35 | SNDRV_PCM_INFO_MMAP_VALID | | |
36 | SNDRV_PCM_INFO_PAUSE | | |
37 | SNDRV_PCM_INFO_RESUME, | |
38 | .formats = SNDRV_PCM_FMTBIT_S16_LE | | |
39 | SNDRV_PCM_FMTBIT_U16_LE | | |
40 | SNDRV_PCM_FMTBIT_S24_LE | | |
41 | SNDRV_PCM_FMTBIT_U24_LE | | |
42 | SNDRV_PCM_FMTBIT_U8 | | |
43 | SNDRV_PCM_FMTBIT_S8, | |
44 | .channels_min = 2, | |
45 | .channels_max = 2, | |
46 | .buffer_bytes_max = MAX_IDMA_BUFFER, | |
47 | .period_bytes_min = 128, | |
48 | .period_bytes_max = MAX_IDMA_PERIOD, | |
49 | .periods_min = 1, | |
50 | .periods_max = 2, | |
51 | }; | |
52 | ||
53 | struct idma_ctrl { | |
54 | spinlock_t lock; | |
55 | int state; | |
56 | dma_addr_t start; | |
57 | dma_addr_t pos; | |
58 | dma_addr_t end; | |
59 | dma_addr_t period; | |
60 | dma_addr_t periodsz; | |
61 | void *token; | |
62 | void (*cb)(void *dt, int bytes_xfer); | |
63 | }; | |
64 | ||
65 | static struct idma_info { | |
66 | spinlock_t lock; | |
67 | void __iomem *regs; | |
68 | dma_addr_t lp_tx_addr; | |
69 | } idma; | |
70 | ||
cb00e3a1 AB |
71 | static int idma_irq; |
72 | ||
f09aecd5 SK |
73 | static void idma_getpos(dma_addr_t *src) |
74 | { | |
75 | *src = idma.lp_tx_addr + | |
76 | (readl(idma.regs + I2STRNCNT) & 0xffffff) * 4; | |
77 | } | |
78 | ||
79 | static int idma_enqueue(struct snd_pcm_substream *substream) | |
80 | { | |
81 | struct snd_pcm_runtime *runtime = substream->runtime; | |
82 | struct idma_ctrl *prtd = substream->runtime->private_data; | |
83 | u32 val; | |
84 | ||
85 | spin_lock(&prtd->lock); | |
86 | prtd->token = (void *) substream; | |
87 | spin_unlock(&prtd->lock); | |
88 | ||
89 | /* Internal DMA Level0 Interrupt Address */ | |
90 | val = idma.lp_tx_addr + prtd->periodsz; | |
91 | writel(val, idma.regs + I2SLVL0ADDR); | |
92 | ||
93 | /* Start address0 of I2S internal DMA operation. */ | |
94 | val = idma.lp_tx_addr; | |
95 | writel(val, idma.regs + I2SSTR0); | |
96 | ||
97 | /* | |
98 | * Transfer block size for I2S internal DMA. | |
99 | * Should decide transfer size before start dma operation | |
100 | */ | |
101 | val = readl(idma.regs + I2SSIZE); | |
102 | val &= ~(I2SSIZE_TRNMSK << I2SSIZE_SHIFT); | |
103 | val |= (((runtime->dma_bytes >> 2) & | |
104 | I2SSIZE_TRNMSK) << I2SSIZE_SHIFT); | |
105 | writel(val, idma.regs + I2SSIZE); | |
106 | ||
107 | val = readl(idma.regs + I2SAHB); | |
108 | val |= AHB_INTENLVL0; | |
109 | writel(val, idma.regs + I2SAHB); | |
110 | ||
111 | return 0; | |
112 | } | |
113 | ||
114 | static void idma_setcallbk(struct snd_pcm_substream *substream, | |
115 | void (*cb)(void *, int)) | |
116 | { | |
117 | struct idma_ctrl *prtd = substream->runtime->private_data; | |
118 | ||
119 | spin_lock(&prtd->lock); | |
120 | prtd->cb = cb; | |
121 | spin_unlock(&prtd->lock); | |
122 | } | |
123 | ||
124 | static void idma_control(int op) | |
125 | { | |
126 | u32 val = readl(idma.regs + I2SAHB); | |
127 | ||
128 | spin_lock(&idma.lock); | |
129 | ||
130 | switch (op) { | |
131 | case LPAM_DMA_START: | |
132 | val |= (AHB_INTENLVL0 | AHB_DMAEN); | |
133 | break; | |
134 | case LPAM_DMA_STOP: | |
135 | val &= ~(AHB_INTENLVL0 | AHB_DMAEN); | |
136 | break; | |
137 | default: | |
138 | spin_unlock(&idma.lock); | |
139 | return; | |
140 | } | |
141 | ||
142 | writel(val, idma.regs + I2SAHB); | |
143 | spin_unlock(&idma.lock); | |
144 | } | |
145 | ||
146 | static void idma_done(void *id, int bytes_xfer) | |
147 | { | |
148 | struct snd_pcm_substream *substream = id; | |
149 | struct idma_ctrl *prtd = substream->runtime->private_data; | |
150 | ||
151 | if (prtd && (prtd->state & ST_RUNNING)) | |
152 | snd_pcm_period_elapsed(substream); | |
153 | } | |
154 | ||
155 | static int idma_hw_params(struct snd_pcm_substream *substream, | |
156 | struct snd_pcm_hw_params *params) | |
157 | { | |
158 | struct snd_pcm_runtime *runtime = substream->runtime; | |
159 | struct idma_ctrl *prtd = substream->runtime->private_data; | |
160 | u32 mod = readl(idma.regs + I2SMOD); | |
161 | u32 ahb = readl(idma.regs + I2SAHB); | |
162 | ||
163 | ahb |= (AHB_DMARLD | AHB_INTMASK); | |
164 | mod |= MOD_TXS_IDMA; | |
165 | writel(ahb, idma.regs + I2SAHB); | |
166 | writel(mod, idma.regs + I2SMOD); | |
167 | ||
168 | snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); | |
169 | runtime->dma_bytes = params_buffer_bytes(params); | |
170 | ||
171 | prtd->start = prtd->pos = runtime->dma_addr; | |
172 | prtd->period = params_periods(params); | |
173 | prtd->periodsz = params_period_bytes(params); | |
174 | prtd->end = runtime->dma_addr + runtime->dma_bytes; | |
175 | ||
176 | idma_setcallbk(substream, idma_done); | |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
181 | static int idma_hw_free(struct snd_pcm_substream *substream) | |
182 | { | |
183 | snd_pcm_set_runtime_buffer(substream, NULL); | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
188 | static int idma_prepare(struct snd_pcm_substream *substream) | |
189 | { | |
190 | struct idma_ctrl *prtd = substream->runtime->private_data; | |
191 | ||
192 | prtd->pos = prtd->start; | |
193 | ||
194 | /* flush the DMA channel */ | |
195 | idma_control(LPAM_DMA_STOP); | |
196 | idma_enqueue(substream); | |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
201 | static int idma_trigger(struct snd_pcm_substream *substream, int cmd) | |
202 | { | |
203 | struct idma_ctrl *prtd = substream->runtime->private_data; | |
204 | int ret = 0; | |
205 | ||
206 | spin_lock(&prtd->lock); | |
207 | ||
208 | switch (cmd) { | |
209 | case SNDRV_PCM_TRIGGER_RESUME: | |
210 | case SNDRV_PCM_TRIGGER_START: | |
211 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
212 | prtd->state |= ST_RUNNING; | |
213 | idma_control(LPAM_DMA_START); | |
214 | break; | |
215 | ||
216 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
217 | case SNDRV_PCM_TRIGGER_STOP: | |
218 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
219 | prtd->state &= ~ST_RUNNING; | |
220 | idma_control(LPAM_DMA_STOP); | |
221 | break; | |
222 | ||
223 | default: | |
224 | ret = -EINVAL; | |
225 | break; | |
226 | } | |
227 | ||
228 | spin_unlock(&prtd->lock); | |
229 | ||
230 | return ret; | |
231 | } | |
232 | ||
233 | static snd_pcm_uframes_t | |
234 | idma_pointer(struct snd_pcm_substream *substream) | |
235 | { | |
236 | struct snd_pcm_runtime *runtime = substream->runtime; | |
237 | struct idma_ctrl *prtd = runtime->private_data; | |
238 | dma_addr_t src; | |
239 | unsigned long res; | |
240 | ||
241 | spin_lock(&prtd->lock); | |
242 | ||
243 | idma_getpos(&src); | |
244 | res = src - prtd->start; | |
245 | ||
246 | spin_unlock(&prtd->lock); | |
247 | ||
248 | return bytes_to_frames(substream->runtime, res); | |
249 | } | |
250 | ||
251 | static int idma_mmap(struct snd_pcm_substream *substream, | |
252 | struct vm_area_struct *vma) | |
253 | { | |
254 | struct snd_pcm_runtime *runtime = substream->runtime; | |
255 | unsigned long size, offset; | |
256 | int ret; | |
257 | ||
258 | /* From snd_pcm_lib_mmap_iomem */ | |
259 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
260 | vma->vm_flags |= VM_IO; | |
261 | size = vma->vm_end - vma->vm_start; | |
262 | offset = vma->vm_pgoff << PAGE_SHIFT; | |
263 | ret = io_remap_pfn_range(vma, vma->vm_start, | |
264 | (runtime->dma_addr + offset) >> PAGE_SHIFT, | |
265 | size, vma->vm_page_prot); | |
266 | ||
267 | return ret; | |
268 | } | |
269 | ||
270 | static irqreturn_t iis_irq(int irqno, void *dev_id) | |
271 | { | |
272 | struct idma_ctrl *prtd = (struct idma_ctrl *)dev_id; | |
273 | u32 iiscon, iisahb, val, addr; | |
274 | ||
275 | iisahb = readl(idma.regs + I2SAHB); | |
276 | iiscon = readl(idma.regs + I2SCON); | |
277 | ||
278 | val = (iisahb & AHB_LVL0INT) ? AHB_CLRLVL0INT : 0; | |
279 | ||
280 | if (val) { | |
281 | iisahb |= val; | |
282 | writel(iisahb, idma.regs + I2SAHB); | |
283 | ||
284 | addr = readl(idma.regs + I2SLVL0ADDR) - idma.lp_tx_addr; | |
285 | addr += prtd->periodsz; | |
286 | addr %= (prtd->end - prtd->start); | |
287 | addr += idma.lp_tx_addr; | |
288 | ||
289 | writel(addr, idma.regs + I2SLVL0ADDR); | |
290 | ||
291 | if (prtd->cb) | |
292 | prtd->cb(prtd->token, prtd->period); | |
293 | } | |
294 | ||
295 | return IRQ_HANDLED; | |
296 | } | |
297 | ||
298 | static int idma_open(struct snd_pcm_substream *substream) | |
299 | { | |
300 | struct snd_pcm_runtime *runtime = substream->runtime; | |
301 | struct idma_ctrl *prtd; | |
302 | int ret; | |
303 | ||
304 | snd_soc_set_runtime_hwparams(substream, &idma_hardware); | |
305 | ||
306 | prtd = kzalloc(sizeof(struct idma_ctrl), GFP_KERNEL); | |
307 | if (prtd == NULL) | |
308 | return -ENOMEM; | |
309 | ||
cb00e3a1 | 310 | ret = request_irq(idma_irq, iis_irq, 0, "i2s", prtd); |
f09aecd5 SK |
311 | if (ret < 0) { |
312 | pr_err("fail to claim i2s irq , ret = %d\n", ret); | |
313 | kfree(prtd); | |
314 | return ret; | |
315 | } | |
316 | ||
317 | spin_lock_init(&prtd->lock); | |
318 | ||
319 | runtime->private_data = prtd; | |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
324 | static int idma_close(struct snd_pcm_substream *substream) | |
325 | { | |
326 | struct snd_pcm_runtime *runtime = substream->runtime; | |
327 | struct idma_ctrl *prtd = runtime->private_data; | |
328 | ||
cb00e3a1 | 329 | free_irq(idma_irq, prtd); |
f09aecd5 SK |
330 | |
331 | if (!prtd) | |
332 | pr_err("idma_close called with prtd == NULL\n"); | |
333 | ||
334 | kfree(prtd); | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
339 | static struct snd_pcm_ops idma_ops = { | |
340 | .open = idma_open, | |
341 | .close = idma_close, | |
342 | .ioctl = snd_pcm_lib_ioctl, | |
343 | .trigger = idma_trigger, | |
344 | .pointer = idma_pointer, | |
345 | .mmap = idma_mmap, | |
346 | .hw_params = idma_hw_params, | |
347 | .hw_free = idma_hw_free, | |
348 | .prepare = idma_prepare, | |
349 | }; | |
350 | ||
351 | static void idma_free(struct snd_pcm *pcm) | |
352 | { | |
353 | struct snd_pcm_substream *substream; | |
354 | struct snd_dma_buffer *buf; | |
355 | ||
356 | substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; | |
357 | if (!substream) | |
358 | return; | |
359 | ||
360 | buf = &substream->dma_buffer; | |
361 | if (!buf->area) | |
362 | return; | |
363 | ||
364 | iounmap(buf->area); | |
365 | ||
366 | buf->area = NULL; | |
367 | buf->addr = 0; | |
368 | } | |
369 | ||
370 | static int preallocate_idma_buffer(struct snd_pcm *pcm, int stream) | |
371 | { | |
372 | struct snd_pcm_substream *substream = pcm->streams[stream].substream; | |
373 | struct snd_dma_buffer *buf = &substream->dma_buffer; | |
374 | ||
375 | buf->dev.dev = pcm->card->dev; | |
376 | buf->private_data = NULL; | |
377 | ||
378 | /* Assign PCM buffer pointers */ | |
379 | buf->dev.type = SNDRV_DMA_TYPE_CONTINUOUS; | |
380 | buf->addr = idma.lp_tx_addr; | |
381 | buf->bytes = idma_hardware.buffer_bytes_max; | |
382 | buf->area = (unsigned char *)ioremap(buf->addr, buf->bytes); | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
387 | static u64 idma_mask = DMA_BIT_MASK(32); | |
388 | ||
389 | static int idma_new(struct snd_soc_pcm_runtime *rtd) | |
390 | { | |
391 | struct snd_card *card = rtd->card->snd_card; | |
f09aecd5 SK |
392 | struct snd_pcm *pcm = rtd->pcm; |
393 | int ret = 0; | |
394 | ||
395 | if (!card->dev->dma_mask) | |
396 | card->dev->dma_mask = &idma_mask; | |
397 | if (!card->dev->coherent_dma_mask) | |
398 | card->dev->coherent_dma_mask = DMA_BIT_MASK(32); | |
399 | ||
25e9e756 | 400 | if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) { |
f09aecd5 SK |
401 | ret = preallocate_idma_buffer(pcm, |
402 | SNDRV_PCM_STREAM_PLAYBACK); | |
b2ed1b0b | 403 | } |
f09aecd5 SK |
404 | |
405 | return ret; | |
406 | } | |
407 | ||
9b8f5695 | 408 | void idma_reg_addr_init(void __iomem *regs, dma_addr_t addr) |
f09aecd5 SK |
409 | { |
410 | spin_lock_init(&idma.lock); | |
411 | idma.regs = regs; | |
412 | idma.lp_tx_addr = addr; | |
413 | } | |
414 | ||
8858d218 | 415 | static struct snd_soc_platform_driver asoc_idma_platform = { |
f09aecd5 SK |
416 | .ops = &idma_ops, |
417 | .pcm_new = idma_new, | |
418 | .pcm_free = idma_free, | |
419 | }; | |
420 | ||
fdca21ad | 421 | static int asoc_idma_platform_probe(struct platform_device *pdev) |
f09aecd5 | 422 | { |
cb00e3a1 AB |
423 | idma_irq = platform_get_irq(pdev, 0); |
424 | if (idma_irq < 0) | |
425 | return idma_irq; | |
426 | ||
f09aecd5 SK |
427 | return snd_soc_register_platform(&pdev->dev, &asoc_idma_platform); |
428 | } | |
429 | ||
fdca21ad | 430 | static int asoc_idma_platform_remove(struct platform_device *pdev) |
f09aecd5 SK |
431 | { |
432 | snd_soc_unregister_platform(&pdev->dev); | |
433 | return 0; | |
434 | } | |
435 | ||
436 | static struct platform_driver asoc_idma_driver = { | |
437 | .driver = { | |
438 | .name = "samsung-idma", | |
439 | .owner = THIS_MODULE, | |
440 | }, | |
441 | ||
442 | .probe = asoc_idma_platform_probe, | |
fdca21ad | 443 | .remove = asoc_idma_platform_remove, |
f09aecd5 SK |
444 | }; |
445 | ||
e00c3f55 | 446 | module_platform_driver(asoc_idma_driver); |
f09aecd5 SK |
447 | |
448 | MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>"); | |
449 | MODULE_DESCRIPTION("Samsung ASoC IDMA Driver"); | |
450 | MODULE_LICENSE("GPL"); |