[deliverable/linux.git] / sound / soc / samsung / pcm.c

/* sound/soc/samsung/pcm.c
 *
 * ALSA SoC Audio Layer - S3C PCM-Controller driver
 *
 * Copyright (c) 2009 Samsung Electronics Co. Ltd
 * Author: Jaswinder Singh <jassisinghbrar@gmail.com>
 * based upon I2S drivers by Ben Dooks.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>

#include <sound/soc.h>
#include <sound/pcm_params.h>

#include <linux/platform_data/asoc-s3c.h>

#include "dma.h"
#include "pcm.h"

/*Register Offsets */
#define S3C_PCM_CTL		0x00
#define S3C_PCM_CLKCTL		0x04
#define S3C_PCM_TXFIFO		0x08
#define S3C_PCM_RXFIFO		0x0C
#define S3C_PCM_IRQCTL		0x10
#define S3C_PCM_IRQSTAT		0x14
#define S3C_PCM_FIFOSTAT	0x18
#define S3C_PCM_CLRINT		0x20

/* PCM_CTL Bit-Fields */
#define S3C_PCM_CTL_TXDIPSTICK_MASK	0x3f
#define S3C_PCM_CTL_TXDIPSTICK_SHIFT	13
#define S3C_PCM_CTL_RXDIPSTICK_MASK	0x3f
#define S3C_PCM_CTL_RXDIPSTICK_SHIFT	7
#define S3C_PCM_CTL_TXDMA_EN		(0x1 << 6)
#define S3C_PCM_CTL_RXDMA_EN		(0x1 << 5)
#define S3C_PCM_CTL_TXMSB_AFTER_FSYNC	(0x1 << 4)
#define S3C_PCM_CTL_RXMSB_AFTER_FSYNC	(0x1 << 3)
#define S3C_PCM_CTL_TXFIFO_EN		(0x1 << 2)
#define S3C_PCM_CTL_RXFIFO_EN		(0x1 << 1)
#define S3C_PCM_CTL_ENABLE		(0x1 << 0)

/* PCM_CLKCTL Bit-Fields */
#define S3C_PCM_CLKCTL_SERCLK_EN	(0x1 << 19)
#define S3C_PCM_CLKCTL_SERCLKSEL_PCLK	(0x1 << 18)
#define S3C_PCM_CLKCTL_SCLKDIV_MASK	0x1ff
#define S3C_PCM_CLKCTL_SYNCDIV_MASK	0x1ff
#define S3C_PCM_CLKCTL_SCLKDIV_SHIFT	9
#define S3C_PCM_CLKCTL_SYNCDIV_SHIFT	0

/* PCM_TXFIFO Bit-Fields */
#define S3C_PCM_TXFIFO_DVALID	(0x1 << 16)
#define S3C_PCM_TXFIFO_DATA_MSK	(0xffff << 0)

/* PCM_RXFIFO Bit-Fields */
#define S3C_PCM_RXFIFO_DVALID	(0x1 << 16)
#define S3C_PCM_RXFIFO_DATA_MSK	(0xffff << 0)

/* PCM_IRQCTL Bit-Fields */
#define S3C_PCM_IRQCTL_IRQEN		(0x1 << 14)
#define S3C_PCM_IRQCTL_WRDEN		(0x1 << 12)
#define S3C_PCM_IRQCTL_TXEMPTYEN	(0x1 << 11)
#define S3C_PCM_IRQCTL_TXALMSTEMPTYEN	(0x1 << 10)
#define S3C_PCM_IRQCTL_TXFULLEN		(0x1 << 9)
#define S3C_PCM_IRQCTL_TXALMSTFULLEN	(0x1 << 8)
#define S3C_PCM_IRQCTL_TXSTARVEN	(0x1 << 7)
#define S3C_PCM_IRQCTL_TXERROVRFLEN	(0x1 << 6)
#define S3C_PCM_IRQCTL_RXEMPTEN		(0x1 << 5)
#define S3C_PCM_IRQCTL_RXALMSTEMPTEN	(0x1 << 4)
#define S3C_PCM_IRQCTL_RXFULLEN		(0x1 << 3)
#define S3C_PCM_IRQCTL_RXALMSTFULLEN	(0x1 << 2)
#define S3C_PCM_IRQCTL_RXSTARVEN	(0x1 << 1)
#define S3C_PCM_IRQCTL_RXERROVRFLEN	(0x1 << 0)

/* PCM_IRQSTAT Bit-Fields */
#define S3C_PCM_IRQSTAT_IRQPND		(0x1 << 13)
#define S3C_PCM_IRQSTAT_WRD_XFER	(0x1 << 12)
#define S3C_PCM_IRQSTAT_TXEMPTY		(0x1 << 11)
#define S3C_PCM_IRQSTAT_TXALMSTEMPTY	(0x1 << 10)
#define S3C_PCM_IRQSTAT_TXFULL		(0x1 << 9)
#define S3C_PCM_IRQSTAT_TXALMSTFULL	(0x1 << 8)
#define S3C_PCM_IRQSTAT_TXSTARV		(0x1 << 7)
#define S3C_PCM_IRQSTAT_TXERROVRFL	(0x1 << 6)
#define S3C_PCM_IRQSTAT_RXEMPT		(0x1 << 5)
#define S3C_PCM_IRQSTAT_RXALMSTEMPT	(0x1 << 4)
#define S3C_PCM_IRQSTAT_RXFULL		(0x1 << 3)
#define S3C_PCM_IRQSTAT_RXALMSTFULL	(0x1 << 2)
#define S3C_PCM_IRQSTAT_RXSTARV		(0x1 << 1)
#define S3C_PCM_IRQSTAT_RXERROVRFL	(0x1 << 0)

/* PCM_FIFOSTAT Bit-Fields */
#define S3C_PCM_FIFOSTAT_TXCNT_MSK		(0x3f << 14)
#define S3C_PCM_FIFOSTAT_TXFIFOEMPTY		(0x1 << 13)
#define S3C_PCM_FIFOSTAT_TXFIFOALMSTEMPTY	(0x1 << 12)
#define S3C_PCM_FIFOSTAT_TXFIFOFULL		(0x1 << 11)
#define S3C_PCM_FIFOSTAT_TXFIFOALMSTFULL	(0x1 << 10)
#define S3C_PCM_FIFOSTAT_RXCNT_MSK		(0x3f << 4)
#define S3C_PCM_FIFOSTAT_RXFIFOEMPTY		(0x1 << 3)
#define S3C_PCM_FIFOSTAT_RXFIFOALMSTEMPTY	(0x1 << 2)
#define S3C_PCM_FIFOSTAT_RXFIFOFULL		(0x1 << 1)
#define S3C_PCM_FIFOSTAT_RXFIFOALMSTFULL	(0x1 << 0)

/**
 * struct s3c_pcm_info - S3C PCM Controller information
 * @dev: The parent device passed to use from the probe.
 * @regs: The pointer to the device register block.
 * @dma_playback: DMA information for playback channel.
 * @dma_capture: DMA information for capture channel.
 */
struct s3c_pcm_info {
	spinlock_t lock;
	struct device	*dev;
	void __iomem	*regs;

	unsigned int sclk_per_fs;

	/* Whether to keep PCMSCLK enabled even when idle(no active xfer) */
	unsigned int idleclk;

	struct clk	*pclk;
	struct clk	*cclk;

	struct snd_dmaengine_dai_dma_data *dma_playback;
	struct snd_dmaengine_dai_dma_data *dma_capture;
};

static struct snd_dmaengine_dai_dma_data s3c_pcm_stereo_out[] = {
	[0] = {
		.addr_width	= 4,
	},
	[1] = {
		.addr_width	= 4,
	},
};

static struct snd_dmaengine_dai_dma_data s3c_pcm_stereo_in[] = {
	[0] = {
		.addr_width	= 4,
	},
	[1] = {
		.addr_width	= 4,
	},
};

static struct s3c_pcm_info s3c_pcm[2];

static void s3c_pcm_snd_txctrl(struct s3c_pcm_info *pcm, int on)
{
	void __iomem *regs = pcm->regs;
	u32 ctl, clkctl;

	clkctl = readl(regs + S3C_PCM_CLKCTL);
	ctl = readl(regs + S3C_PCM_CTL);
	ctl &= ~(S3C_PCM_CTL_TXDIPSTICK_MASK
			 << S3C_PCM_CTL_TXDIPSTICK_SHIFT);

	if (on) {
		ctl |= S3C_PCM_CTL_TXDMA_EN;
		ctl |= S3C_PCM_CTL_TXFIFO_EN;
		ctl |= S3C_PCM_CTL_ENABLE;
		ctl |= (0x4<<S3C_PCM_CTL_TXDIPSTICK_SHIFT);
		clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
	} else {
		ctl &= ~S3C_PCM_CTL_TXDMA_EN;
		ctl &= ~S3C_PCM_CTL_TXFIFO_EN;

		if (!(ctl & S3C_PCM_CTL_RXFIFO_EN)) {
			ctl &= ~S3C_PCM_CTL_ENABLE;
			if (!pcm->idleclk)
				clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
		}
	}

	writel(clkctl, regs + S3C_PCM_CLKCTL);
	writel(ctl, regs + S3C_PCM_CTL);
}

static void s3c_pcm_snd_rxctrl(struct s3c_pcm_info *pcm, int on)
{
	void __iomem *regs = pcm->regs;
	u32 ctl, clkctl;

	ctl = readl(regs + S3C_PCM_CTL);
	clkctl = readl(regs + S3C_PCM_CLKCTL);
	ctl &= ~(S3C_PCM_CTL_RXDIPSTICK_MASK
			 << S3C_PCM_CTL_RXDIPSTICK_SHIFT);

	if (on) {
		ctl |= S3C_PCM_CTL_RXDMA_EN;
		ctl |= S3C_PCM_CTL_RXFIFO_EN;
		ctl |= S3C_PCM_CTL_ENABLE;
		ctl |= (0x20<<S3C_PCM_CTL_RXDIPSTICK_SHIFT);
		clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
	} else {
		ctl &= ~S3C_PCM_CTL_RXDMA_EN;
		ctl &= ~S3C_PCM_CTL_RXFIFO_EN;

		if (!(ctl & S3C_PCM_CTL_TXFIFO_EN)) {
			ctl &= ~S3C_PCM_CTL_ENABLE;
			if (!pcm->idleclk)
				clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
		}
	}

	writel(clkctl, regs + S3C_PCM_CLKCTL);
	writel(ctl, regs + S3C_PCM_CTL);
}

static int s3c_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
	unsigned long flags;

	dev_dbg(pcm->dev, "Entered %s\n", __func__);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		spin_lock_irqsave(&pcm->lock, flags);

		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			s3c_pcm_snd_rxctrl(pcm, 1);
		else
			s3c_pcm_snd_txctrl(pcm, 1);

		spin_unlock_irqrestore(&pcm->lock, flags);
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		spin_lock_irqsave(&pcm->lock, flags);

		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			s3c_pcm_snd_rxctrl(pcm, 0);
		else
			s3c_pcm_snd_txctrl(pcm, 0);

		spin_unlock_irqrestore(&pcm->lock, flags);
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

static int s3c_pcm_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *socdai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
	void __iomem *regs = pcm->regs;
	struct clk *clk;
	int sclk_div, sync_div;
	unsigned long flags;
	u32 clkctl;

	dev_dbg(pcm->dev, "Entered %s\n", __func__);

	/* Strictly check for sample size */
	switch (params_width(params)) {
	case 16:
		break;
	default:
		return -EINVAL;
	}

	spin_lock_irqsave(&pcm->lock, flags);

	/* Get hold of the PCMSOURCE_CLK */
	clkctl = readl(regs + S3C_PCM_CLKCTL);
	if (clkctl & S3C_PCM_CLKCTL_SERCLKSEL_PCLK)
		clk = pcm->pclk;
	else
		clk = pcm->cclk;

	/* Set the SCLK divider */
	sclk_div = clk_get_rate(clk) / pcm->sclk_per_fs /
					params_rate(params) / 2 - 1;

	clkctl &= ~(S3C_PCM_CLKCTL_SCLKDIV_MASK
			<< S3C_PCM_CLKCTL_SCLKDIV_SHIFT);
	clkctl |= ((sclk_div & S3C_PCM_CLKCTL_SCLKDIV_MASK)
			<< S3C_PCM_CLKCTL_SCLKDIV_SHIFT);

	/* Set the SYNC divider */
	sync_div = pcm->sclk_per_fs - 1;

	clkctl &= ~(S3C_PCM_CLKCTL_SYNCDIV_MASK
				<< S3C_PCM_CLKCTL_SYNCDIV_SHIFT);
	clkctl |= ((sync_div & S3C_PCM_CLKCTL_SYNCDIV_MASK)
				<< S3C_PCM_CLKCTL_SYNCDIV_SHIFT);

	writel(clkctl, regs + S3C_PCM_CLKCTL);

	spin_unlock_irqrestore(&pcm->lock, flags);

	dev_dbg(pcm->dev, "PCMSOURCE_CLK-%lu SCLK=%ufs SCLK_DIV=%d SYNC_DIV=%d\n",
				clk_get_rate(clk), pcm->sclk_per_fs,
				sclk_div, sync_div);

	return 0;
}

static int s3c_pcm_set_fmt(struct snd_soc_dai *cpu_dai,
			       unsigned int fmt)
{
	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
	void __iomem *regs = pcm->regs;
	unsigned long flags;
	int ret = 0;
	u32 ctl;

	dev_dbg(pcm->dev, "Entered %s\n", __func__);

	spin_lock_irqsave(&pcm->lock, flags);

	ctl = readl(regs + S3C_PCM_CTL);

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_IB_NF:
		/* Nothing to do, IB_NF by default */
		break;
	default:
		dev_err(pcm->dev, "Unsupported clock inversion!\n");
		ret = -EINVAL;
		goto exit;
	}

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* Nothing to do, Master by default */
		break;
	default:
		dev_err(pcm->dev, "Unsupported master/slave format!\n");
		ret = -EINVAL;
		goto exit;
	}

	switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
	case SND_SOC_DAIFMT_CONT:
		pcm->idleclk = 1;
		break;
	case SND_SOC_DAIFMT_GATED:
		pcm->idleclk = 0;
		break;
	default:
		dev_err(pcm->dev, "Invalid Clock gating request!\n");
		ret = -EINVAL;
		goto exit;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_DSP_A:
		ctl |= S3C_PCM_CTL_TXMSB_AFTER_FSYNC;
		ctl |= S3C_PCM_CTL_RXMSB_AFTER_FSYNC;
		break;
	case SND_SOC_DAIFMT_DSP_B:
		ctl &= ~S3C_PCM_CTL_TXMSB_AFTER_FSYNC;
		ctl &= ~S3C_PCM_CTL_RXMSB_AFTER_FSYNC;
		break;
	default:
		dev_err(pcm->dev, "Unsupported data format!\n");
		ret = -EINVAL;
		goto exit;
	}

	writel(ctl, regs + S3C_PCM_CTL);

exit:
	spin_unlock_irqrestore(&pcm->lock, flags);

	return ret;
}

static int s3c_pcm_set_clkdiv(struct snd_soc_dai *cpu_dai,
						int div_id, int div)
{
	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);

	switch (div_id) {
	case S3C_PCM_SCLK_PER_FS:
		pcm->sclk_per_fs = div;
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

static int s3c_pcm_set_sysclk(struct snd_soc_dai *cpu_dai,
				  int clk_id, unsigned int freq, int dir)
{
	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
	void __iomem *regs = pcm->regs;
	u32 clkctl = readl(regs + S3C_PCM_CLKCTL);

	switch (clk_id) {
	case S3C_PCM_CLKSRC_PCLK:
		clkctl |= S3C_PCM_CLKCTL_SERCLKSEL_PCLK;
		break;

	case S3C_PCM_CLKSRC_MUX:
		clkctl &= ~S3C_PCM_CLKCTL_SERCLKSEL_PCLK;

		if (clk_get_rate(pcm->cclk) != freq)
			clk_set_rate(pcm->cclk, freq);

		break;

	default:
		return -EINVAL;
	}

	writel(clkctl, regs + S3C_PCM_CLKCTL);

	return 0;
}

static const struct snd_soc_dai_ops s3c_pcm_dai_ops = {
	.set_sysclk	= s3c_pcm_set_sysclk,
	.set_clkdiv	= s3c_pcm_set_clkdiv,
	.trigger	= s3c_pcm_trigger,
	.hw_params	= s3c_pcm_hw_params,
	.set_fmt	= s3c_pcm_set_fmt,
};

static int s3c_pcm_dai_probe(struct snd_soc_dai *dai)
{
	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(dai);

	snd_soc_dai_init_dma_data(dai, pcm->dma_playback, pcm->dma_capture);

	return 0;
}

#define S3C_PCM_RATES  SNDRV_PCM_RATE_8000_96000

#define S3C_PCM_DAI_DECLARE			\
	.symmetric_rates = 1,					\
	.probe = s3c_pcm_dai_probe,				\
	.ops = &s3c_pcm_dai_ops,				\
	.playback = {						\
		.channels_min	= 2,				\
		.channels_max	= 2,				\
		.rates		= S3C_PCM_RATES,		\
		.formats	= SNDRV_PCM_FMTBIT_S16_LE,	\
	},							\
	.capture = {						\
		.channels_min	= 2,				\
		.channels_max	= 2,				\
		.rates		= S3C_PCM_RATES,		\
		.formats	= SNDRV_PCM_FMTBIT_S16_LE,	\
	}

static struct snd_soc_dai_driver s3c_pcm_dai[] = {
	[0] = {
		.name	= "samsung-pcm.0",
		S3C_PCM_DAI_DECLARE,
	},
	[1] = {
		.name	= "samsung-pcm.1",
		S3C_PCM_DAI_DECLARE,
	},
};

static const struct snd_soc_component_driver s3c_pcm_component = {
	.name		= "s3c-pcm",
};

static int s3c_pcm_dev_probe(struct platform_device *pdev)
{
	struct s3c_pcm_info *pcm;
	struct resource *mem_res;
	struct s3c_audio_pdata *pcm_pdata;
	dma_filter_fn filter;
	int ret;

	/* Check for valid device index */
	if ((pdev->id < 0) || pdev->id >= ARRAY_SIZE(s3c_pcm)) {
		dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
		return -EINVAL;
	}

	pcm_pdata = pdev->dev.platform_data;

	/* Check for availability of necessary resource */
	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem_res) {
		dev_err(&pdev->dev, "Unable to get register resource\n");
		return -ENXIO;
	}

	if (pcm_pdata && pcm_pdata->cfg_gpio && pcm_pdata->cfg_gpio(pdev)) {
		dev_err(&pdev->dev, "Unable to configure gpio\n");
		return -EINVAL;
	}

	pcm = &s3c_pcm[pdev->id];
	pcm->dev = &pdev->dev;

	spin_lock_init(&pcm->lock);

	/* Default is 128fs */
	pcm->sclk_per_fs = 128;

	pcm->cclk = devm_clk_get(&pdev->dev, "audio-bus");
	if (IS_ERR(pcm->cclk)) {
		dev_err(&pdev->dev, "failed to get audio-bus\n");
		ret = PTR_ERR(pcm->cclk);
		goto err1;
	}
	clk_prepare_enable(pcm->cclk);

	/* record our pcm structure for later use in the callbacks */
	dev_set_drvdata(&pdev->dev, pcm);

	if (!request_mem_region(mem_res->start,
				resource_size(mem_res), "samsung-pcm")) {
		dev_err(&pdev->dev, "Unable to request register region\n");
		ret = -EBUSY;
		goto err2;
	}

	pcm->regs = ioremap(mem_res->start, 0x100);
	if (pcm->regs == NULL) {
		dev_err(&pdev->dev, "cannot ioremap registers\n");
		ret = -ENXIO;
		goto err3;
	}

	pcm->pclk = devm_clk_get(&pdev->dev, "pcm");
	if (IS_ERR(pcm->pclk)) {
		dev_err(&pdev->dev, "failed to get pcm_clock\n");
		ret = -ENOENT;
		goto err4;
	}
	clk_prepare_enable(pcm->pclk);

	s3c_pcm_stereo_in[pdev->id].addr = mem_res->start + S3C_PCM_RXFIFO;
	s3c_pcm_stereo_out[pdev->id].addr = mem_res->start + S3C_PCM_TXFIFO;

	filter = NULL;
	if (pcm_pdata) {
		s3c_pcm_stereo_in[pdev->id].filter_data = pcm_pdata->dma_capture;
		s3c_pcm_stereo_out[pdev->id].filter_data = pcm_pdata->dma_playback;
		filter = pcm_pdata->dma_filter;
	}

	pcm->dma_capture = &s3c_pcm_stereo_in[pdev->id];
	pcm->dma_playback = &s3c_pcm_stereo_out[pdev->id];

	pm_runtime_enable(&pdev->dev);

	ret = devm_snd_soc_register_component(&pdev->dev, &s3c_pcm_component,
					 &s3c_pcm_dai[pdev->id], 1);
	if (ret != 0) {
		dev_err(&pdev->dev, "failed to get register DAI: %d\n", ret);
		goto err5;
	}

	ret = samsung_asoc_dma_platform_register(&pdev->dev, filter,
						 NULL, NULL);
	if (ret) {
		dev_err(&pdev->dev, "failed to get register DMA: %d\n", ret);
		goto err5;
	}

	return 0;

err5:
	clk_disable_unprepare(pcm->pclk);
err4:
	iounmap(pcm->regs);
err3:
	release_mem_region(mem_res->start, resource_size(mem_res));
err2:
	clk_disable_unprepare(pcm->cclk);
err1:
	return ret;
}

static int s3c_pcm_dev_remove(struct platform_device *pdev)
{
	struct s3c_pcm_info *pcm = &s3c_pcm[pdev->id];
	struct resource *mem_res;

	pm_runtime_disable(&pdev->dev);

	iounmap(pcm->regs);

	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(mem_res->start, resource_size(mem_res));

	clk_disable_unprepare(pcm->cclk);
	clk_disable_unprepare(pcm->pclk);

	return 0;
}

static struct platform_driver s3c_pcm_driver = {
	.probe  = s3c_pcm_dev_probe,
	.remove = s3c_pcm_dev_remove,
	.driver = {
		.name = "samsung-pcm",
	},
};

module_platform_driver(s3c_pcm_driver);

/* Module information */
MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
MODULE_DESCRIPTION("S3C PCM Controller Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:samsung-pcm");
Commit	Line	Data
5033f43c	1	/* sound/soc/samsung/pcm.c
357a1db9 JB	2	*
	3	* ALSA SoC Audio Layer - S3C PCM-Controller driver
	4	*
	5	* Copyright (c) 2009 Samsung Electronics Co. Ltd
df8ad335	6	* Author: Jaswinder Singh <jassisinghbrar@gmail.com>
357a1db9 JB	7	* based upon I2S drivers by Ben Dooks.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
357a1db9	14	#include <linux/clk.h>
357a1db9	15	#include <linux/io.h>
da155d5b	16	#include <linux/module.h>
c5cf4dbc	17	#include <linux/pm_runtime.h>
357a1db9	18
357a1db9	19	#include <sound/soc.h>
0378b6ac	20	#include <sound/pcm_params.h>
357a1db9	21
436d42c6	22	#include <linux/platform_data/asoc-s3c.h>
357a1db9	23
4b640cf3	24	#include "dma.h"
158a7828	25	#include "pcm.h"
357a1db9	26
9c6df19e SY	27	/Register Offsets /
	28	#define S3C_PCM_CTL 0x00
	29	#define S3C_PCM_CLKCTL 0x04
	30	#define S3C_PCM_TXFIFO 0x08
	31	#define S3C_PCM_RXFIFO 0x0C
	32	#define S3C_PCM_IRQCTL 0x10
	33	#define S3C_PCM_IRQSTAT 0x14
	34	#define S3C_PCM_FIFOSTAT 0x18
	35	#define S3C_PCM_CLRINT 0x20
	36
	37	/* PCM_CTL Bit-Fields */
	38	#define S3C_PCM_CTL_TXDIPSTICK_MASK 0x3f
	39	#define S3C_PCM_CTL_TXDIPSTICK_SHIFT 13
	40	#define S3C_PCM_CTL_RXDIPSTICK_MASK 0x3f
	41	#define S3C_PCM_CTL_RXDIPSTICK_SHIFT 7
	42	#define S3C_PCM_CTL_TXDMA_EN (0x1 << 6)
	43	#define S3C_PCM_CTL_RXDMA_EN (0x1 << 5)
	44	#define S3C_PCM_CTL_TXMSB_AFTER_FSYNC (0x1 << 4)
	45	#define S3C_PCM_CTL_RXMSB_AFTER_FSYNC (0x1 << 3)
	46	#define S3C_PCM_CTL_TXFIFO_EN (0x1 << 2)
	47	#define S3C_PCM_CTL_RXFIFO_EN (0x1 << 1)
	48	#define S3C_PCM_CTL_ENABLE (0x1 << 0)
	49
	50	/* PCM_CLKCTL Bit-Fields */
	51	#define S3C_PCM_CLKCTL_SERCLK_EN (0x1 << 19)
	52	#define S3C_PCM_CLKCTL_SERCLKSEL_PCLK (0x1 << 18)
	53	#define S3C_PCM_CLKCTL_SCLKDIV_MASK 0x1ff
	54	#define S3C_PCM_CLKCTL_SYNCDIV_MASK 0x1ff
	55	#define S3C_PCM_CLKCTL_SCLKDIV_SHIFT 9
	56	#define S3C_PCM_CLKCTL_SYNCDIV_SHIFT 0
	57
	58	/* PCM_TXFIFO Bit-Fields */
	59	#define S3C_PCM_TXFIFO_DVALID (0x1 << 16)
	60	#define S3C_PCM_TXFIFO_DATA_MSK (0xffff << 0)
	61
	62	/* PCM_RXFIFO Bit-Fields */
	63	#define S3C_PCM_RXFIFO_DVALID (0x1 << 16)
	64	#define S3C_PCM_RXFIFO_DATA_MSK (0xffff << 0)
	65
	66	/* PCM_IRQCTL Bit-Fields */
	67	#define S3C_PCM_IRQCTL_IRQEN (0x1 << 14)
	68	#define S3C_PCM_IRQCTL_WRDEN (0x1 << 12)
	69	#define S3C_PCM_IRQCTL_TXEMPTYEN (0x1 << 11)
	70	#define S3C_PCM_IRQCTL_TXALMSTEMPTYEN (0x1 << 10)
	71	#define S3C_PCM_IRQCTL_TXFULLEN (0x1 << 9)
	72	#define S3C_PCM_IRQCTL_TXALMSTFULLEN (0x1 << 8)
	73	#define S3C_PCM_IRQCTL_TXSTARVEN (0x1 << 7)
	74	#define S3C_PCM_IRQCTL_TXERROVRFLEN (0x1 << 6)
	75	#define S3C_PCM_IRQCTL_RXEMPTEN (0x1 << 5)
	76	#define S3C_PCM_IRQCTL_RXALMSTEMPTEN (0x1 << 4)
	77	#define S3C_PCM_IRQCTL_RXFULLEN (0x1 << 3)
	78	#define S3C_PCM_IRQCTL_RXALMSTFULLEN (0x1 << 2)
	79	#define S3C_PCM_IRQCTL_RXSTARVEN (0x1 << 1)
	80	#define S3C_PCM_IRQCTL_RXERROVRFLEN (0x1 << 0)
	81
	82	/* PCM_IRQSTAT Bit-Fields */
	83	#define S3C_PCM_IRQSTAT_IRQPND (0x1 << 13)
	84	#define S3C_PCM_IRQSTAT_WRD_XFER (0x1 << 12)
	85	#define S3C_PCM_IRQSTAT_TXEMPTY (0x1 << 11)
	86	#define S3C_PCM_IRQSTAT_TXALMSTEMPTY (0x1 << 10)
	87	#define S3C_PCM_IRQSTAT_TXFULL (0x1 << 9)
	88	#define S3C_PCM_IRQSTAT_TXALMSTFULL (0x1 << 8)
	89	#define S3C_PCM_IRQSTAT_TXSTARV (0x1 << 7)
	90	#define S3C_PCM_IRQSTAT_TXERROVRFL (0x1 << 6)
91	#define S3C_PCM_IRQSTAT_RXEMPT (0x1 << 5)
92	#define S3C_PCM_IRQSTAT_RXALMSTEMPT (0x1 << 4)
93	#define S3C_PCM_IRQSTAT_RXFULL (0x1 << 3)
94	#define S3C_PCM_IRQSTAT_RXALMSTFULL (0x1 << 2)
95	#define S3C_PCM_IRQSTAT_RXSTARV (0x1 << 1)
96	#define S3C_PCM_IRQSTAT_RXERROVRFL (0x1 << 0)
97
98	/* PCM_FIFOSTAT Bit-Fields */
99	#define S3C_PCM_FIFOSTAT_TXCNT_MSK (0x3f << 14)
100	#define S3C_PCM_FIFOSTAT_TXFIFOEMPTY (0x1 << 13)
101	#define S3C_PCM_FIFOSTAT_TXFIFOALMSTEMPTY (0x1 << 12)
102	#define S3C_PCM_FIFOSTAT_TXFIFOFULL (0x1 << 11)
103	#define S3C_PCM_FIFOSTAT_TXFIFOALMSTFULL (0x1 << 10)
104	#define S3C_PCM_FIFOSTAT_RXCNT_MSK (0x3f << 4)
105	#define S3C_PCM_FIFOSTAT_RXFIFOEMPTY (0x1 << 3)
106	#define S3C_PCM_FIFOSTAT_RXFIFOALMSTEMPTY (0x1 << 2)
107	#define S3C_PCM_FIFOSTAT_RXFIFOFULL (0x1 << 1)
108	#define S3C_PCM_FIFOSTAT_RXFIFOALMSTFULL (0x1 << 0)
109
110	/**
111	* struct s3c_pcm_info - S3C PCM Controller information
112	* @dev: The parent device passed to use from the probe.
113	* @regs: The pointer to the device register block.
114	* @dma_playback: DMA information for playback channel.
115	* @dma_capture: DMA information for capture channel.
116	*/
117	struct s3c_pcm_info {
118	spinlock_t lock;
119	struct device *dev;
120	void __iomem *regs;
121
122	unsigned int sclk_per_fs;
123
124	/* Whether to keep PCMSCLK enabled even when idle(no active xfer) */
125	unsigned int idleclk;
126
127	struct clk *pclk;
128	struct clk *cclk;
129
2feb6165 SN	130	struct snd_dmaengine_dai_dma_data *dma_playback;
2feb6165 SN	131	struct snd_dmaengine_dai_dma_data *dma_capture;
9c6df19e SY	132	};
9c6df19e SY	133
2feb6165	134	static struct snd_dmaengine_dai_dma_data s3c_pcm_stereo_out[] = {
357a1db9	135	[0] = {
2feb6165	136	.addr_width = 4,
357a1db9 JB	137	},
357a1db9 JB	138	[1] = {
2feb6165	139	.addr_width = 4,
357a1db9 JB	140	},
	141	};
	142
2feb6165	143	static struct snd_dmaengine_dai_dma_data s3c_pcm_stereo_in[] = {
357a1db9	144	[0] = {
2feb6165	145	.addr_width = 4,
357a1db9 JB	146	},
357a1db9 JB	147	[1] = {
2feb6165	148	.addr_width = 4,
357a1db9 JB	149	},
	150	};
	151
	152	static struct s3c_pcm_info s3c_pcm[2];
	153
357a1db9 JB	154	static void s3c_pcm_snd_txctrl(struct s3c_pcm_info *pcm, int on)
	155	{
	156	void __iomem *regs = pcm->regs;
	157	u32 ctl, clkctl;
	158
	159	clkctl = readl(regs + S3C_PCM_CLKCTL);
	160	ctl = readl(regs + S3C_PCM_CTL);
	161	ctl &= ~(S3C_PCM_CTL_TXDIPSTICK_MASK
	162	<< S3C_PCM_CTL_TXDIPSTICK_SHIFT);
	163
	164	if (on) {
	165	ctl \|= S3C_PCM_CTL_TXDMA_EN;
	166	ctl \|= S3C_PCM_CTL_TXFIFO_EN;
	167	ctl \|= S3C_PCM_CTL_ENABLE;
29f9e39a	168	ctl \|= (0x4<<S3C_PCM_CTL_TXDIPSTICK_SHIFT);
357a1db9 JB	169	clkctl \|= S3C_PCM_CLKCTL_SERCLK_EN;
	170	} else {
	171	ctl &= ~S3C_PCM_CTL_TXDMA_EN;
	172	ctl &= ~S3C_PCM_CTL_TXFIFO_EN;
	173
	174	if (!(ctl & S3C_PCM_CTL_RXFIFO_EN)) {
	175	ctl &= ~S3C_PCM_CTL_ENABLE;
	176	if (!pcm->idleclk)
	177	clkctl \|= S3C_PCM_CLKCTL_SERCLK_EN;
	178	}
	179	}
	180
	181	writel(clkctl, regs + S3C_PCM_CLKCTL);
	182	writel(ctl, regs + S3C_PCM_CTL);
	183	}
	184
	185	static void s3c_pcm_snd_rxctrl(struct s3c_pcm_info *pcm, int on)
	186	{
	187	void __iomem *regs = pcm->regs;
	188	u32 ctl, clkctl;
	189
	190	ctl = readl(regs + S3C_PCM_CTL);
	191	clkctl = readl(regs + S3C_PCM_CLKCTL);
0cca9012 SY	192	ctl &= ~(S3C_PCM_CTL_RXDIPSTICK_MASK
0cca9012 SY	193	<< S3C_PCM_CTL_RXDIPSTICK_SHIFT);
357a1db9 JB	194
	195	if (on) {
	196	ctl \|= S3C_PCM_CTL_RXDMA_EN;
	197	ctl \|= S3C_PCM_CTL_RXFIFO_EN;
	198	ctl \|= S3C_PCM_CTL_ENABLE;
0cca9012	199	ctl \|= (0x20<<S3C_PCM_CTL_RXDIPSTICK_SHIFT);
357a1db9 JB	200	clkctl \|= S3C_PCM_CLKCTL_SERCLK_EN;
	201	} else {
	202	ctl &= ~S3C_PCM_CTL_RXDMA_EN;
	203	ctl &= ~S3C_PCM_CTL_RXFIFO_EN;
	204
	205	if (!(ctl & S3C_PCM_CTL_TXFIFO_EN)) {
	206	ctl &= ~S3C_PCM_CTL_ENABLE;
	207	if (!pcm->idleclk)
	208	clkctl \|= S3C_PCM_CLKCTL_SERCLK_EN;
	209	}
	210	}
	211
	212	writel(clkctl, regs + S3C_PCM_CLKCTL);
	213	writel(ctl, regs + S3C_PCM_CTL);
	214	}
	215
	216	static int s3c_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
	217	struct snd_soc_dai *dai)
	218	{
	219	struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad	220	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
357a1db9 JB	221	unsigned long flags;
	222
	223	dev_dbg(pcm->dev, "Entered %s\n", __func__);
	224
	225	switch (cmd) {
	226	case SNDRV_PCM_TRIGGER_START:
	227	case SNDRV_PCM_TRIGGER_RESUME:
	228	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	229	spin_lock_irqsave(&pcm->lock, flags);
	230
	231	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	232	s3c_pcm_snd_rxctrl(pcm, 1);
	233	else
	234	s3c_pcm_snd_txctrl(pcm, 1);
	235
	236	spin_unlock_irqrestore(&pcm->lock, flags);
	237	break;
	238
	239	case SNDRV_PCM_TRIGGER_STOP:
	240	case SNDRV_PCM_TRIGGER_SUSPEND:
	241	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	242	spin_lock_irqsave(&pcm->lock, flags);
	243
	244	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	245	s3c_pcm_snd_rxctrl(pcm, 0);
	246	else
	247	s3c_pcm_snd_txctrl(pcm, 0);
	248
	249	spin_unlock_irqrestore(&pcm->lock, flags);
	250	break;
	251
	252	default:
	253	return -EINVAL;
	254	}
	255
	256	return 0;
	257	}
	258
	259	static int s3c_pcm_hw_params(struct snd_pcm_substream *substream,
	260	struct snd_pcm_hw_params *params,
	261	struct snd_soc_dai *socdai)
	262	{
	263	struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad	264	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
357a1db9 JB	265	void __iomem *regs = pcm->regs;
	266	struct clk *clk;
	267	int sclk_div, sync_div;
	268	unsigned long flags;
	269	u32 clkctl;
	270
	271	dev_dbg(pcm->dev, "Entered %s\n", __func__);
	272
357a1db9	273	/* Strictly check for sample size */
88ce1465 TB	274	switch (params_width(params)) {
88ce1465 TB	275	case 16:
357a1db9 JB	276	break;
	277	default:
	278	return -EINVAL;
	279	}
	280
	281	spin_lock_irqsave(&pcm->lock, flags);
	282
	283	/* Get hold of the PCMSOURCE_CLK */
	284	clkctl = readl(regs + S3C_PCM_CLKCTL);
	285	if (clkctl & S3C_PCM_CLKCTL_SERCLKSEL_PCLK)
	286	clk = pcm->pclk;
	287	else
	288	clk = pcm->cclk;
	289
	290	/* Set the SCLK divider */
	291	sclk_div = clk_get_rate(clk) / pcm->sclk_per_fs /
	292	params_rate(params) / 2 - 1;
	293
	294	clkctl &= ~(S3C_PCM_CLKCTL_SCLKDIV_MASK
	295	<< S3C_PCM_CLKCTL_SCLKDIV_SHIFT);
	296	clkctl \|= ((sclk_div & S3C_PCM_CLKCTL_SCLKDIV_MASK)
	297	<< S3C_PCM_CLKCTL_SCLKDIV_SHIFT);
	298
	299	/* Set the SYNC divider */
	300	sync_div = pcm->sclk_per_fs - 1;
	301
	302	clkctl &= ~(S3C_PCM_CLKCTL_SYNCDIV_MASK
	303	<< S3C_PCM_CLKCTL_SYNCDIV_SHIFT);
	304	clkctl \|= ((sync_div & S3C_PCM_CLKCTL_SYNCDIV_MASK)
	305	<< S3C_PCM_CLKCTL_SYNCDIV_SHIFT);
	306
	307	writel(clkctl, regs + S3C_PCM_CLKCTL);
	308
	309	spin_unlock_irqrestore(&pcm->lock, flags);
	310
59cdd9bc	311	dev_dbg(pcm->dev, "PCMSOURCE_CLK-%lu SCLK=%ufs SCLK_DIV=%d SYNC_DIV=%d\n",
357a1db9 JB	312	clk_get_rate(clk), pcm->sclk_per_fs,
	313	sclk_div, sync_div);
	314
	315	return 0;
	316	}
	317
	318	static int s3c_pcm_set_fmt(struct snd_soc_dai *cpu_dai,
	319	unsigned int fmt)
	320	{
f0fba2ad	321	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
357a1db9 JB	322	void __iomem *regs = pcm->regs;
	323	unsigned long flags;
	324	int ret = 0;
	325	u32 ctl;
	326
	327	dev_dbg(pcm->dev, "Entered %s\n", __func__);
	328
	329	spin_lock_irqsave(&pcm->lock, flags);
	330
	331	ctl = readl(regs + S3C_PCM_CTL);
	332
	333	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
68e0c669 SK	334	case SND_SOC_DAIFMT_IB_NF:
68e0c669 SK	335	/* Nothing to do, IB_NF by default */
357a1db9 JB	336	break;
	337	default:
	338	dev_err(pcm->dev, "Unsupported clock inversion!\n");
	339	ret = -EINVAL;
	340	goto exit;
	341	}
	342
	343	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	344	case SND_SOC_DAIFMT_CBS_CFS:
	345	/* Nothing to do, Master by default */
	346	break;
	347	default:
	348	dev_err(pcm->dev, "Unsupported master/slave format!\n");
	349	ret = -EINVAL;
	350	goto exit;
	351	}
	352
	353	switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
	354	case SND_SOC_DAIFMT_CONT:
	355	pcm->idleclk = 1;
	356	break;
	357	case SND_SOC_DAIFMT_GATED:
	358	pcm->idleclk = 0;
	359	break;
	360	default:
	361	dev_err(pcm->dev, "Invalid Clock gating request!\n");
	362	ret = -EINVAL;
	363	goto exit;
	364	}
	365
	366	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	367	case SND_SOC_DAIFMT_DSP_A:
	368	ctl \|= S3C_PCM_CTL_TXMSB_AFTER_FSYNC;
	369	ctl \|= S3C_PCM_CTL_RXMSB_AFTER_FSYNC;
	370	break;
	371	case SND_SOC_DAIFMT_DSP_B:
	372	ctl &= ~S3C_PCM_CTL_TXMSB_AFTER_FSYNC;
	373	ctl &= ~S3C_PCM_CTL_RXMSB_AFTER_FSYNC;
	374	break;
	375	default:
	376	dev_err(pcm->dev, "Unsupported data format!\n");
	377	ret = -EINVAL;
	378	goto exit;
	379	}
	380
	381	writel(ctl, regs + S3C_PCM_CTL);
	382
	383	exit:
	384	spin_unlock_irqrestore(&pcm->lock, flags);
	385
	386	return ret;
	387	}
	388
	389	static int s3c_pcm_set_clkdiv(struct snd_soc_dai *cpu_dai,
	390	int div_id, int div)
	391	{
f0fba2ad	392	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
357a1db9 JB	393
	394	switch (div_id) {
	395	case S3C_PCM_SCLK_PER_FS:
	396	pcm->sclk_per_fs = div;
	397	break;
	398
	399	default:
	400	return -EINVAL;
	401	}
	402
	403	return 0;
	404	}
	405
	406	static int s3c_pcm_set_sysclk(struct snd_soc_dai *cpu_dai,
	407	int clk_id, unsigned int freq, int dir)
	408	{
f0fba2ad	409	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
357a1db9 JB	410	void __iomem *regs = pcm->regs;
	411	u32 clkctl = readl(regs + S3C_PCM_CLKCTL);
	412
	413	switch (clk_id) {
	414	case S3C_PCM_CLKSRC_PCLK:
	415	clkctl \|= S3C_PCM_CLKCTL_SERCLKSEL_PCLK;
	416	break;
	417
	418	case S3C_PCM_CLKSRC_MUX:
	419	clkctl &= ~S3C_PCM_CLKCTL_SERCLKSEL_PCLK;
	420
	421	if (clk_get_rate(pcm->cclk) != freq)
	422	clk_set_rate(pcm->cclk, freq);
	423
	424	break;
	425
	426	default:
	427	return -EINVAL;
	428	}
	429
	430	writel(clkctl, regs + S3C_PCM_CLKCTL);
	431
	432	return 0;
	433	}
	434
85e7652d	435	static const struct snd_soc_dai_ops s3c_pcm_dai_ops = {
357a1db9 JB	436	.set_sysclk = s3c_pcm_set_sysclk,
	437	.set_clkdiv = s3c_pcm_set_clkdiv,
	438	.trigger = s3c_pcm_trigger,
	439	.hw_params = s3c_pcm_hw_params,
	440	.set_fmt = s3c_pcm_set_fmt,
	441	};
	442
3688569e MB	443	static int s3c_pcm_dai_probe(struct snd_soc_dai *dai)
	444	{
	445	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(dai);
	446
	447	snd_soc_dai_init_dma_data(dai, pcm->dma_playback, pcm->dma_capture);
	448
	449	return 0;
	450	}
	451
357a1db9 JB	452	#define S3C_PCM_RATES SNDRV_PCM_RATE_8000_96000
357a1db9 JB	453
f0fba2ad	454	#define S3C_PCM_DAI_DECLARE \
357a1db9	455	.symmetric_rates = 1, \
3688569e	456	.probe = s3c_pcm_dai_probe, \
357a1db9 JB	457	.ops = &s3c_pcm_dai_ops, \
	458	.playback = { \
	459	.channels_min = 2, \
	460	.channels_max = 2, \
	461	.rates = S3C_PCM_RATES, \
	462	.formats = SNDRV_PCM_FMTBIT_S16_LE, \
	463	}, \
	464	.capture = { \
	465	.channels_min = 2, \
	466	.channels_max = 2, \
	467	.rates = S3C_PCM_RATES, \
	468	.formats = SNDRV_PCM_FMTBIT_S16_LE, \
12280fae	469	}
357a1db9	470
5ab2ab6a	471	static struct snd_soc_dai_driver s3c_pcm_dai[] = {
12280fae JB	472	[0] = {
	473	.name = "samsung-pcm.0",
	474	S3C_PCM_DAI_DECLARE,
	475	},
	476	[1] = {
	477	.name = "samsung-pcm.1",
	478	S3C_PCM_DAI_DECLARE,
	479	},
357a1db9	480	};
357a1db9	481
fc466ba3 KM	482	static const struct snd_soc_component_driver s3c_pcm_component = {
	483	.name = "s3c-pcm",
	484	};
	485
fdca21ad	486	static int s3c_pcm_dev_probe(struct platform_device *pdev)
357a1db9 JB	487	{
357a1db9 JB	488	struct s3c_pcm_info *pcm;
b9a1a743	489	struct resource *mem_res;
357a1db9	490	struct s3c_audio_pdata *pcm_pdata;
9bdca822	491	dma_filter_fn filter;
357a1db9 JB	492	int ret;
	493
	494	/* Check for valid device index */
	495	if ((pdev->id < 0) \|\| pdev->id >= ARRAY_SIZE(s3c_pcm)) {
	496	dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
	497	return -EINVAL;
	498	}
	499
	500	pcm_pdata = pdev->dev.platform_data;
	501
	502	/* Check for availability of necessary resource */
357a1db9 JB	503	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	504	if (!mem_res) {
	505	dev_err(&pdev->dev, "Unable to get register resource\n");
	506	return -ENXIO;
	507	}
	508
	509	if (pcm_pdata && pcm_pdata->cfg_gpio && pcm_pdata->cfg_gpio(pdev)) {
	510	dev_err(&pdev->dev, "Unable to configure gpio\n");
	511	return -EINVAL;
	512	}
	513
	514	pcm = &s3c_pcm[pdev->id];
	515	pcm->dev = &pdev->dev;
	516
	517	spin_lock_init(&pcm->lock);
	518
357a1db9 JB	519	/* Default is 128fs */
	520	pcm->sclk_per_fs = 128;
	521
1d55417e	522	pcm->cclk = devm_clk_get(&pdev->dev, "audio-bus");
357a1db9 JB	523	if (IS_ERR(pcm->cclk)) {
	524	dev_err(&pdev->dev, "failed to get audio-bus\n");
	525	ret = PTR_ERR(pcm->cclk);
	526	goto err1;
	527	}
dc2c9eb8	528	clk_prepare_enable(pcm->cclk);
357a1db9 JB	529
357a1db9 JB	530	/* record our pcm structure for later use in the callbacks */
f0fba2ad	531	dev_set_drvdata(&pdev->dev, pcm);
357a1db9 JB	532
	533	if (!request_mem_region(mem_res->start,
	534	resource_size(mem_res), "samsung-pcm")) {
	535	dev_err(&pdev->dev, "Unable to request register region\n");
	536	ret = -EBUSY;
	537	goto err2;
	538	}
	539
	540	pcm->regs = ioremap(mem_res->start, 0x100);
	541	if (pcm->regs == NULL) {
	542	dev_err(&pdev->dev, "cannot ioremap registers\n");
	543	ret = -ENXIO;
	544	goto err3;
	545	}
	546
1d55417e	547	pcm->pclk = devm_clk_get(&pdev->dev, "pcm");
357a1db9 JB	548	if (IS_ERR(pcm->pclk)) {
	549	dev_err(&pdev->dev, "failed to get pcm_clock\n");
	550	ret = -ENOENT;
	551	goto err4;
	552	}
dc2c9eb8	553	clk_prepare_enable(pcm->pclk);
357a1db9	554
2feb6165 SN	555	s3c_pcm_stereo_in[pdev->id].addr = mem_res->start + S3C_PCM_RXFIFO;
2feb6165 SN	556	s3c_pcm_stereo_out[pdev->id].addr = mem_res->start + S3C_PCM_TXFIFO;
357a1db9	557
9bdca822	558	filter = NULL;
b9a1a743	559	if (pcm_pdata) {
2feb6165 SN	560	s3c_pcm_stereo_in[pdev->id].filter_data = pcm_pdata->dma_capture;
2feb6165 SN	561	s3c_pcm_stereo_out[pdev->id].filter_data = pcm_pdata->dma_playback;
9bdca822	562	filter = pcm_pdata->dma_filter;
b9a1a743	563	}
357a1db9 JB	564
	565	pcm->dma_capture = &s3c_pcm_stereo_in[pdev->id];
	566	pcm->dma_playback = &s3c_pcm_stereo_out[pdev->id];
	567
c5cf4dbc MB	568	pm_runtime_enable(&pdev->dev);
c5cf4dbc MB	569
7253e354	570	ret = devm_snd_soc_register_component(&pdev->dev, &s3c_pcm_component,
fc466ba3	571	&s3c_pcm_dai[pdev->id], 1);
0c9f1105 MB	572	if (ret != 0) {
	573	dev_err(&pdev->dev, "failed to get register DAI: %d\n", ret);
	574	goto err5;
	575	}
	576
42a74e77 SN	577	ret = samsung_asoc_dma_platform_register(&pdev->dev, filter,
42a74e77 SN	578	NULL, NULL);
a08485d8 PV	579	if (ret) {
a08485d8 PV	580	dev_err(&pdev->dev, "failed to get register DMA: %d\n", ret);
7253e354	581	goto err5;
a08485d8 PV	582	}
a08485d8 PV	583
357a1db9 JB	584	return 0;
	585
	586	err5:
dc2c9eb8	587	clk_disable_unprepare(pcm->pclk);
357a1db9 JB	588	err4:
	589	iounmap(pcm->regs);
	590	err3:
	591	release_mem_region(mem_res->start, resource_size(mem_res));
	592	err2:
dc2c9eb8	593	clk_disable_unprepare(pcm->cclk);
357a1db9 JB	594	err1:
	595	return ret;
	596	}
	597
fdca21ad	598	static int s3c_pcm_dev_remove(struct platform_device *pdev)
357a1db9 JB	599	{
	600	struct s3c_pcm_info *pcm = &s3c_pcm[pdev->id];
	601	struct resource *mem_res;
	602
c5cf4dbc MB	603	pm_runtime_disable(&pdev->dev);
c5cf4dbc MB	604
357a1db9 JB	605	iounmap(pcm->regs);
	606
	607	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	608	release_mem_region(mem_res->start, resource_size(mem_res));
	609
dc2c9eb8 TA	610	clk_disable_unprepare(pcm->cclk);
dc2c9eb8 TA	611	clk_disable_unprepare(pcm->pclk);
357a1db9 JB	612
	613	return 0;
	614	}
	615
	616	static struct platform_driver s3c_pcm_driver = {
	617	.probe = s3c_pcm_dev_probe,
fdca21ad	618	.remove = s3c_pcm_dev_remove,
357a1db9	619	.driver = {
5fbdedf0	620	.name = "samsung-pcm",
357a1db9 JB	621	},
	622	};
	623
e00c3f55	624	module_platform_driver(s3c_pcm_driver);
357a1db9 JB	625
357a1db9 JB	626	/* Module information */
df8ad335	627	MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
357a1db9 JB	628	MODULE_DESCRIPTION("S3C PCM Controller Driver");
357a1db9 JB	629	MODULE_LICENSE("GPL");
5fbdedf0	630	MODULE_ALIAS("platform:samsung-pcm");