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s3c-camif: Use CONFIG_ARCH_S3C64XX to check for S3C64XX support
[deliverable/linux.git] / sound / soc / samsung / s3c-i2s-v2.c
CommitLineData
b3ff0466 1/* ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
dc85447b
BD		 2 *
3 * Copyright (c) 2006 Wolfson Microelectronics PLC.
4 * Graeme Gregory graeme.gregory@wolfsonmicro.com
5 * linux@wolfsonmicro.com
6 *
7 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
8 * http://armlinux.simtec.co.uk/
9 * Ben Dooks <ben@simtec.co.uk>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
f3a54a28 17#include <linux/module.h>
dc85447b
BD		 18#include <linux/delay.h>
19#include <linux/clk.h>
dc85447b
BD		 20#include <linux/io.h>
21
dc85447b 22#include <sound/soc.h>
0378b6ac 23#include <sound/pcm_params.h>
dc85447b 24
dc85447b
BD		 25#include <mach/dma.h>
26
d07e7ce9 27#include "regs-i2s-v2.h"
dc85447b 28#include "s3c-i2s-v2.h"
4b640cf3 29#include "dma.h"
dc85447b 30
8a0f62b8
MB		 31#undef S3C_IIS_V2_SUPPORTED
32
5c519767
CC		 33#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) \
34 || defined(CONFIG_CPU_S5PV210)
8a0f62b8
MB		 35#define S3C_IIS_V2_SUPPORTED
36#endif
37
38#ifdef CONFIG_PLAT_S3C64XX
39#define S3C_IIS_V2_SUPPORTED
40#endif
41
42#ifndef S3C_IIS_V2_SUPPORTED
43#error Unsupported CPU model
44#endif
45
dc85447b 46#define S3C2412_I2S_DEBUG_CON 0
dc85447b
BD		 47
48static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
49{
f0fba2ad 50 return snd_soc_dai_get_drvdata(cpu_dai);
dc85447b
BD		 51}
52
53#define bit_set(v, b) (((v) & (b)) ? 1 : 0)
54
55#if S3C2412_I2S_DEBUG_CON
56static void dbg_showcon(const char *fn, u32 con)
57{
58 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
59 bit_set(con, S3C2412_IISCON_LRINDEX),
60 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
61 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
62 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
63 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
64
65 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
66 fn,
67 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
68 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
69 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
70 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
71 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
72 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
73 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
74 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
75}
76#else
77static inline void dbg_showcon(const char *fn, u32 con)
78{
79}
80#endif
81
82
83/* Turn on or off the transmission path. */
abbc8246 84static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 85{
86 void __iomem *regs = i2s->regs;
87 u32 fic, con, mod;
88
ee7d4767 89 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 90
91 fic = readl(regs + S3C2412_IISFIC);
92 con = readl(regs + S3C2412_IISCON);
93 mod = readl(regs + S3C2412_IISMOD);
94
ee7d4767 95 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 96
97 if (on) {
98 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
99 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
100 con &= ~S3C2412_IISCON_TXCH_PAUSE;
101
102 switch (mod & S3C2412_IISMOD_MODE_MASK) {
103 case S3C2412_IISMOD_MODE_TXONLY:
104 case S3C2412_IISMOD_MODE_TXRX:
105 /* do nothing, we are in the right mode */
106 break;
107
108 case S3C2412_IISMOD_MODE_RXONLY:
109 mod &= ~S3C2412_IISMOD_MODE_MASK;
110 mod |= S3C2412_IISMOD_MODE_TXRX;
111 break;
112
113 default:
abbc8246
MB		 114 dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
115 mod & S3C2412_IISMOD_MODE_MASK);
116 break;
dc85447b
BD		 117 }
118
119 writel(con, regs + S3C2412_IISCON);
120 writel(mod, regs + S3C2412_IISMOD);
121 } else {
122 /* Note, we do not have any indication that the FIFO problems
123 * tha the S3C2410/2440 had apply here, so we should be able
124 * to disable the DMA and TX without resetting the FIFOS.
125 */
126
127 con |= S3C2412_IISCON_TXDMA_PAUSE;
128 con |= S3C2412_IISCON_TXCH_PAUSE;
129 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
130
131 switch (mod & S3C2412_IISMOD_MODE_MASK) {
132 case S3C2412_IISMOD_MODE_TXRX:
133 mod &= ~S3C2412_IISMOD_MODE_MASK;
134 mod |= S3C2412_IISMOD_MODE_RXONLY;
135 break;
136
137 case S3C2412_IISMOD_MODE_TXONLY:
138 mod &= ~S3C2412_IISMOD_MODE_MASK;
139 con &= ~S3C2412_IISCON_IIS_ACTIVE;
140 break;
141
142 default:
abbc8246
MB		 143 dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
144 mod & S3C2412_IISMOD_MODE_MASK);
145 break;
dc85447b
BD		 146 }
147
148 writel(mod, regs + S3C2412_IISMOD);
149 writel(con, regs + S3C2412_IISCON);
150 }
151
152 fic = readl(regs + S3C2412_IISFIC);
153 dbg_showcon(__func__, con);
ee7d4767 154 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 155}
dc85447b 156
abbc8246 157static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b
BD		 158{
159 void __iomem *regs = i2s->regs;
160 u32 fic, con, mod;
161
ee7d4767 162 pr_debug("%s(%d)\n", __func__, on);
dc85447b
BD		 163
164 fic = readl(regs + S3C2412_IISFIC);
165 con = readl(regs + S3C2412_IISCON);
166 mod = readl(regs + S3C2412_IISMOD);
167
ee7d4767 168 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b
BD		 169
170 if (on) {
171 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
172 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
173 con &= ~S3C2412_IISCON_RXCH_PAUSE;
174
175 switch (mod & S3C2412_IISMOD_MODE_MASK) {
176 case S3C2412_IISMOD_MODE_TXRX:
177 case S3C2412_IISMOD_MODE_RXONLY:
178 /* do nothing, we are in the right mode */
179 break;
180
181 case S3C2412_IISMOD_MODE_TXONLY:
182 mod &= ~S3C2412_IISMOD_MODE_MASK;
183 mod |= S3C2412_IISMOD_MODE_TXRX;
184 break;
185
186 default:
abbc8246
MB		 187 dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
188 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 189 }
190
191 writel(mod, regs + S3C2412_IISMOD);
192 writel(con, regs + S3C2412_IISCON);
193 } else {
194 /* See txctrl notes on FIFOs. */
195
196 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
197 con |= S3C2412_IISCON_RXDMA_PAUSE;
198 con |= S3C2412_IISCON_RXCH_PAUSE;
199
200 switch (mod & S3C2412_IISMOD_MODE_MASK) {
201 case S3C2412_IISMOD_MODE_RXONLY:
202 con &= ~S3C2412_IISCON_IIS_ACTIVE;
203 mod &= ~S3C2412_IISMOD_MODE_MASK;
204 break;
205
206 case S3C2412_IISMOD_MODE_TXRX:
207 mod &= ~S3C2412_IISMOD_MODE_MASK;
208 mod |= S3C2412_IISMOD_MODE_TXONLY;
209 break;
210
211 default:
abbc8246
MB		 212 dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
213 mod & S3C2412_IISMOD_MODE_MASK);
dc85447b
BD		 214 }
215
216 writel(con, regs + S3C2412_IISCON);
217 writel(mod, regs + S3C2412_IISMOD);
218 }
219
220 fic = readl(regs + S3C2412_IISFIC);
ee7d4767 221 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b 222}
dc85447b 223
fa68e002
J		 224#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
225
dc85447b
BD		 226/*
227 * Wait for the LR signal to allow synchronisation to the L/R clock
228 * from the codec. May only be needed for slave mode.
229 */
230static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
231{
232 u32 iiscon;
fa68e002 233 unsigned long loops = msecs_to_loops(5);
dc85447b 234
ee7d4767 235 pr_debug("Entered %s\n", __func__);
dc85447b 236
fa68e002 237 while (--loops) {
dc85447b
BD		 238 iiscon = readl(i2s->regs + S3C2412_IISCON);
239 if (iiscon & S3C2412_IISCON_LRINDEX)
240 break;
241
fa68e002
J		 242 cpu_relax();
243 }
244
245 if (!loops) {
246 printk(KERN_ERR "%s: timeout\n", __func__);
247 return -ETIMEDOUT;
dc85447b
BD		 248 }
249
250 return 0;
251}
252
253/*
254 * Set S3C2412 I2S DAI format
255 */
256static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
257 unsigned int fmt)
258{
259 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
260 u32 iismod;
261
ee7d4767 262 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 263
264 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 265 pr_debug("hw_params r: IISMOD: %x \n", iismod);
dc85447b 266
dc85447b
BD		 267 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
268 case SND_SOC_DAIFMT_CBM_CFM:
269 i2s->master = 0;
ce76f9fd 270 iismod |= S3C2412_IISMOD_SLAVE;
dc85447b
BD		 271 break;
272 case SND_SOC_DAIFMT_CBS_CFS:
273 i2s->master = 1;
ce76f9fd 274 iismod &= ~S3C2412_IISMOD_SLAVE;
dc85447b
BD		 275 break;
276 default:
38e43c81 277 pr_err("unknwon master/slave format\n");
dc85447b
BD		 278 return -EINVAL;
279 }
280
281 iismod &= ~S3C2412_IISMOD_SDF_MASK;
282
283 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
284 case SND_SOC_DAIFMT_RIGHT_J:
fd5ad654 285 iismod |= S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 286 iismod |= S3C2412_IISMOD_SDF_MSB;
287 break;
288 case SND_SOC_DAIFMT_LEFT_J:
fd5ad654 289 iismod |= S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 290 iismod |= S3C2412_IISMOD_SDF_LSB;
291 break;
292 case SND_SOC_DAIFMT_I2S:
fd5ad654 293 iismod &= ~S3C2412_IISMOD_LR_RLOW;
dc85447b
BD		 294 iismod |= S3C2412_IISMOD_SDF_IIS;
295 break;
296 default:
38e43c81 297 pr_err("Unknown data format\n");
dc85447b
BD		 298 return -EINVAL;
299 }
300
301 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 302 pr_debug("hw_params w: IISMOD: %x \n", iismod);
dc85447b
BD		 303 return 0;
304}
305
9c9b1257 306static int s3c_i2sv2_hw_params(struct snd_pcm_substream *substream,
dc85447b 307 struct snd_pcm_hw_params *params,
f0fba2ad 308 struct snd_soc_dai *dai)
dc85447b 309{
f0fba2ad 310 struct s3c_i2sv2_info *i2s = to_info(dai);
fd23b7de 311 struct s3c_dma_params *dma_data;
dc85447b
BD		 312 u32 iismod;
313
ee7d4767 314 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 315
316 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
fd23b7de 317 dma_data = i2s->dma_playback;
dc85447b 318 else
fd23b7de
DM		 319 dma_data = i2s->dma_capture;
320
f0fba2ad 321 snd_soc_dai_set_dma_data(dai, substream, dma_data);
dc85447b
BD		 322
323 /* Working copies of register */
324 iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767 325 pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
dc85447b 326
bf328826 327 iismod &= ~S3C64XX_IISMOD_BLC_MASK;
553b1dd5
MB		 328 /* Sample size */
329 switch (params_format(params)) {
330 case SNDRV_PCM_FORMAT_S8:
bf328826 331 iismod |= S3C64XX_IISMOD_BLC_8BIT;
553b1dd5
MB		 332 break;
333 case SNDRV_PCM_FORMAT_S16_LE:
553b1dd5
MB		 334 break;
335 case SNDRV_PCM_FORMAT_S24_LE:
bf328826 336 iismod |= S3C64XX_IISMOD_BLC_24BIT;
553b1dd5
MB		 337 break;
338 }
dc85447b
BD		 339
340 writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767 341 pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
8a7c2518
JB		 342
343 return 0;
344}
345
346static int s3c_i2sv2_set_sysclk(struct snd_soc_dai *cpu_dai,
347 int clk_id, unsigned int freq, int dir)
348{
349 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
350 u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
351
352 pr_debug("Entered %s\n", __func__);
353 pr_debug("%s r: IISMOD: %x\n", __func__, iismod);
354
355 switch (clk_id) {
356 case S3C_I2SV2_CLKSRC_PCLK:
357 iismod &= ~S3C2412_IISMOD_IMS_SYSMUX;
358 break;
359
360 case S3C_I2SV2_CLKSRC_AUDIOBUS:
361 iismod |= S3C2412_IISMOD_IMS_SYSMUX;
362 break;
363
364 case S3C_I2SV2_CLKSRC_CDCLK:
365 /* Error if controller doesn't have the CDCLKCON bit */
366 if (!(i2s->feature & S3C_FEATURE_CDCLKCON))
367 return -EINVAL;
368
369 switch (dir) {
370 case SND_SOC_CLOCK_IN:
371 iismod |= S3C64XX_IISMOD_CDCLKCON;
372 break;
373 case SND_SOC_CLOCK_OUT:
374 iismod &= ~S3C64XX_IISMOD_CDCLKCON;
375 break;
376 default:
377 return -EINVAL;
378 }
379 break;
380
381 default:
382 return -EINVAL;
383 }
384
385 writel(iismod, i2s->regs + S3C2412_IISMOD);
386 pr_debug("%s w: IISMOD: %x\n", __func__, iismod);
387
dc85447b
BD		 388 return 0;
389}
390
391static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
392 struct snd_soc_dai *dai)
393{
394 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 395 struct s3c_i2sv2_info *i2s = to_info(rtd->cpu_dai);
dc85447b
BD		 396 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
397 unsigned long irqs;
398 int ret = 0;
fd23b7de 399 struct s3c_dma_params *dma_data =
f0fba2ad 400 snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
dc85447b 401
ee7d4767 402 pr_debug("Entered %s\n", __func__);
dc85447b
BD		 403
404 switch (cmd) {
405 case SNDRV_PCM_TRIGGER_START:
406 /* On start, ensure that the FIFOs are cleared and reset. */
407
408 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
409 i2s->regs + S3C2412_IISFIC);
410
411 /* clear again, just in case */
412 writel(0x0, i2s->regs + S3C2412_IISFIC);
413
414 case SNDRV_PCM_TRIGGER_RESUME:
415 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
416 if (!i2s->master) {
417 ret = s3c2412_snd_lrsync(i2s);
418 if (ret)
419 goto exit_err;
420 }
421
422 local_irq_save(irqs);
423
424 if (capture)
425 s3c2412_snd_rxctrl(i2s, 1);
426 else
427 s3c2412_snd_txctrl(i2s, 1);
428
429 local_irq_restore(irqs);
faf907c7
SL		 430
431 /*
432 * Load the next buffer to DMA to meet the reqirement
433 * of the auto reload mechanism of S3C24XX.
434 * This call won't bother S3C64XX.
435 */
fd23b7de 436 s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
faf907c7 437
dc85447b
BD		 438 break;
439
440 case SNDRV_PCM_TRIGGER_STOP:
441 case SNDRV_PCM_TRIGGER_SUSPEND:
442 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
443 local_irq_save(irqs);
444
445 if (capture)
446 s3c2412_snd_rxctrl(i2s, 0);
447 else
448 s3c2412_snd_txctrl(i2s, 0);
449
450 local_irq_restore(irqs);
451 break;
452 default:
453 ret = -EINVAL;
454 break;
455 }
456
457exit_err:
458 return ret;
459}
460
461/*
462 * Set S3C2412 Clock dividers
463 */
464static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
465 int div_id, int div)
466{
467 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
468 u32 reg;
469
ee7d4767 470 pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
dc85447b
BD		 471
472 switch (div_id) {
473 case S3C_I2SV2_DIV_BCLK:
51c6ab13
JB		 474 switch (div) {
475 case 16:
476 div = S3C2412_IISMOD_BCLK_16FS;
477 break;
fd5ad654 478
51c6ab13
JB		 479 case 32:
480 div = S3C2412_IISMOD_BCLK_32FS;
481 break;
fd5ad654 482
51c6ab13
JB		 483 case 24:
484 div = S3C2412_IISMOD_BCLK_24FS;
485 break;
fd5ad654 486
51c6ab13
JB		 487 case 48:
488 div = S3C2412_IISMOD_BCLK_48FS;
489 break;
fd5ad654 490
51c6ab13
JB		 491 default:
492 return -EINVAL;
fd5ad654
J		 493 }
494
dc85447b
BD		 495 reg = readl(i2s->regs + S3C2412_IISMOD);
496 reg &= ~S3C2412_IISMOD_BCLK_MASK;
497 writel(reg | div, i2s->regs + S3C2412_IISMOD);
498
ee7d4767 499 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 500 break;
501
502 case S3C_I2SV2_DIV_RCLK:
51c6ab13
JB		 503 switch (div) {
504 case 256:
505 div = S3C2412_IISMOD_RCLK_256FS;
506 break;
dc85447b 507
51c6ab13
JB		 508 case 384:
509 div = S3C2412_IISMOD_RCLK_384FS;
510 break;
dc85447b 511
51c6ab13
JB		 512 case 512:
513 div = S3C2412_IISMOD_RCLK_512FS;
514 break;
dc85447b 515
51c6ab13
JB		 516 case 768:
517 div = S3C2412_IISMOD_RCLK_768FS;
518 break;
dc85447b 519
51c6ab13
JB		 520 default:
521 return -EINVAL;
dc85447b
BD		 522 }
523
524 reg = readl(i2s->regs + S3C2412_IISMOD);
525 reg &= ~S3C2412_IISMOD_RCLK_MASK;
526 writel(reg | div, i2s->regs + S3C2412_IISMOD);
ee7d4767 527 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b
BD		 528 break;
529
530 case S3C_I2SV2_DIV_PRESCALER:
531 if (div >= 0) {
532 writel((div << 8) | S3C2412_IISPSR_PSREN,
533 i2s->regs + S3C2412_IISPSR);
534 } else {
535 writel(0x0, i2s->regs + S3C2412_IISPSR);
536 }
ee7d4767 537 pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
dc85447b
BD		 538 break;
539
540 default:
541 return -EINVAL;
542 }
543
544 return 0;
545}
546
1ca75780
MB		 547static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream,
548 struct snd_soc_dai *dai)
549{
550 struct s3c_i2sv2_info *i2s = to_info(dai);
551 u32 reg = readl(i2s->regs + S3C2412_IISFIC);
552 snd_pcm_sframes_t delay;
553
554 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
555 delay = S3C2412_IISFIC_TXCOUNT(reg);
556 else
557 delay = S3C2412_IISFIC_RXCOUNT(reg);
558
559 return delay;
560}
561
57282427
JB		 562struct clk *s3c_i2sv2_get_clock(struct snd_soc_dai *cpu_dai)
563{
564 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
565 u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
566
567 if (iismod & S3C2412_IISMOD_IMS_SYSMUX)
568 return i2s->iis_cclk;
569 else
570 return i2s->iis_pclk;
571}
572EXPORT_SYMBOL_GPL(s3c_i2sv2_get_clock);
573
dc85447b
BD		 574/* default table of all avaialable root fs divisors */
575static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
576
1d2b7ae9
BD		 577int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
578 unsigned int *fstab,
579 unsigned int rate, struct clk *clk)
dc85447b
BD		 580{
581 unsigned long clkrate = clk_get_rate(clk);
582 unsigned int div;
583 unsigned int fsclk;
584 unsigned int actual;
585 unsigned int fs;
586 unsigned int fsdiv;
587 signed int deviation = 0;
588 unsigned int best_fs = 0;
589 unsigned int best_div = 0;
590 unsigned int best_rate = 0;
591 unsigned int best_deviation = INT_MAX;
592
af3ea7bd
MB		 593 pr_debug("Input clock rate %ldHz\n", clkrate);
594
dc85447b
BD		 595 if (fstab == NULL)
596 fstab = iis_fs_tab;
597
598 for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
599 fsdiv = iis_fs_tab[fs];
600
601 fsclk = clkrate / fsdiv;
602 div = fsclk / rate;
603
604 if ((fsclk % rate) > (rate / 2))
605 div++;
606
607 if (div <= 1)
608 continue;
609
610 actual = clkrate / (fsdiv * div);
611 deviation = actual - rate;
612
449bd54d 613 printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
dc85447b
BD		 614 fsdiv, div, actual, deviation);
615
616 deviation = abs(deviation);
617
618 if (deviation < best_deviation) {
619 best_fs = fsdiv;
620 best_div = div;
621 best_rate = actual;
622 best_deviation = deviation;
623 }
624
625 if (deviation == 0)
626 break;
627 }
628
449bd54d 629 printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
dc85447b
BD		 630 best_fs, best_div, best_rate);
631
632 info->fs_div = best_fs;
633 info->clk_div = best_div;
634
635 return 0;
636}
1d2b7ae9 637EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
dc85447b 638
f0fba2ad 639int s3c_i2sv2_probe(struct snd_soc_dai *dai,
dc85447b
BD		 640 struct s3c_i2sv2_info *i2s,
641 unsigned long base)
642{
f0fba2ad 643 struct device *dev = dai->dev;
07736d48 644 unsigned int iismod;
dc85447b
BD		 645
646 i2s->dev = dev;
647
648 /* record our i2s structure for later use in the callbacks */
f0fba2ad 649 snd_soc_dai_set_drvdata(dai, i2s);
c86bde54 650
dc85447b
BD		 651 i2s->regs = ioremap(base, 0x100);
652 if (i2s->regs == NULL) {
653 dev_err(dev, "cannot ioremap registers\n");
654 return -ENXIO;
655 }
656
657 i2s->iis_pclk = clk_get(dev, "iis");
fd5ad654 658 if (IS_ERR(i2s->iis_pclk)) {
b52a5195 659 dev_err(dev, "failed to get iis_clock\n");
dc85447b
BD		 660 iounmap(i2s->regs);
661 return -ENOENT;
662 }
663
664 clk_enable(i2s->iis_pclk);
665
07736d48
MB		 666 /* Mark ourselves as in TXRX mode so we can run through our cleanup
667 * process without warnings. */
668 iismod = readl(i2s->regs + S3C2412_IISMOD);
669 iismod |= S3C2412_IISMOD_MODE_TXRX;
670 writel(iismod, i2s->regs + S3C2412_IISMOD);
dc85447b
BD		 671 s3c2412_snd_txctrl(i2s, 0);
672 s3c2412_snd_rxctrl(i2s, 0);
673
674 return 0;
675}
dc85447b
BD		 676EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
677
678#ifdef CONFIG_PM
679static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
680{
681 struct s3c_i2sv2_info *i2s = to_info(dai);
682 u32 iismod;
683
684 if (dai->active) {
685 i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
686 i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
687 i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
688
689 /* some basic suspend checks */
690
691 iismod = readl(i2s->regs + S3C2412_IISMOD);
692
693 if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
694 pr_warning("%s: RXDMA active?\n", __func__);
695
696 if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
697 pr_warning("%s: TXDMA active?\n", __func__);
698
699 if (iismod & S3C2412_IISCON_IIS_ACTIVE)
700 pr_warning("%s: IIS active\n", __func__);
701 }
702
703 return 0;
704}
705
706static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
707{
708 struct s3c_i2sv2_info *i2s = to_info(dai);
709
710 pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
711 dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
712
713 if (dai->active) {
714 writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
715 writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
716 writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
717
718 writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
719 i2s->regs + S3C2412_IISFIC);
720
721 ndelay(250);
722 writel(0x0, i2s->regs + S3C2412_IISFIC);
723 }
724
725 return 0;
726}
727#else
728#define s3c2412_i2s_suspend NULL
729#define s3c2412_i2s_resume NULL
730#endif
731
eca3b01d
KM		 732int s3c_i2sv2_register_component(struct device *dev, int id,
733 struct snd_soc_component_driver *cmp_drv,
734 struct snd_soc_dai_driver *dai_drv)
dc85447b 735{
f0fba2ad 736 struct snd_soc_dai_ops *ops = drv->ops;
3715c6aa
BD		 737
738 ops->trigger = s3c2412_i2s_trigger;
9c9b1257
JB		 739 if (!ops->hw_params)
740 ops->hw_params = s3c_i2sv2_hw_params;
3715c6aa
BD		 741 ops->set_fmt = s3c2412_i2s_set_fmt;
742 ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
8a7c2518 743 ops->set_sysclk = s3c_i2sv2_set_sysclk;
dc85447b 744
1ca75780
MB		 745 /* Allow overriding by (for example) IISv4 */
746 if (!ops->delay)
08226614 747 ops->delay = s3c2412_i2s_delay;
1ca75780 748
f0fba2ad
LG		 749 drv->suspend = s3c2412_i2s_suspend;
750 drv->resume = s3c2412_i2s_resume;
dc85447b 751
eca3b01d 752 return snd_soc_register_component(dev, cmp_drv, dai_drv, 1);
dc85447b 753}
eca3b01d 754EXPORT_SYMBOL_GPL(s3c_i2sv2_register_component);
a396e32e
MB		 755
756MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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