[deliverable/linux.git] / sound / soc / samsung / s3c24xx-i2s.c

/*
 * s3c24xx-i2s.c  --  ALSA Soc Audio Layer
 *
 * (c) 2006 Wolfson Microelectronics PLC.
 * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
 *
 * Copyright 2004-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */

#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/module.h>

#include <sound/soc.h>
#include <sound/pcm_params.h>

#include <mach/dma.h>
#include <mach/gpio-samsung.h>
#include <plat/gpio-cfg.h>
#include "regs-iis.h"

#include "dma.h"
#include "s3c24xx-i2s.h"

static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_out = {
	.client		=
		(struct s3c_dma_client *)&s3c24xx_i2s_pcm_stereo_out,
	.channel	= DMACH_I2S_OUT,
	.ch_name	= "tx",
	.dma_size	= 2,
};

static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_in = {
	.client		=
		(struct s3c_dma_client *)&s3c24xx_i2s_pcm_stereo_in,
	.channel	= DMACH_I2S_IN,
	.ch_name	= "rx",
	.dma_size	= 2,
};

struct s3c24xx_i2s_info {
	void __iomem	*regs;
	struct clk	*iis_clk;
	u32		iiscon;
	u32		iismod;
	u32		iisfcon;
	u32		iispsr;
};
static struct s3c24xx_i2s_info s3c24xx_i2s;

static void s3c24xx_snd_txctrl(int on)
{
	u32 iisfcon;
	u32 iiscon;
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);

	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);

	if (on) {
		iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
		iiscon  |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
		iiscon  &= ~S3C2410_IISCON_TXIDLE;
		iismod  |= S3C2410_IISMOD_TXMODE;

		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
	} else {
		/* note, we have to disable the FIFOs otherwise bad things
		 * seem to happen when the DMA stops. According to the
		 * Samsung supplied kernel, this should allow the DMA
		 * engine and FIFOs to reset. If this isn't allowed, the
		 * DMA engine will simply freeze randomly.
		 */

		iisfcon &= ~S3C2410_IISFCON_TXENABLE;
		iisfcon &= ~S3C2410_IISFCON_TXDMA;
		iiscon  |=  S3C2410_IISCON_TXIDLE;
		iiscon  &= ~S3C2410_IISCON_TXDMAEN;
		iismod  &= ~S3C2410_IISMOD_TXMODE;

		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
	}

	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
}

static void s3c24xx_snd_rxctrl(int on)
{
	u32 iisfcon;
	u32 iiscon;
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);

	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);

	if (on) {
		iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
		iiscon  |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
		iiscon  &= ~S3C2410_IISCON_RXIDLE;
		iismod  |= S3C2410_IISMOD_RXMODE;

		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
	} else {
		/* note, we have to disable the FIFOs otherwise bad things
		 * seem to happen when the DMA stops. According to the
		 * Samsung supplied kernel, this should allow the DMA
		 * engine and FIFOs to reset. If this isn't allowed, the
		 * DMA engine will simply freeze randomly.
		 */

		iisfcon &= ~S3C2410_IISFCON_RXENABLE;
		iisfcon &= ~S3C2410_IISFCON_RXDMA;
		iiscon  |= S3C2410_IISCON_RXIDLE;
		iiscon  &= ~S3C2410_IISCON_RXDMAEN;
		iismod  &= ~S3C2410_IISMOD_RXMODE;

		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
	}

	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
}

/*
 * Wait for the LR signal to allow synchronisation to the L/R clock
 * from the codec. May only be needed for slave mode.
 */
static int s3c24xx_snd_lrsync(void)
{
	u32 iiscon;
	int timeout = 50; /* 5ms */

	pr_debug("Entered %s\n", __func__);

	while (1) {
		iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
		if (iiscon & S3C2410_IISCON_LRINDEX)
			break;

		if (!timeout--)
			return -ETIMEDOUT;
		udelay(100);
	}

	return 0;
}

/*
 * Check whether CPU is the master or slave
 */
static inline int s3c24xx_snd_is_clkmaster(void)
{
	pr_debug("Entered %s\n", __func__);

	return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
}

/*
 * Set S3C24xx I2S DAI format
 */
static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
		unsigned int fmt)
{
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params r: IISMOD: %x \n", iismod);

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		iismod |= S3C2410_IISMOD_SLAVE;
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
		iismod &= ~S3C2410_IISMOD_SLAVE;
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_LEFT_J:
		iismod |= S3C2410_IISMOD_MSB;
		break;
	case SND_SOC_DAIFMT_I2S:
		iismod &= ~S3C2410_IISMOD_MSB;
		break;
	default:
		return -EINVAL;
	}

	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params w: IISMOD: %x \n", iismod);
	return 0;
}

static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct snd_dmaengine_dai_dma_data *dma_data;
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	dma_data = snd_soc_dai_get_dma_data(dai, substream);

	/* Working copies of register */
	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params r: IISMOD: %x\n", iismod);

	switch (params_width(params)) {
	case 8:
		iismod &= ~S3C2410_IISMOD_16BIT;
		dma_data->addr_width = 1;
		break;
	case 16:
		iismod |= S3C2410_IISMOD_16BIT;
		dma_data->addr_width = 2;
		break;
	default:
		return -EINVAL;
	}

	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params w: IISMOD: %x\n", iismod);
	return 0;
}

static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	int ret = 0;

	pr_debug("Entered %s\n", __func__);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (!s3c24xx_snd_is_clkmaster()) {
			ret = s3c24xx_snd_lrsync();
			if (ret)
				goto exit_err;
		}

		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			s3c24xx_snd_rxctrl(1);
		else
			s3c24xx_snd_txctrl(1);

		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			s3c24xx_snd_rxctrl(0);
		else
			s3c24xx_snd_txctrl(0);
		break;
	default:
		ret = -EINVAL;
		break;
	}

exit_err:
	return ret;
}

/*
 * Set S3C24xx Clock source
 */
static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
	int clk_id, unsigned int freq, int dir)
{
	u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);

	pr_debug("Entered %s\n", __func__);

	iismod &= ~S3C2440_IISMOD_MPLL;

	switch (clk_id) {
	case S3C24XX_CLKSRC_PCLK:
		break;
	case S3C24XX_CLKSRC_MPLL:
		iismod |= S3C2440_IISMOD_MPLL;
		break;
	default:
		return -EINVAL;
	}

	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	return 0;
}

/*
 * Set S3C24xx Clock dividers
 */
static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
	int div_id, int div)
{
	u32 reg;

	pr_debug("Entered %s\n", __func__);

	switch (div_id) {
	case S3C24XX_DIV_BCLK:
		reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
		writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
		break;
	case S3C24XX_DIV_MCLK:
		reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
		writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
		break;
	case S3C24XX_DIV_PRESCALER:
		writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
		reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
		writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

/*
 * To avoid duplicating clock code, allow machine driver to
 * get the clockrate from here.
 */
u32 s3c24xx_i2s_get_clockrate(void)
{
	return clk_get_rate(s3c24xx_i2s.iis_clk);
}
EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);

static int s3c24xx_i2s_probe(struct snd_soc_dai *dai)
{
	pr_debug("Entered %s\n", __func__);

	samsung_asoc_init_dma_data(dai, &s3c24xx_i2s_pcm_stereo_out,
		&s3c24xx_i2s_pcm_stereo_in);

	s3c24xx_i2s.iis_clk = devm_clk_get(dai->dev, "iis");
	if (IS_ERR(s3c24xx_i2s.iis_clk)) {
		pr_err("failed to get iis_clock\n");
		return PTR_ERR(s3c24xx_i2s.iis_clk);
	}
	clk_enable(s3c24xx_i2s.iis_clk);

	/* Configure the I2S pins (GPE0...GPE4) in correct mode */
	s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
			      S3C_GPIO_PULL_NONE);

	writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);

	s3c24xx_snd_txctrl(0);
	s3c24xx_snd_rxctrl(0);

	return 0;
}

#ifdef CONFIG_PM
static int s3c24xx_i2s_suspend(struct snd_soc_dai *cpu_dai)
{
	pr_debug("Entered %s\n", __func__);

	s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);

	clk_disable(s3c24xx_i2s.iis_clk);

	return 0;
}

static int s3c24xx_i2s_resume(struct snd_soc_dai *cpu_dai)
{
	pr_debug("Entered %s\n", __func__);
	clk_enable(s3c24xx_i2s.iis_clk);

	writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);

	return 0;
}
#else
#define s3c24xx_i2s_suspend NULL
#define s3c24xx_i2s_resume NULL
#endif


#define S3C24XX_I2S_RATES \
	(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
	SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
	SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)

static const struct snd_soc_dai_ops s3c24xx_i2s_dai_ops = {
	.trigger	= s3c24xx_i2s_trigger,
	.hw_params	= s3c24xx_i2s_hw_params,
	.set_fmt	= s3c24xx_i2s_set_fmt,
	.set_clkdiv	= s3c24xx_i2s_set_clkdiv,
	.set_sysclk	= s3c24xx_i2s_set_sysclk,
};

static struct snd_soc_dai_driver s3c24xx_i2s_dai = {
	.probe = s3c24xx_i2s_probe,
	.suspend = s3c24xx_i2s_suspend,
	.resume = s3c24xx_i2s_resume,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = S3C24XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = S3C24XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = &s3c24xx_i2s_dai_ops,
};

static const struct snd_soc_component_driver s3c24xx_i2s_component = {
	.name		= "s3c24xx-i2s",
};

static int s3c24xx_iis_dev_probe(struct platform_device *pdev)
{
	int ret = 0;
	struct resource *res;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "Can't get IO resource.\n");
		return -ENOENT;
	}
	s3c24xx_i2s.regs = devm_ioremap_resource(&pdev->dev, res);
	if (s3c24xx_i2s.regs == NULL)
		return -ENXIO;

	s3c24xx_i2s_pcm_stereo_out.dma_addr = res->start + S3C2410_IISFIFO;
	s3c24xx_i2s_pcm_stereo_in.dma_addr = res->start + S3C2410_IISFIFO;

	ret = devm_snd_soc_register_component(&pdev->dev,
			&s3c24xx_i2s_component, &s3c24xx_i2s_dai, 1);
	if (ret) {
		pr_err("failed to register the dai\n");
		return ret;
	}

	ret = samsung_asoc_dma_platform_register(&pdev->dev);
	if (ret)
		pr_err("failed to register the dma: %d\n", ret);

	return ret;
}

static struct platform_driver s3c24xx_iis_driver = {
	.probe  = s3c24xx_iis_dev_probe,
	.driver = {
		.name = "s3c24xx-iis",
		.owner = THIS_MODULE,
	},
};

module_platform_driver(s3c24xx_iis_driver);

/* Module information */
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:s3c24xx-iis");
Commit	Line	Data
c1422a66 BD	1	/*
	2	* s3c24xx-i2s.c -- ALSA Soc Audio Layer
	3	*
	4	* (c) 2006 Wolfson Microelectronics PLC.
	5	* Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
	6	*
c8efef17	7	* Copyright 2004-2005 Simtec Electronics
c1422a66 BD	8	* http://armlinux.simtec.co.uk/
	9	* Ben Dooks <ben@simtec.co.uk>
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or (at your
	14	* option) any later version.
c1422a66 BD	15	*/
c1422a66 BD	16
c1422a66 BD	17	#include <linux/delay.h>
c1422a66 BD	18	#include <linux/clk.h>
40efc15f	19	#include <linux/io.h>
ec976d6e	20	#include <linux/gpio.h>
da155d5b	21	#include <linux/module.h>
ec976d6e	22
c1422a66	23	#include <sound/soc.h>
0378b6ac	24	#include <sound/pcm_params.h>
c1422a66	25
a09e64fb	26	#include <mach/dma.h>
abffae64 SK	27	#include <mach/gpio-samsung.h>
abffae64 SK	28	#include <plat/gpio-cfg.h>
5d229ce5	29	#include "regs-iis.h"
aa9673cf	30
4b640cf3	31	#include "dma.h"
c1422a66 BD	32	#include "s3c24xx-i2s.h"
c1422a66 BD	33
faa31776	34	static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_out = {
87b132bc VK	35	.client =
87b132bc VK	36	(struct s3c_dma_client *)&s3c24xx_i2s_pcm_stereo_out,
c1422a66	37	.channel = DMACH_I2S_OUT,
87b132bc	38	.ch_name = "tx",
e81208fe	39	.dma_size = 2,
c1422a66 BD	40	};
c1422a66 BD	41
faa31776	42	static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_in = {
87b132bc VK	43	.client =
87b132bc VK	44	(struct s3c_dma_client *)&s3c24xx_i2s_pcm_stereo_in,
c1422a66	45	.channel = DMACH_I2S_IN,
87b132bc	46	.ch_name = "rx",
e81208fe	47	.dma_size = 2,
c1422a66 BD	48	};
	49
	50	struct s3c24xx_i2s_info {
	51	void __iomem *regs;
	52	struct clk *iis_clk;
5cd919a2 GG	53	u32 iiscon;
	54	u32 iismod;
	55	u32 iisfcon;
	56	u32 iispsr;
c1422a66 BD	57	};
	58	static struct s3c24xx_i2s_info s3c24xx_i2s;
	59
	60	static void s3c24xx_snd_txctrl(int on)
	61	{
	62	u32 iisfcon;
	63	u32 iiscon;
	64	u32 iismod;
	65
ee7d4767	66	pr_debug("Entered %s\n", __func__);
c1422a66 BD	67
	68	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	69	iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	70	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	71
5314adc3	72	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	73
	74	if (on) {
	75	iisfcon \|= S3C2410_IISFCON_TXDMA \| S3C2410_IISFCON_TXENABLE;
	76	iiscon \|= S3C2410_IISCON_TXDMAEN \| S3C2410_IISCON_IISEN;
	77	iiscon &= ~S3C2410_IISCON_TXIDLE;
	78	iismod \|= S3C2410_IISMOD_TXMODE;
	79
	80	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	81	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	82	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	83	} else {
	84	/* note, we have to disable the FIFOs otherwise bad things
	85	* seem to happen when the DMA stops. According to the
	86	* Samsung supplied kernel, this should allow the DMA
	87	* engine and FIFOs to reset. If this isn't allowed, the
	88	* DMA engine will simply freeze randomly.
	89	*/
	90
	91	iisfcon &= ~S3C2410_IISFCON_TXENABLE;
	92	iisfcon &= ~S3C2410_IISFCON_TXDMA;
	93	iiscon \|= S3C2410_IISCON_TXIDLE;
	94	iiscon &= ~S3C2410_IISCON_TXDMAEN;
	95	iismod &= ~S3C2410_IISMOD_TXMODE;
	96
	97	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	98	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	99	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	100	}
	101
5314adc3	102	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	103	}
	104
	105	static void s3c24xx_snd_rxctrl(int on)
	106	{
	107	u32 iisfcon;
	108	u32 iiscon;
	109	u32 iismod;
	110
ee7d4767	111	pr_debug("Entered %s\n", __func__);
c1422a66 BD	112
	113	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	114	iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	115	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	116
5314adc3	117	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	118
	119	if (on) {
	120	iisfcon \|= S3C2410_IISFCON_RXDMA \| S3C2410_IISFCON_RXENABLE;
	121	iiscon \|= S3C2410_IISCON_RXDMAEN \| S3C2410_IISCON_IISEN;
	122	iiscon &= ~S3C2410_IISCON_RXIDLE;
	123	iismod \|= S3C2410_IISMOD_RXMODE;
	124
	125	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	126	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	127	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	128	} else {
	129	/* note, we have to disable the FIFOs otherwise bad things
	130	* seem to happen when the DMA stops. According to the
	131	* Samsung supplied kernel, this should allow the DMA
	132	* engine and FIFOs to reset. If this isn't allowed, the
	133	* DMA engine will simply freeze randomly.
	134	*/
	135
0015e7d1 MB	136	iisfcon &= ~S3C2410_IISFCON_RXENABLE;
	137	iisfcon &= ~S3C2410_IISFCON_RXDMA;
	138	iiscon \|= S3C2410_IISCON_RXIDLE;
	139	iiscon &= ~S3C2410_IISCON_RXDMAEN;
c1422a66 BD	140	iismod &= ~S3C2410_IISMOD_RXMODE;
	141
	142	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	143	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	144	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	145	}
	146
5314adc3	147	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	148	}
	149
	150	/*
	151	* Wait for the LR signal to allow synchronisation to the L/R clock
	152	* from the codec. May only be needed for slave mode.
	153	*/
	154	static int s3c24xx_snd_lrsync(void)
	155	{
	156	u32 iiscon;
33e5b222	157	int timeout = 50; /* 5ms */
c1422a66	158
ee7d4767	159	pr_debug("Entered %s\n", __func__);
c1422a66 BD	160
	161	while (1) {
	162	iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	163	if (iiscon & S3C2410_IISCON_LRINDEX)
	164	break;
	165
33e5b222	166	if (!timeout--)
c1422a66	167	return -ETIMEDOUT;
33e5b222	168	udelay(100);
c1422a66 BD	169	}
	170
	171	return 0;
	172	}
	173
	174	/*
	175	* Check whether CPU is the master or slave
	176	*/
	177	static inline int s3c24xx_snd_is_clkmaster(void)
	178	{
ee7d4767	179	pr_debug("Entered %s\n", __func__);
c1422a66 BD	180
	181	return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
	182	}
	183
	184	/*
	185	* Set S3C24xx I2S DAI format
	186	*/
1992a6fb	187	static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
c1422a66 BD	188	unsigned int fmt)
	189	{
	190	u32 iismod;
	191
ee7d4767	192	pr_debug("Entered %s\n", __func__);
c1422a66 BD	193
c1422a66 BD	194	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	195	pr_debug("hw_params r: IISMOD: %x \n", iismod);
c1422a66 BD	196
	197	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	198	case SND_SOC_DAIFMT_CBM_CFM:
	199	iismod \|= S3C2410_IISMOD_SLAVE;
	200	break;
	201	case SND_SOC_DAIFMT_CBS_CFS:
2c36eecf	202	iismod &= ~S3C2410_IISMOD_SLAVE;
c1422a66 BD	203	break;
	204	default:
	205	return -EINVAL;
	206	}
	207
	208	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	209	case SND_SOC_DAIFMT_LEFT_J:
	210	iismod \|= S3C2410_IISMOD_MSB;
	211	break;
	212	case SND_SOC_DAIFMT_I2S:
2c36eecf	213	iismod &= ~S3C2410_IISMOD_MSB;
c1422a66 BD	214	break;
	215	default:
	216	return -EINVAL;
	217	}
	218
	219	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	220	pr_debug("hw_params w: IISMOD: %x \n", iismod);
c1422a66 BD	221	return 0;
	222	}
	223
	224	static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	225	struct snd_pcm_hw_params *params,
dee89c4d MB	226	struct snd_soc_dai *dai)
c1422a66	227	{
87b132bc	228	struct snd_dmaengine_dai_dma_data *dma_data;
c1422a66 BD	229	u32 iismod;
c1422a66 BD	230
ee7d4767	231	pr_debug("Entered %s\n", __func__);
c1422a66	232
87b132bc	233	dma_data = snd_soc_dai_get_dma_data(dai, substream);
c1422a66 BD	234
	235	/* Working copies of register */
	236	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	237	pr_debug("hw_params r: IISMOD: %x\n", iismod);
c1422a66	238
88ce1465 TB	239	switch (params_width(params)) {
88ce1465 TB	240	case 8:
53599bbc	241	iismod &= ~S3C2410_IISMOD_16BIT;
87b132bc	242	dma_data->addr_width = 1;
c1422a66	243	break;
88ce1465	244	case 16:
c1422a66	245	iismod \|= S3C2410_IISMOD_16BIT;
87b132bc	246	dma_data->addr_width = 2;
c1422a66	247	break;
53599bbc CP	248	default:
53599bbc CP	249	return -EINVAL;
c1422a66 BD	250	}
	251
	252	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	253	pr_debug("hw_params w: IISMOD: %x\n", iismod);
c1422a66 BD	254	return 0;
	255	}
	256
dee89c4d MB	257	static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
dee89c4d MB	258	struct snd_soc_dai *dai)
c1422a66 BD	259	{
	260	int ret = 0;
	261
ee7d4767	262	pr_debug("Entered %s\n", __func__);
c1422a66 BD	263
	264	switch (cmd) {
	265	case SNDRV_PCM_TRIGGER_START:
	266	case SNDRV_PCM_TRIGGER_RESUME:
	267	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	268	if (!s3c24xx_snd_is_clkmaster()) {
	269	ret = s3c24xx_snd_lrsync();
	270	if (ret)
	271	goto exit_err;
	272	}
	273
	274	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	275	s3c24xx_snd_rxctrl(1);
	276	else
	277	s3c24xx_snd_txctrl(1);
faf907c7	278
c1422a66 BD	279	break;
	280	case SNDRV_PCM_TRIGGER_STOP:
	281	case SNDRV_PCM_TRIGGER_SUSPEND:
	282	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	283	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	284	s3c24xx_snd_rxctrl(0);
	285	else
	286	s3c24xx_snd_txctrl(0);
	287	break;
	288	default:
	289	ret = -EINVAL;
	290	break;
	291	}
	292
	293	exit_err:
	294	return ret;
	295	}
	296
	297	/*
	298	* Set S3C24xx Clock source
	299	*/
1992a6fb	300	static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
c1422a66 BD	301	int clk_id, unsigned int freq, int dir)
	302	{
	303	u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	304
ee7d4767	305	pr_debug("Entered %s\n", __func__);
c1422a66 BD	306
	307	iismod &= ~S3C2440_IISMOD_MPLL;
	308
	309	switch (clk_id) {
	310	case S3C24XX_CLKSRC_PCLK:
	311	break;
	312	case S3C24XX_CLKSRC_MPLL:
	313	iismod \|= S3C2440_IISMOD_MPLL;
	314	break;
	315	default:
	316	return -EINVAL;
	317	}
	318
	319	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	320	return 0;
	321	}
	322
	323	/*
	324	* Set S3C24xx Clock dividers
	325	*/
1992a6fb	326	static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
c1422a66 BD	327	int div_id, int div)
	328	{
	329	u32 reg;
	330
ee7d4767	331	pr_debug("Entered %s\n", __func__);
c1422a66 BD	332
c1422a66 BD	333	switch (div_id) {
82fb159a	334	case S3C24XX_DIV_BCLK:
c1422a66 BD	335	reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
	336	writel(reg \| div, s3c24xx_i2s.regs + S3C2410_IISMOD);
	337	break;
82fb159a	338	case S3C24XX_DIV_MCLK:
c1422a66 BD	339	reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
	340	writel(reg \| div, s3c24xx_i2s.regs + S3C2410_IISMOD);
	341	break;
	342	case S3C24XX_DIV_PRESCALER:
	343	writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
	344	reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	345	writel(reg \| S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
	346	break;
	347	default:
	348	return -EINVAL;
	349	}
	350
	351	return 0;
	352	}
	353
	354	/*
	355	* To avoid duplicating clock code, allow machine driver to
	356	* get the clockrate from here.
	357	*/
	358	u32 s3c24xx_i2s_get_clockrate(void)
	359	{
	360	return clk_get_rate(s3c24xx_i2s.iis_clk);
	361	}
	362	EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
	363
f0fba2ad	364	static int s3c24xx_i2s_probe(struct snd_soc_dai *dai)
c1422a66	365	{
ee7d4767	366	pr_debug("Entered %s\n", __func__);
c1422a66	367
87b132bc VK	368	samsung_asoc_init_dma_data(dai, &s3c24xx_i2s_pcm_stereo_out,
87b132bc VK	369	&s3c24xx_i2s_pcm_stereo_in);
c1422a66	370
87b132bc	371	s3c24xx_i2s.iis_clk = devm_clk_get(dai->dev, "iis");
7803e329	372	if (IS_ERR(s3c24xx_i2s.iis_clk)) {
b52a5195	373	pr_err("failed to get iis_clock\n");
7803e329	374	return PTR_ERR(s3c24xx_i2s.iis_clk);
c1422a66 BD	375	}
	376	clk_enable(s3c24xx_i2s.iis_clk);
	377
0eed8a18 SN	378	/* Configure the I2S pins (GPE0...GPE4) in correct mode */
	379	s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
	380	S3C_GPIO_PULL_NONE);
c1422a66 BD	381
	382	writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
	383
	384	s3c24xx_snd_txctrl(0);
	385	s3c24xx_snd_rxctrl(0);
	386
	387	return 0;
	388	}
	389
5cd919a2	390	#ifdef CONFIG_PM
dc7d7b83	391	static int s3c24xx_i2s_suspend(struct snd_soc_dai *cpu_dai)
5cd919a2	392	{
ee7d4767	393	pr_debug("Entered %s\n", __func__);
40920307	394
5cd919a2 GG	395	s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	396	s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	397	s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	398	s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);
	399
	400	clk_disable(s3c24xx_i2s.iis_clk);
	401
	402	return 0;
	403	}
	404
dc7d7b83	405	static int s3c24xx_i2s_resume(struct snd_soc_dai *cpu_dai)
5cd919a2	406	{
ee7d4767	407	pr_debug("Entered %s\n", __func__);
5cd919a2 GG	408	clk_enable(s3c24xx_i2s.iis_clk);
	409
	410	writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	411	writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	412	writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	413	writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);
	414
	415	return 0;
	416	}
	417	#else
	418	#define s3c24xx_i2s_suspend NULL
	419	#define s3c24xx_i2s_resume NULL
	420	#endif
	421
	422
c1422a66 BD	423	#define S3C24XX_I2S_RATES \
	424	(SNDRV_PCM_RATE_8000 \| SNDRV_PCM_RATE_11025 \| SNDRV_PCM_RATE_16000 \| \
	425	SNDRV_PCM_RATE_22050 \| SNDRV_PCM_RATE_32000 \| SNDRV_PCM_RATE_44100 \| \
	426	SNDRV_PCM_RATE_48000 \| SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	427
85e7652d	428	static const struct snd_soc_dai_ops s3c24xx_i2s_dai_ops = {
6335d055 EM	429	.trigger = s3c24xx_i2s_trigger,
	430	.hw_params = s3c24xx_i2s_hw_params,
	431	.set_fmt = s3c24xx_i2s_set_fmt,
	432	.set_clkdiv = s3c24xx_i2s_set_clkdiv,
	433	.set_sysclk = s3c24xx_i2s_set_sysclk,
	434	};
	435
f0fba2ad	436	static struct snd_soc_dai_driver s3c24xx_i2s_dai = {
c1422a66	437	.probe = s3c24xx_i2s_probe,
5cd919a2 GG	438	.suspend = s3c24xx_i2s_suspend,
5cd919a2 GG	439	.resume = s3c24xx_i2s_resume,
c1422a66 BD	440	.playback = {
	441	.channels_min = 2,
	442	.channels_max = 2,
	443	.rates = S3C24XX_I2S_RATES,
	444	.formats = SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE,},
	445	.capture = {
	446	.channels_min = 2,
	447	.channels_max = 2,
	448	.rates = S3C24XX_I2S_RATES,
	449	.formats = SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE,},
6335d055	450	.ops = &s3c24xx_i2s_dai_ops,
c1422a66	451	};
f0fba2ad	452
5642ddff KM	453	static const struct snd_soc_component_driver s3c24xx_i2s_component = {
	454	.name = "s3c24xx-i2s",
	455	};
	456
fdca21ad	457	static int s3c24xx_iis_dev_probe(struct platform_device *pdev)
f0fba2ad	458	{
a08485d8	459	int ret = 0;
87b132bc VK	460	struct resource *res;
	461
	462	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	463	if (!res) {
	464	dev_err(&pdev->dev, "Can't get IO resource.\n");
	465	return -ENOENT;
	466	}
	467	s3c24xx_i2s.regs = devm_ioremap_resource(&pdev->dev, res);
	468	if (s3c24xx_i2s.regs == NULL)
	469	return -ENXIO;
	470
	471	s3c24xx_i2s_pcm_stereo_out.dma_addr = res->start + S3C2410_IISFIFO;
	472	s3c24xx_i2s_pcm_stereo_in.dma_addr = res->start + S3C2410_IISFIFO;
a08485d8	473
7253e354 TB	474	ret = devm_snd_soc_register_component(&pdev->dev,
7253e354 TB	475	&s3c24xx_i2s_component, &s3c24xx_i2s_dai, 1);
a08485d8 PV	476	if (ret) {
	477	pr_err("failed to register the dai\n");
	478	return ret;
	479	}
	480
06b10ff9	481	ret = samsung_asoc_dma_platform_register(&pdev->dev);
7253e354	482	if (ret)
a08485d8	483	pr_err("failed to register the dma: %d\n", ret);
a08485d8	484
a08485d8	485	return ret;
f0fba2ad LG	486	}
f0fba2ad LG	487
f0fba2ad LG	488	static struct platform_driver s3c24xx_iis_driver = {
f0fba2ad LG	489	.probe = s3c24xx_iis_dev_probe,
f0fba2ad LG	490	.driver = {
	491	.name = "s3c24xx-iis",
	492	.owner = THIS_MODULE,
	493	},
	494	};
c1422a66	495
e00c3f55	496	module_platform_driver(s3c24xx_iis_driver);
3f4b783c	497
c1422a66 BD	498	/* Module information */
	499	MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
	500	MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
	501	MODULE_LICENSE("GPL");
960d0697	502	MODULE_ALIAS("platform:s3c24xx-iis");