Commit | Line | Data |
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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
785d1c45 | 16 | #include <linux/pm_runtime.h> |
a4d7d550 | 17 | #include <linux/io.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
a4d7d550 | 19 | #include <sound/soc.h> |
a4d7d550 | 20 | #include <sound/sh_fsi.h> |
a4d7d550 KM |
21 | |
22 | #define DO_FMT 0x0000 | |
23 | #define DOFF_CTL 0x0004 | |
24 | #define DOFF_ST 0x0008 | |
25 | #define DI_FMT 0x000C | |
26 | #define DIFF_CTL 0x0010 | |
27 | #define DIFF_ST 0x0014 | |
28 | #define CKG1 0x0018 | |
29 | #define CKG2 0x001C | |
30 | #define DIDT 0x0020 | |
31 | #define DODT 0x0024 | |
32 | #define MUTE_ST 0x0028 | |
3bc28070 KM |
33 | #define OUT_SEL 0x0030 |
34 | #define REG_END OUT_SEL | |
cc780d38 | 35 | |
3bc28070 KM |
36 | #define A_MST_CTLR 0x0180 |
37 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
38 | #define CPU_INT_ST 0x01F4 |
39 | #define CPU_IEMSK 0x01F8 | |
40 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
41 | #define INT_ST 0x0200 |
42 | #define IEMSK 0x0204 | |
43 | #define IMSK 0x0208 | |
44 | #define MUTE 0x020C | |
45 | #define CLK_RST 0x0210 | |
46 | #define SOFT_RST 0x0214 | |
4a942b45 | 47 | #define FIFO_SZ 0x0218 |
3bc28070 | 48 | #define MREG_START A_MST_CTLR |
4a942b45 | 49 | #define MREG_END FIFO_SZ |
a4d7d550 KM |
50 | |
51 | /* DO_FMT */ | |
52 | /* DI_FMT */ | |
a7ffb52b KM |
53 | #define CR_MONO (0x0 << 4) |
54 | #define CR_MONO_D (0x1 << 4) | |
55 | #define CR_PCM (0x2 << 4) | |
56 | #define CR_I2S (0x3 << 4) | |
57 | #define CR_TDM (0x4 << 4) | |
58 | #define CR_TDM_D (0x5 << 4) | |
3bc28070 | 59 | #define CR_SPDIF 0x00100120 |
a4d7d550 KM |
60 | |
61 | /* DOFF_CTL */ | |
62 | /* DIFF_CTL */ | |
63 | #define IRQ_HALF 0x00100000 | |
64 | #define FIFO_CLR 0x00000001 | |
65 | ||
66 | /* DOFF_ST */ | |
67 | #define ERR_OVER 0x00000010 | |
68 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 69 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 70 | |
ccad7b44 KM |
71 | /* CKG1 */ |
72 | #define ACKMD_MASK 0x00007000 | |
73 | #define BPFMD_MASK 0x00000700 | |
74 | ||
3bc28070 KM |
75 | /* A/B MST_CTLR */ |
76 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
77 | #define SE (1 << 0) /* Fix the master clock */ | |
78 | ||
a4d7d550 KM |
79 | /* CLK_RST */ |
80 | #define B_CLK 0x00000010 | |
81 | #define A_CLK 0x00000001 | |
82 | ||
83 | /* INT_ST */ | |
84 | #define INT_B_IN (1 << 12) | |
85 | #define INT_B_OUT (1 << 8) | |
86 | #define INT_A_IN (1 << 4) | |
87 | #define INT_A_OUT (1 << 0) | |
88 | ||
feb58cff KM |
89 | /* SOFT_RST */ |
90 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
91 | #define PASR (1 << 8) /* Port A Software Reset */ | |
92 | #define IR (1 << 4) /* Interrupt Reset */ | |
93 | #define FSISR (1 << 0) /* Software Reset */ | |
94 | ||
4a942b45 KM |
95 | /* FIFO_SZ */ |
96 | #define OUT_SZ_MASK 0x7 | |
97 | #define BO_SZ_SHIFT 8 | |
98 | #define AO_SZ_SHIFT 0 | |
99 | ||
a4d7d550 KM |
100 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
101 | ||
102 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
103 | ||
5bfb9ad0 KM |
104 | /* |
105 | * FSI driver use below type name for variable | |
106 | * | |
107 | * xxx_len : data length | |
108 | * xxx_width : data width | |
109 | * xxx_offset : data offset | |
110 | * xxx_num : number of data | |
111 | */ | |
112 | ||
c8fe2574 KM |
113 | /* |
114 | * struct | |
115 | */ | |
a4d7d550 | 116 | |
a4d7d550 KM |
117 | struct fsi_priv { |
118 | void __iomem *base; | |
119 | struct snd_pcm_substream *substream; | |
71f6e064 | 120 | struct fsi_master *master; |
a4d7d550 | 121 | |
5bfb9ad0 KM |
122 | int fifo_max_num; |
123 | int chan_num; | |
a4d7d550 | 124 | |
5bfb9ad0 KM |
125 | int buff_offset; |
126 | int buff_len; | |
a4d7d550 | 127 | int period_len; |
5bfb9ad0 | 128 | int period_num; |
3bc28070 KM |
129 | |
130 | u32 mst_ctrl; | |
a4d7d550 KM |
131 | }; |
132 | ||
73b92c1f KM |
133 | struct fsi_core { |
134 | int ver; | |
135 | ||
cc780d38 KM |
136 | u32 int_st; |
137 | u32 iemsk; | |
138 | u32 imsk; | |
139 | }; | |
140 | ||
a4d7d550 KM |
141 | struct fsi_master { |
142 | void __iomem *base; | |
143 | int irq; | |
a4d7d550 KM |
144 | struct fsi_priv fsia; |
145 | struct fsi_priv fsib; | |
73b92c1f | 146 | struct fsi_core *core; |
a4d7d550 | 147 | struct sh_fsi_platform_info *info; |
8fc176d5 | 148 | spinlock_t lock; |
a4d7d550 KM |
149 | }; |
150 | ||
c8fe2574 KM |
151 | /* |
152 | * basic read write function | |
153 | */ | |
a4d7d550 | 154 | |
0f69d978 | 155 | static void __fsi_reg_write(u32 reg, u32 data) |
a4d7d550 KM |
156 | { |
157 | /* valid data area is 24bit */ | |
158 | data &= 0x00ffffff; | |
159 | ||
0f69d978 | 160 | __raw_writel(data, reg); |
a4d7d550 KM |
161 | } |
162 | ||
163 | static u32 __fsi_reg_read(u32 reg) | |
164 | { | |
0f69d978 | 165 | return __raw_readl(reg); |
a4d7d550 KM |
166 | } |
167 | ||
0f69d978 | 168 | static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data) |
a4d7d550 KM |
169 | { |
170 | u32 val = __fsi_reg_read(reg); | |
171 | ||
172 | val &= ~mask; | |
173 | val |= data & mask; | |
174 | ||
0f69d978 | 175 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
176 | } |
177 | ||
0f69d978 | 178 | static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data) |
a4d7d550 | 179 | { |
d7854147 KM |
180 | if (reg > REG_END) { |
181 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 182 | return; |
d7854147 | 183 | } |
a4d7d550 | 184 | |
0f69d978 | 185 | __fsi_reg_write((u32)(fsi->base + reg), data); |
a4d7d550 KM |
186 | } |
187 | ||
188 | static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg) | |
189 | { | |
d7854147 KM |
190 | if (reg > REG_END) { |
191 | pr_err("fsi: register access err (%s)\n", __func__); | |
a4d7d550 | 192 | return 0; |
d7854147 | 193 | } |
a4d7d550 KM |
194 | |
195 | return __fsi_reg_read((u32)(fsi->base + reg)); | |
196 | } | |
197 | ||
0f69d978 | 198 | static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data) |
a4d7d550 | 199 | { |
d7854147 KM |
200 | if (reg > REG_END) { |
201 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 202 | return; |
d7854147 | 203 | } |
a4d7d550 | 204 | |
0f69d978 | 205 | __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data); |
a4d7d550 KM |
206 | } |
207 | ||
0f69d978 | 208 | static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data) |
a4d7d550 | 209 | { |
8fc176d5 KM |
210 | unsigned long flags; |
211 | ||
a4d7d550 | 212 | if ((reg < MREG_START) || |
d7854147 KM |
213 | (reg > MREG_END)) { |
214 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 215 | return; |
d7854147 | 216 | } |
a4d7d550 | 217 | |
8fc176d5 | 218 | spin_lock_irqsave(&master->lock, flags); |
0f69d978 | 219 | __fsi_reg_write((u32)(master->base + reg), data); |
8fc176d5 | 220 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
221 | } |
222 | ||
71f6e064 | 223 | static u32 fsi_master_read(struct fsi_master *master, u32 reg) |
a4d7d550 | 224 | { |
8fc176d5 KM |
225 | u32 ret; |
226 | unsigned long flags; | |
227 | ||
a4d7d550 | 228 | if ((reg < MREG_START) || |
d7854147 KM |
229 | (reg > MREG_END)) { |
230 | pr_err("fsi: register access err (%s)\n", __func__); | |
a4d7d550 | 231 | return 0; |
d7854147 | 232 | } |
a4d7d550 | 233 | |
8fc176d5 KM |
234 | spin_lock_irqsave(&master->lock, flags); |
235 | ret = __fsi_reg_read((u32)(master->base + reg)); | |
236 | spin_unlock_irqrestore(&master->lock, flags); | |
237 | ||
238 | return ret; | |
a4d7d550 KM |
239 | } |
240 | ||
0f69d978 | 241 | static void fsi_master_mask_set(struct fsi_master *master, |
71f6e064 | 242 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 243 | { |
8fc176d5 KM |
244 | unsigned long flags; |
245 | ||
a4d7d550 | 246 | if ((reg < MREG_START) || |
d7854147 KM |
247 | (reg > MREG_END)) { |
248 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 249 | return; |
d7854147 | 250 | } |
a4d7d550 | 251 | |
8fc176d5 | 252 | spin_lock_irqsave(&master->lock, flags); |
0f69d978 | 253 | __fsi_reg_mask_set((u32)(master->base + reg), mask, data); |
8fc176d5 | 254 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
255 | } |
256 | ||
c8fe2574 KM |
257 | /* |
258 | * basic function | |
259 | */ | |
a4d7d550 | 260 | |
71f6e064 | 261 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 262 | { |
71f6e064 | 263 | return fsi->master; |
a4d7d550 KM |
264 | } |
265 | ||
266 | static int fsi_is_port_a(struct fsi_priv *fsi) | |
267 | { | |
71f6e064 KM |
268 | return fsi->master->base == fsi->base; |
269 | } | |
a4d7d550 | 270 | |
142e8174 | 271 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
272 | { |
273 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 274 | |
f0fba2ad | 275 | return rtd->cpu_dai; |
142e8174 KM |
276 | } |
277 | ||
278 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) | |
279 | { | |
280 | struct snd_soc_dai *dai = fsi_get_dai(substream); | |
f0fba2ad | 281 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 282 | |
f0fba2ad LG |
283 | if (dai->id == 0) |
284 | return &master->fsia; | |
285 | else | |
286 | return &master->fsib; | |
a4d7d550 KM |
287 | } |
288 | ||
289 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) | |
290 | { | |
291 | int is_porta = fsi_is_port_a(fsi); | |
71f6e064 | 292 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
293 | |
294 | return is_porta ? master->info->porta_flags : | |
295 | master->info->portb_flags; | |
296 | } | |
297 | ||
298 | static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play) | |
299 | { | |
300 | u32 mode; | |
301 | u32 flags = fsi_get_info_flags(fsi); | |
302 | ||
303 | mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE; | |
304 | ||
305 | /* return | |
306 | * 1 : master mode | |
307 | * 0 : slave mode | |
308 | */ | |
309 | ||
310 | return (mode & flags) != mode; | |
311 | } | |
312 | ||
313 | static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play) | |
314 | { | |
315 | int is_porta = fsi_is_port_a(fsi); | |
316 | u32 data; | |
317 | ||
318 | if (is_porta) | |
319 | data = is_play ? (1 << 0) : (1 << 4); | |
320 | else | |
321 | data = is_play ? (1 << 8) : (1 << 12); | |
322 | ||
323 | return data; | |
324 | } | |
325 | ||
326 | static void fsi_stream_push(struct fsi_priv *fsi, | |
327 | struct snd_pcm_substream *substream, | |
328 | u32 buffer_len, | |
329 | u32 period_len) | |
330 | { | |
331 | fsi->substream = substream; | |
5bfb9ad0 KM |
332 | fsi->buff_len = buffer_len; |
333 | fsi->buff_offset = 0; | |
a4d7d550 | 334 | fsi->period_len = period_len; |
5bfb9ad0 | 335 | fsi->period_num = 0; |
a4d7d550 KM |
336 | } |
337 | ||
338 | static void fsi_stream_pop(struct fsi_priv *fsi) | |
339 | { | |
340 | fsi->substream = NULL; | |
5bfb9ad0 KM |
341 | fsi->buff_len = 0; |
342 | fsi->buff_offset = 0; | |
a4d7d550 | 343 | fsi->period_len = 0; |
5bfb9ad0 | 344 | fsi->period_num = 0; |
a4d7d550 KM |
345 | } |
346 | ||
5bfb9ad0 | 347 | static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
348 | { |
349 | u32 status; | |
350 | u32 reg = is_play ? DOFF_ST : DIFF_ST; | |
5bfb9ad0 | 351 | int data_num; |
a4d7d550 KM |
352 | |
353 | status = fsi_reg_read(fsi, reg); | |
5bfb9ad0 KM |
354 | data_num = 0x1ff & (status >> 8); |
355 | data_num *= fsi->chan_num; | |
356 | ||
357 | return data_num; | |
358 | } | |
a4d7d550 | 359 | |
5bfb9ad0 KM |
360 | static int fsi_len2num(int len, int width) |
361 | { | |
362 | return len / width; | |
363 | } | |
364 | ||
365 | #define fsi_num2offset(a, b) fsi_num2len(a, b) | |
366 | static int fsi_num2len(int num, int width) | |
367 | { | |
368 | return num * width; | |
a4d7d550 KM |
369 | } |
370 | ||
b9fde18c KM |
371 | /* |
372 | * dma function | |
373 | */ | |
374 | ||
c79eab3e KM |
375 | static u8 *fsi_dma_get_area(struct fsi_priv *fsi) |
376 | { | |
5bfb9ad0 | 377 | return fsi->substream->runtime->dma_area + fsi->buff_offset; |
c79eab3e KM |
378 | } |
379 | ||
5bfb9ad0 | 380 | static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
381 | { |
382 | u16 *start; | |
383 | int i; | |
384 | ||
385 | start = (u16 *)fsi_dma_get_area(fsi); | |
386 | ||
5bfb9ad0 | 387 | for (i = 0; i < num; i++) |
b9fde18c KM |
388 | fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8)); |
389 | } | |
390 | ||
5bfb9ad0 | 391 | static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
392 | { |
393 | u16 *start; | |
394 | int i; | |
395 | ||
396 | start = (u16 *)fsi_dma_get_area(fsi); | |
397 | ||
5bfb9ad0 | 398 | for (i = 0; i < num; i++) |
b9fde18c KM |
399 | *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); |
400 | } | |
401 | ||
5bfb9ad0 | 402 | static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
403 | { |
404 | u32 *start; | |
405 | int i; | |
406 | ||
407 | start = (u32 *)fsi_dma_get_area(fsi); | |
408 | ||
5bfb9ad0 | 409 | for (i = 0; i < num; i++) |
b9fde18c KM |
410 | fsi_reg_write(fsi, DODT, *(start + i)); |
411 | } | |
412 | ||
5bfb9ad0 | 413 | static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
414 | { |
415 | u32 *start; | |
416 | int i; | |
417 | ||
418 | start = (u32 *)fsi_dma_get_area(fsi); | |
419 | ||
5bfb9ad0 | 420 | for (i = 0; i < num; i++) |
b9fde18c KM |
421 | *(start + i) = fsi_reg_read(fsi, DIDT); |
422 | } | |
423 | ||
c8fe2574 KM |
424 | /* |
425 | * irq function | |
426 | */ | |
a4d7d550 | 427 | |
a4d7d550 KM |
428 | static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) |
429 | { | |
430 | u32 data = fsi_port_ab_io_bit(fsi, is_play); | |
71f6e064 | 431 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 432 | |
73b92c1f KM |
433 | fsi_master_mask_set(master, master->core->imsk, data, data); |
434 | fsi_master_mask_set(master, master->core->iemsk, data, data); | |
a4d7d550 KM |
435 | } |
436 | ||
437 | static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | |
438 | { | |
439 | u32 data = fsi_port_ab_io_bit(fsi, is_play); | |
71f6e064 | 440 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 441 | |
73b92c1f KM |
442 | fsi_master_mask_set(master, master->core->imsk, data, 0); |
443 | fsi_master_mask_set(master, master->core->iemsk, data, 0); | |
a4d7d550 KM |
444 | } |
445 | ||
10ea76cc KM |
446 | static u32 fsi_irq_get_status(struct fsi_master *master) |
447 | { | |
73b92c1f | 448 | return fsi_master_read(master, master->core->int_st); |
10ea76cc KM |
449 | } |
450 | ||
451 | static void fsi_irq_clear_all_status(struct fsi_master *master) | |
452 | { | |
73b92c1f | 453 | fsi_master_write(master, master->core->int_st, 0); |
a4d7d550 KM |
454 | } |
455 | ||
10ea76cc KM |
456 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
457 | { | |
458 | u32 data = 0; | |
459 | struct fsi_master *master = fsi_get_master(fsi); | |
460 | ||
461 | data |= fsi_port_ab_io_bit(fsi, 0); | |
462 | data |= fsi_port_ab_io_bit(fsi, 1); | |
463 | ||
464 | /* clear interrupt factor */ | |
73b92c1f | 465 | fsi_master_mask_set(master, master->core->int_st, data, 0); |
10ea76cc KM |
466 | } |
467 | ||
c8fe2574 KM |
468 | /* |
469 | * SPDIF master clock function | |
470 | * | |
471 | * These functions are used later FSI2 | |
472 | */ | |
3bc28070 KM |
473 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
474 | { | |
475 | struct fsi_master *master = fsi_get_master(fsi); | |
476 | u32 val = BP | SE; | |
477 | ||
478 | if (master->core->ver < 2) { | |
479 | pr_err("fsi: register access err (%s)\n", __func__); | |
480 | return; | |
481 | } | |
482 | ||
483 | if (enable) | |
484 | fsi_master_mask_set(master, fsi->mst_ctrl, val, val); | |
485 | else | |
486 | fsi_master_mask_set(master, fsi->mst_ctrl, val, 0); | |
487 | } | |
488 | ||
c8fe2574 KM |
489 | /* |
490 | * ctrl function | |
491 | */ | |
10ea76cc | 492 | |
a4d7d550 KM |
493 | static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable) |
494 | { | |
495 | u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4); | |
71f6e064 | 496 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
497 | |
498 | if (enable) | |
71f6e064 | 499 | fsi_master_mask_set(master, CLK_RST, val, val); |
a4d7d550 | 500 | else |
71f6e064 | 501 | fsi_master_mask_set(master, CLK_RST, val, 0); |
a4d7d550 KM |
502 | } |
503 | ||
4a942b45 KM |
504 | static void fsi_fifo_init(struct fsi_priv *fsi, |
505 | int is_play, | |
506 | struct snd_soc_dai *dai) | |
a4d7d550 | 507 | { |
4a942b45 KM |
508 | struct fsi_master *master = fsi_get_master(fsi); |
509 | u32 ctrl, shift, i; | |
a4d7d550 | 510 | |
4a942b45 KM |
511 | /* get on-chip RAM capacity */ |
512 | shift = fsi_master_read(master, FIFO_SZ); | |
513 | shift >>= fsi_is_port_a(fsi) ? AO_SZ_SHIFT : BO_SZ_SHIFT; | |
514 | shift &= OUT_SZ_MASK; | |
5bfb9ad0 KM |
515 | fsi->fifo_max_num = 256 << shift; |
516 | dev_dbg(dai->dev, "fifo = %d words\n", fsi->fifo_max_num); | |
a4d7d550 | 517 | |
4a942b45 KM |
518 | /* |
519 | * The maximum number of sample data varies depending | |
520 | * on the number of channels selected for the format. | |
521 | * | |
522 | * FIFOs are used in 4-channel units in 3-channel mode | |
523 | * and in 8-channel units in 5- to 7-channel mode | |
524 | * meaning that more FIFOs than the required size of DPRAM | |
525 | * are used. | |
526 | * | |
527 | * ex) if 256 words of DP-RAM is connected | |
528 | * 1 channel: 256 (256 x 1 = 256) | |
529 | * 2 channels: 128 (128 x 2 = 256) | |
530 | * 3 channels: 64 ( 64 x 3 = 192) | |
531 | * 4 channels: 64 ( 64 x 4 = 256) | |
532 | * 5 channels: 32 ( 32 x 5 = 160) | |
533 | * 6 channels: 32 ( 32 x 6 = 192) | |
534 | * 7 channels: 32 ( 32 x 7 = 224) | |
535 | * 8 channels: 32 ( 32 x 8 = 256) | |
536 | */ | |
5bfb9ad0 KM |
537 | for (i = 1; i < fsi->chan_num; i <<= 1) |
538 | fsi->fifo_max_num >>= 1; | |
539 | dev_dbg(dai->dev, "%d channel %d store\n", | |
540 | fsi->chan_num, fsi->fifo_max_num); | |
a4d7d550 | 541 | |
a4d7d550 | 542 | ctrl = is_play ? DOFF_CTL : DIFF_CTL; |
a4d7d550 KM |
543 | |
544 | /* set interrupt generation factor */ | |
545 | fsi_reg_write(fsi, ctrl, IRQ_HALF); | |
546 | ||
547 | /* clear FIFO */ | |
548 | fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR); | |
a4d7d550 KM |
549 | } |
550 | ||
71f6e064 | 551 | static void fsi_soft_all_reset(struct fsi_master *master) |
a4d7d550 | 552 | { |
a4d7d550 | 553 | /* port AB reset */ |
feb58cff | 554 | fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0); |
a4d7d550 KM |
555 | mdelay(10); |
556 | ||
557 | /* soft reset */ | |
feb58cff KM |
558 | fsi_master_mask_set(master, SOFT_RST, FSISR, 0); |
559 | fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR); | |
a4d7d550 KM |
560 | mdelay(10); |
561 | } | |
562 | ||
d8b33534 | 563 | static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int startup, int is_play) |
a4d7d550 KM |
564 | { |
565 | struct snd_pcm_runtime *runtime; | |
566 | struct snd_pcm_substream *substream = NULL; | |
59c3b003 | 567 | u32 status; |
d8b33534 KM |
568 | u32 status_reg = is_play ? DOFF_ST : DIFF_ST; |
569 | int data_residue_num; | |
570 | int data_num; | |
571 | int data_num_max; | |
5bfb9ad0 | 572 | int ch_width; |
b9fde18c | 573 | int over_period; |
d8b33534 | 574 | void (*fn)(struct fsi_priv *fsi, int size); |
a4d7d550 KM |
575 | |
576 | if (!fsi || | |
577 | !fsi->substream || | |
578 | !fsi->substream->runtime) | |
579 | return -EINVAL; | |
580 | ||
1c418d1f KM |
581 | over_period = 0; |
582 | substream = fsi->substream; | |
583 | runtime = substream->runtime; | |
a4d7d550 KM |
584 | |
585 | /* FSI FIFO has limit. | |
586 | * So, this driver can not send periods data at a time | |
587 | */ | |
5bfb9ad0 KM |
588 | if (fsi->buff_offset >= |
589 | fsi_num2offset(fsi->period_num + 1, fsi->period_len)) { | |
a4d7d550 | 590 | |
1c418d1f | 591 | over_period = 1; |
5bfb9ad0 | 592 | fsi->period_num = (fsi->period_num + 1) % runtime->periods; |
a4d7d550 | 593 | |
5bfb9ad0 KM |
594 | if (0 == fsi->period_num) |
595 | fsi->buff_offset = 0; | |
a4d7d550 KM |
596 | } |
597 | ||
598 | /* get 1 channel data width */ | |
5bfb9ad0 | 599 | ch_width = frames_to_bytes(runtime, 1) / fsi->chan_num; |
a4d7d550 | 600 | |
d8b33534 KM |
601 | /* get residue data number of alsa */ |
602 | data_residue_num = fsi_len2num(fsi->buff_len - fsi->buff_offset, | |
603 | ch_width); | |
604 | ||
605 | if (is_play) { | |
606 | /* | |
607 | * for play-back | |
608 | * | |
609 | * data_num_max : number of FSI fifo free space | |
610 | * data_num : number of ALSA residue data | |
611 | */ | |
612 | data_num_max = fsi->fifo_max_num * fsi->chan_num; | |
613 | data_num_max -= fsi_get_fifo_data_num(fsi, is_play); | |
614 | ||
615 | data_num = data_residue_num; | |
616 | ||
617 | switch (ch_width) { | |
618 | case 2: | |
619 | fn = fsi_dma_soft_push16; | |
620 | break; | |
621 | case 4: | |
622 | fn = fsi_dma_soft_push32; | |
623 | break; | |
624 | default: | |
625 | return -EINVAL; | |
626 | } | |
627 | } else { | |
628 | /* | |
629 | * for capture | |
630 | * | |
631 | * data_num_max : number of ALSA free space | |
632 | * data_num : number of data in FSI fifo | |
633 | */ | |
634 | data_num_max = data_residue_num; | |
635 | data_num = fsi_get_fifo_data_num(fsi, is_play); | |
636 | ||
637 | switch (ch_width) { | |
638 | case 2: | |
639 | fn = fsi_dma_soft_pop16; | |
640 | break; | |
641 | case 4: | |
642 | fn = fsi_dma_soft_pop32; | |
643 | break; | |
644 | default: | |
645 | return -EINVAL; | |
646 | } | |
647 | } | |
a4d7d550 | 648 | |
d8b33534 | 649 | data_num = min(data_num, data_num_max); |
a4d7d550 | 650 | |
d8b33534 | 651 | fn(fsi, data_num); |
a4d7d550 | 652 | |
d8b33534 KM |
653 | /* update buff_offset */ |
654 | fsi->buff_offset += fsi_num2offset(data_num, ch_width); | |
a4d7d550 | 655 | |
d8b33534 KM |
656 | /* check fifo status */ |
657 | status = fsi_reg_read(fsi, status_reg); | |
47fc9a0a | 658 | if (!startup) { |
59c3b003 | 659 | struct snd_soc_dai *dai = fsi_get_dai(substream); |
47fc9a0a KM |
660 | |
661 | if (status & ERR_OVER) | |
662 | dev_err(dai->dev, "over run\n"); | |
663 | if (status & ERR_UNDER) | |
664 | dev_err(dai->dev, "under run\n"); | |
59c3b003 | 665 | } |
d8b33534 | 666 | fsi_reg_write(fsi, status_reg, 0); |
59c3b003 | 667 | |
d8b33534 KM |
668 | /* re-enable irq */ |
669 | fsi_irq_enable(fsi, is_play); | |
a4d7d550 | 670 | |
1c418d1f | 671 | if (over_period) |
a4d7d550 KM |
672 | snd_pcm_period_elapsed(substream); |
673 | ||
47fc9a0a | 674 | return 0; |
a4d7d550 KM |
675 | } |
676 | ||
47fc9a0a | 677 | static int fsi_data_pop(struct fsi_priv *fsi, int startup) |
07102f3c | 678 | { |
d8b33534 KM |
679 | return fsi_fifo_data_ctrl(fsi, startup, 0); |
680 | } | |
07102f3c | 681 | |
d8b33534 KM |
682 | static int fsi_data_push(struct fsi_priv *fsi, int startup) |
683 | { | |
684 | return fsi_fifo_data_ctrl(fsi, startup, 1); | |
07102f3c KM |
685 | } |
686 | ||
a4d7d550 KM |
687 | static irqreturn_t fsi_interrupt(int irq, void *data) |
688 | { | |
71f6e064 | 689 | struct fsi_master *master = data; |
10ea76cc | 690 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
691 | |
692 | /* clear irq status */ | |
feb58cff KM |
693 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
694 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 KM |
695 | |
696 | if (int_st & INT_A_OUT) | |
47fc9a0a | 697 | fsi_data_push(&master->fsia, 0); |
a4d7d550 | 698 | if (int_st & INT_B_OUT) |
47fc9a0a | 699 | fsi_data_push(&master->fsib, 0); |
07102f3c | 700 | if (int_st & INT_A_IN) |
47fc9a0a | 701 | fsi_data_pop(&master->fsia, 0); |
07102f3c | 702 | if (int_st & INT_B_IN) |
47fc9a0a | 703 | fsi_data_pop(&master->fsib, 0); |
a4d7d550 | 704 | |
10ea76cc | 705 | fsi_irq_clear_all_status(master); |
a4d7d550 KM |
706 | |
707 | return IRQ_HANDLED; | |
708 | } | |
709 | ||
c8fe2574 KM |
710 | /* |
711 | * dai ops | |
712 | */ | |
a4d7d550 | 713 | |
a4d7d550 KM |
714 | static int fsi_dai_startup(struct snd_pcm_substream *substream, |
715 | struct snd_soc_dai *dai) | |
716 | { | |
71f6e064 | 717 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 | 718 | u32 flags = fsi_get_info_flags(fsi); |
3bc28070 | 719 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
720 | u32 fmt; |
721 | u32 reg; | |
722 | u32 data; | |
723 | int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); | |
724 | int is_master; | |
725 | int ret = 0; | |
726 | ||
785d1c45 | 727 | pm_runtime_get_sync(dai->dev); |
a4d7d550 KM |
728 | |
729 | /* CKG1 */ | |
730 | data = is_play ? (1 << 0) : (1 << 4); | |
731 | is_master = fsi_is_master_mode(fsi, is_play); | |
732 | if (is_master) | |
733 | fsi_reg_mask_set(fsi, CKG1, data, data); | |
734 | else | |
735 | fsi_reg_mask_set(fsi, CKG1, data, 0); | |
736 | ||
737 | /* clock inversion (CKG2) */ | |
738 | data = 0; | |
b427b44c KM |
739 | if (SH_FSI_LRM_INV & flags) |
740 | data |= 1 << 12; | |
741 | if (SH_FSI_BRM_INV & flags) | |
742 | data |= 1 << 8; | |
743 | if (SH_FSI_LRS_INV & flags) | |
744 | data |= 1 << 4; | |
745 | if (SH_FSI_BRS_INV & flags) | |
746 | data |= 1 << 0; | |
747 | ||
a4d7d550 KM |
748 | fsi_reg_write(fsi, CKG2, data); |
749 | ||
750 | /* do fmt, di fmt */ | |
751 | data = 0; | |
752 | reg = is_play ? DO_FMT : DI_FMT; | |
753 | fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags); | |
754 | switch (fmt) { | |
755 | case SH_FSI_FMT_MONO: | |
a7ffb52b | 756 | data = CR_MONO; |
5bfb9ad0 | 757 | fsi->chan_num = 1; |
a4d7d550 KM |
758 | break; |
759 | case SH_FSI_FMT_MONO_DELAY: | |
a7ffb52b | 760 | data = CR_MONO_D; |
5bfb9ad0 | 761 | fsi->chan_num = 1; |
a4d7d550 KM |
762 | break; |
763 | case SH_FSI_FMT_PCM: | |
a7ffb52b | 764 | data = CR_PCM; |
5bfb9ad0 | 765 | fsi->chan_num = 2; |
a4d7d550 KM |
766 | break; |
767 | case SH_FSI_FMT_I2S: | |
a7ffb52b | 768 | data = CR_I2S; |
5bfb9ad0 | 769 | fsi->chan_num = 2; |
a4d7d550 KM |
770 | break; |
771 | case SH_FSI_FMT_TDM: | |
5bfb9ad0 | 772 | fsi->chan_num = is_play ? |
a4d7d550 | 773 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); |
5bfb9ad0 | 774 | data = CR_TDM | (fsi->chan_num - 1); |
a4d7d550 KM |
775 | break; |
776 | case SH_FSI_FMT_TDM_DELAY: | |
5bfb9ad0 | 777 | fsi->chan_num = is_play ? |
a4d7d550 | 778 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); |
5bfb9ad0 | 779 | data = CR_TDM_D | (fsi->chan_num - 1); |
a4d7d550 | 780 | break; |
3bc28070 KM |
781 | case SH_FSI_FMT_SPDIF: |
782 | if (master->core->ver < 2) { | |
783 | dev_err(dai->dev, "This FSI can not use SPDIF\n"); | |
784 | return -EINVAL; | |
785 | } | |
786 | data = CR_SPDIF; | |
5bfb9ad0 | 787 | fsi->chan_num = 2; |
3bc28070 KM |
788 | fsi_spdif_clk_ctrl(fsi, 1); |
789 | fsi_reg_mask_set(fsi, OUT_SEL, 0x0010, 0x0010); | |
790 | break; | |
a4d7d550 KM |
791 | default: |
792 | dev_err(dai->dev, "unknown format.\n"); | |
793 | return -EINVAL; | |
794 | } | |
a4d7d550 | 795 | fsi_reg_write(fsi, reg, data); |
a4d7d550 | 796 | |
10ea76cc KM |
797 | /* irq clear */ |
798 | fsi_irq_disable(fsi, is_play); | |
799 | fsi_irq_clear_status(fsi); | |
800 | ||
801 | /* fifo init */ | |
4a942b45 | 802 | fsi_fifo_init(fsi, is_play, dai); |
a4d7d550 KM |
803 | |
804 | return ret; | |
805 | } | |
806 | ||
807 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, | |
808 | struct snd_soc_dai *dai) | |
809 | { | |
71f6e064 | 810 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
811 | int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
812 | ||
813 | fsi_irq_disable(fsi, is_play); | |
814 | fsi_clk_ctrl(fsi, 0); | |
815 | ||
785d1c45 | 816 | pm_runtime_put_sync(dai->dev); |
a4d7d550 KM |
817 | } |
818 | ||
819 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
820 | struct snd_soc_dai *dai) | |
821 | { | |
71f6e064 | 822 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
823 | struct snd_pcm_runtime *runtime = substream->runtime; |
824 | int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
825 | int ret = 0; | |
826 | ||
a4d7d550 KM |
827 | switch (cmd) { |
828 | case SNDRV_PCM_TRIGGER_START: | |
829 | fsi_stream_push(fsi, substream, | |
830 | frames_to_bytes(runtime, runtime->buffer_size), | |
831 | frames_to_bytes(runtime, runtime->period_size)); | |
47fc9a0a | 832 | ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1); |
a4d7d550 KM |
833 | break; |
834 | case SNDRV_PCM_TRIGGER_STOP: | |
835 | fsi_irq_disable(fsi, is_play); | |
836 | fsi_stream_pop(fsi); | |
837 | break; | |
838 | } | |
839 | ||
840 | return ret; | |
841 | } | |
842 | ||
ccad7b44 KM |
843 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
844 | struct snd_pcm_hw_params *params, | |
845 | struct snd_soc_dai *dai) | |
846 | { | |
847 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
848 | struct fsi_master *master = fsi_get_master(fsi); | |
849 | int (*set_rate)(int is_porta, int rate) = master->info->set_rate; | |
850 | int fsi_ver = master->core->ver; | |
851 | int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); | |
852 | int ret; | |
853 | ||
854 | /* if slave mode, set_rate is not needed */ | |
855 | if (!fsi_is_master_mode(fsi, is_play)) | |
856 | return 0; | |
857 | ||
858 | /* it is error if no set_rate */ | |
859 | if (!set_rate) | |
860 | return -EIO; | |
861 | ||
ccad7b44 KM |
862 | ret = set_rate(fsi_is_port_a(fsi), params_rate(params)); |
863 | if (ret > 0) { | |
864 | u32 data = 0; | |
865 | ||
866 | switch (ret & SH_FSI_ACKMD_MASK) { | |
867 | default: | |
868 | /* FALL THROUGH */ | |
869 | case SH_FSI_ACKMD_512: | |
870 | data |= (0x0 << 12); | |
871 | break; | |
872 | case SH_FSI_ACKMD_256: | |
873 | data |= (0x1 << 12); | |
874 | break; | |
875 | case SH_FSI_ACKMD_128: | |
876 | data |= (0x2 << 12); | |
877 | break; | |
878 | case SH_FSI_ACKMD_64: | |
879 | data |= (0x3 << 12); | |
880 | break; | |
881 | case SH_FSI_ACKMD_32: | |
882 | if (fsi_ver < 2) | |
883 | dev_err(dai->dev, "unsupported ACKMD\n"); | |
884 | else | |
885 | data |= (0x4 << 12); | |
886 | break; | |
887 | } | |
888 | ||
889 | switch (ret & SH_FSI_BPFMD_MASK) { | |
890 | default: | |
891 | /* FALL THROUGH */ | |
892 | case SH_FSI_BPFMD_32: | |
893 | data |= (0x0 << 8); | |
894 | break; | |
895 | case SH_FSI_BPFMD_64: | |
896 | data |= (0x1 << 8); | |
897 | break; | |
898 | case SH_FSI_BPFMD_128: | |
899 | data |= (0x2 << 8); | |
900 | break; | |
901 | case SH_FSI_BPFMD_256: | |
902 | data |= (0x3 << 8); | |
903 | break; | |
904 | case SH_FSI_BPFMD_512: | |
905 | data |= (0x4 << 8); | |
906 | break; | |
907 | case SH_FSI_BPFMD_16: | |
908 | if (fsi_ver < 2) | |
909 | dev_err(dai->dev, "unsupported ACKMD\n"); | |
910 | else | |
911 | data |= (0x7 << 8); | |
912 | break; | |
913 | } | |
914 | ||
915 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
916 | udelay(10); | |
917 | fsi_clk_ctrl(fsi, 1); | |
918 | ret = 0; | |
919 | } | |
ccad7b44 KM |
920 | |
921 | return ret; | |
922 | ||
923 | } | |
924 | ||
a4d7d550 KM |
925 | static struct snd_soc_dai_ops fsi_dai_ops = { |
926 | .startup = fsi_dai_startup, | |
927 | .shutdown = fsi_dai_shutdown, | |
928 | .trigger = fsi_dai_trigger, | |
ccad7b44 | 929 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
930 | }; |
931 | ||
c8fe2574 KM |
932 | /* |
933 | * pcm ops | |
934 | */ | |
a4d7d550 | 935 | |
a4d7d550 KM |
936 | static struct snd_pcm_hardware fsi_pcm_hardware = { |
937 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
938 | SNDRV_PCM_INFO_MMAP | | |
939 | SNDRV_PCM_INFO_MMAP_VALID | | |
940 | SNDRV_PCM_INFO_PAUSE, | |
941 | .formats = FSI_FMTS, | |
942 | .rates = FSI_RATES, | |
943 | .rate_min = 8000, | |
944 | .rate_max = 192000, | |
945 | .channels_min = 1, | |
946 | .channels_max = 2, | |
947 | .buffer_bytes_max = 64 * 1024, | |
948 | .period_bytes_min = 32, | |
949 | .period_bytes_max = 8192, | |
950 | .periods_min = 1, | |
951 | .periods_max = 32, | |
952 | .fifo_size = 256, | |
953 | }; | |
954 | ||
955 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
956 | { | |
957 | struct snd_pcm_runtime *runtime = substream->runtime; | |
958 | int ret = 0; | |
959 | ||
960 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
961 | ||
962 | ret = snd_pcm_hw_constraint_integer(runtime, | |
963 | SNDRV_PCM_HW_PARAM_PERIODS); | |
964 | ||
965 | return ret; | |
966 | } | |
967 | ||
968 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
969 | struct snd_pcm_hw_params *hw_params) | |
970 | { | |
971 | return snd_pcm_lib_malloc_pages(substream, | |
972 | params_buffer_bytes(hw_params)); | |
973 | } | |
974 | ||
975 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
976 | { | |
977 | return snd_pcm_lib_free_pages(substream); | |
978 | } | |
979 | ||
980 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
981 | { | |
982 | struct snd_pcm_runtime *runtime = substream->runtime; | |
71f6e064 | 983 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
984 | long location; |
985 | ||
5bfb9ad0 | 986 | location = (fsi->buff_offset - 1); |
a4d7d550 KM |
987 | if (location < 0) |
988 | location = 0; | |
989 | ||
990 | return bytes_to_frames(runtime, location); | |
991 | } | |
992 | ||
993 | static struct snd_pcm_ops fsi_pcm_ops = { | |
994 | .open = fsi_pcm_open, | |
995 | .ioctl = snd_pcm_lib_ioctl, | |
996 | .hw_params = fsi_hw_params, | |
997 | .hw_free = fsi_hw_free, | |
998 | .pointer = fsi_pointer, | |
999 | }; | |
1000 | ||
c8fe2574 KM |
1001 | /* |
1002 | * snd_soc_platform | |
1003 | */ | |
a4d7d550 | 1004 | |
a4d7d550 KM |
1005 | #define PREALLOC_BUFFER (32 * 1024) |
1006 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1007 | ||
1008 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1009 | { | |
1010 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1011 | } | |
1012 | ||
1013 | static int fsi_pcm_new(struct snd_card *card, | |
1014 | struct snd_soc_dai *dai, | |
1015 | struct snd_pcm *pcm) | |
1016 | { | |
1017 | /* | |
1018 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1019 | * in MMAP mode (i.e. aplay -M) | |
1020 | */ | |
1021 | return snd_pcm_lib_preallocate_pages_for_all( | |
1022 | pcm, | |
1023 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1024 | snd_dma_continuous_data(GFP_KERNEL), | |
1025 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1026 | } | |
1027 | ||
c8fe2574 KM |
1028 | /* |
1029 | * alsa struct | |
1030 | */ | |
a4d7d550 | 1031 | |
f0fba2ad | 1032 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1033 | { |
f0fba2ad | 1034 | .name = "fsia-dai", |
a4d7d550 KM |
1035 | .playback = { |
1036 | .rates = FSI_RATES, | |
1037 | .formats = FSI_FMTS, | |
1038 | .channels_min = 1, | |
1039 | .channels_max = 8, | |
1040 | }, | |
07102f3c KM |
1041 | .capture = { |
1042 | .rates = FSI_RATES, | |
1043 | .formats = FSI_FMTS, | |
1044 | .channels_min = 1, | |
1045 | .channels_max = 8, | |
1046 | }, | |
a4d7d550 KM |
1047 | .ops = &fsi_dai_ops, |
1048 | }, | |
1049 | { | |
f0fba2ad | 1050 | .name = "fsib-dai", |
a4d7d550 KM |
1051 | .playback = { |
1052 | .rates = FSI_RATES, | |
1053 | .formats = FSI_FMTS, | |
1054 | .channels_min = 1, | |
1055 | .channels_max = 8, | |
1056 | }, | |
07102f3c KM |
1057 | .capture = { |
1058 | .rates = FSI_RATES, | |
1059 | .formats = FSI_FMTS, | |
1060 | .channels_min = 1, | |
1061 | .channels_max = 8, | |
1062 | }, | |
a4d7d550 KM |
1063 | .ops = &fsi_dai_ops, |
1064 | }, | |
1065 | }; | |
a4d7d550 | 1066 | |
f0fba2ad LG |
1067 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1068 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1069 | .pcm_new = fsi_pcm_new, |
1070 | .pcm_free = fsi_pcm_free, | |
1071 | }; | |
a4d7d550 | 1072 | |
c8fe2574 KM |
1073 | /* |
1074 | * platform function | |
1075 | */ | |
a4d7d550 | 1076 | |
a4d7d550 KM |
1077 | static int fsi_probe(struct platform_device *pdev) |
1078 | { | |
71f6e064 | 1079 | struct fsi_master *master; |
cc780d38 | 1080 | const struct platform_device_id *id_entry; |
a4d7d550 | 1081 | struct resource *res; |
a4d7d550 KM |
1082 | unsigned int irq; |
1083 | int ret; | |
1084 | ||
cc780d38 KM |
1085 | id_entry = pdev->id_entry; |
1086 | if (!id_entry) { | |
1087 | dev_err(&pdev->dev, "unknown fsi device\n"); | |
1088 | return -ENODEV; | |
1089 | } | |
1090 | ||
a4d7d550 KM |
1091 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1092 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 1093 | if (!res || (int)irq <= 0) { |
a4d7d550 KM |
1094 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
1095 | ret = -ENODEV; | |
1096 | goto exit; | |
1097 | } | |
1098 | ||
1099 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
1100 | if (!master) { | |
1101 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
1102 | ret = -ENOMEM; | |
1103 | goto exit; | |
1104 | } | |
1105 | ||
1106 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
1107 | if (!master->base) { | |
1108 | ret = -ENXIO; | |
1109 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
1110 | goto exit_kfree; | |
1111 | } | |
1112 | ||
3bc28070 | 1113 | /* master setting */ |
a4d7d550 KM |
1114 | master->irq = irq; |
1115 | master->info = pdev->dev.platform_data; | |
3bc28070 KM |
1116 | master->core = (struct fsi_core *)id_entry->driver_data; |
1117 | spin_lock_init(&master->lock); | |
1118 | ||
1119 | /* FSI A setting */ | |
a4d7d550 | 1120 | master->fsia.base = master->base; |
71f6e064 | 1121 | master->fsia.master = master; |
3bc28070 KM |
1122 | master->fsia.mst_ctrl = A_MST_CTLR; |
1123 | ||
1124 | /* FSI B setting */ | |
a4d7d550 | 1125 | master->fsib.base = master->base + 0x40; |
71f6e064 | 1126 | master->fsib.master = master; |
3bc28070 | 1127 | master->fsib.mst_ctrl = B_MST_CTLR; |
a4d7d550 | 1128 | |
785d1c45 KM |
1129 | pm_runtime_enable(&pdev->dev); |
1130 | pm_runtime_resume(&pdev->dev); | |
f0fba2ad | 1131 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 1132 | |
71f6e064 | 1133 | fsi_soft_all_reset(master); |
a4d7d550 | 1134 | |
cc780d38 KM |
1135 | ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, |
1136 | id_entry->name, master); | |
a4d7d550 KM |
1137 | if (ret) { |
1138 | dev_err(&pdev->dev, "irq request err\n"); | |
9ddc9aa9 | 1139 | goto exit_iounmap; |
a4d7d550 KM |
1140 | } |
1141 | ||
f0fba2ad | 1142 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
1143 | if (ret < 0) { |
1144 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1145 | goto exit_free_irq; | |
1146 | } | |
1147 | ||
f0fba2ad | 1148 | return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); |
a4d7d550 KM |
1149 | |
1150 | exit_free_irq: | |
1151 | free_irq(irq, master); | |
a4d7d550 KM |
1152 | exit_iounmap: |
1153 | iounmap(master->base); | |
785d1c45 | 1154 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
1155 | exit_kfree: |
1156 | kfree(master); | |
1157 | master = NULL; | |
1158 | exit: | |
1159 | return ret; | |
1160 | } | |
1161 | ||
1162 | static int fsi_remove(struct platform_device *pdev) | |
1163 | { | |
71f6e064 KM |
1164 | struct fsi_master *master; |
1165 | ||
f0fba2ad | 1166 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 1167 | |
f0fba2ad LG |
1168 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); |
1169 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 | 1170 | |
785d1c45 | 1171 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 1172 | |
a4d7d550 KM |
1173 | free_irq(master->irq, master); |
1174 | ||
1175 | iounmap(master->base); | |
1176 | kfree(master); | |
71f6e064 | 1177 | |
a4d7d550 KM |
1178 | return 0; |
1179 | } | |
1180 | ||
785d1c45 KM |
1181 | static int fsi_runtime_nop(struct device *dev) |
1182 | { | |
1183 | /* Runtime PM callback shared between ->runtime_suspend() | |
1184 | * and ->runtime_resume(). Simply returns success. | |
1185 | * | |
1186 | * This driver re-initializes all registers after | |
1187 | * pm_runtime_get_sync() anyway so there is no need | |
1188 | * to save and restore registers here. | |
1189 | */ | |
1190 | return 0; | |
1191 | } | |
1192 | ||
1193 | static struct dev_pm_ops fsi_pm_ops = { | |
1194 | .runtime_suspend = fsi_runtime_nop, | |
1195 | .runtime_resume = fsi_runtime_nop, | |
1196 | }; | |
1197 | ||
73b92c1f KM |
1198 | static struct fsi_core fsi1_core = { |
1199 | .ver = 1, | |
1200 | ||
1201 | /* Interrupt */ | |
cc780d38 KM |
1202 | .int_st = INT_ST, |
1203 | .iemsk = IEMSK, | |
1204 | .imsk = IMSK, | |
1205 | }; | |
1206 | ||
73b92c1f KM |
1207 | static struct fsi_core fsi2_core = { |
1208 | .ver = 2, | |
1209 | ||
1210 | /* Interrupt */ | |
cc780d38 KM |
1211 | .int_st = CPU_INT_ST, |
1212 | .iemsk = CPU_IEMSK, | |
1213 | .imsk = CPU_IMSK, | |
1214 | }; | |
1215 | ||
1216 | static struct platform_device_id fsi_id_table[] = { | |
73b92c1f KM |
1217 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
1218 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
05c69450 | 1219 | {}, |
cc780d38 | 1220 | }; |
d85a6d7b | 1221 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 1222 | |
a4d7d550 KM |
1223 | static struct platform_driver fsi_driver = { |
1224 | .driver = { | |
f0fba2ad | 1225 | .name = "fsi-pcm-audio", |
785d1c45 | 1226 | .pm = &fsi_pm_ops, |
a4d7d550 KM |
1227 | }, |
1228 | .probe = fsi_probe, | |
1229 | .remove = fsi_remove, | |
cc780d38 | 1230 | .id_table = fsi_id_table, |
a4d7d550 KM |
1231 | }; |
1232 | ||
1233 | static int __init fsi_mobile_init(void) | |
1234 | { | |
1235 | return platform_driver_register(&fsi_driver); | |
1236 | } | |
1237 | ||
1238 | static void __exit fsi_mobile_exit(void) | |
1239 | { | |
1240 | platform_driver_unregister(&fsi_driver); | |
1241 | } | |
d85a6d7b | 1242 | |
a4d7d550 KM |
1243 | module_init(fsi_mobile_init); |
1244 | module_exit(fsi_mobile_exit); | |
1245 | ||
1246 | MODULE_LICENSE("GPL"); | |
1247 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1248 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); |