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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
785d1c45 | 16 | #include <linux/pm_runtime.h> |
a4d7d550 | 17 | #include <linux/io.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
da155d5b | 19 | #include <linux/module.h> |
a4d7d550 | 20 | #include <sound/soc.h> |
a4d7d550 | 21 | #include <sound/sh_fsi.h> |
a4d7d550 | 22 | |
e8c8b631 KM |
23 | /* PortA/PortB register */ |
24 | #define REG_DO_FMT 0x0000 | |
25 | #define REG_DOFF_CTL 0x0004 | |
26 | #define REG_DOFF_ST 0x0008 | |
27 | #define REG_DI_FMT 0x000C | |
28 | #define REG_DIFF_CTL 0x0010 | |
29 | #define REG_DIFF_ST 0x0014 | |
30 | #define REG_CKG1 0x0018 | |
31 | #define REG_CKG2 0x001C | |
32 | #define REG_DIDT 0x0020 | |
33 | #define REG_DODT 0x0024 | |
34 | #define REG_MUTE_ST 0x0028 | |
65ff03f4 | 35 | #define REG_OUT_DMAC 0x002C |
e8c8b631 | 36 | #define REG_OUT_SEL 0x0030 |
65ff03f4 | 37 | #define REG_IN_DMAC 0x0038 |
cc780d38 | 38 | |
43fa95ca KM |
39 | /* master register */ |
40 | #define MST_CLK_RST 0x0210 | |
41 | #define MST_SOFT_RST 0x0214 | |
42 | #define MST_FIFO_SZ 0x0218 | |
43 | ||
44 | /* core register (depend on FSI version) */ | |
3bc28070 KM |
45 | #define A_MST_CTLR 0x0180 |
46 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
47 | #define CPU_INT_ST 0x01F4 |
48 | #define CPU_IEMSK 0x01F8 | |
49 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
50 | #define INT_ST 0x0200 |
51 | #define IEMSK 0x0204 | |
52 | #define IMSK 0x0208 | |
a4d7d550 KM |
53 | |
54 | /* DO_FMT */ | |
55 | /* DI_FMT */ | |
f7d711e3 KM |
56 | #define CR_BWS_24 (0x0 << 20) /* FSI2 */ |
57 | #define CR_BWS_16 (0x1 << 20) /* FSI2 */ | |
58 | #define CR_BWS_20 (0x2 << 20) /* FSI2 */ | |
59 | ||
60 | #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ | |
61 | #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ | |
62 | #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ | |
63 | ||
a7ffb52b KM |
64 | #define CR_MONO (0x0 << 4) |
65 | #define CR_MONO_D (0x1 << 4) | |
66 | #define CR_PCM (0x2 << 4) | |
67 | #define CR_I2S (0x3 << 4) | |
68 | #define CR_TDM (0x4 << 4) | |
69 | #define CR_TDM_D (0x5 << 4) | |
a4d7d550 KM |
70 | |
71 | /* DOFF_CTL */ | |
72 | /* DIFF_CTL */ | |
73 | #define IRQ_HALF 0x00100000 | |
74 | #define FIFO_CLR 0x00000001 | |
75 | ||
76 | /* DOFF_ST */ | |
77 | #define ERR_OVER 0x00000010 | |
78 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 79 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 80 | |
ccad7b44 KM |
81 | /* CKG1 */ |
82 | #define ACKMD_MASK 0x00007000 | |
83 | #define BPFMD_MASK 0x00000700 | |
4d805f7b KM |
84 | #define DIMD (1 << 4) |
85 | #define DOMD (1 << 0) | |
ccad7b44 | 86 | |
3bc28070 KM |
87 | /* A/B MST_CTLR */ |
88 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
89 | #define SE (1 << 0) /* Fix the master clock */ | |
90 | ||
a4d7d550 | 91 | /* CLK_RST */ |
1f5e2a31 KM |
92 | #define CRB (1 << 4) |
93 | #define CRA (1 << 0) | |
a4d7d550 | 94 | |
cf6edd00 KM |
95 | /* IO SHIFT / MACRO */ |
96 | #define BI_SHIFT 12 | |
97 | #define BO_SHIFT 8 | |
98 | #define AI_SHIFT 4 | |
99 | #define AO_SHIFT 0 | |
100 | #define AB_IO(param, shift) (param << shift) | |
a4d7d550 | 101 | |
feb58cff KM |
102 | /* SOFT_RST */ |
103 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
104 | #define PASR (1 << 8) /* Port A Software Reset */ | |
105 | #define IR (1 << 4) /* Interrupt Reset */ | |
106 | #define FSISR (1 << 0) /* Software Reset */ | |
107 | ||
f7d711e3 KM |
108 | /* OUT_SEL (FSI2) */ |
109 | #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ | |
110 | /* 1: Biphase and serial */ | |
111 | ||
4a942b45 | 112 | /* FIFO_SZ */ |
cf6edd00 | 113 | #define FIFO_SZ_MASK 0x7 |
4a942b45 | 114 | |
a4d7d550 KM |
115 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
116 | ||
117 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
118 | ||
d7c5762b KM |
119 | typedef int (*set_rate_func)(struct device *dev, int is_porta, int rate, int enable); |
120 | ||
5bfb9ad0 KM |
121 | /* |
122 | * FSI driver use below type name for variable | |
123 | * | |
5bfb9ad0 | 124 | * xxx_num : number of data |
2e651baf KM |
125 | * xxx_pos : position of data |
126 | * xxx_capa : capacity of data | |
127 | */ | |
128 | ||
129 | /* | |
130 | * period/frame/sample image | |
131 | * | |
132 | * ex) PCM (2ch) | |
133 | * | |
134 | * period pos period pos | |
135 | * [n] [n + 1] | |
136 | * |<-------------------- period--------------------->| | |
137 | * ==|============================================ ... =|== | |
138 | * | | | |
139 | * ||<----- frame ----->|<------ frame ----->| ... | | |
140 | * |+--------------------+--------------------+- ... | | |
141 | * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | | |
142 | * |+--------------------+--------------------+- ... | | |
143 | * ==|============================================ ... =|== | |
144 | */ | |
145 | ||
146 | /* | |
147 | * FSI FIFO image | |
148 | * | |
149 | * | | | |
150 | * | | | |
151 | * | [ sample ] | | |
152 | * | [ sample ] | | |
153 | * | [ sample ] | | |
154 | * | [ sample ] | | |
155 | * --> go to codecs | |
5bfb9ad0 KM |
156 | */ |
157 | ||
c8fe2574 KM |
158 | /* |
159 | * struct | |
160 | */ | |
a4d7d550 | 161 | |
5e97313a | 162 | struct fsi_stream_handler; |
93193c2b | 163 | struct fsi_stream { |
a4d7d550 | 164 | |
5e97313a KM |
165 | /* |
166 | * these are initialized by fsi_stream_init() | |
167 | */ | |
168 | struct snd_pcm_substream *substream; | |
2e651baf KM |
169 | int fifo_sample_capa; /* sample capacity of FSI FIFO */ |
170 | int buff_sample_capa; /* sample capacity of ALSA buffer */ | |
171 | int buff_sample_pos; /* sample position of ALSA buffer */ | |
172 | int period_samples; /* sample number / 1 period */ | |
173 | int period_pos; /* current period position */ | |
c1e6f10e | 174 | int sample_width; /* sample width */ |
1ec9bc35 KM |
175 | int uerr_num; |
176 | int oerr_num; | |
5e97313a KM |
177 | |
178 | /* | |
179 | * thse are initialized by fsi_handler_init() | |
180 | */ | |
181 | struct fsi_stream_handler *handler; | |
182 | struct fsi_priv *priv; | |
93193c2b KM |
183 | }; |
184 | ||
185 | struct fsi_priv { | |
186 | void __iomem *base; | |
187 | struct fsi_master *master; | |
188 | ||
189 | struct fsi_stream playback; | |
190 | struct fsi_stream capture; | |
3bc28070 | 191 | |
9478e0b6 KM |
192 | u32 do_fmt; |
193 | u32 di_fmt; | |
194 | ||
6a9ebad8 KM |
195 | int chan_num:16; |
196 | int clk_master:1; | |
9478e0b6 | 197 | int spdif:1; |
6a9ebad8 | 198 | |
d4bc99b9 | 199 | long rate; |
a4d7d550 KM |
200 | }; |
201 | ||
5e97313a KM |
202 | struct fsi_stream_handler { |
203 | int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io); | |
204 | int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io); | |
205 | int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io); | |
206 | }; | |
207 | #define fsi_stream_handler_call(io, func, args...) \ | |
208 | (!(io) ? -ENODEV : \ | |
209 | !((io)->handler->func) ? 0 : \ | |
210 | (io)->handler->func(args)) | |
211 | ||
73b92c1f KM |
212 | struct fsi_core { |
213 | int ver; | |
214 | ||
cc780d38 KM |
215 | u32 int_st; |
216 | u32 iemsk; | |
217 | u32 imsk; | |
2b0e7302 KM |
218 | u32 a_mclk; |
219 | u32 b_mclk; | |
cc780d38 KM |
220 | }; |
221 | ||
a4d7d550 KM |
222 | struct fsi_master { |
223 | void __iomem *base; | |
224 | int irq; | |
a4d7d550 KM |
225 | struct fsi_priv fsia; |
226 | struct fsi_priv fsib; | |
73b92c1f | 227 | struct fsi_core *core; |
a4d7d550 | 228 | struct sh_fsi_platform_info *info; |
8fc176d5 | 229 | spinlock_t lock; |
a4d7d550 KM |
230 | }; |
231 | ||
7b1b3331 KM |
232 | static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io); |
233 | ||
c8fe2574 KM |
234 | /* |
235 | * basic read write function | |
236 | */ | |
a4d7d550 | 237 | |
ca7aceef | 238 | static void __fsi_reg_write(u32 __iomem *reg, u32 data) |
a4d7d550 KM |
239 | { |
240 | /* valid data area is 24bit */ | |
241 | data &= 0x00ffffff; | |
242 | ||
0f69d978 | 243 | __raw_writel(data, reg); |
a4d7d550 KM |
244 | } |
245 | ||
ca7aceef | 246 | static u32 __fsi_reg_read(u32 __iomem *reg) |
a4d7d550 | 247 | { |
0f69d978 | 248 | return __raw_readl(reg); |
a4d7d550 KM |
249 | } |
250 | ||
ca7aceef | 251 | static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) |
a4d7d550 KM |
252 | { |
253 | u32 val = __fsi_reg_read(reg); | |
254 | ||
255 | val &= ~mask; | |
256 | val |= data & mask; | |
257 | ||
0f69d978 | 258 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
259 | } |
260 | ||
e8c8b631 | 261 | #define fsi_reg_write(p, r, d)\ |
8918b843 | 262 | __fsi_reg_write((p->base + REG_##r), d) |
a4d7d550 | 263 | |
e8c8b631 | 264 | #define fsi_reg_read(p, r)\ |
8918b843 | 265 | __fsi_reg_read((p->base + REG_##r)) |
a4d7d550 | 266 | |
e8c8b631 | 267 | #define fsi_reg_mask_set(p, r, m, d)\ |
8918b843 | 268 | __fsi_reg_mask_set((p->base + REG_##r), m, d) |
a4d7d550 | 269 | |
43fa95ca KM |
270 | #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) |
271 | #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) | |
272 | static u32 _fsi_master_read(struct fsi_master *master, u32 reg) | |
a4d7d550 | 273 | { |
8fc176d5 KM |
274 | u32 ret; |
275 | unsigned long flags; | |
276 | ||
8fc176d5 | 277 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 278 | ret = __fsi_reg_read(master->base + reg); |
8fc176d5 KM |
279 | spin_unlock_irqrestore(&master->lock, flags); |
280 | ||
281 | return ret; | |
a4d7d550 KM |
282 | } |
283 | ||
43fa95ca KM |
284 | #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) |
285 | #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) | |
286 | static void _fsi_master_mask_set(struct fsi_master *master, | |
71f6e064 | 287 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 288 | { |
8fc176d5 KM |
289 | unsigned long flags; |
290 | ||
8fc176d5 | 291 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 292 | __fsi_reg_mask_set(master->base + reg, mask, data); |
8fc176d5 | 293 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
294 | } |
295 | ||
c8fe2574 KM |
296 | /* |
297 | * basic function | |
298 | */ | |
a4d7d550 | 299 | |
71f6e064 | 300 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 301 | { |
71f6e064 | 302 | return fsi->master; |
a4d7d550 KM |
303 | } |
304 | ||
6a9ebad8 KM |
305 | static int fsi_is_clk_master(struct fsi_priv *fsi) |
306 | { | |
307 | return fsi->clk_master; | |
308 | } | |
309 | ||
a4d7d550 KM |
310 | static int fsi_is_port_a(struct fsi_priv *fsi) |
311 | { | |
71f6e064 KM |
312 | return fsi->master->base == fsi->base; |
313 | } | |
a4d7d550 | 314 | |
9478e0b6 KM |
315 | static int fsi_is_spdif(struct fsi_priv *fsi) |
316 | { | |
317 | return fsi->spdif; | |
318 | } | |
319 | ||
a449e467 KM |
320 | static int fsi_is_play(struct snd_pcm_substream *substream) |
321 | { | |
322 | return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
323 | } | |
324 | ||
142e8174 | 325 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
326 | { |
327 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 328 | |
f0fba2ad | 329 | return rtd->cpu_dai; |
142e8174 KM |
330 | } |
331 | ||
0d032c19 | 332 | static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) |
142e8174 | 333 | { |
f0fba2ad | 334 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 335 | |
f0fba2ad LG |
336 | if (dai->id == 0) |
337 | return &master->fsia; | |
338 | else | |
339 | return &master->fsib; | |
a4d7d550 KM |
340 | } |
341 | ||
0d032c19 KM |
342 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) |
343 | { | |
344 | return fsi_get_priv_frm_dai(fsi_get_dai(substream)); | |
345 | } | |
346 | ||
d7c5762b KM |
347 | static set_rate_func fsi_get_info_set_rate(struct fsi_master *master) |
348 | { | |
349 | if (!master->info) | |
350 | return NULL; | |
351 | ||
352 | return master->info->set_rate; | |
353 | } | |
354 | ||
a4d7d550 KM |
355 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) |
356 | { | |
357 | int is_porta = fsi_is_port_a(fsi); | |
71f6e064 | 358 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 359 | |
d7c5762b KM |
360 | if (!master->info) |
361 | return 0; | |
362 | ||
a4d7d550 KM |
363 | return is_porta ? master->info->porta_flags : |
364 | master->info->portb_flags; | |
365 | } | |
366 | ||
cf6edd00 | 367 | static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
368 | { |
369 | int is_porta = fsi_is_port_a(fsi); | |
cf6edd00 | 370 | u32 shift; |
a4d7d550 KM |
371 | |
372 | if (is_porta) | |
cf6edd00 | 373 | shift = is_play ? AO_SHIFT : AI_SHIFT; |
a4d7d550 | 374 | else |
cf6edd00 | 375 | shift = is_play ? BO_SHIFT : BI_SHIFT; |
a4d7d550 | 376 | |
cf6edd00 | 377 | return shift; |
a4d7d550 KM |
378 | } |
379 | ||
2e651baf KM |
380 | static int fsi_frame2sample(struct fsi_priv *fsi, int frames) |
381 | { | |
382 | return frames * fsi->chan_num; | |
383 | } | |
384 | ||
385 | static int fsi_sample2frame(struct fsi_priv *fsi, int samples) | |
386 | { | |
387 | return samples / fsi->chan_num; | |
388 | } | |
389 | ||
7b1b3331 KM |
390 | static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, |
391 | struct fsi_stream *io) | |
4e62d84d | 392 | { |
7b1b3331 | 393 | int is_play = fsi_stream_is_play(fsi, io); |
4e62d84d KM |
394 | u32 status; |
395 | int frames; | |
396 | ||
397 | status = is_play ? | |
398 | fsi_reg_read(fsi, DOFF_ST) : | |
399 | fsi_reg_read(fsi, DIFF_ST); | |
400 | ||
401 | frames = 0x1ff & (status >> 8); | |
402 | ||
403 | return fsi_frame2sample(fsi, frames); | |
404 | } | |
405 | ||
406 | static void fsi_count_fifo_err(struct fsi_priv *fsi) | |
407 | { | |
408 | u32 ostatus = fsi_reg_read(fsi, DOFF_ST); | |
409 | u32 istatus = fsi_reg_read(fsi, DIFF_ST); | |
410 | ||
411 | if (ostatus & ERR_OVER) | |
412 | fsi->playback.oerr_num++; | |
413 | ||
414 | if (ostatus & ERR_UNDER) | |
415 | fsi->playback.uerr_num++; | |
416 | ||
417 | if (istatus & ERR_OVER) | |
418 | fsi->capture.oerr_num++; | |
419 | ||
420 | if (istatus & ERR_UNDER) | |
421 | fsi->capture.uerr_num++; | |
422 | ||
423 | fsi_reg_write(fsi, DOFF_ST, 0); | |
424 | fsi_reg_write(fsi, DIFF_ST, 0); | |
425 | } | |
426 | ||
427 | /* | |
428 | * fsi_stream_xx() function | |
429 | */ | |
a449e467 KM |
430 | static inline int fsi_stream_is_play(struct fsi_priv *fsi, |
431 | struct fsi_stream *io) | |
4e62d84d | 432 | { |
a449e467 | 433 | return &fsi->playback == io; |
4e62d84d KM |
434 | } |
435 | ||
436 | static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi, | |
437 | int is_play) | |
438 | { | |
439 | return is_play ? &fsi->playback : &fsi->capture; | |
440 | } | |
441 | ||
cda828ca KM |
442 | static int fsi_stream_is_working(struct fsi_priv *fsi, |
443 | int is_play) | |
444 | { | |
4e62d84d | 445 | struct fsi_stream *io = fsi_stream_get(fsi, is_play); |
cda828ca KM |
446 | struct fsi_master *master = fsi_get_master(fsi); |
447 | unsigned long flags; | |
448 | int ret; | |
449 | ||
450 | spin_lock_irqsave(&master->lock, flags); | |
451 | ret = !!io->substream; | |
452 | spin_unlock_irqrestore(&master->lock, flags); | |
453 | ||
454 | return ret; | |
455 | } | |
456 | ||
5e97313a KM |
457 | static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io) |
458 | { | |
459 | return io->priv; | |
460 | } | |
461 | ||
8c415295 | 462 | static void fsi_stream_init(struct fsi_priv *fsi, |
93193c2b | 463 | int is_play, |
0ffe296a | 464 | struct snd_pcm_substream *substream) |
a4d7d550 | 465 | { |
4e62d84d | 466 | struct fsi_stream *io = fsi_stream_get(fsi, is_play); |
0ffe296a | 467 | struct snd_pcm_runtime *runtime = substream->runtime; |
2da65892 KM |
468 | struct fsi_master *master = fsi_get_master(fsi); |
469 | unsigned long flags; | |
93193c2b | 470 | |
2da65892 | 471 | spin_lock_irqsave(&master->lock, flags); |
93193c2b | 472 | io->substream = substream; |
2e651baf KM |
473 | io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); |
474 | io->buff_sample_pos = 0; | |
475 | io->period_samples = fsi_frame2sample(fsi, runtime->period_size); | |
476 | io->period_pos = 0; | |
c1e6f10e | 477 | io->sample_width = samples_to_bytes(runtime, 1); |
1ec9bc35 KM |
478 | io->oerr_num = -1; /* ignore 1st err */ |
479 | io->uerr_num = -1; /* ignore 1st err */ | |
2da65892 | 480 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
481 | } |
482 | ||
8c415295 | 483 | static void fsi_stream_quit(struct fsi_priv *fsi, int is_play) |
a4d7d550 | 484 | { |
4e62d84d | 485 | struct fsi_stream *io = fsi_stream_get(fsi, is_play); |
1ec9bc35 | 486 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); |
2da65892 KM |
487 | struct fsi_master *master = fsi_get_master(fsi); |
488 | unsigned long flags; | |
1ec9bc35 | 489 | |
2da65892 | 490 | spin_lock_irqsave(&master->lock, flags); |
1ec9bc35 KM |
491 | |
492 | if (io->oerr_num > 0) | |
493 | dev_err(dai->dev, "over_run = %d\n", io->oerr_num); | |
494 | ||
495 | if (io->uerr_num > 0) | |
496 | dev_err(dai->dev, "under_run = %d\n", io->uerr_num); | |
93193c2b KM |
497 | |
498 | io->substream = NULL; | |
2e651baf KM |
499 | io->buff_sample_capa = 0; |
500 | io->buff_sample_pos = 0; | |
501 | io->period_samples = 0; | |
502 | io->period_pos = 0; | |
c1e6f10e | 503 | io->sample_width = 0; |
1ec9bc35 KM |
504 | io->oerr_num = 0; |
505 | io->uerr_num = 0; | |
2da65892 | 506 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
507 | } |
508 | ||
5e97313a KM |
509 | static int fsi_stream_transfer(struct fsi_stream *io) |
510 | { | |
511 | struct fsi_priv *fsi = fsi_stream_to_priv(io); | |
512 | if (!fsi) | |
513 | return -EIO; | |
514 | ||
515 | return fsi_stream_handler_call(io, transfer, fsi, io); | |
516 | } | |
517 | ||
518 | static int fsi_stream_probe(struct fsi_priv *fsi) | |
519 | { | |
520 | struct fsi_stream *io; | |
521 | int ret1, ret2; | |
522 | ||
523 | io = &fsi->playback; | |
524 | ret1 = fsi_stream_handler_call(io, probe, fsi, io); | |
525 | ||
526 | io = &fsi->capture; | |
527 | ret2 = fsi_stream_handler_call(io, probe, fsi, io); | |
528 | ||
529 | if (ret1 < 0) | |
530 | return ret1; | |
531 | if (ret2 < 0) | |
532 | return ret2; | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
537 | static int fsi_stream_remove(struct fsi_priv *fsi) | |
538 | { | |
539 | struct fsi_stream *io; | |
540 | int ret1, ret2; | |
541 | ||
542 | io = &fsi->playback; | |
543 | ret1 = fsi_stream_handler_call(io, remove, fsi, io); | |
544 | ||
545 | io = &fsi->capture; | |
546 | ret2 = fsi_stream_handler_call(io, remove, fsi, io); | |
547 | ||
548 | if (ret1 < 0) | |
549 | return ret1; | |
550 | if (ret2 < 0) | |
551 | return ret2; | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
c8fe2574 KM |
556 | /* |
557 | * irq function | |
558 | */ | |
a4d7d550 | 559 | |
a4d7d550 KM |
560 | static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) |
561 | { | |
cf6edd00 | 562 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 563 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 564 | |
43fa95ca KM |
565 | fsi_core_mask_set(master, imsk, data, data); |
566 | fsi_core_mask_set(master, iemsk, data, data); | |
a4d7d550 KM |
567 | } |
568 | ||
569 | static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | |
570 | { | |
cf6edd00 | 571 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 572 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 573 | |
43fa95ca KM |
574 | fsi_core_mask_set(master, imsk, data, 0); |
575 | fsi_core_mask_set(master, iemsk, data, 0); | |
a4d7d550 KM |
576 | } |
577 | ||
10ea76cc KM |
578 | static u32 fsi_irq_get_status(struct fsi_master *master) |
579 | { | |
43fa95ca | 580 | return fsi_core_read(master, int_st); |
10ea76cc KM |
581 | } |
582 | ||
10ea76cc KM |
583 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
584 | { | |
585 | u32 data = 0; | |
586 | struct fsi_master *master = fsi_get_master(fsi); | |
587 | ||
cf6edd00 KM |
588 | data |= AB_IO(1, fsi_get_port_shift(fsi, 0)); |
589 | data |= AB_IO(1, fsi_get_port_shift(fsi, 1)); | |
10ea76cc KM |
590 | |
591 | /* clear interrupt factor */ | |
43fa95ca | 592 | fsi_core_mask_set(master, int_st, data, 0); |
10ea76cc KM |
593 | } |
594 | ||
c8fe2574 KM |
595 | /* |
596 | * SPDIF master clock function | |
597 | * | |
598 | * These functions are used later FSI2 | |
599 | */ | |
3bc28070 KM |
600 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
601 | { | |
602 | struct fsi_master *master = fsi_get_master(fsi); | |
2b0e7302 | 603 | u32 mask, val; |
3bc28070 KM |
604 | |
605 | if (master->core->ver < 2) { | |
606 | pr_err("fsi: register access err (%s)\n", __func__); | |
607 | return; | |
608 | } | |
609 | ||
2b0e7302 KM |
610 | mask = BP | SE; |
611 | val = enable ? mask : 0; | |
612 | ||
613 | fsi_is_port_a(fsi) ? | |
43fa95ca KM |
614 | fsi_core_mask_set(master, a_mclk, mask, val) : |
615 | fsi_core_mask_set(master, b_mclk, mask, val); | |
3bc28070 KM |
616 | } |
617 | ||
c8fe2574 | 618 | /* |
1f5e2a31 | 619 | * clock function |
c8fe2574 | 620 | */ |
4f56cde1 KM |
621 | static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi, |
622 | long rate, int enable) | |
623 | { | |
624 | struct fsi_master *master = fsi_get_master(fsi); | |
625 | set_rate_func set_rate = fsi_get_info_set_rate(master); | |
626 | int fsi_ver = master->core->ver; | |
627 | int ret; | |
628 | ||
629 | ret = set_rate(dev, fsi_is_port_a(fsi), rate, enable); | |
630 | if (ret < 0) /* error */ | |
631 | return ret; | |
632 | ||
633 | if (!enable) | |
634 | return 0; | |
635 | ||
636 | if (ret > 0) { | |
637 | u32 data = 0; | |
638 | ||
639 | switch (ret & SH_FSI_ACKMD_MASK) { | |
640 | default: | |
641 | /* FALL THROUGH */ | |
642 | case SH_FSI_ACKMD_512: | |
643 | data |= (0x0 << 12); | |
644 | break; | |
645 | case SH_FSI_ACKMD_256: | |
646 | data |= (0x1 << 12); | |
647 | break; | |
648 | case SH_FSI_ACKMD_128: | |
649 | data |= (0x2 << 12); | |
650 | break; | |
651 | case SH_FSI_ACKMD_64: | |
652 | data |= (0x3 << 12); | |
653 | break; | |
654 | case SH_FSI_ACKMD_32: | |
655 | if (fsi_ver < 2) | |
656 | dev_err(dev, "unsupported ACKMD\n"); | |
657 | else | |
658 | data |= (0x4 << 12); | |
659 | break; | |
660 | } | |
661 | ||
662 | switch (ret & SH_FSI_BPFMD_MASK) { | |
663 | default: | |
664 | /* FALL THROUGH */ | |
665 | case SH_FSI_BPFMD_32: | |
666 | data |= (0x0 << 8); | |
667 | break; | |
668 | case SH_FSI_BPFMD_64: | |
669 | data |= (0x1 << 8); | |
670 | break; | |
671 | case SH_FSI_BPFMD_128: | |
672 | data |= (0x2 << 8); | |
673 | break; | |
674 | case SH_FSI_BPFMD_256: | |
675 | data |= (0x3 << 8); | |
676 | break; | |
677 | case SH_FSI_BPFMD_512: | |
678 | data |= (0x4 << 8); | |
679 | break; | |
680 | case SH_FSI_BPFMD_16: | |
681 | if (fsi_ver < 2) | |
682 | dev_err(dev, "unsupported ACKMD\n"); | |
683 | else | |
684 | data |= (0x7 << 8); | |
685 | break; | |
686 | } | |
687 | ||
688 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
689 | udelay(10); | |
690 | ret = 0; | |
691 | } | |
692 | ||
693 | return ret; | |
4f56cde1 KM |
694 | } |
695 | ||
1ddddd36 KM |
696 | #define fsi_port_start(f, i) __fsi_port_clk_ctrl(f, i, 1) |
697 | #define fsi_port_stop(f, i) __fsi_port_clk_ctrl(f, i, 0) | |
698 | static void __fsi_port_clk_ctrl(struct fsi_priv *fsi, int is_play, int enable) | |
a4d7d550 | 699 | { |
71f6e064 | 700 | struct fsi_master *master = fsi_get_master(fsi); |
1f5e2a31 | 701 | u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; |
a4d7d550 | 702 | |
1ddddd36 KM |
703 | if (enable) |
704 | fsi_irq_enable(fsi, is_play); | |
705 | else | |
706 | fsi_irq_disable(fsi, is_play); | |
707 | ||
cda828ca | 708 | if (fsi_is_clk_master(fsi)) |
1f5e2a31 | 709 | fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); |
a4d7d550 KM |
710 | } |
711 | ||
1b0ca1a0 | 712 | |
1f5e2a31 | 713 | /* |
1b0ca1a0 | 714 | * pio data transfer handler |
1f5e2a31 | 715 | */ |
1b0ca1a0 KM |
716 | static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples) |
717 | { | |
718 | u16 *buf = (u16 *)_buf; | |
719 | int i; | |
720 | ||
721 | for (i = 0; i < samples; i++) | |
722 | fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8)); | |
723 | } | |
724 | ||
725 | static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples) | |
726 | { | |
727 | u16 *buf = (u16 *)_buf; | |
728 | int i; | |
729 | ||
730 | for (i = 0; i < samples; i++) | |
731 | *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); | |
732 | } | |
733 | ||
734 | static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples) | |
735 | { | |
736 | u32 *buf = (u32 *)_buf; | |
737 | int i; | |
738 | ||
739 | for (i = 0; i < samples; i++) | |
740 | fsi_reg_write(fsi, DODT, *(buf + i)); | |
741 | } | |
742 | ||
743 | static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples) | |
744 | { | |
745 | u32 *buf = (u32 *)_buf; | |
746 | int i; | |
747 | ||
748 | for (i = 0; i < samples; i++) | |
749 | *(buf + i) = fsi_reg_read(fsi, DIDT); | |
750 | } | |
751 | ||
752 | static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io) | |
753 | { | |
754 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
755 | ||
756 | return runtime->dma_area + | |
757 | samples_to_bytes(runtime, io->buff_sample_pos); | |
758 | } | |
759 | ||
760 | static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io, | |
95b0cf05 KM |
761 | void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples), |
762 | void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples), | |
763 | int samples) | |
a4d7d550 KM |
764 | { |
765 | struct snd_pcm_runtime *runtime; | |
376cf38a | 766 | struct snd_pcm_substream *substream; |
95b0cf05 | 767 | u8 *buf; |
b9fde18c | 768 | int over_period; |
a4d7d550 KM |
769 | |
770 | if (!fsi || | |
93193c2b KM |
771 | !io->substream || |
772 | !io->substream->runtime) | |
a4d7d550 KM |
773 | return -EINVAL; |
774 | ||
1c418d1f | 775 | over_period = 0; |
93193c2b | 776 | substream = io->substream; |
1c418d1f | 777 | runtime = substream->runtime; |
a4d7d550 KM |
778 | |
779 | /* FSI FIFO has limit. | |
780 | * So, this driver can not send periods data at a time | |
781 | */ | |
2e651baf KM |
782 | if (io->buff_sample_pos >= |
783 | io->period_samples * (io->period_pos + 1)) { | |
a4d7d550 | 784 | |
1c418d1f | 785 | over_period = 1; |
2e651baf | 786 | io->period_pos = (io->period_pos + 1) % runtime->periods; |
a4d7d550 | 787 | |
2e651baf KM |
788 | if (0 == io->period_pos) |
789 | io->buff_sample_pos = 0; | |
a4d7d550 KM |
790 | } |
791 | ||
95b0cf05 KM |
792 | buf = fsi_pio_get_area(fsi, io); |
793 | ||
376cf38a KM |
794 | switch (io->sample_width) { |
795 | case 2: | |
95b0cf05 | 796 | run16(fsi, buf, samples); |
376cf38a KM |
797 | break; |
798 | case 4: | |
95b0cf05 | 799 | run32(fsi, buf, samples); |
376cf38a KM |
800 | break; |
801 | default: | |
802 | return -EINVAL; | |
d8b33534 | 803 | } |
a4d7d550 | 804 | |
2e651baf KM |
805 | /* update buff_sample_pos */ |
806 | io->buff_sample_pos += samples; | |
a4d7d550 | 807 | |
1c418d1f | 808 | if (over_period) |
a4d7d550 KM |
809 | snd_pcm_period_elapsed(substream); |
810 | ||
47fc9a0a | 811 | return 0; |
a4d7d550 KM |
812 | } |
813 | ||
5e97313a | 814 | static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io) |
07102f3c | 815 | { |
376cf38a KM |
816 | int sample_residues; /* samples in FSI fifo */ |
817 | int sample_space; /* ALSA free samples space */ | |
818 | int samples; | |
376cf38a | 819 | |
7b1b3331 | 820 | sample_residues = fsi_get_current_fifo_samples(fsi, io); |
376cf38a KM |
821 | sample_space = io->buff_sample_capa - io->buff_sample_pos; |
822 | ||
823 | samples = min(sample_residues, sample_space); | |
824 | ||
1b0ca1a0 | 825 | return fsi_pio_transfer(fsi, io, |
d78629e2 KM |
826 | fsi_pio_pop16, |
827 | fsi_pio_pop32, | |
376cf38a | 828 | samples); |
d8b33534 | 829 | } |
07102f3c | 830 | |
5e97313a | 831 | static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io) |
d8b33534 | 832 | { |
376cf38a KM |
833 | int sample_residues; /* ALSA residue samples */ |
834 | int sample_space; /* FSI fifo free samples space */ | |
835 | int samples; | |
376cf38a KM |
836 | |
837 | sample_residues = io->buff_sample_capa - io->buff_sample_pos; | |
838 | sample_space = io->fifo_sample_capa - | |
7b1b3331 | 839 | fsi_get_current_fifo_samples(fsi, io); |
376cf38a KM |
840 | |
841 | samples = min(sample_residues, sample_space); | |
842 | ||
1b0ca1a0 | 843 | return fsi_pio_transfer(fsi, io, |
d78629e2 KM |
844 | fsi_pio_push16, |
845 | fsi_pio_push32, | |
376cf38a | 846 | samples); |
07102f3c KM |
847 | } |
848 | ||
5e97313a KM |
849 | static struct fsi_stream_handler fsi_pio_push_handler = { |
850 | .transfer = fsi_pio_push, | |
851 | }; | |
852 | ||
853 | static struct fsi_stream_handler fsi_pio_pop_handler = { | |
854 | .transfer = fsi_pio_pop, | |
855 | }; | |
856 | ||
a4d7d550 KM |
857 | static irqreturn_t fsi_interrupt(int irq, void *data) |
858 | { | |
71f6e064 | 859 | struct fsi_master *master = data; |
10ea76cc | 860 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
861 | |
862 | /* clear irq status */ | |
feb58cff KM |
863 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
864 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 | 865 | |
cf6edd00 | 866 | if (int_st & AB_IO(1, AO_SHIFT)) |
5e97313a | 867 | fsi_stream_transfer(&master->fsia.playback); |
cf6edd00 | 868 | if (int_st & AB_IO(1, BO_SHIFT)) |
5e97313a | 869 | fsi_stream_transfer(&master->fsib.playback); |
cf6edd00 | 870 | if (int_st & AB_IO(1, AI_SHIFT)) |
5e97313a | 871 | fsi_stream_transfer(&master->fsia.capture); |
cf6edd00 | 872 | if (int_st & AB_IO(1, BI_SHIFT)) |
5e97313a | 873 | fsi_stream_transfer(&master->fsib.capture); |
1ec9bc35 KM |
874 | |
875 | fsi_count_fifo_err(&master->fsia); | |
876 | fsi_count_fifo_err(&master->fsib); | |
a4d7d550 | 877 | |
48d78e58 KM |
878 | fsi_irq_clear_status(&master->fsia); |
879 | fsi_irq_clear_status(&master->fsib); | |
a4d7d550 KM |
880 | |
881 | return IRQ_HANDLED; | |
882 | } | |
883 | ||
c8fe2574 KM |
884 | /* |
885 | * dai ops | |
886 | */ | |
b49e8027 KM |
887 | static void fsi_fifo_init(struct fsi_priv *fsi, |
888 | int is_play, | |
889 | struct device *dev) | |
890 | { | |
891 | struct fsi_master *master = fsi_get_master(fsi); | |
892 | struct fsi_stream *io = fsi_stream_get(fsi, is_play); | |
893 | u32 shift, i; | |
894 | int frame_capa; | |
895 | ||
896 | /* get on-chip RAM capacity */ | |
897 | shift = fsi_master_read(master, FIFO_SZ); | |
898 | shift >>= fsi_get_port_shift(fsi, is_play); | |
899 | shift &= FIFO_SZ_MASK; | |
900 | frame_capa = 256 << shift; | |
901 | dev_dbg(dev, "fifo = %d words\n", frame_capa); | |
902 | ||
903 | /* | |
904 | * The maximum number of sample data varies depending | |
905 | * on the number of channels selected for the format. | |
906 | * | |
907 | * FIFOs are used in 4-channel units in 3-channel mode | |
908 | * and in 8-channel units in 5- to 7-channel mode | |
909 | * meaning that more FIFOs than the required size of DPRAM | |
910 | * are used. | |
911 | * | |
912 | * ex) if 256 words of DP-RAM is connected | |
913 | * 1 channel: 256 (256 x 1 = 256) | |
914 | * 2 channels: 128 (128 x 2 = 256) | |
915 | * 3 channels: 64 ( 64 x 3 = 192) | |
916 | * 4 channels: 64 ( 64 x 4 = 256) | |
917 | * 5 channels: 32 ( 32 x 5 = 160) | |
918 | * 6 channels: 32 ( 32 x 6 = 192) | |
919 | * 7 channels: 32 ( 32 x 7 = 224) | |
920 | * 8 channels: 32 ( 32 x 8 = 256) | |
921 | */ | |
922 | for (i = 1; i < fsi->chan_num; i <<= 1) | |
923 | frame_capa >>= 1; | |
924 | dev_dbg(dev, "%d channel %d store\n", | |
925 | fsi->chan_num, frame_capa); | |
926 | ||
927 | io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); | |
928 | ||
929 | /* | |
930 | * set interrupt generation factor | |
931 | * clear FIFO | |
932 | */ | |
933 | if (is_play) { | |
934 | fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); | |
935 | fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); | |
936 | } else { | |
937 | fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); | |
938 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
939 | } | |
940 | } | |
a4d7d550 | 941 | |
23ca8533 KM |
942 | static int fsi_hw_startup(struct fsi_priv *fsi, |
943 | int is_play, | |
944 | struct device *dev) | |
a4d7d550 | 945 | { |
65ff03f4 KM |
946 | struct fsi_master *master = fsi_get_master(fsi); |
947 | int fsi_ver = master->core->ver; | |
93193c2b | 948 | u32 flags = fsi_get_info_flags(fsi); |
9478e0b6 | 949 | u32 data = 0; |
a4d7d550 | 950 | |
9478e0b6 KM |
951 | /* clock setting */ |
952 | if (fsi_is_clk_master(fsi)) | |
953 | data = DIMD | DOMD; | |
954 | ||
955 | fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); | |
a4d7d550 KM |
956 | |
957 | /* clock inversion (CKG2) */ | |
958 | data = 0; | |
b427b44c KM |
959 | if (SH_FSI_LRM_INV & flags) |
960 | data |= 1 << 12; | |
961 | if (SH_FSI_BRM_INV & flags) | |
962 | data |= 1 << 8; | |
963 | if (SH_FSI_LRS_INV & flags) | |
964 | data |= 1 << 4; | |
965 | if (SH_FSI_BRS_INV & flags) | |
966 | data |= 1 << 0; | |
967 | ||
a4d7d550 KM |
968 | fsi_reg_write(fsi, CKG2, data); |
969 | ||
9478e0b6 KM |
970 | /* set format */ |
971 | fsi_reg_write(fsi, DO_FMT, fsi->do_fmt); | |
972 | fsi_reg_write(fsi, DI_FMT, fsi->di_fmt); | |
973 | ||
974 | /* spdif ? */ | |
975 | if (fsi_is_spdif(fsi)) { | |
976 | fsi_spdif_clk_ctrl(fsi, 1); | |
977 | fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); | |
978 | } | |
979 | ||
65ff03f4 KM |
980 | /* |
981 | * FIXME | |
982 | * | |
983 | * FSI driver assumed that data package is in-back. | |
984 | * FSI2 chip can select it. | |
985 | */ | |
986 | if (fsi_ver >= 2) { | |
987 | fsi_reg_write(fsi, OUT_DMAC, (1 << 4)); | |
988 | fsi_reg_write(fsi, IN_DMAC, (1 << 4)); | |
989 | } | |
990 | ||
10ea76cc KM |
991 | /* irq clear */ |
992 | fsi_irq_disable(fsi, is_play); | |
993 | fsi_irq_clear_status(fsi); | |
994 | ||
995 | /* fifo init */ | |
23ca8533 | 996 | fsi_fifo_init(fsi, is_play, dev); |
a4d7d550 | 997 | |
a68a3b4e | 998 | return 0; |
a4d7d550 KM |
999 | } |
1000 | ||
23ca8533 | 1001 | static void fsi_hw_shutdown(struct fsi_priv *fsi, |
23ca8533 KM |
1002 | struct device *dev) |
1003 | { | |
1004 | if (fsi_is_clk_master(fsi)) | |
1005 | fsi_set_master_clk(dev, fsi, fsi->rate, 0); | |
23ca8533 KM |
1006 | } |
1007 | ||
1008 | static int fsi_dai_startup(struct snd_pcm_substream *substream, | |
1009 | struct snd_soc_dai *dai) | |
1010 | { | |
1011 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
1012 | int is_play = fsi_is_play(substream); | |
1013 | ||
1014 | return fsi_hw_startup(fsi, is_play, dai->dev); | |
1015 | } | |
1016 | ||
a4d7d550 KM |
1017 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, |
1018 | struct snd_soc_dai *dai) | |
1019 | { | |
71f6e064 | 1020 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 | 1021 | |
41bba151 | 1022 | fsi_hw_shutdown(fsi, dai->dev); |
d4bc99b9 | 1023 | fsi->rate = 0; |
a4d7d550 KM |
1024 | } |
1025 | ||
1026 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
1027 | struct snd_soc_dai *dai) | |
1028 | { | |
71f6e064 | 1029 | struct fsi_priv *fsi = fsi_get_priv(substream); |
5e97313a | 1030 | struct fsi_stream *io = fsi_stream_get(fsi, fsi_is_play(substream)); |
00545785 | 1031 | int is_play = fsi_is_play(substream); |
a4d7d550 KM |
1032 | int ret = 0; |
1033 | ||
a4d7d550 KM |
1034 | switch (cmd) { |
1035 | case SNDRV_PCM_TRIGGER_START: | |
8c415295 | 1036 | fsi_stream_init(fsi, is_play, substream); |
5e97313a KM |
1037 | ret = fsi_stream_transfer(io); |
1038 | if (0 == ret) | |
1039 | fsi_port_start(fsi, is_play); | |
a4d7d550 KM |
1040 | break; |
1041 | case SNDRV_PCM_TRIGGER_STOP: | |
1ddddd36 | 1042 | fsi_port_stop(fsi, is_play); |
8c415295 | 1043 | fsi_stream_quit(fsi, is_play); |
a4d7d550 KM |
1044 | break; |
1045 | } | |
1046 | ||
1047 | return ret; | |
1048 | } | |
1049 | ||
f17c13ca KM |
1050 | static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) |
1051 | { | |
1052 | u32 data = 0; | |
1053 | ||
1054 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1055 | case SND_SOC_DAIFMT_I2S: | |
1056 | data = CR_I2S; | |
1057 | fsi->chan_num = 2; | |
1058 | break; | |
1059 | case SND_SOC_DAIFMT_LEFT_J: | |
1060 | data = CR_PCM; | |
1061 | fsi->chan_num = 2; | |
1062 | break; | |
1063 | default: | |
1064 | return -EINVAL; | |
1065 | } | |
1066 | ||
9478e0b6 KM |
1067 | fsi->do_fmt = data; |
1068 | fsi->di_fmt = data; | |
f17c13ca KM |
1069 | |
1070 | return 0; | |
1071 | } | |
1072 | ||
1073 | static int fsi_set_fmt_spdif(struct fsi_priv *fsi) | |
1074 | { | |
1075 | struct fsi_master *master = fsi_get_master(fsi); | |
1076 | u32 data = 0; | |
1077 | ||
1078 | if (master->core->ver < 2) | |
1079 | return -EINVAL; | |
1080 | ||
1081 | data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM; | |
1082 | fsi->chan_num = 2; | |
9478e0b6 | 1083 | fsi->spdif = 1; |
f17c13ca | 1084 | |
9478e0b6 KM |
1085 | fsi->do_fmt = data; |
1086 | fsi->di_fmt = data; | |
f17c13ca KM |
1087 | |
1088 | return 0; | |
1089 | } | |
1090 | ||
4d805f7b KM |
1091 | static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
1092 | { | |
1093 | struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); | |
6a9ebad8 KM |
1094 | struct fsi_master *master = fsi_get_master(fsi); |
1095 | set_rate_func set_rate = fsi_get_info_set_rate(master); | |
f17c13ca | 1096 | u32 flags = fsi_get_info_flags(fsi); |
4d805f7b KM |
1097 | int ret; |
1098 | ||
4d805f7b KM |
1099 | /* set master/slave audio interface */ |
1100 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1101 | case SND_SOC_DAIFMT_CBM_CFM: | |
6a9ebad8 | 1102 | fsi->clk_master = 1; |
4d805f7b KM |
1103 | break; |
1104 | case SND_SOC_DAIFMT_CBS_CFS: | |
1105 | break; | |
1106 | default: | |
9478e0b6 | 1107 | return -EINVAL; |
4d805f7b | 1108 | } |
6a9ebad8 KM |
1109 | |
1110 | if (fsi_is_clk_master(fsi) && !set_rate) { | |
1111 | dev_err(dai->dev, "platform doesn't have set_rate\n"); | |
9478e0b6 | 1112 | return -EINVAL; |
6a9ebad8 KM |
1113 | } |
1114 | ||
f17c13ca KM |
1115 | /* set format */ |
1116 | switch (flags & SH_FSI_FMT_MASK) { | |
1117 | case SH_FSI_FMT_DAI: | |
1118 | ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); | |
1119 | break; | |
1120 | case SH_FSI_FMT_SPDIF: | |
1121 | ret = fsi_set_fmt_spdif(fsi); | |
1122 | break; | |
1123 | default: | |
1124 | ret = -EINVAL; | |
1125 | } | |
4d805f7b | 1126 | |
4d805f7b KM |
1127 | return ret; |
1128 | } | |
1129 | ||
ccad7b44 KM |
1130 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
1131 | struct snd_pcm_hw_params *params, | |
1132 | struct snd_soc_dai *dai) | |
1133 | { | |
1134 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
d4bc99b9 | 1135 | long rate = params_rate(params); |
ccad7b44 KM |
1136 | int ret; |
1137 | ||
6a9ebad8 | 1138 | if (!fsi_is_clk_master(fsi)) |
ccad7b44 KM |
1139 | return 0; |
1140 | ||
4f56cde1 KM |
1141 | ret = fsi_set_master_clk(dai->dev, fsi, rate, 1); |
1142 | if (ret < 0) | |
d4bc99b9 | 1143 | return ret; |
ccad7b44 | 1144 | |
d4bc99b9 | 1145 | fsi->rate = rate; |
ccad7b44 KM |
1146 | |
1147 | return ret; | |
ccad7b44 KM |
1148 | } |
1149 | ||
85e7652d | 1150 | static const struct snd_soc_dai_ops fsi_dai_ops = { |
a4d7d550 KM |
1151 | .startup = fsi_dai_startup, |
1152 | .shutdown = fsi_dai_shutdown, | |
1153 | .trigger = fsi_dai_trigger, | |
4d805f7b | 1154 | .set_fmt = fsi_dai_set_fmt, |
ccad7b44 | 1155 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
1156 | }; |
1157 | ||
c8fe2574 KM |
1158 | /* |
1159 | * pcm ops | |
1160 | */ | |
a4d7d550 | 1161 | |
a4d7d550 KM |
1162 | static struct snd_pcm_hardware fsi_pcm_hardware = { |
1163 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
1164 | SNDRV_PCM_INFO_MMAP | | |
1165 | SNDRV_PCM_INFO_MMAP_VALID | | |
1166 | SNDRV_PCM_INFO_PAUSE, | |
1167 | .formats = FSI_FMTS, | |
1168 | .rates = FSI_RATES, | |
1169 | .rate_min = 8000, | |
1170 | .rate_max = 192000, | |
1171 | .channels_min = 1, | |
1172 | .channels_max = 2, | |
1173 | .buffer_bytes_max = 64 * 1024, | |
1174 | .period_bytes_min = 32, | |
1175 | .period_bytes_max = 8192, | |
1176 | .periods_min = 1, | |
1177 | .periods_max = 32, | |
1178 | .fifo_size = 256, | |
1179 | }; | |
1180 | ||
1181 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
1182 | { | |
1183 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1184 | int ret = 0; | |
1185 | ||
1186 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
1187 | ||
1188 | ret = snd_pcm_hw_constraint_integer(runtime, | |
1189 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1190 | ||
1191 | return ret; | |
1192 | } | |
1193 | ||
1194 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
1195 | struct snd_pcm_hw_params *hw_params) | |
1196 | { | |
1197 | return snd_pcm_lib_malloc_pages(substream, | |
1198 | params_buffer_bytes(hw_params)); | |
1199 | } | |
1200 | ||
1201 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
1202 | { | |
1203 | return snd_pcm_lib_free_pages(substream); | |
1204 | } | |
1205 | ||
1206 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
1207 | { | |
71f6e064 | 1208 | struct fsi_priv *fsi = fsi_get_priv(substream); |
4e62d84d | 1209 | struct fsi_stream *io = fsi_stream_get(fsi, fsi_is_play(substream)); |
2e651baf | 1210 | int samples_pos = io->buff_sample_pos - 1; |
a4d7d550 | 1211 | |
2e651baf KM |
1212 | if (samples_pos < 0) |
1213 | samples_pos = 0; | |
a4d7d550 | 1214 | |
2e651baf | 1215 | return fsi_sample2frame(fsi, samples_pos); |
a4d7d550 KM |
1216 | } |
1217 | ||
1218 | static struct snd_pcm_ops fsi_pcm_ops = { | |
1219 | .open = fsi_pcm_open, | |
1220 | .ioctl = snd_pcm_lib_ioctl, | |
1221 | .hw_params = fsi_hw_params, | |
1222 | .hw_free = fsi_hw_free, | |
1223 | .pointer = fsi_pointer, | |
1224 | }; | |
1225 | ||
c8fe2574 KM |
1226 | /* |
1227 | * snd_soc_platform | |
1228 | */ | |
a4d7d550 | 1229 | |
a4d7d550 KM |
1230 | #define PREALLOC_BUFFER (32 * 1024) |
1231 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1232 | ||
1233 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1234 | { | |
1235 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1236 | } | |
1237 | ||
552d1ef6 | 1238 | static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd) |
a4d7d550 | 1239 | { |
552d1ef6 LG |
1240 | struct snd_pcm *pcm = rtd->pcm; |
1241 | ||
a4d7d550 KM |
1242 | /* |
1243 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1244 | * in MMAP mode (i.e. aplay -M) | |
1245 | */ | |
1246 | return snd_pcm_lib_preallocate_pages_for_all( | |
1247 | pcm, | |
1248 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1249 | snd_dma_continuous_data(GFP_KERNEL), | |
1250 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1251 | } | |
1252 | ||
c8fe2574 KM |
1253 | /* |
1254 | * alsa struct | |
1255 | */ | |
a4d7d550 | 1256 | |
f0fba2ad | 1257 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1258 | { |
f0fba2ad | 1259 | .name = "fsia-dai", |
a4d7d550 KM |
1260 | .playback = { |
1261 | .rates = FSI_RATES, | |
1262 | .formats = FSI_FMTS, | |
1263 | .channels_min = 1, | |
1264 | .channels_max = 8, | |
1265 | }, | |
07102f3c KM |
1266 | .capture = { |
1267 | .rates = FSI_RATES, | |
1268 | .formats = FSI_FMTS, | |
1269 | .channels_min = 1, | |
1270 | .channels_max = 8, | |
1271 | }, | |
a4d7d550 KM |
1272 | .ops = &fsi_dai_ops, |
1273 | }, | |
1274 | { | |
f0fba2ad | 1275 | .name = "fsib-dai", |
a4d7d550 KM |
1276 | .playback = { |
1277 | .rates = FSI_RATES, | |
1278 | .formats = FSI_FMTS, | |
1279 | .channels_min = 1, | |
1280 | .channels_max = 8, | |
1281 | }, | |
07102f3c KM |
1282 | .capture = { |
1283 | .rates = FSI_RATES, | |
1284 | .formats = FSI_FMTS, | |
1285 | .channels_min = 1, | |
1286 | .channels_max = 8, | |
1287 | }, | |
a4d7d550 KM |
1288 | .ops = &fsi_dai_ops, |
1289 | }, | |
1290 | }; | |
a4d7d550 | 1291 | |
f0fba2ad LG |
1292 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1293 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1294 | .pcm_new = fsi_pcm_new, |
1295 | .pcm_free = fsi_pcm_free, | |
1296 | }; | |
a4d7d550 | 1297 | |
c8fe2574 KM |
1298 | /* |
1299 | * platform function | |
1300 | */ | |
5e97313a KM |
1301 | static void fsi_handler_init(struct fsi_priv *fsi) |
1302 | { | |
1303 | fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */ | |
1304 | fsi->playback.priv = fsi; | |
1305 | fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */ | |
1306 | fsi->capture.priv = fsi; | |
1307 | } | |
a4d7d550 | 1308 | |
a4d7d550 KM |
1309 | static int fsi_probe(struct platform_device *pdev) |
1310 | { | |
71f6e064 | 1311 | struct fsi_master *master; |
cc780d38 | 1312 | const struct platform_device_id *id_entry; |
a4d7d550 | 1313 | struct resource *res; |
a4d7d550 KM |
1314 | unsigned int irq; |
1315 | int ret; | |
1316 | ||
cc780d38 KM |
1317 | id_entry = pdev->id_entry; |
1318 | if (!id_entry) { | |
1319 | dev_err(&pdev->dev, "unknown fsi device\n"); | |
1320 | return -ENODEV; | |
1321 | } | |
1322 | ||
a4d7d550 KM |
1323 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1324 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 1325 | if (!res || (int)irq <= 0) { |
a4d7d550 KM |
1326 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
1327 | ret = -ENODEV; | |
1328 | goto exit; | |
1329 | } | |
1330 | ||
1331 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
1332 | if (!master) { | |
1333 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
1334 | ret = -ENOMEM; | |
1335 | goto exit; | |
1336 | } | |
1337 | ||
1338 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
1339 | if (!master->base) { | |
1340 | ret = -ENXIO; | |
1341 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
1342 | goto exit_kfree; | |
1343 | } | |
1344 | ||
3bc28070 | 1345 | /* master setting */ |
a4d7d550 KM |
1346 | master->irq = irq; |
1347 | master->info = pdev->dev.platform_data; | |
3bc28070 KM |
1348 | master->core = (struct fsi_core *)id_entry->driver_data; |
1349 | spin_lock_init(&master->lock); | |
1350 | ||
1351 | /* FSI A setting */ | |
a4d7d550 | 1352 | master->fsia.base = master->base; |
71f6e064 | 1353 | master->fsia.master = master; |
5e97313a KM |
1354 | fsi_handler_init(&master->fsia); |
1355 | ret = fsi_stream_probe(&master->fsia); | |
1356 | if (ret < 0) { | |
1357 | dev_err(&pdev->dev, "FSIA stream probe failed\n"); | |
1358 | goto exit_iounmap; | |
1359 | } | |
3bc28070 KM |
1360 | |
1361 | /* FSI B setting */ | |
a4d7d550 | 1362 | master->fsib.base = master->base + 0x40; |
71f6e064 | 1363 | master->fsib.master = master; |
5e97313a KM |
1364 | fsi_handler_init(&master->fsib); |
1365 | ret = fsi_stream_probe(&master->fsib); | |
1366 | if (ret < 0) { | |
1367 | dev_err(&pdev->dev, "FSIB stream probe failed\n"); | |
1368 | goto exit_fsia; | |
1369 | } | |
a4d7d550 | 1370 | |
785d1c45 | 1371 | pm_runtime_enable(&pdev->dev); |
f0fba2ad | 1372 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 1373 | |
88e24c3a | 1374 | ret = request_irq(irq, &fsi_interrupt, 0, |
cc780d38 | 1375 | id_entry->name, master); |
a4d7d550 KM |
1376 | if (ret) { |
1377 | dev_err(&pdev->dev, "irq request err\n"); | |
5e97313a | 1378 | goto exit_fsib; |
a4d7d550 KM |
1379 | } |
1380 | ||
f0fba2ad | 1381 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
1382 | if (ret < 0) { |
1383 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1384 | goto exit_free_irq; | |
1385 | } | |
1386 | ||
0b5ec87d KM |
1387 | ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai, |
1388 | ARRAY_SIZE(fsi_soc_dai)); | |
1389 | if (ret < 0) { | |
1390 | dev_err(&pdev->dev, "cannot snd dai register\n"); | |
1391 | goto exit_snd_soc; | |
1392 | } | |
a4d7d550 | 1393 | |
0b5ec87d KM |
1394 | return ret; |
1395 | ||
1396 | exit_snd_soc: | |
1397 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 KM |
1398 | exit_free_irq: |
1399 | free_irq(irq, master); | |
5e97313a KM |
1400 | exit_fsib: |
1401 | fsi_stream_remove(&master->fsib); | |
1402 | exit_fsia: | |
1403 | fsi_stream_remove(&master->fsia); | |
a4d7d550 KM |
1404 | exit_iounmap: |
1405 | iounmap(master->base); | |
785d1c45 | 1406 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
1407 | exit_kfree: |
1408 | kfree(master); | |
1409 | master = NULL; | |
1410 | exit: | |
1411 | return ret; | |
1412 | } | |
1413 | ||
1414 | static int fsi_remove(struct platform_device *pdev) | |
1415 | { | |
71f6e064 KM |
1416 | struct fsi_master *master; |
1417 | ||
f0fba2ad | 1418 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 1419 | |
d985f27e | 1420 | free_irq(master->irq, master); |
785d1c45 | 1421 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 1422 | |
d985f27e KM |
1423 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); |
1424 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 | 1425 | |
5e97313a KM |
1426 | fsi_stream_remove(&master->fsia); |
1427 | fsi_stream_remove(&master->fsib); | |
1428 | ||
a4d7d550 KM |
1429 | iounmap(master->base); |
1430 | kfree(master); | |
71f6e064 | 1431 | |
a4d7d550 KM |
1432 | return 0; |
1433 | } | |
1434 | ||
106c79ec | 1435 | static void __fsi_suspend(struct fsi_priv *fsi, |
cda828ca | 1436 | int is_play, |
4f56cde1 | 1437 | struct device *dev) |
106c79ec | 1438 | { |
cda828ca KM |
1439 | if (!fsi_stream_is_working(fsi, is_play)) |
1440 | return; | |
106c79ec | 1441 | |
cda828ca | 1442 | fsi_port_stop(fsi, is_play); |
41bba151 | 1443 | fsi_hw_shutdown(fsi, dev); |
106c79ec KM |
1444 | } |
1445 | ||
1446 | static void __fsi_resume(struct fsi_priv *fsi, | |
cda828ca | 1447 | int is_play, |
4f56cde1 | 1448 | struct device *dev) |
106c79ec | 1449 | { |
cda828ca KM |
1450 | if (!fsi_stream_is_working(fsi, is_play)) |
1451 | return; | |
106c79ec | 1452 | |
cda828ca KM |
1453 | fsi_hw_startup(fsi, is_play, dev); |
1454 | ||
1455 | if (fsi_is_clk_master(fsi) && fsi->rate) | |
4f56cde1 | 1456 | fsi_set_master_clk(dev, fsi, fsi->rate, 1); |
cda828ca KM |
1457 | |
1458 | fsi_port_start(fsi, is_play); | |
1459 | ||
106c79ec KM |
1460 | } |
1461 | ||
1462 | static int fsi_suspend(struct device *dev) | |
1463 | { | |
1464 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
1465 | struct fsi_priv *fsia = &master->fsia; |
1466 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 1467 | |
cda828ca KM |
1468 | __fsi_suspend(fsia, 1, dev); |
1469 | __fsi_suspend(fsia, 0, dev); | |
106c79ec | 1470 | |
cda828ca KM |
1471 | __fsi_suspend(fsib, 1, dev); |
1472 | __fsi_suspend(fsib, 0, dev); | |
106c79ec KM |
1473 | |
1474 | return 0; | |
1475 | } | |
1476 | ||
1477 | static int fsi_resume(struct device *dev) | |
1478 | { | |
1479 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
1480 | struct fsi_priv *fsia = &master->fsia; |
1481 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 1482 | |
cda828ca KM |
1483 | __fsi_resume(fsia, 1, dev); |
1484 | __fsi_resume(fsia, 0, dev); | |
106c79ec | 1485 | |
cda828ca KM |
1486 | __fsi_resume(fsib, 1, dev); |
1487 | __fsi_resume(fsib, 0, dev); | |
106c79ec KM |
1488 | |
1489 | return 0; | |
1490 | } | |
1491 | ||
785d1c45 | 1492 | static struct dev_pm_ops fsi_pm_ops = { |
106c79ec KM |
1493 | .suspend = fsi_suspend, |
1494 | .resume = fsi_resume, | |
785d1c45 KM |
1495 | }; |
1496 | ||
73b92c1f KM |
1497 | static struct fsi_core fsi1_core = { |
1498 | .ver = 1, | |
1499 | ||
1500 | /* Interrupt */ | |
cc780d38 KM |
1501 | .int_st = INT_ST, |
1502 | .iemsk = IEMSK, | |
1503 | .imsk = IMSK, | |
1504 | }; | |
1505 | ||
73b92c1f KM |
1506 | static struct fsi_core fsi2_core = { |
1507 | .ver = 2, | |
1508 | ||
1509 | /* Interrupt */ | |
cc780d38 KM |
1510 | .int_st = CPU_INT_ST, |
1511 | .iemsk = CPU_IEMSK, | |
1512 | .imsk = CPU_IMSK, | |
2b0e7302 KM |
1513 | .a_mclk = A_MST_CTLR, |
1514 | .b_mclk = B_MST_CTLR, | |
cc780d38 KM |
1515 | }; |
1516 | ||
1517 | static struct platform_device_id fsi_id_table[] = { | |
73b92c1f KM |
1518 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
1519 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
05c69450 | 1520 | {}, |
cc780d38 | 1521 | }; |
d85a6d7b | 1522 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 1523 | |
a4d7d550 KM |
1524 | static struct platform_driver fsi_driver = { |
1525 | .driver = { | |
f0fba2ad | 1526 | .name = "fsi-pcm-audio", |
785d1c45 | 1527 | .pm = &fsi_pm_ops, |
a4d7d550 KM |
1528 | }, |
1529 | .probe = fsi_probe, | |
1530 | .remove = fsi_remove, | |
cc780d38 | 1531 | .id_table = fsi_id_table, |
a4d7d550 KM |
1532 | }; |
1533 | ||
cb5e8738 | 1534 | module_platform_driver(fsi_driver); |
a4d7d550 KM |
1535 | |
1536 | MODULE_LICENSE("GPL"); | |
1537 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1538 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); | |
b3c27b51 | 1539 | MODULE_ALIAS("platform:fsi-pcm-audio"); |