Merge branch 'for-chris' of git://git.jan-o-sch.net/btrfs-unstable into for-linus
[deliverable/linux.git] / sound / soc / sh / fsi.c
CommitLineData
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1/*
2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
a4d7d550 15#include <linux/delay.h>
7da9ced6 16#include <linux/dma-mapping.h>
785d1c45 17#include <linux/pm_runtime.h>
a4d7d550 18#include <linux/io.h>
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19#include <linux/scatterlist.h>
20#include <linux/sh_dma.h>
5a0e3ad6 21#include <linux/slab.h>
da155d5b 22#include <linux/module.h>
a4d7d550 23#include <sound/soc.h>
a4d7d550 24#include <sound/sh_fsi.h>
a4d7d550 25
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26/* PortA/PortB register */
27#define REG_DO_FMT 0x0000
28#define REG_DOFF_CTL 0x0004
29#define REG_DOFF_ST 0x0008
30#define REG_DI_FMT 0x000C
31#define REG_DIFF_CTL 0x0010
32#define REG_DIFF_ST 0x0014
33#define REG_CKG1 0x0018
34#define REG_CKG2 0x001C
35#define REG_DIDT 0x0020
36#define REG_DODT 0x0024
37#define REG_MUTE_ST 0x0028
65ff03f4 38#define REG_OUT_DMAC 0x002C
e8c8b631 39#define REG_OUT_SEL 0x0030
65ff03f4 40#define REG_IN_DMAC 0x0038
cc780d38 41
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42/* master register */
43#define MST_CLK_RST 0x0210
44#define MST_SOFT_RST 0x0214
45#define MST_FIFO_SZ 0x0218
46
47/* core register (depend on FSI version) */
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48#define A_MST_CTLR 0x0180
49#define B_MST_CTLR 0x01A0
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50#define CPU_INT_ST 0x01F4
51#define CPU_IEMSK 0x01F8
52#define CPU_IMSK 0x01FC
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53#define INT_ST 0x0200
54#define IEMSK 0x0204
55#define IMSK 0x0208
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56
57/* DO_FMT */
58/* DI_FMT */
7da9ced6 59#define CR_BWS_MASK (0x3 << 20) /* FSI2 */
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60#define CR_BWS_24 (0x0 << 20) /* FSI2 */
61#define CR_BWS_16 (0x1 << 20) /* FSI2 */
62#define CR_BWS_20 (0x2 << 20) /* FSI2 */
63
64#define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
65#define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
66#define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
67
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68#define CR_MONO (0x0 << 4)
69#define CR_MONO_D (0x1 << 4)
70#define CR_PCM (0x2 << 4)
71#define CR_I2S (0x3 << 4)
72#define CR_TDM (0x4 << 4)
73#define CR_TDM_D (0x5 << 4)
a4d7d550 74
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75/* OUT_DMAC */
76/* IN_DMAC */
77#define VDMD_MASK (0x3 << 4)
78#define VDMD_FRONT (0x0 << 4) /* Package in front */
79#define VDMD_BACK (0x1 << 4) /* Package in back */
80#define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */
81
82#define DMA_ON (0x1 << 0)
83
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84/* DOFF_CTL */
85/* DIFF_CTL */
86#define IRQ_HALF 0x00100000
87#define FIFO_CLR 0x00000001
88
89/* DOFF_ST */
90#define ERR_OVER 0x00000010
91#define ERR_UNDER 0x00000001
59c3b003 92#define ST_ERR (ERR_OVER | ERR_UNDER)
a4d7d550 93
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94/* CKG1 */
95#define ACKMD_MASK 0x00007000
96#define BPFMD_MASK 0x00000700
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97#define DIMD (1 << 4)
98#define DOMD (1 << 0)
ccad7b44 99
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100/* A/B MST_CTLR */
101#define BP (1 << 4) /* Fix the signal of Biphase output */
102#define SE (1 << 0) /* Fix the master clock */
103
a4d7d550 104/* CLK_RST */
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105#define CRB (1 << 4)
106#define CRA (1 << 0)
a4d7d550 107
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108/* IO SHIFT / MACRO */
109#define BI_SHIFT 12
110#define BO_SHIFT 8
111#define AI_SHIFT 4
112#define AO_SHIFT 0
113#define AB_IO(param, shift) (param << shift)
a4d7d550 114
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115/* SOFT_RST */
116#define PBSR (1 << 12) /* Port B Software Reset */
117#define PASR (1 << 8) /* Port A Software Reset */
118#define IR (1 << 4) /* Interrupt Reset */
119#define FSISR (1 << 0) /* Software Reset */
120
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121/* OUT_SEL (FSI2) */
122#define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
123 /* 1: Biphase and serial */
124
4a942b45 125/* FIFO_SZ */
cf6edd00 126#define FIFO_SZ_MASK 0x7
4a942b45 127
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128#define FSI_RATES SNDRV_PCM_RATE_8000_96000
129
130#define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
131
fec691e7 132typedef int (*set_rate_func)(struct device *dev, int rate, int enable);
d7c5762b 133
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134/*
135 * FSI driver use below type name for variable
136 *
5bfb9ad0 137 * xxx_num : number of data
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138 * xxx_pos : position of data
139 * xxx_capa : capacity of data
140 */
141
142/*
143 * period/frame/sample image
144 *
145 * ex) PCM (2ch)
146 *
147 * period pos period pos
148 * [n] [n + 1]
149 * |<-------------------- period--------------------->|
150 * ==|============================================ ... =|==
151 * | |
152 * ||<----- frame ----->|<------ frame ----->| ... |
153 * |+--------------------+--------------------+- ... |
154 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
155 * |+--------------------+--------------------+- ... |
156 * ==|============================================ ... =|==
157 */
158
159/*
160 * FSI FIFO image
161 *
162 * | |
163 * | |
164 * | [ sample ] |
165 * | [ sample ] |
166 * | [ sample ] |
167 * | [ sample ] |
168 * --> go to codecs
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169 */
170
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171/*
172 * struct
173 */
a4d7d550 174
5e97313a 175struct fsi_stream_handler;
93193c2b 176struct fsi_stream {
a4d7d550 177
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178 /*
179 * these are initialized by fsi_stream_init()
180 */
181 struct snd_pcm_substream *substream;
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182 int fifo_sample_capa; /* sample capacity of FSI FIFO */
183 int buff_sample_capa; /* sample capacity of ALSA buffer */
184 int buff_sample_pos; /* sample position of ALSA buffer */
185 int period_samples; /* sample number / 1 period */
186 int period_pos; /* current period position */
c1e6f10e 187 int sample_width; /* sample width */
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188 int uerr_num;
189 int oerr_num;
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190
191 /*
192 * thse are initialized by fsi_handler_init()
193 */
194 struct fsi_stream_handler *handler;
195 struct fsi_priv *priv;
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196
197 /*
198 * these are for DMAEngine
199 */
200 struct dma_chan *chan;
201 struct sh_dmae_slave slave; /* see fsi_handler_init() */
202 struct tasklet_struct tasklet;
203 dma_addr_t dma;
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204};
205
206struct fsi_priv {
207 void __iomem *base;
208 struct fsi_master *master;
fec691e7 209 struct sh_fsi_port_info *info;
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210
211 struct fsi_stream playback;
212 struct fsi_stream capture;
3bc28070 213
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214 u32 do_fmt;
215 u32 di_fmt;
216
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217 int chan_num:16;
218 int clk_master:1;
9478e0b6 219 int spdif:1;
6a9ebad8 220
d4bc99b9 221 long rate;
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222};
223
5e97313a 224struct fsi_stream_handler {
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225 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
226 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
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227 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io);
228 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
229 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
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230 void (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
231 int enable);
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232};
233#define fsi_stream_handler_call(io, func, args...) \
234 (!(io) ? -ENODEV : \
235 !((io)->handler->func) ? 0 : \
236 (io)->handler->func(args))
237
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238struct fsi_core {
239 int ver;
240
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241 u32 int_st;
242 u32 iemsk;
243 u32 imsk;
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244 u32 a_mclk;
245 u32 b_mclk;
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246};
247
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248struct fsi_master {
249 void __iomem *base;
250 int irq;
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251 struct fsi_priv fsia;
252 struct fsi_priv fsib;
73b92c1f 253 struct fsi_core *core;
8fc176d5 254 spinlock_t lock;
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255};
256
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257static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io);
258
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259/*
260 * basic read write function
261 */
a4d7d550 262
ca7aceef 263static void __fsi_reg_write(u32 __iomem *reg, u32 data)
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264{
265 /* valid data area is 24bit */
266 data &= 0x00ffffff;
267
0f69d978 268 __raw_writel(data, reg);
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269}
270
ca7aceef 271static u32 __fsi_reg_read(u32 __iomem *reg)
a4d7d550 272{
0f69d978 273 return __raw_readl(reg);
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274}
275
ca7aceef 276static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
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277{
278 u32 val = __fsi_reg_read(reg);
279
280 val &= ~mask;
281 val |= data & mask;
282
0f69d978 283 __fsi_reg_write(reg, val);
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284}
285
e8c8b631 286#define fsi_reg_write(p, r, d)\
8918b843 287 __fsi_reg_write((p->base + REG_##r), d)
a4d7d550 288
e8c8b631 289#define fsi_reg_read(p, r)\
8918b843 290 __fsi_reg_read((p->base + REG_##r))
a4d7d550 291
e8c8b631 292#define fsi_reg_mask_set(p, r, m, d)\
8918b843 293 __fsi_reg_mask_set((p->base + REG_##r), m, d)
a4d7d550 294
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295#define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
296#define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
297static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
a4d7d550 298{
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299 u32 ret;
300 unsigned long flags;
301
8fc176d5 302 spin_lock_irqsave(&master->lock, flags);
ca7aceef 303 ret = __fsi_reg_read(master->base + reg);
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304 spin_unlock_irqrestore(&master->lock, flags);
305
306 return ret;
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307}
308
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309#define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
310#define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
311static void _fsi_master_mask_set(struct fsi_master *master,
71f6e064 312 u32 reg, u32 mask, u32 data)
a4d7d550 313{
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314 unsigned long flags;
315
8fc176d5 316 spin_lock_irqsave(&master->lock, flags);
ca7aceef 317 __fsi_reg_mask_set(master->base + reg, mask, data);
8fc176d5 318 spin_unlock_irqrestore(&master->lock, flags);
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319}
320
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321/*
322 * basic function
323 */
a4d7d550 324
71f6e064 325static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
a4d7d550 326{
71f6e064 327 return fsi->master;
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328}
329
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330static int fsi_is_clk_master(struct fsi_priv *fsi)
331{
332 return fsi->clk_master;
333}
334
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335static int fsi_is_port_a(struct fsi_priv *fsi)
336{
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337 return fsi->master->base == fsi->base;
338}
a4d7d550 339
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340static int fsi_is_spdif(struct fsi_priv *fsi)
341{
342 return fsi->spdif;
343}
344
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345static int fsi_is_play(struct snd_pcm_substream *substream)
346{
347 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
348}
349
142e8174 350static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
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351{
352 struct snd_soc_pcm_runtime *rtd = substream->private_data;
142e8174 353
f0fba2ad 354 return rtd->cpu_dai;
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355}
356
0d032c19 357static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
142e8174 358{
f0fba2ad 359 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
a4d7d550 360
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361 if (dai->id == 0)
362 return &master->fsia;
363 else
364 return &master->fsib;
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365}
366
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367static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
368{
369 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
370}
371
fec691e7 372static set_rate_func fsi_get_info_set_rate(struct fsi_priv *fsi)
d7c5762b 373{
fec691e7 374 if (!fsi->info)
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375 return NULL;
376
fec691e7 377 return fsi->info->set_rate;
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378}
379
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380static u32 fsi_get_info_flags(struct fsi_priv *fsi)
381{
fec691e7 382 if (!fsi->info)
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383 return 0;
384
fec691e7 385 return fsi->info->flags;
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386}
387
938e2a8d 388static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
a4d7d550 389{
938e2a8d 390 int is_play = fsi_stream_is_play(fsi, io);
a4d7d550 391 int is_porta = fsi_is_port_a(fsi);
cf6edd00 392 u32 shift;
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393
394 if (is_porta)
cf6edd00 395 shift = is_play ? AO_SHIFT : AI_SHIFT;
a4d7d550 396 else
cf6edd00 397 shift = is_play ? BO_SHIFT : BI_SHIFT;
a4d7d550 398
cf6edd00 399 return shift;
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400}
401
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402static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
403{
404 return frames * fsi->chan_num;
405}
406
407static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
408{
409 return samples / fsi->chan_num;
410}
411
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412static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
413 struct fsi_stream *io)
4e62d84d 414{
7b1b3331 415 int is_play = fsi_stream_is_play(fsi, io);
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416 u32 status;
417 int frames;
418
419 status = is_play ?
420 fsi_reg_read(fsi, DOFF_ST) :
421 fsi_reg_read(fsi, DIFF_ST);
422
423 frames = 0x1ff & (status >> 8);
424
425 return fsi_frame2sample(fsi, frames);
426}
427
428static void fsi_count_fifo_err(struct fsi_priv *fsi)
429{
430 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
431 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
432
433 if (ostatus & ERR_OVER)
434 fsi->playback.oerr_num++;
435
436 if (ostatus & ERR_UNDER)
437 fsi->playback.uerr_num++;
438
439 if (istatus & ERR_OVER)
440 fsi->capture.oerr_num++;
441
442 if (istatus & ERR_UNDER)
443 fsi->capture.uerr_num++;
444
445 fsi_reg_write(fsi, DOFF_ST, 0);
446 fsi_reg_write(fsi, DIFF_ST, 0);
447}
448
449/*
450 * fsi_stream_xx() function
451 */
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452static inline int fsi_stream_is_play(struct fsi_priv *fsi,
453 struct fsi_stream *io)
4e62d84d 454{
a449e467 455 return &fsi->playback == io;
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456}
457
458static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
938e2a8d 459 struct snd_pcm_substream *substream)
4e62d84d 460{
938e2a8d 461 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
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462}
463
cda828ca 464static int fsi_stream_is_working(struct fsi_priv *fsi,
938e2a8d 465 struct fsi_stream *io)
cda828ca 466{
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467 struct fsi_master *master = fsi_get_master(fsi);
468 unsigned long flags;
469 int ret;
470
471 spin_lock_irqsave(&master->lock, flags);
97df8187 472 ret = !!(io->substream && io->substream->runtime);
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473 spin_unlock_irqrestore(&master->lock, flags);
474
475 return ret;
476}
477
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478static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
479{
480 return io->priv;
481}
482
8c415295 483static void fsi_stream_init(struct fsi_priv *fsi,
938e2a8d 484 struct fsi_stream *io,
0ffe296a 485 struct snd_pcm_substream *substream)
a4d7d550 486{
0ffe296a 487 struct snd_pcm_runtime *runtime = substream->runtime;
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488 struct fsi_master *master = fsi_get_master(fsi);
489 unsigned long flags;
93193c2b 490
2da65892 491 spin_lock_irqsave(&master->lock, flags);
93193c2b 492 io->substream = substream;
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493 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
494 io->buff_sample_pos = 0;
495 io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
496 io->period_pos = 0;
c1e6f10e 497 io->sample_width = samples_to_bytes(runtime, 1);
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498 io->oerr_num = -1; /* ignore 1st err */
499 io->uerr_num = -1; /* ignore 1st err */
83344027 500 fsi_stream_handler_call(io, init, fsi, io);
2da65892 501 spin_unlock_irqrestore(&master->lock, flags);
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502}
503
938e2a8d 504static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
a4d7d550 505{
1ec9bc35 506 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
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507 struct fsi_master *master = fsi_get_master(fsi);
508 unsigned long flags;
1ec9bc35 509
2da65892 510 spin_lock_irqsave(&master->lock, flags);
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511
512 if (io->oerr_num > 0)
513 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
514
515 if (io->uerr_num > 0)
516 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
93193c2b 517
83344027 518 fsi_stream_handler_call(io, quit, fsi, io);
93193c2b 519 io->substream = NULL;
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520 io->buff_sample_capa = 0;
521 io->buff_sample_pos = 0;
522 io->period_samples = 0;
523 io->period_pos = 0;
c1e6f10e 524 io->sample_width = 0;
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525 io->oerr_num = 0;
526 io->uerr_num = 0;
2da65892 527 spin_unlock_irqrestore(&master->lock, flags);
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528}
529
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530static int fsi_stream_transfer(struct fsi_stream *io)
531{
532 struct fsi_priv *fsi = fsi_stream_to_priv(io);
533 if (!fsi)
534 return -EIO;
535
536 return fsi_stream_handler_call(io, transfer, fsi, io);
537}
538
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539#define fsi_stream_start(fsi, io)\
540 fsi_stream_handler_call(io, start_stop, fsi, io, 1)
541
542#define fsi_stream_stop(fsi, io)\
543 fsi_stream_handler_call(io, start_stop, fsi, io, 0)
544
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545static int fsi_stream_probe(struct fsi_priv *fsi)
546{
547 struct fsi_stream *io;
548 int ret1, ret2;
549
550 io = &fsi->playback;
551 ret1 = fsi_stream_handler_call(io, probe, fsi, io);
552
553 io = &fsi->capture;
554 ret2 = fsi_stream_handler_call(io, probe, fsi, io);
555
556 if (ret1 < 0)
557 return ret1;
558 if (ret2 < 0)
559 return ret2;
560
561 return 0;
562}
563
564static int fsi_stream_remove(struct fsi_priv *fsi)
565{
566 struct fsi_stream *io;
567 int ret1, ret2;
568
569 io = &fsi->playback;
570 ret1 = fsi_stream_handler_call(io, remove, fsi, io);
571
572 io = &fsi->capture;
573 ret2 = fsi_stream_handler_call(io, remove, fsi, io);
574
575 if (ret1 < 0)
576 return ret1;
577 if (ret2 < 0)
578 return ret2;
579
580 return 0;
581}
582
c8fe2574
KM
583/*
584 * irq function
585 */
a4d7d550 586
938e2a8d 587static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
a4d7d550 588{
938e2a8d 589 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
71f6e064 590 struct fsi_master *master = fsi_get_master(fsi);
a4d7d550 591
43fa95ca
KM
592 fsi_core_mask_set(master, imsk, data, data);
593 fsi_core_mask_set(master, iemsk, data, data);
a4d7d550
KM
594}
595
938e2a8d 596static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
a4d7d550 597{
938e2a8d 598 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
71f6e064 599 struct fsi_master *master = fsi_get_master(fsi);
a4d7d550 600
43fa95ca
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601 fsi_core_mask_set(master, imsk, data, 0);
602 fsi_core_mask_set(master, iemsk, data, 0);
a4d7d550
KM
603}
604
10ea76cc
KM
605static u32 fsi_irq_get_status(struct fsi_master *master)
606{
43fa95ca 607 return fsi_core_read(master, int_st);
10ea76cc
KM
608}
609
10ea76cc
KM
610static void fsi_irq_clear_status(struct fsi_priv *fsi)
611{
612 u32 data = 0;
613 struct fsi_master *master = fsi_get_master(fsi);
614
938e2a8d
KM
615 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
616 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
10ea76cc
KM
617
618 /* clear interrupt factor */
43fa95ca 619 fsi_core_mask_set(master, int_st, data, 0);
10ea76cc
KM
620}
621
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622/*
623 * SPDIF master clock function
624 *
625 * These functions are used later FSI2
626 */
3bc28070
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627static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
628{
629 struct fsi_master *master = fsi_get_master(fsi);
2b0e7302 630 u32 mask, val;
3bc28070
KM
631
632 if (master->core->ver < 2) {
633 pr_err("fsi: register access err (%s)\n", __func__);
634 return;
635 }
636
2b0e7302
KM
637 mask = BP | SE;
638 val = enable ? mask : 0;
639
640 fsi_is_port_a(fsi) ?
43fa95ca
KM
641 fsi_core_mask_set(master, a_mclk, mask, val) :
642 fsi_core_mask_set(master, b_mclk, mask, val);
3bc28070
KM
643}
644
c8fe2574 645/*
1f5e2a31 646 * clock function
c8fe2574 647 */
4f56cde1
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648static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi,
649 long rate, int enable)
650{
651 struct fsi_master *master = fsi_get_master(fsi);
fec691e7 652 set_rate_func set_rate = fsi_get_info_set_rate(fsi);
4f56cde1
KM
653 int fsi_ver = master->core->ver;
654 int ret;
655
fec691e7
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656 if (!set_rate)
657 return 0;
658
659 ret = set_rate(dev, rate, enable);
4f56cde1
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660 if (ret < 0) /* error */
661 return ret;
662
663 if (!enable)
664 return 0;
665
666 if (ret > 0) {
667 u32 data = 0;
668
669 switch (ret & SH_FSI_ACKMD_MASK) {
670 default:
671 /* FALL THROUGH */
672 case SH_FSI_ACKMD_512:
673 data |= (0x0 << 12);
674 break;
675 case SH_FSI_ACKMD_256:
676 data |= (0x1 << 12);
677 break;
678 case SH_FSI_ACKMD_128:
679 data |= (0x2 << 12);
680 break;
681 case SH_FSI_ACKMD_64:
682 data |= (0x3 << 12);
683 break;
684 case SH_FSI_ACKMD_32:
685 if (fsi_ver < 2)
686 dev_err(dev, "unsupported ACKMD\n");
687 else
688 data |= (0x4 << 12);
689 break;
690 }
691
692 switch (ret & SH_FSI_BPFMD_MASK) {
693 default:
694 /* FALL THROUGH */
695 case SH_FSI_BPFMD_32:
696 data |= (0x0 << 8);
697 break;
698 case SH_FSI_BPFMD_64:
699 data |= (0x1 << 8);
700 break;
701 case SH_FSI_BPFMD_128:
702 data |= (0x2 << 8);
703 break;
704 case SH_FSI_BPFMD_256:
705 data |= (0x3 << 8);
706 break;
707 case SH_FSI_BPFMD_512:
708 data |= (0x4 << 8);
709 break;
710 case SH_FSI_BPFMD_16:
711 if (fsi_ver < 2)
712 dev_err(dev, "unsupported ACKMD\n");
713 else
714 data |= (0x7 << 8);
715 break;
716 }
717
718 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
719 udelay(10);
720 ret = 0;
721 }
722
723 return ret;
4f56cde1
KM
724}
725
1f5e2a31 726/*
1b0ca1a0 727 * pio data transfer handler
1f5e2a31 728 */
1b0ca1a0
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729static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
730{
731 u16 *buf = (u16 *)_buf;
732 int i;
733
734 for (i = 0; i < samples; i++)
735 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
736}
737
738static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
739{
740 u16 *buf = (u16 *)_buf;
741 int i;
742
743 for (i = 0; i < samples; i++)
744 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
745}
746
747static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
748{
749 u32 *buf = (u32 *)_buf;
750 int i;
751
752 for (i = 0; i < samples; i++)
753 fsi_reg_write(fsi, DODT, *(buf + i));
754}
755
756static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
757{
758 u32 *buf = (u32 *)_buf;
759 int i;
760
761 for (i = 0; i < samples; i++)
762 *(buf + i) = fsi_reg_read(fsi, DIDT);
763}
764
765static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
766{
767 struct snd_pcm_runtime *runtime = io->substream->runtime;
768
769 return runtime->dma_area +
770 samples_to_bytes(runtime, io->buff_sample_pos);
771}
772
773static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
95b0cf05
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774 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
775 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
776 int samples)
a4d7d550
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777{
778 struct snd_pcm_runtime *runtime;
376cf38a 779 struct snd_pcm_substream *substream;
95b0cf05 780 u8 *buf;
b9fde18c 781 int over_period;
a4d7d550 782
97df8187 783 if (!fsi_stream_is_working(fsi, io))
a4d7d550
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784 return -EINVAL;
785
1c418d1f 786 over_period = 0;
93193c2b 787 substream = io->substream;
1c418d1f 788 runtime = substream->runtime;
a4d7d550
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789
790 /* FSI FIFO has limit.
791 * So, this driver can not send periods data at a time
792 */
2e651baf
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793 if (io->buff_sample_pos >=
794 io->period_samples * (io->period_pos + 1)) {
a4d7d550 795
1c418d1f 796 over_period = 1;
2e651baf 797 io->period_pos = (io->period_pos + 1) % runtime->periods;
a4d7d550 798
2e651baf
KM
799 if (0 == io->period_pos)
800 io->buff_sample_pos = 0;
a4d7d550
KM
801 }
802
95b0cf05
KM
803 buf = fsi_pio_get_area(fsi, io);
804
376cf38a
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805 switch (io->sample_width) {
806 case 2:
95b0cf05 807 run16(fsi, buf, samples);
376cf38a
KM
808 break;
809 case 4:
95b0cf05 810 run32(fsi, buf, samples);
376cf38a
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811 break;
812 default:
813 return -EINVAL;
d8b33534 814 }
a4d7d550 815
2e651baf
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816 /* update buff_sample_pos */
817 io->buff_sample_pos += samples;
a4d7d550 818
1c418d1f 819 if (over_period)
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820 snd_pcm_period_elapsed(substream);
821
47fc9a0a 822 return 0;
a4d7d550
KM
823}
824
5e97313a 825static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
07102f3c 826{
376cf38a
KM
827 int sample_residues; /* samples in FSI fifo */
828 int sample_space; /* ALSA free samples space */
829 int samples;
376cf38a 830
7b1b3331 831 sample_residues = fsi_get_current_fifo_samples(fsi, io);
376cf38a
KM
832 sample_space = io->buff_sample_capa - io->buff_sample_pos;
833
834 samples = min(sample_residues, sample_space);
835
1b0ca1a0 836 return fsi_pio_transfer(fsi, io,
d78629e2
KM
837 fsi_pio_pop16,
838 fsi_pio_pop32,
376cf38a 839 samples);
d8b33534 840}
07102f3c 841
5e97313a 842static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
d8b33534 843{
376cf38a
KM
844 int sample_residues; /* ALSA residue samples */
845 int sample_space; /* FSI fifo free samples space */
846 int samples;
376cf38a
KM
847
848 sample_residues = io->buff_sample_capa - io->buff_sample_pos;
849 sample_space = io->fifo_sample_capa -
7b1b3331 850 fsi_get_current_fifo_samples(fsi, io);
376cf38a
KM
851
852 samples = min(sample_residues, sample_space);
853
1b0ca1a0 854 return fsi_pio_transfer(fsi, io,
d78629e2
KM
855 fsi_pio_push16,
856 fsi_pio_push32,
376cf38a 857 samples);
07102f3c
KM
858}
859
180346ed
KM
860static void fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
861 int enable)
862{
863 struct fsi_master *master = fsi_get_master(fsi);
864 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
865
866 if (enable)
867 fsi_irq_enable(fsi, io);
868 else
869 fsi_irq_disable(fsi, io);
870
871 if (fsi_is_clk_master(fsi))
872 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
873}
874
5e97313a
KM
875static struct fsi_stream_handler fsi_pio_push_handler = {
876 .transfer = fsi_pio_push,
180346ed 877 .start_stop = fsi_pio_start_stop,
5e97313a
KM
878};
879
880static struct fsi_stream_handler fsi_pio_pop_handler = {
881 .transfer = fsi_pio_pop,
180346ed 882 .start_stop = fsi_pio_start_stop,
5e97313a
KM
883};
884
a4d7d550
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885static irqreturn_t fsi_interrupt(int irq, void *data)
886{
71f6e064 887 struct fsi_master *master = data;
10ea76cc 888 u32 int_st = fsi_irq_get_status(master);
a4d7d550
KM
889
890 /* clear irq status */
feb58cff
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891 fsi_master_mask_set(master, SOFT_RST, IR, 0);
892 fsi_master_mask_set(master, SOFT_RST, IR, IR);
a4d7d550 893
cf6edd00 894 if (int_st & AB_IO(1, AO_SHIFT))
5e97313a 895 fsi_stream_transfer(&master->fsia.playback);
cf6edd00 896 if (int_st & AB_IO(1, BO_SHIFT))
5e97313a 897 fsi_stream_transfer(&master->fsib.playback);
cf6edd00 898 if (int_st & AB_IO(1, AI_SHIFT))
5e97313a 899 fsi_stream_transfer(&master->fsia.capture);
cf6edd00 900 if (int_st & AB_IO(1, BI_SHIFT))
5e97313a 901 fsi_stream_transfer(&master->fsib.capture);
1ec9bc35
KM
902
903 fsi_count_fifo_err(&master->fsia);
904 fsi_count_fifo_err(&master->fsib);
a4d7d550 905
48d78e58
KM
906 fsi_irq_clear_status(&master->fsia);
907 fsi_irq_clear_status(&master->fsib);
a4d7d550
KM
908
909 return IRQ_HANDLED;
910}
911
7da9ced6
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912/*
913 * dma data transfer handler
914 */
915static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
916{
917 struct snd_pcm_runtime *runtime = io->substream->runtime;
918 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
919 enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ?
920 DMA_TO_DEVICE : DMA_FROM_DEVICE;
921
922 io->dma = dma_map_single(dai->dev, runtime->dma_area,
923 snd_pcm_lib_buffer_bytes(io->substream), dir);
924 return 0;
925}
926
927static int fsi_dma_quit(struct fsi_priv *fsi, struct fsi_stream *io)
928{
929 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
930 enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ?
931 DMA_TO_DEVICE : DMA_FROM_DEVICE;
932
933 dma_unmap_single(dai->dev, io->dma,
934 snd_pcm_lib_buffer_bytes(io->substream), dir);
935 return 0;
936}
937
938static void fsi_dma_complete(void *data)
939{
940 struct fsi_stream *io = (struct fsi_stream *)data;
941 struct fsi_priv *fsi = fsi_stream_to_priv(io);
942 struct snd_pcm_runtime *runtime = io->substream->runtime;
943 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
944 enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ?
945 DMA_TO_DEVICE : DMA_FROM_DEVICE;
946
947 dma_sync_single_for_cpu(dai->dev, io->dma,
948 samples_to_bytes(runtime, io->period_samples), dir);
949
950 io->buff_sample_pos += io->period_samples;
951 io->period_pos++;
952
953 if (io->period_pos >= runtime->periods) {
954 io->period_pos = 0;
955 io->buff_sample_pos = 0;
956 }
957
958 fsi_count_fifo_err(fsi);
959 fsi_stream_transfer(io);
960
961 snd_pcm_period_elapsed(io->substream);
962}
963
964static dma_addr_t fsi_dma_get_area(struct fsi_stream *io)
965{
966 struct snd_pcm_runtime *runtime = io->substream->runtime;
967
968 return io->dma + samples_to_bytes(runtime, io->buff_sample_pos);
969}
970
971static void fsi_dma_do_tasklet(unsigned long data)
972{
973 struct fsi_stream *io = (struct fsi_stream *)data;
974 struct fsi_priv *fsi = fsi_stream_to_priv(io);
975 struct dma_chan *chan;
976 struct snd_soc_dai *dai;
977 struct dma_async_tx_descriptor *desc;
978 struct scatterlist sg;
979 struct snd_pcm_runtime *runtime;
980 enum dma_data_direction dir;
981 dma_cookie_t cookie;
982 int is_play = fsi_stream_is_play(fsi, io);
983 int len;
984 dma_addr_t buf;
985
986 if (!fsi_stream_is_working(fsi, io))
987 return;
988
989 dai = fsi_get_dai(io->substream);
990 chan = io->chan;
991 runtime = io->substream->runtime;
992 dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
993 len = samples_to_bytes(runtime, io->period_samples);
994 buf = fsi_dma_get_area(io);
995
996 dma_sync_single_for_device(dai->dev, io->dma, len, dir);
997
998 sg_init_table(&sg, 1);
999 sg_set_page(&sg, pfn_to_page(PFN_DOWN(buf)),
1000 len , offset_in_page(buf));
1001 sg_dma_address(&sg) = buf;
1002 sg_dma_len(&sg) = len;
1003
cdf27f37
PM
1004 desc = dmaengine_prep_slave_sg(chan, &sg, 1, dir,
1005 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
7da9ced6 1006 if (!desc) {
cdf27f37 1007 dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n");
7da9ced6
KM
1008 return;
1009 }
1010
1011 desc->callback = fsi_dma_complete;
1012 desc->callback_param = io;
1013
1014 cookie = desc->tx_submit(desc);
1015 if (cookie < 0) {
1016 dev_err(dai->dev, "tx_submit() fail\n");
1017 return;
1018 }
1019
1020 dma_async_issue_pending(chan);
1021
1022 /*
1023 * FIXME
1024 *
1025 * In DMAEngine case, codec and FSI cannot be started simultaneously
1026 * since FSI is using tasklet.
1027 * Therefore, in capture case, probably FSI FIFO will have got
1028 * overflow error in this point.
1029 * in that case, DMA cannot start transfer until error was cleared.
1030 */
1031 if (!is_play) {
1032 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
1033 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1034 fsi_reg_write(fsi, DIFF_ST, 0);
1035 }
1036 }
1037}
1038
1039static bool fsi_dma_filter(struct dma_chan *chan, void *param)
1040{
1041 struct sh_dmae_slave *slave = param;
1042
1043 chan->private = slave;
1044
1045 return true;
1046}
1047
1048static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
1049{
1050 tasklet_schedule(&io->tasklet);
1051
1052 return 0;
1053}
1054
1055static void fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1056 int start)
1057{
1058 u32 bws;
1059 u32 dma;
1060
1061 switch (io->sample_width * start) {
1062 case 2:
1063 bws = CR_BWS_16;
1064 dma = VDMD_STREAM | DMA_ON;
1065 break;
1066 case 4:
1067 bws = CR_BWS_24;
1068 dma = VDMD_BACK | DMA_ON;
1069 break;
1070 default:
1071 bws = 0;
1072 dma = 0;
1073 }
1074
1075 fsi_reg_mask_set(fsi, DO_FMT, CR_BWS_MASK, bws);
1076 fsi_reg_write(fsi, OUT_DMAC, dma);
1077}
1078
1079static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io)
1080{
1081 dma_cap_mask_t mask;
1082
1083 dma_cap_zero(mask);
1084 dma_cap_set(DMA_SLAVE, mask);
1085
1086 io->chan = dma_request_channel(mask, fsi_dma_filter, &io->slave);
1087 if (!io->chan)
1088 return -EIO;
1089
1090 tasklet_init(&io->tasklet, fsi_dma_do_tasklet, (unsigned long)io);
1091
1092 return 0;
1093}
1094
1095static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
1096{
1097 tasklet_kill(&io->tasklet);
1098
1099 fsi_stream_stop(fsi, io);
1100
1101 if (io->chan)
1102 dma_release_channel(io->chan);
1103
1104 io->chan = NULL;
1105 return 0;
1106}
1107
1108static struct fsi_stream_handler fsi_dma_push_handler = {
1109 .init = fsi_dma_init,
1110 .quit = fsi_dma_quit,
1111 .probe = fsi_dma_probe,
1112 .transfer = fsi_dma_transfer,
1113 .remove = fsi_dma_remove,
1114 .start_stop = fsi_dma_push_start_stop,
1115};
1116
c8fe2574
KM
1117/*
1118 * dai ops
1119 */
b49e8027 1120static void fsi_fifo_init(struct fsi_priv *fsi,
938e2a8d 1121 struct fsi_stream *io,
b49e8027
KM
1122 struct device *dev)
1123{
1124 struct fsi_master *master = fsi_get_master(fsi);
938e2a8d 1125 int is_play = fsi_stream_is_play(fsi, io);
b49e8027
KM
1126 u32 shift, i;
1127 int frame_capa;
1128
1129 /* get on-chip RAM capacity */
1130 shift = fsi_master_read(master, FIFO_SZ);
938e2a8d 1131 shift >>= fsi_get_port_shift(fsi, io);
b49e8027
KM
1132 shift &= FIFO_SZ_MASK;
1133 frame_capa = 256 << shift;
1134 dev_dbg(dev, "fifo = %d words\n", frame_capa);
1135
1136 /*
1137 * The maximum number of sample data varies depending
1138 * on the number of channels selected for the format.
1139 *
1140 * FIFOs are used in 4-channel units in 3-channel mode
1141 * and in 8-channel units in 5- to 7-channel mode
1142 * meaning that more FIFOs than the required size of DPRAM
1143 * are used.
1144 *
1145 * ex) if 256 words of DP-RAM is connected
1146 * 1 channel: 256 (256 x 1 = 256)
1147 * 2 channels: 128 (128 x 2 = 256)
1148 * 3 channels: 64 ( 64 x 3 = 192)
1149 * 4 channels: 64 ( 64 x 4 = 256)
1150 * 5 channels: 32 ( 32 x 5 = 160)
1151 * 6 channels: 32 ( 32 x 6 = 192)
1152 * 7 channels: 32 ( 32 x 7 = 224)
1153 * 8 channels: 32 ( 32 x 8 = 256)
1154 */
1155 for (i = 1; i < fsi->chan_num; i <<= 1)
1156 frame_capa >>= 1;
1157 dev_dbg(dev, "%d channel %d store\n",
1158 fsi->chan_num, frame_capa);
1159
1160 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
1161
1162 /*
1163 * set interrupt generation factor
1164 * clear FIFO
1165 */
1166 if (is_play) {
1167 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
1168 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
1169 } else {
1170 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
1171 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1172 }
1173}
a4d7d550 1174
23ca8533 1175static int fsi_hw_startup(struct fsi_priv *fsi,
938e2a8d 1176 struct fsi_stream *io,
23ca8533 1177 struct device *dev)
a4d7d550 1178{
65ff03f4
KM
1179 struct fsi_master *master = fsi_get_master(fsi);
1180 int fsi_ver = master->core->ver;
93193c2b 1181 u32 flags = fsi_get_info_flags(fsi);
9478e0b6 1182 u32 data = 0;
a4d7d550 1183
9478e0b6
KM
1184 /* clock setting */
1185 if (fsi_is_clk_master(fsi))
1186 data = DIMD | DOMD;
1187
1188 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
a4d7d550
KM
1189
1190 /* clock inversion (CKG2) */
1191 data = 0;
b427b44c
KM
1192 if (SH_FSI_LRM_INV & flags)
1193 data |= 1 << 12;
1194 if (SH_FSI_BRM_INV & flags)
1195 data |= 1 << 8;
1196 if (SH_FSI_LRS_INV & flags)
1197 data |= 1 << 4;
1198 if (SH_FSI_BRS_INV & flags)
1199 data |= 1 << 0;
1200
a4d7d550
KM
1201 fsi_reg_write(fsi, CKG2, data);
1202
9478e0b6
KM
1203 /* set format */
1204 fsi_reg_write(fsi, DO_FMT, fsi->do_fmt);
1205 fsi_reg_write(fsi, DI_FMT, fsi->di_fmt);
1206
1207 /* spdif ? */
1208 if (fsi_is_spdif(fsi)) {
1209 fsi_spdif_clk_ctrl(fsi, 1);
1210 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
1211 }
1212
65ff03f4
KM
1213 /*
1214 * FIXME
1215 *
1216 * FSI driver assumed that data package is in-back.
1217 * FSI2 chip can select it.
1218 */
1219 if (fsi_ver >= 2) {
1220 fsi_reg_write(fsi, OUT_DMAC, (1 << 4));
1221 fsi_reg_write(fsi, IN_DMAC, (1 << 4));
1222 }
1223
10ea76cc 1224 /* irq clear */
938e2a8d 1225 fsi_irq_disable(fsi, io);
10ea76cc
KM
1226 fsi_irq_clear_status(fsi);
1227
1228 /* fifo init */
938e2a8d 1229 fsi_fifo_init(fsi, io, dev);
a4d7d550 1230
a68a3b4e 1231 return 0;
a4d7d550
KM
1232}
1233
23ca8533 1234static void fsi_hw_shutdown(struct fsi_priv *fsi,
23ca8533
KM
1235 struct device *dev)
1236{
1237 if (fsi_is_clk_master(fsi))
1238 fsi_set_master_clk(dev, fsi, fsi->rate, 0);
23ca8533
KM
1239}
1240
1241static int fsi_dai_startup(struct snd_pcm_substream *substream,
1242 struct snd_soc_dai *dai)
1243{
1244 struct fsi_priv *fsi = fsi_get_priv(substream);
23ca8533 1245
938e2a8d 1246 return fsi_hw_startup(fsi, fsi_stream_get(fsi, substream), dai->dev);
23ca8533
KM
1247}
1248
a4d7d550
KM
1249static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
1250 struct snd_soc_dai *dai)
1251{
71f6e064 1252 struct fsi_priv *fsi = fsi_get_priv(substream);
a4d7d550 1253
41bba151 1254 fsi_hw_shutdown(fsi, dai->dev);
d4bc99b9 1255 fsi->rate = 0;
a4d7d550
KM
1256}
1257
1258static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
1259 struct snd_soc_dai *dai)
1260{
71f6e064 1261 struct fsi_priv *fsi = fsi_get_priv(substream);
938e2a8d 1262 struct fsi_stream *io = fsi_stream_get(fsi, substream);
a4d7d550
KM
1263 int ret = 0;
1264
a4d7d550
KM
1265 switch (cmd) {
1266 case SNDRV_PCM_TRIGGER_START:
938e2a8d 1267 fsi_stream_init(fsi, io, substream);
5e97313a
KM
1268 ret = fsi_stream_transfer(io);
1269 if (0 == ret)
180346ed 1270 fsi_stream_start(fsi, io);
a4d7d550
KM
1271 break;
1272 case SNDRV_PCM_TRIGGER_STOP:
180346ed 1273 fsi_stream_stop(fsi, io);
938e2a8d 1274 fsi_stream_quit(fsi, io);
a4d7d550
KM
1275 break;
1276 }
1277
1278 return ret;
1279}
1280
f17c13ca
KM
1281static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
1282{
1283 u32 data = 0;
1284
1285 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1286 case SND_SOC_DAIFMT_I2S:
1287 data = CR_I2S;
1288 fsi->chan_num = 2;
1289 break;
1290 case SND_SOC_DAIFMT_LEFT_J:
1291 data = CR_PCM;
1292 fsi->chan_num = 2;
1293 break;
1294 default:
1295 return -EINVAL;
1296 }
1297
9478e0b6
KM
1298 fsi->do_fmt = data;
1299 fsi->di_fmt = data;
f17c13ca
KM
1300
1301 return 0;
1302}
1303
1304static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
1305{
1306 struct fsi_master *master = fsi_get_master(fsi);
1307 u32 data = 0;
1308
1309 if (master->core->ver < 2)
1310 return -EINVAL;
1311
1312 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
1313 fsi->chan_num = 2;
9478e0b6 1314 fsi->spdif = 1;
f17c13ca 1315
9478e0b6
KM
1316 fsi->do_fmt = data;
1317 fsi->di_fmt = data;
f17c13ca
KM
1318
1319 return 0;
1320}
1321
4d805f7b
KM
1322static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1323{
1324 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
fec691e7 1325 set_rate_func set_rate = fsi_get_info_set_rate(fsi);
f17c13ca 1326 u32 flags = fsi_get_info_flags(fsi);
4d805f7b
KM
1327 int ret;
1328
4d805f7b
KM
1329 /* set master/slave audio interface */
1330 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1331 case SND_SOC_DAIFMT_CBM_CFM:
6a9ebad8 1332 fsi->clk_master = 1;
4d805f7b
KM
1333 break;
1334 case SND_SOC_DAIFMT_CBS_CFS:
1335 break;
1336 default:
9478e0b6 1337 return -EINVAL;
4d805f7b 1338 }
6a9ebad8
KM
1339
1340 if (fsi_is_clk_master(fsi) && !set_rate) {
1341 dev_err(dai->dev, "platform doesn't have set_rate\n");
9478e0b6 1342 return -EINVAL;
6a9ebad8
KM
1343 }
1344
f17c13ca
KM
1345 /* set format */
1346 switch (flags & SH_FSI_FMT_MASK) {
1347 case SH_FSI_FMT_DAI:
1348 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1349 break;
1350 case SH_FSI_FMT_SPDIF:
1351 ret = fsi_set_fmt_spdif(fsi);
1352 break;
1353 default:
1354 ret = -EINVAL;
1355 }
4d805f7b 1356
4d805f7b
KM
1357 return ret;
1358}
1359
ccad7b44
KM
1360static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
1361 struct snd_pcm_hw_params *params,
1362 struct snd_soc_dai *dai)
1363{
1364 struct fsi_priv *fsi = fsi_get_priv(substream);
d4bc99b9 1365 long rate = params_rate(params);
ccad7b44
KM
1366 int ret;
1367
6a9ebad8 1368 if (!fsi_is_clk_master(fsi))
ccad7b44
KM
1369 return 0;
1370
4f56cde1
KM
1371 ret = fsi_set_master_clk(dai->dev, fsi, rate, 1);
1372 if (ret < 0)
d4bc99b9 1373 return ret;
ccad7b44 1374
d4bc99b9 1375 fsi->rate = rate;
ccad7b44
KM
1376
1377 return ret;
ccad7b44
KM
1378}
1379
85e7652d 1380static const struct snd_soc_dai_ops fsi_dai_ops = {
a4d7d550
KM
1381 .startup = fsi_dai_startup,
1382 .shutdown = fsi_dai_shutdown,
1383 .trigger = fsi_dai_trigger,
4d805f7b 1384 .set_fmt = fsi_dai_set_fmt,
ccad7b44 1385 .hw_params = fsi_dai_hw_params,
a4d7d550
KM
1386};
1387
c8fe2574
KM
1388/*
1389 * pcm ops
1390 */
a4d7d550 1391
a4d7d550
KM
1392static struct snd_pcm_hardware fsi_pcm_hardware = {
1393 .info = SNDRV_PCM_INFO_INTERLEAVED |
1394 SNDRV_PCM_INFO_MMAP |
1395 SNDRV_PCM_INFO_MMAP_VALID |
1396 SNDRV_PCM_INFO_PAUSE,
1397 .formats = FSI_FMTS,
1398 .rates = FSI_RATES,
1399 .rate_min = 8000,
1400 .rate_max = 192000,
1401 .channels_min = 1,
1402 .channels_max = 2,
1403 .buffer_bytes_max = 64 * 1024,
1404 .period_bytes_min = 32,
1405 .period_bytes_max = 8192,
1406 .periods_min = 1,
1407 .periods_max = 32,
1408 .fifo_size = 256,
1409};
1410
1411static int fsi_pcm_open(struct snd_pcm_substream *substream)
1412{
1413 struct snd_pcm_runtime *runtime = substream->runtime;
1414 int ret = 0;
1415
1416 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1417
1418 ret = snd_pcm_hw_constraint_integer(runtime,
1419 SNDRV_PCM_HW_PARAM_PERIODS);
1420
1421 return ret;
1422}
1423
1424static int fsi_hw_params(struct snd_pcm_substream *substream,
1425 struct snd_pcm_hw_params *hw_params)
1426{
1427 return snd_pcm_lib_malloc_pages(substream,
1428 params_buffer_bytes(hw_params));
1429}
1430
1431static int fsi_hw_free(struct snd_pcm_substream *substream)
1432{
1433 return snd_pcm_lib_free_pages(substream);
1434}
1435
1436static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1437{
71f6e064 1438 struct fsi_priv *fsi = fsi_get_priv(substream);
938e2a8d 1439 struct fsi_stream *io = fsi_stream_get(fsi, substream);
a4d7d550 1440
1987877d 1441 return fsi_sample2frame(fsi, io->buff_sample_pos);
a4d7d550
KM
1442}
1443
1444static struct snd_pcm_ops fsi_pcm_ops = {
1445 .open = fsi_pcm_open,
1446 .ioctl = snd_pcm_lib_ioctl,
1447 .hw_params = fsi_hw_params,
1448 .hw_free = fsi_hw_free,
1449 .pointer = fsi_pointer,
1450};
1451
c8fe2574
KM
1452/*
1453 * snd_soc_platform
1454 */
a4d7d550 1455
a4d7d550
KM
1456#define PREALLOC_BUFFER (32 * 1024)
1457#define PREALLOC_BUFFER_MAX (32 * 1024)
1458
1459static void fsi_pcm_free(struct snd_pcm *pcm)
1460{
1461 snd_pcm_lib_preallocate_free_for_all(pcm);
1462}
1463
552d1ef6 1464static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd)
a4d7d550 1465{
552d1ef6
LG
1466 struct snd_pcm *pcm = rtd->pcm;
1467
a4d7d550
KM
1468 /*
1469 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1470 * in MMAP mode (i.e. aplay -M)
1471 */
1472 return snd_pcm_lib_preallocate_pages_for_all(
1473 pcm,
1474 SNDRV_DMA_TYPE_CONTINUOUS,
1475 snd_dma_continuous_data(GFP_KERNEL),
1476 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1477}
1478
c8fe2574
KM
1479/*
1480 * alsa struct
1481 */
a4d7d550 1482
f0fba2ad 1483static struct snd_soc_dai_driver fsi_soc_dai[] = {
a4d7d550 1484 {
f0fba2ad 1485 .name = "fsia-dai",
a4d7d550
KM
1486 .playback = {
1487 .rates = FSI_RATES,
1488 .formats = FSI_FMTS,
1489 .channels_min = 1,
1490 .channels_max = 8,
1491 },
07102f3c
KM
1492 .capture = {
1493 .rates = FSI_RATES,
1494 .formats = FSI_FMTS,
1495 .channels_min = 1,
1496 .channels_max = 8,
1497 },
a4d7d550
KM
1498 .ops = &fsi_dai_ops,
1499 },
1500 {
f0fba2ad 1501 .name = "fsib-dai",
a4d7d550
KM
1502 .playback = {
1503 .rates = FSI_RATES,
1504 .formats = FSI_FMTS,
1505 .channels_min = 1,
1506 .channels_max = 8,
1507 },
07102f3c
KM
1508 .capture = {
1509 .rates = FSI_RATES,
1510 .formats = FSI_FMTS,
1511 .channels_min = 1,
1512 .channels_max = 8,
1513 },
a4d7d550
KM
1514 .ops = &fsi_dai_ops,
1515 },
1516};
a4d7d550 1517
f0fba2ad
LG
1518static struct snd_soc_platform_driver fsi_soc_platform = {
1519 .ops = &fsi_pcm_ops,
a4d7d550
KM
1520 .pcm_new = fsi_pcm_new,
1521 .pcm_free = fsi_pcm_free,
1522};
a4d7d550 1523
c8fe2574
KM
1524/*
1525 * platform function
1526 */
5e97313a
KM
1527static void fsi_handler_init(struct fsi_priv *fsi)
1528{
1529 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */
1530 fsi->playback.priv = fsi;
1531 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */
1532 fsi->capture.priv = fsi;
7da9ced6
KM
1533
1534 if (fsi->info->tx_id) {
1535 fsi->playback.slave.slave_id = fsi->info->tx_id;
1536 fsi->playback.handler = &fsi_dma_push_handler;
1537 }
5e97313a 1538}
a4d7d550 1539
a4d7d550
KM
1540static int fsi_probe(struct platform_device *pdev)
1541{
71f6e064 1542 struct fsi_master *master;
cc780d38 1543 const struct platform_device_id *id_entry;
fec691e7 1544 struct sh_fsi_platform_info *info = pdev->dev.platform_data;
a4d7d550 1545 struct resource *res;
a4d7d550
KM
1546 unsigned int irq;
1547 int ret;
1548
cc780d38
KM
1549 id_entry = pdev->id_entry;
1550 if (!id_entry) {
1551 dev_err(&pdev->dev, "unknown fsi device\n");
1552 return -ENODEV;
1553 }
1554
a4d7d550
KM
1555 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1556 irq = platform_get_irq(pdev, 0);
b6aa1793 1557 if (!res || (int)irq <= 0) {
a4d7d550
KM
1558 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1559 ret = -ENODEV;
1560 goto exit;
1561 }
1562
1563 master = kzalloc(sizeof(*master), GFP_KERNEL);
1564 if (!master) {
1565 dev_err(&pdev->dev, "Could not allocate master\n");
1566 ret = -ENOMEM;
1567 goto exit;
1568 }
1569
1570 master->base = ioremap_nocache(res->start, resource_size(res));
1571 if (!master->base) {
1572 ret = -ENXIO;
1573 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1574 goto exit_kfree;
1575 }
1576
3bc28070 1577 /* master setting */
a4d7d550 1578 master->irq = irq;
3bc28070
KM
1579 master->core = (struct fsi_core *)id_entry->driver_data;
1580 spin_lock_init(&master->lock);
1581
1582 /* FSI A setting */
a4d7d550 1583 master->fsia.base = master->base;
71f6e064 1584 master->fsia.master = master;
fec691e7 1585 master->fsia.info = &info->port_a;
5e97313a
KM
1586 fsi_handler_init(&master->fsia);
1587 ret = fsi_stream_probe(&master->fsia);
1588 if (ret < 0) {
1589 dev_err(&pdev->dev, "FSIA stream probe failed\n");
1590 goto exit_iounmap;
1591 }
3bc28070
KM
1592
1593 /* FSI B setting */
a4d7d550 1594 master->fsib.base = master->base + 0x40;
71f6e064 1595 master->fsib.master = master;
fec691e7 1596 master->fsib.info = &info->port_b;
5e97313a
KM
1597 fsi_handler_init(&master->fsib);
1598 ret = fsi_stream_probe(&master->fsib);
1599 if (ret < 0) {
1600 dev_err(&pdev->dev, "FSIB stream probe failed\n");
1601 goto exit_fsia;
1602 }
a4d7d550 1603
785d1c45 1604 pm_runtime_enable(&pdev->dev);
f0fba2ad 1605 dev_set_drvdata(&pdev->dev, master);
a4d7d550 1606
88e24c3a 1607 ret = request_irq(irq, &fsi_interrupt, 0,
cc780d38 1608 id_entry->name, master);
a4d7d550
KM
1609 if (ret) {
1610 dev_err(&pdev->dev, "irq request err\n");
5e97313a 1611 goto exit_fsib;
a4d7d550
KM
1612 }
1613
f0fba2ad 1614 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
a4d7d550
KM
1615 if (ret < 0) {
1616 dev_err(&pdev->dev, "cannot snd soc register\n");
1617 goto exit_free_irq;
1618 }
1619
0b5ec87d
KM
1620 ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai,
1621 ARRAY_SIZE(fsi_soc_dai));
1622 if (ret < 0) {
1623 dev_err(&pdev->dev, "cannot snd dai register\n");
1624 goto exit_snd_soc;
1625 }
a4d7d550 1626
0b5ec87d
KM
1627 return ret;
1628
1629exit_snd_soc:
1630 snd_soc_unregister_platform(&pdev->dev);
a4d7d550
KM
1631exit_free_irq:
1632 free_irq(irq, master);
5e97313a
KM
1633exit_fsib:
1634 fsi_stream_remove(&master->fsib);
1635exit_fsia:
1636 fsi_stream_remove(&master->fsia);
a4d7d550
KM
1637exit_iounmap:
1638 iounmap(master->base);
785d1c45 1639 pm_runtime_disable(&pdev->dev);
a4d7d550
KM
1640exit_kfree:
1641 kfree(master);
1642 master = NULL;
1643exit:
1644 return ret;
1645}
1646
1647static int fsi_remove(struct platform_device *pdev)
1648{
71f6e064
KM
1649 struct fsi_master *master;
1650
f0fba2ad 1651 master = dev_get_drvdata(&pdev->dev);
71f6e064 1652
d985f27e 1653 free_irq(master->irq, master);
785d1c45 1654 pm_runtime_disable(&pdev->dev);
a4d7d550 1655
d985f27e
KM
1656 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1657 snd_soc_unregister_platform(&pdev->dev);
a4d7d550 1658
5e97313a
KM
1659 fsi_stream_remove(&master->fsia);
1660 fsi_stream_remove(&master->fsib);
1661
a4d7d550
KM
1662 iounmap(master->base);
1663 kfree(master);
71f6e064 1664
a4d7d550
KM
1665 return 0;
1666}
1667
106c79ec 1668static void __fsi_suspend(struct fsi_priv *fsi,
938e2a8d 1669 struct fsi_stream *io,
4f56cde1 1670 struct device *dev)
106c79ec 1671{
938e2a8d 1672 if (!fsi_stream_is_working(fsi, io))
cda828ca 1673 return;
106c79ec 1674
180346ed 1675 fsi_stream_stop(fsi, io);
41bba151 1676 fsi_hw_shutdown(fsi, dev);
106c79ec
KM
1677}
1678
1679static void __fsi_resume(struct fsi_priv *fsi,
938e2a8d 1680 struct fsi_stream *io,
4f56cde1 1681 struct device *dev)
106c79ec 1682{
938e2a8d 1683 if (!fsi_stream_is_working(fsi, io))
cda828ca 1684 return;
106c79ec 1685
938e2a8d 1686 fsi_hw_startup(fsi, io, dev);
cda828ca
KM
1687
1688 if (fsi_is_clk_master(fsi) && fsi->rate)
4f56cde1 1689 fsi_set_master_clk(dev, fsi, fsi->rate, 1);
cda828ca 1690
180346ed 1691 fsi_stream_start(fsi, io);
106c79ec
KM
1692}
1693
1694static int fsi_suspend(struct device *dev)
1695{
1696 struct fsi_master *master = dev_get_drvdata(dev);
cda828ca
KM
1697 struct fsi_priv *fsia = &master->fsia;
1698 struct fsi_priv *fsib = &master->fsib;
106c79ec 1699
938e2a8d
KM
1700 __fsi_suspend(fsia, &fsia->playback, dev);
1701 __fsi_suspend(fsia, &fsia->capture, dev);
106c79ec 1702
938e2a8d
KM
1703 __fsi_suspend(fsib, &fsib->playback, dev);
1704 __fsi_suspend(fsib, &fsib->capture, dev);
106c79ec
KM
1705
1706 return 0;
1707}
1708
1709static int fsi_resume(struct device *dev)
1710{
1711 struct fsi_master *master = dev_get_drvdata(dev);
cda828ca
KM
1712 struct fsi_priv *fsia = &master->fsia;
1713 struct fsi_priv *fsib = &master->fsib;
106c79ec 1714
938e2a8d
KM
1715 __fsi_resume(fsia, &fsia->playback, dev);
1716 __fsi_resume(fsia, &fsia->capture, dev);
106c79ec 1717
938e2a8d
KM
1718 __fsi_resume(fsib, &fsib->playback, dev);
1719 __fsi_resume(fsib, &fsib->capture, dev);
106c79ec
KM
1720
1721 return 0;
1722}
1723
785d1c45 1724static struct dev_pm_ops fsi_pm_ops = {
106c79ec
KM
1725 .suspend = fsi_suspend,
1726 .resume = fsi_resume,
785d1c45
KM
1727};
1728
73b92c1f
KM
1729static struct fsi_core fsi1_core = {
1730 .ver = 1,
1731
1732 /* Interrupt */
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1733 .int_st = INT_ST,
1734 .iemsk = IEMSK,
1735 .imsk = IMSK,
1736};
1737
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1738static struct fsi_core fsi2_core = {
1739 .ver = 2,
1740
1741 /* Interrupt */
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1742 .int_st = CPU_INT_ST,
1743 .iemsk = CPU_IEMSK,
1744 .imsk = CPU_IMSK,
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1745 .a_mclk = A_MST_CTLR,
1746 .b_mclk = B_MST_CTLR,
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1747};
1748
1749static struct platform_device_id fsi_id_table[] = {
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1750 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1751 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
05c69450 1752 {},
cc780d38 1753};
d85a6d7b 1754MODULE_DEVICE_TABLE(platform, fsi_id_table);
cc780d38 1755
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1756static struct platform_driver fsi_driver = {
1757 .driver = {
f0fba2ad 1758 .name = "fsi-pcm-audio",
785d1c45 1759 .pm = &fsi_pm_ops,
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1760 },
1761 .probe = fsi_probe,
1762 .remove = fsi_remove,
cc780d38 1763 .id_table = fsi_id_table,
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1764};
1765
cb5e8738 1766module_platform_driver(fsi_driver);
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1767
1768MODULE_LICENSE("GPL");
1769MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1770MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
b3c27b51 1771MODULE_ALIAS("platform:fsi-pcm-audio");
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