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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
7da9ced6 | 16 | #include <linux/dma-mapping.h> |
785d1c45 | 17 | #include <linux/pm_runtime.h> |
a4d7d550 | 18 | #include <linux/io.h> |
9e7b6d60 KM |
19 | #include <linux/of.h> |
20 | #include <linux/of_device.h> | |
7da9ced6 KM |
21 | #include <linux/scatterlist.h> |
22 | #include <linux/sh_dma.h> | |
5a0e3ad6 | 23 | #include <linux/slab.h> |
da155d5b | 24 | #include <linux/module.h> |
57451e43 | 25 | #include <linux/workqueue.h> |
a4d7d550 | 26 | #include <sound/soc.h> |
ab6f6d85 | 27 | #include <sound/pcm_params.h> |
a4d7d550 | 28 | #include <sound/sh_fsi.h> |
a4d7d550 | 29 | |
e8c8b631 KM |
30 | /* PortA/PortB register */ |
31 | #define REG_DO_FMT 0x0000 | |
32 | #define REG_DOFF_CTL 0x0004 | |
33 | #define REG_DOFF_ST 0x0008 | |
34 | #define REG_DI_FMT 0x000C | |
35 | #define REG_DIFF_CTL 0x0010 | |
36 | #define REG_DIFF_ST 0x0014 | |
37 | #define REG_CKG1 0x0018 | |
38 | #define REG_CKG2 0x001C | |
39 | #define REG_DIDT 0x0020 | |
40 | #define REG_DODT 0x0024 | |
41 | #define REG_MUTE_ST 0x0028 | |
65ff03f4 | 42 | #define REG_OUT_DMAC 0x002C |
e8c8b631 | 43 | #define REG_OUT_SEL 0x0030 |
65ff03f4 | 44 | #define REG_IN_DMAC 0x0038 |
cc780d38 | 45 | |
43fa95ca KM |
46 | /* master register */ |
47 | #define MST_CLK_RST 0x0210 | |
48 | #define MST_SOFT_RST 0x0214 | |
49 | #define MST_FIFO_SZ 0x0218 | |
50 | ||
51 | /* core register (depend on FSI version) */ | |
3bc28070 KM |
52 | #define A_MST_CTLR 0x0180 |
53 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
54 | #define CPU_INT_ST 0x01F4 |
55 | #define CPU_IEMSK 0x01F8 | |
56 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
57 | #define INT_ST 0x0200 |
58 | #define IEMSK 0x0204 | |
59 | #define IMSK 0x0208 | |
a4d7d550 KM |
60 | |
61 | /* DO_FMT */ | |
62 | /* DI_FMT */ | |
7da9ced6 | 63 | #define CR_BWS_MASK (0x3 << 20) /* FSI2 */ |
f7d711e3 KM |
64 | #define CR_BWS_24 (0x0 << 20) /* FSI2 */ |
65 | #define CR_BWS_16 (0x1 << 20) /* FSI2 */ | |
66 | #define CR_BWS_20 (0x2 << 20) /* FSI2 */ | |
67 | ||
68 | #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ | |
69 | #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ | |
70 | #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ | |
71 | ||
a7ffb52b KM |
72 | #define CR_MONO (0x0 << 4) |
73 | #define CR_MONO_D (0x1 << 4) | |
74 | #define CR_PCM (0x2 << 4) | |
75 | #define CR_I2S (0x3 << 4) | |
76 | #define CR_TDM (0x4 << 4) | |
77 | #define CR_TDM_D (0x5 << 4) | |
a4d7d550 | 78 | |
7da9ced6 KM |
79 | /* OUT_DMAC */ |
80 | /* IN_DMAC */ | |
81 | #define VDMD_MASK (0x3 << 4) | |
82 | #define VDMD_FRONT (0x0 << 4) /* Package in front */ | |
83 | #define VDMD_BACK (0x1 << 4) /* Package in back */ | |
84 | #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */ | |
85 | ||
86 | #define DMA_ON (0x1 << 0) | |
87 | ||
a4d7d550 KM |
88 | /* DOFF_CTL */ |
89 | /* DIFF_CTL */ | |
90 | #define IRQ_HALF 0x00100000 | |
91 | #define FIFO_CLR 0x00000001 | |
92 | ||
93 | /* DOFF_ST */ | |
94 | #define ERR_OVER 0x00000010 | |
95 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 96 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 97 | |
ccad7b44 KM |
98 | /* CKG1 */ |
99 | #define ACKMD_MASK 0x00007000 | |
100 | #define BPFMD_MASK 0x00000700 | |
4d805f7b KM |
101 | #define DIMD (1 << 4) |
102 | #define DOMD (1 << 0) | |
ccad7b44 | 103 | |
3bc28070 KM |
104 | /* A/B MST_CTLR */ |
105 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
106 | #define SE (1 << 0) /* Fix the master clock */ | |
107 | ||
a4d7d550 | 108 | /* CLK_RST */ |
1f5e2a31 KM |
109 | #define CRB (1 << 4) |
110 | #define CRA (1 << 0) | |
a4d7d550 | 111 | |
cf6edd00 KM |
112 | /* IO SHIFT / MACRO */ |
113 | #define BI_SHIFT 12 | |
114 | #define BO_SHIFT 8 | |
115 | #define AI_SHIFT 4 | |
116 | #define AO_SHIFT 0 | |
117 | #define AB_IO(param, shift) (param << shift) | |
a4d7d550 | 118 | |
feb58cff KM |
119 | /* SOFT_RST */ |
120 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
121 | #define PASR (1 << 8) /* Port A Software Reset */ | |
122 | #define IR (1 << 4) /* Interrupt Reset */ | |
123 | #define FSISR (1 << 0) /* Software Reset */ | |
124 | ||
f7d711e3 KM |
125 | /* OUT_SEL (FSI2) */ |
126 | #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ | |
127 | /* 1: Biphase and serial */ | |
128 | ||
4a942b45 | 129 | /* FIFO_SZ */ |
cf6edd00 | 130 | #define FIFO_SZ_MASK 0x7 |
4a942b45 | 131 | |
a4d7d550 KM |
132 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
133 | ||
134 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
135 | ||
766812e6 KM |
136 | /* |
137 | * bus options | |
138 | * | |
139 | * 0x000000BA | |
140 | * | |
141 | * A : sample widtht 16bit setting | |
142 | * B : sample widtht 24bit setting | |
143 | */ | |
144 | ||
145 | #define SHIFT_16DATA 0 | |
146 | #define SHIFT_24DATA 4 | |
147 | ||
148 | #define PACKAGE_24BITBUS_BACK 0 | |
149 | #define PACKAGE_24BITBUS_FRONT 1 | |
150 | #define PACKAGE_16BITBUS_STREAM 2 | |
151 | ||
152 | #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA) | |
153 | #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF) | |
154 | ||
5bfb9ad0 KM |
155 | /* |
156 | * FSI driver use below type name for variable | |
157 | * | |
5bfb9ad0 | 158 | * xxx_num : number of data |
2e651baf KM |
159 | * xxx_pos : position of data |
160 | * xxx_capa : capacity of data | |
161 | */ | |
162 | ||
163 | /* | |
164 | * period/frame/sample image | |
165 | * | |
166 | * ex) PCM (2ch) | |
167 | * | |
168 | * period pos period pos | |
169 | * [n] [n + 1] | |
170 | * |<-------------------- period--------------------->| | |
171 | * ==|============================================ ... =|== | |
172 | * | | | |
173 | * ||<----- frame ----->|<------ frame ----->| ... | | |
174 | * |+--------------------+--------------------+- ... | | |
175 | * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | | |
176 | * |+--------------------+--------------------+- ... | | |
177 | * ==|============================================ ... =|== | |
178 | */ | |
179 | ||
180 | /* | |
181 | * FSI FIFO image | |
182 | * | |
183 | * | | | |
184 | * | | | |
185 | * | [ sample ] | | |
186 | * | [ sample ] | | |
187 | * | [ sample ] | | |
188 | * | [ sample ] | | |
189 | * --> go to codecs | |
5bfb9ad0 KM |
190 | */ |
191 | ||
ab6f6d85 KM |
192 | /* |
193 | * FSI clock | |
194 | * | |
195 | * FSIxCLK [CPG] (ick) -------> | | |
196 | * |-> FSI_DIV (div)-> FSI2 | |
197 | * FSIxCK [external] (xck) ---> | | |
198 | */ | |
199 | ||
c8fe2574 KM |
200 | /* |
201 | * struct | |
202 | */ | |
a4d7d550 | 203 | |
5e97313a | 204 | struct fsi_stream_handler; |
93193c2b | 205 | struct fsi_stream { |
a4d7d550 | 206 | |
5e97313a KM |
207 | /* |
208 | * these are initialized by fsi_stream_init() | |
209 | */ | |
210 | struct snd_pcm_substream *substream; | |
2e651baf KM |
211 | int fifo_sample_capa; /* sample capacity of FSI FIFO */ |
212 | int buff_sample_capa; /* sample capacity of ALSA buffer */ | |
213 | int buff_sample_pos; /* sample position of ALSA buffer */ | |
214 | int period_samples; /* sample number / 1 period */ | |
215 | int period_pos; /* current period position */ | |
c1e6f10e | 216 | int sample_width; /* sample width */ |
1ec9bc35 KM |
217 | int uerr_num; |
218 | int oerr_num; | |
5e97313a | 219 | |
766812e6 KM |
220 | /* |
221 | * bus options | |
222 | */ | |
223 | u32 bus_option; | |
224 | ||
5e97313a KM |
225 | /* |
226 | * thse are initialized by fsi_handler_init() | |
227 | */ | |
228 | struct fsi_stream_handler *handler; | |
229 | struct fsi_priv *priv; | |
7da9ced6 KM |
230 | |
231 | /* | |
232 | * these are for DMAEngine | |
233 | */ | |
234 | struct dma_chan *chan; | |
235 | struct sh_dmae_slave slave; /* see fsi_handler_init() */ | |
57451e43 | 236 | struct work_struct work; |
7da9ced6 | 237 | dma_addr_t dma; |
93193c2b KM |
238 | }; |
239 | ||
ab6f6d85 KM |
240 | struct fsi_clk { |
241 | /* see [FSI clock] */ | |
242 | struct clk *own; | |
243 | struct clk *xck; | |
244 | struct clk *ick; | |
245 | struct clk *div; | |
246 | int (*set_rate)(struct device *dev, | |
6cbdbffb | 247 | struct fsi_priv *fsi); |
ab6f6d85 KM |
248 | |
249 | unsigned long rate; | |
250 | unsigned int count; | |
251 | }; | |
252 | ||
93193c2b KM |
253 | struct fsi_priv { |
254 | void __iomem *base; | |
255 | struct fsi_master *master; | |
256 | ||
257 | struct fsi_stream playback; | |
258 | struct fsi_stream capture; | |
3bc28070 | 259 | |
ab6f6d85 KM |
260 | struct fsi_clk clock; |
261 | ||
9c59dd34 | 262 | u32 fmt; |
9478e0b6 | 263 | |
6a9ebad8 KM |
264 | int chan_num:16; |
265 | int clk_master:1; | |
ab6340c4 | 266 | int clk_cpg:1; |
9478e0b6 | 267 | int spdif:1; |
2522acd2 | 268 | int enable_stream:1; |
3449f5fa KM |
269 | int bit_clk_inv:1; |
270 | int lr_clk_inv:1; | |
a4d7d550 KM |
271 | }; |
272 | ||
5e97313a | 273 | struct fsi_stream_handler { |
83344027 KM |
274 | int (*init)(struct fsi_priv *fsi, struct fsi_stream *io); |
275 | int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io); | |
b1226dc5 | 276 | int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev); |
5e97313a KM |
277 | int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io); |
278 | int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io); | |
180346ed KM |
279 | void (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io, |
280 | int enable); | |
5e97313a KM |
281 | }; |
282 | #define fsi_stream_handler_call(io, func, args...) \ | |
283 | (!(io) ? -ENODEV : \ | |
284 | !((io)->handler->func) ? 0 : \ | |
285 | (io)->handler->func(args)) | |
286 | ||
73b92c1f KM |
287 | struct fsi_core { |
288 | int ver; | |
289 | ||
cc780d38 KM |
290 | u32 int_st; |
291 | u32 iemsk; | |
292 | u32 imsk; | |
2b0e7302 KM |
293 | u32 a_mclk; |
294 | u32 b_mclk; | |
cc780d38 KM |
295 | }; |
296 | ||
a4d7d550 KM |
297 | struct fsi_master { |
298 | void __iomem *base; | |
299 | int irq; | |
a4d7d550 KM |
300 | struct fsi_priv fsia; |
301 | struct fsi_priv fsib; | |
9e7b6d60 | 302 | const struct fsi_core *core; |
8fc176d5 | 303 | spinlock_t lock; |
a4d7d550 KM |
304 | }; |
305 | ||
7b1b3331 KM |
306 | static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io); |
307 | ||
c8fe2574 KM |
308 | /* |
309 | * basic read write function | |
310 | */ | |
a4d7d550 | 311 | |
ca7aceef | 312 | static void __fsi_reg_write(u32 __iomem *reg, u32 data) |
a4d7d550 KM |
313 | { |
314 | /* valid data area is 24bit */ | |
315 | data &= 0x00ffffff; | |
316 | ||
0f69d978 | 317 | __raw_writel(data, reg); |
a4d7d550 KM |
318 | } |
319 | ||
ca7aceef | 320 | static u32 __fsi_reg_read(u32 __iomem *reg) |
a4d7d550 | 321 | { |
0f69d978 | 322 | return __raw_readl(reg); |
a4d7d550 KM |
323 | } |
324 | ||
ca7aceef | 325 | static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) |
a4d7d550 KM |
326 | { |
327 | u32 val = __fsi_reg_read(reg); | |
328 | ||
329 | val &= ~mask; | |
330 | val |= data & mask; | |
331 | ||
0f69d978 | 332 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
333 | } |
334 | ||
e8c8b631 | 335 | #define fsi_reg_write(p, r, d)\ |
8918b843 | 336 | __fsi_reg_write((p->base + REG_##r), d) |
a4d7d550 | 337 | |
e8c8b631 | 338 | #define fsi_reg_read(p, r)\ |
8918b843 | 339 | __fsi_reg_read((p->base + REG_##r)) |
a4d7d550 | 340 | |
e8c8b631 | 341 | #define fsi_reg_mask_set(p, r, m, d)\ |
8918b843 | 342 | __fsi_reg_mask_set((p->base + REG_##r), m, d) |
a4d7d550 | 343 | |
43fa95ca KM |
344 | #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) |
345 | #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) | |
346 | static u32 _fsi_master_read(struct fsi_master *master, u32 reg) | |
a4d7d550 | 347 | { |
8fc176d5 KM |
348 | u32 ret; |
349 | unsigned long flags; | |
350 | ||
8fc176d5 | 351 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 352 | ret = __fsi_reg_read(master->base + reg); |
8fc176d5 KM |
353 | spin_unlock_irqrestore(&master->lock, flags); |
354 | ||
355 | return ret; | |
a4d7d550 KM |
356 | } |
357 | ||
43fa95ca KM |
358 | #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) |
359 | #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) | |
360 | static void _fsi_master_mask_set(struct fsi_master *master, | |
71f6e064 | 361 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 362 | { |
8fc176d5 KM |
363 | unsigned long flags; |
364 | ||
8fc176d5 | 365 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 366 | __fsi_reg_mask_set(master->base + reg, mask, data); |
8fc176d5 | 367 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
368 | } |
369 | ||
c8fe2574 KM |
370 | /* |
371 | * basic function | |
372 | */ | |
284c6f65 KM |
373 | static int fsi_version(struct fsi_master *master) |
374 | { | |
375 | return master->core->ver; | |
376 | } | |
a4d7d550 | 377 | |
71f6e064 | 378 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 379 | { |
71f6e064 | 380 | return fsi->master; |
a4d7d550 KM |
381 | } |
382 | ||
6a9ebad8 KM |
383 | static int fsi_is_clk_master(struct fsi_priv *fsi) |
384 | { | |
385 | return fsi->clk_master; | |
386 | } | |
387 | ||
a4d7d550 KM |
388 | static int fsi_is_port_a(struct fsi_priv *fsi) |
389 | { | |
71f6e064 KM |
390 | return fsi->master->base == fsi->base; |
391 | } | |
a4d7d550 | 392 | |
9478e0b6 KM |
393 | static int fsi_is_spdif(struct fsi_priv *fsi) |
394 | { | |
395 | return fsi->spdif; | |
396 | } | |
397 | ||
2522acd2 KM |
398 | static int fsi_is_enable_stream(struct fsi_priv *fsi) |
399 | { | |
400 | return fsi->enable_stream; | |
401 | } | |
402 | ||
a449e467 KM |
403 | static int fsi_is_play(struct snd_pcm_substream *substream) |
404 | { | |
405 | return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
406 | } | |
407 | ||
142e8174 | 408 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
409 | { |
410 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 411 | |
f0fba2ad | 412 | return rtd->cpu_dai; |
142e8174 KM |
413 | } |
414 | ||
0d032c19 | 415 | static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) |
142e8174 | 416 | { |
f0fba2ad | 417 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 418 | |
f0fba2ad LG |
419 | if (dai->id == 0) |
420 | return &master->fsia; | |
421 | else | |
422 | return &master->fsib; | |
a4d7d550 KM |
423 | } |
424 | ||
0d032c19 KM |
425 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) |
426 | { | |
427 | return fsi_get_priv_frm_dai(fsi_get_dai(substream)); | |
428 | } | |
429 | ||
938e2a8d | 430 | static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 431 | { |
938e2a8d | 432 | int is_play = fsi_stream_is_play(fsi, io); |
a4d7d550 | 433 | int is_porta = fsi_is_port_a(fsi); |
cf6edd00 | 434 | u32 shift; |
a4d7d550 KM |
435 | |
436 | if (is_porta) | |
cf6edd00 | 437 | shift = is_play ? AO_SHIFT : AI_SHIFT; |
a4d7d550 | 438 | else |
cf6edd00 | 439 | shift = is_play ? BO_SHIFT : BI_SHIFT; |
a4d7d550 | 440 | |
cf6edd00 | 441 | return shift; |
a4d7d550 KM |
442 | } |
443 | ||
2e651baf KM |
444 | static int fsi_frame2sample(struct fsi_priv *fsi, int frames) |
445 | { | |
446 | return frames * fsi->chan_num; | |
447 | } | |
448 | ||
449 | static int fsi_sample2frame(struct fsi_priv *fsi, int samples) | |
450 | { | |
451 | return samples / fsi->chan_num; | |
452 | } | |
453 | ||
7b1b3331 KM |
454 | static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, |
455 | struct fsi_stream *io) | |
4e62d84d | 456 | { |
7b1b3331 | 457 | int is_play = fsi_stream_is_play(fsi, io); |
4e62d84d KM |
458 | u32 status; |
459 | int frames; | |
460 | ||
461 | status = is_play ? | |
462 | fsi_reg_read(fsi, DOFF_ST) : | |
463 | fsi_reg_read(fsi, DIFF_ST); | |
464 | ||
465 | frames = 0x1ff & (status >> 8); | |
466 | ||
467 | return fsi_frame2sample(fsi, frames); | |
468 | } | |
469 | ||
470 | static void fsi_count_fifo_err(struct fsi_priv *fsi) | |
471 | { | |
472 | u32 ostatus = fsi_reg_read(fsi, DOFF_ST); | |
473 | u32 istatus = fsi_reg_read(fsi, DIFF_ST); | |
474 | ||
475 | if (ostatus & ERR_OVER) | |
476 | fsi->playback.oerr_num++; | |
477 | ||
478 | if (ostatus & ERR_UNDER) | |
479 | fsi->playback.uerr_num++; | |
480 | ||
481 | if (istatus & ERR_OVER) | |
482 | fsi->capture.oerr_num++; | |
483 | ||
484 | if (istatus & ERR_UNDER) | |
485 | fsi->capture.uerr_num++; | |
486 | ||
487 | fsi_reg_write(fsi, DOFF_ST, 0); | |
488 | fsi_reg_write(fsi, DIFF_ST, 0); | |
489 | } | |
490 | ||
491 | /* | |
492 | * fsi_stream_xx() function | |
493 | */ | |
a449e467 KM |
494 | static inline int fsi_stream_is_play(struct fsi_priv *fsi, |
495 | struct fsi_stream *io) | |
4e62d84d | 496 | { |
a449e467 | 497 | return &fsi->playback == io; |
4e62d84d KM |
498 | } |
499 | ||
500 | static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi, | |
938e2a8d | 501 | struct snd_pcm_substream *substream) |
4e62d84d | 502 | { |
938e2a8d | 503 | return fsi_is_play(substream) ? &fsi->playback : &fsi->capture; |
4e62d84d KM |
504 | } |
505 | ||
cda828ca | 506 | static int fsi_stream_is_working(struct fsi_priv *fsi, |
938e2a8d | 507 | struct fsi_stream *io) |
cda828ca | 508 | { |
cda828ca KM |
509 | struct fsi_master *master = fsi_get_master(fsi); |
510 | unsigned long flags; | |
511 | int ret; | |
512 | ||
513 | spin_lock_irqsave(&master->lock, flags); | |
97df8187 | 514 | ret = !!(io->substream && io->substream->runtime); |
cda828ca KM |
515 | spin_unlock_irqrestore(&master->lock, flags); |
516 | ||
517 | return ret; | |
518 | } | |
519 | ||
5e97313a KM |
520 | static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io) |
521 | { | |
522 | return io->priv; | |
523 | } | |
524 | ||
8c415295 | 525 | static void fsi_stream_init(struct fsi_priv *fsi, |
938e2a8d | 526 | struct fsi_stream *io, |
0ffe296a | 527 | struct snd_pcm_substream *substream) |
a4d7d550 | 528 | { |
0ffe296a | 529 | struct snd_pcm_runtime *runtime = substream->runtime; |
2da65892 KM |
530 | struct fsi_master *master = fsi_get_master(fsi); |
531 | unsigned long flags; | |
93193c2b | 532 | |
2da65892 | 533 | spin_lock_irqsave(&master->lock, flags); |
93193c2b | 534 | io->substream = substream; |
2e651baf KM |
535 | io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); |
536 | io->buff_sample_pos = 0; | |
537 | io->period_samples = fsi_frame2sample(fsi, runtime->period_size); | |
538 | io->period_pos = 0; | |
c1e6f10e | 539 | io->sample_width = samples_to_bytes(runtime, 1); |
766812e6 | 540 | io->bus_option = 0; |
1ec9bc35 KM |
541 | io->oerr_num = -1; /* ignore 1st err */ |
542 | io->uerr_num = -1; /* ignore 1st err */ | |
83344027 | 543 | fsi_stream_handler_call(io, init, fsi, io); |
2da65892 | 544 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
545 | } |
546 | ||
938e2a8d | 547 | static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 548 | { |
1ec9bc35 | 549 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); |
2da65892 KM |
550 | struct fsi_master *master = fsi_get_master(fsi); |
551 | unsigned long flags; | |
1ec9bc35 | 552 | |
2da65892 | 553 | spin_lock_irqsave(&master->lock, flags); |
1ec9bc35 KM |
554 | |
555 | if (io->oerr_num > 0) | |
556 | dev_err(dai->dev, "over_run = %d\n", io->oerr_num); | |
557 | ||
558 | if (io->uerr_num > 0) | |
559 | dev_err(dai->dev, "under_run = %d\n", io->uerr_num); | |
93193c2b | 560 | |
83344027 | 561 | fsi_stream_handler_call(io, quit, fsi, io); |
93193c2b | 562 | io->substream = NULL; |
2e651baf KM |
563 | io->buff_sample_capa = 0; |
564 | io->buff_sample_pos = 0; | |
565 | io->period_samples = 0; | |
566 | io->period_pos = 0; | |
c1e6f10e | 567 | io->sample_width = 0; |
766812e6 | 568 | io->bus_option = 0; |
1ec9bc35 KM |
569 | io->oerr_num = 0; |
570 | io->uerr_num = 0; | |
2da65892 | 571 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
572 | } |
573 | ||
5e97313a KM |
574 | static int fsi_stream_transfer(struct fsi_stream *io) |
575 | { | |
576 | struct fsi_priv *fsi = fsi_stream_to_priv(io); | |
577 | if (!fsi) | |
578 | return -EIO; | |
579 | ||
580 | return fsi_stream_handler_call(io, transfer, fsi, io); | |
581 | } | |
582 | ||
180346ed KM |
583 | #define fsi_stream_start(fsi, io)\ |
584 | fsi_stream_handler_call(io, start_stop, fsi, io, 1) | |
585 | ||
586 | #define fsi_stream_stop(fsi, io)\ | |
587 | fsi_stream_handler_call(io, start_stop, fsi, io, 0) | |
588 | ||
b1226dc5 | 589 | static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev) |
5e97313a KM |
590 | { |
591 | struct fsi_stream *io; | |
592 | int ret1, ret2; | |
593 | ||
594 | io = &fsi->playback; | |
b1226dc5 | 595 | ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev); |
5e97313a KM |
596 | |
597 | io = &fsi->capture; | |
b1226dc5 | 598 | ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev); |
5e97313a KM |
599 | |
600 | if (ret1 < 0) | |
601 | return ret1; | |
602 | if (ret2 < 0) | |
603 | return ret2; | |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
608 | static int fsi_stream_remove(struct fsi_priv *fsi) | |
609 | { | |
610 | struct fsi_stream *io; | |
611 | int ret1, ret2; | |
612 | ||
613 | io = &fsi->playback; | |
614 | ret1 = fsi_stream_handler_call(io, remove, fsi, io); | |
615 | ||
616 | io = &fsi->capture; | |
617 | ret2 = fsi_stream_handler_call(io, remove, fsi, io); | |
618 | ||
619 | if (ret1 < 0) | |
620 | return ret1; | |
621 | if (ret2 < 0) | |
622 | return ret2; | |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
766812e6 KM |
627 | /* |
628 | * format/bus/dma setting | |
629 | */ | |
630 | static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io, | |
631 | u32 bus, struct device *dev) | |
632 | { | |
633 | struct fsi_master *master = fsi_get_master(fsi); | |
634 | int is_play = fsi_stream_is_play(fsi, io); | |
635 | u32 fmt = fsi->fmt; | |
636 | ||
637 | if (fsi_version(master) >= 2) { | |
638 | u32 dma = 0; | |
639 | ||
640 | /* | |
641 | * FSI2 needs DMA/Bus setting | |
642 | */ | |
643 | switch (bus) { | |
644 | case PACKAGE_24BITBUS_FRONT: | |
645 | fmt |= CR_BWS_24; | |
646 | dma |= VDMD_FRONT; | |
647 | dev_dbg(dev, "24bit bus / package in front\n"); | |
648 | break; | |
649 | case PACKAGE_16BITBUS_STREAM: | |
650 | fmt |= CR_BWS_16; | |
651 | dma |= VDMD_STREAM; | |
652 | dev_dbg(dev, "16bit bus / stream mode\n"); | |
653 | break; | |
654 | case PACKAGE_24BITBUS_BACK: | |
655 | default: | |
656 | fmt |= CR_BWS_24; | |
657 | dma |= VDMD_BACK; | |
658 | dev_dbg(dev, "24bit bus / package in back\n"); | |
659 | break; | |
660 | } | |
661 | ||
662 | if (is_play) | |
663 | fsi_reg_write(fsi, OUT_DMAC, dma); | |
664 | else | |
665 | fsi_reg_write(fsi, IN_DMAC, dma); | |
666 | } | |
667 | ||
668 | if (is_play) | |
669 | fsi_reg_write(fsi, DO_FMT, fmt); | |
670 | else | |
671 | fsi_reg_write(fsi, DI_FMT, fmt); | |
672 | } | |
673 | ||
c8fe2574 KM |
674 | /* |
675 | * irq function | |
676 | */ | |
a4d7d550 | 677 | |
938e2a8d | 678 | static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 679 | { |
938e2a8d | 680 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); |
71f6e064 | 681 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 682 | |
43fa95ca KM |
683 | fsi_core_mask_set(master, imsk, data, data); |
684 | fsi_core_mask_set(master, iemsk, data, data); | |
a4d7d550 KM |
685 | } |
686 | ||
938e2a8d | 687 | static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 688 | { |
938e2a8d | 689 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); |
71f6e064 | 690 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 691 | |
43fa95ca KM |
692 | fsi_core_mask_set(master, imsk, data, 0); |
693 | fsi_core_mask_set(master, iemsk, data, 0); | |
a4d7d550 KM |
694 | } |
695 | ||
10ea76cc KM |
696 | static u32 fsi_irq_get_status(struct fsi_master *master) |
697 | { | |
43fa95ca | 698 | return fsi_core_read(master, int_st); |
10ea76cc KM |
699 | } |
700 | ||
10ea76cc KM |
701 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
702 | { | |
703 | u32 data = 0; | |
704 | struct fsi_master *master = fsi_get_master(fsi); | |
705 | ||
938e2a8d KM |
706 | data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback)); |
707 | data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture)); | |
10ea76cc KM |
708 | |
709 | /* clear interrupt factor */ | |
43fa95ca | 710 | fsi_core_mask_set(master, int_st, data, 0); |
10ea76cc KM |
711 | } |
712 | ||
c8fe2574 KM |
713 | /* |
714 | * SPDIF master clock function | |
715 | * | |
716 | * These functions are used later FSI2 | |
717 | */ | |
3bc28070 KM |
718 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
719 | { | |
720 | struct fsi_master *master = fsi_get_master(fsi); | |
2b0e7302 | 721 | u32 mask, val; |
3bc28070 | 722 | |
2b0e7302 KM |
723 | mask = BP | SE; |
724 | val = enable ? mask : 0; | |
725 | ||
726 | fsi_is_port_a(fsi) ? | |
43fa95ca KM |
727 | fsi_core_mask_set(master, a_mclk, mask, val) : |
728 | fsi_core_mask_set(master, b_mclk, mask, val); | |
3bc28070 KM |
729 | } |
730 | ||
c8fe2574 | 731 | /* |
1f5e2a31 | 732 | * clock function |
c8fe2574 | 733 | */ |
ab6f6d85 KM |
734 | static int fsi_clk_init(struct device *dev, |
735 | struct fsi_priv *fsi, | |
736 | int xck, | |
737 | int ick, | |
738 | int div, | |
739 | int (*set_rate)(struct device *dev, | |
6cbdbffb | 740 | struct fsi_priv *fsi)) |
ab6f6d85 KM |
741 | { |
742 | struct fsi_clk *clock = &fsi->clock; | |
743 | int is_porta = fsi_is_port_a(fsi); | |
744 | ||
745 | clock->xck = NULL; | |
746 | clock->ick = NULL; | |
747 | clock->div = NULL; | |
748 | clock->rate = 0; | |
749 | clock->count = 0; | |
750 | clock->set_rate = set_rate; | |
751 | ||
752 | clock->own = devm_clk_get(dev, NULL); | |
753 | if (IS_ERR(clock->own)) | |
754 | return -EINVAL; | |
755 | ||
756 | /* external clock */ | |
757 | if (xck) { | |
758 | clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb"); | |
759 | if (IS_ERR(clock->xck)) { | |
760 | dev_err(dev, "can't get xck clock\n"); | |
761 | return -EINVAL; | |
762 | } | |
763 | if (clock->xck == clock->own) { | |
764 | dev_err(dev, "cpu doesn't support xck clock\n"); | |
765 | return -EINVAL; | |
766 | } | |
767 | } | |
768 | ||
769 | /* FSIACLK/FSIBCLK */ | |
770 | if (ick) { | |
771 | clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb"); | |
772 | if (IS_ERR(clock->ick)) { | |
773 | dev_err(dev, "can't get ick clock\n"); | |
774 | return -EINVAL; | |
775 | } | |
776 | if (clock->ick == clock->own) { | |
777 | dev_err(dev, "cpu doesn't support ick clock\n"); | |
778 | return -EINVAL; | |
779 | } | |
780 | } | |
781 | ||
782 | /* FSI-DIV */ | |
783 | if (div) { | |
784 | clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb"); | |
785 | if (IS_ERR(clock->div)) { | |
786 | dev_err(dev, "can't get div clock\n"); | |
787 | return -EINVAL; | |
788 | } | |
789 | if (clock->div == clock->own) { | |
790 | dev_err(dev, "cpu doens't support div clock\n"); | |
791 | return -EINVAL; | |
792 | } | |
793 | } | |
794 | ||
795 | return 0; | |
796 | } | |
797 | ||
798 | #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0) | |
799 | static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate) | |
800 | { | |
801 | fsi->clock.rate = rate; | |
802 | } | |
803 | ||
804 | static int fsi_clk_is_valid(struct fsi_priv *fsi) | |
805 | { | |
806 | return fsi->clock.set_rate && | |
807 | fsi->clock.rate; | |
808 | } | |
809 | ||
810 | static int fsi_clk_enable(struct device *dev, | |
6cbdbffb | 811 | struct fsi_priv *fsi) |
ab6f6d85 KM |
812 | { |
813 | struct fsi_clk *clock = &fsi->clock; | |
814 | int ret = -EINVAL; | |
815 | ||
816 | if (!fsi_clk_is_valid(fsi)) | |
817 | return ret; | |
818 | ||
819 | if (0 == clock->count) { | |
6cbdbffb | 820 | ret = clock->set_rate(dev, fsi); |
ab6f6d85 KM |
821 | if (ret < 0) { |
822 | fsi_clk_invalid(fsi); | |
823 | return ret; | |
824 | } | |
825 | ||
826 | if (clock->xck) | |
827 | clk_enable(clock->xck); | |
828 | if (clock->ick) | |
829 | clk_enable(clock->ick); | |
830 | if (clock->div) | |
831 | clk_enable(clock->div); | |
832 | ||
833 | clock->count++; | |
834 | } | |
835 | ||
836 | return ret; | |
837 | } | |
838 | ||
839 | static int fsi_clk_disable(struct device *dev, | |
840 | struct fsi_priv *fsi) | |
841 | { | |
842 | struct fsi_clk *clock = &fsi->clock; | |
843 | ||
844 | if (!fsi_clk_is_valid(fsi)) | |
845 | return -EINVAL; | |
846 | ||
847 | if (1 == clock->count--) { | |
848 | if (clock->xck) | |
849 | clk_disable(clock->xck); | |
850 | if (clock->ick) | |
851 | clk_disable(clock->ick); | |
852 | if (clock->div) | |
853 | clk_disable(clock->div); | |
854 | } | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
859 | static int fsi_clk_set_ackbpf(struct device *dev, | |
860 | struct fsi_priv *fsi, | |
861 | int ackmd, int bpfmd) | |
862 | { | |
863 | u32 data = 0; | |
864 | ||
865 | /* check ackmd/bpfmd relationship */ | |
866 | if (bpfmd > ackmd) { | |
867 | dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd); | |
868 | return -EINVAL; | |
869 | } | |
870 | ||
871 | /* ACKMD */ | |
872 | switch (ackmd) { | |
873 | case 512: | |
874 | data |= (0x0 << 12); | |
875 | break; | |
876 | case 256: | |
877 | data |= (0x1 << 12); | |
878 | break; | |
879 | case 128: | |
880 | data |= (0x2 << 12); | |
881 | break; | |
882 | case 64: | |
883 | data |= (0x3 << 12); | |
884 | break; | |
885 | case 32: | |
886 | data |= (0x4 << 12); | |
887 | break; | |
888 | default: | |
889 | dev_err(dev, "unsupported ackmd (%d)\n", ackmd); | |
890 | return -EINVAL; | |
891 | } | |
892 | ||
893 | /* BPFMD */ | |
894 | switch (bpfmd) { | |
895 | case 32: | |
896 | data |= (0x0 << 8); | |
897 | break; | |
898 | case 64: | |
899 | data |= (0x1 << 8); | |
900 | break; | |
901 | case 128: | |
902 | data |= (0x2 << 8); | |
903 | break; | |
904 | case 256: | |
905 | data |= (0x3 << 8); | |
906 | break; | |
907 | case 512: | |
908 | data |= (0x4 << 8); | |
909 | break; | |
910 | case 16: | |
911 | data |= (0x7 << 8); | |
912 | break; | |
913 | default: | |
914 | dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd); | |
915 | return -EINVAL; | |
916 | } | |
917 | ||
918 | dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd); | |
919 | ||
920 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
921 | udelay(10); | |
922 | ||
923 | return 0; | |
924 | } | |
925 | ||
926 | static int fsi_clk_set_rate_external(struct device *dev, | |
6cbdbffb | 927 | struct fsi_priv *fsi) |
ab6f6d85 KM |
928 | { |
929 | struct clk *xck = fsi->clock.xck; | |
930 | struct clk *ick = fsi->clock.ick; | |
6cbdbffb | 931 | unsigned long rate = fsi->clock.rate; |
ab6f6d85 KM |
932 | unsigned long xrate; |
933 | int ackmd, bpfmd; | |
934 | int ret = 0; | |
935 | ||
936 | /* check clock rate */ | |
937 | xrate = clk_get_rate(xck); | |
938 | if (xrate % rate) { | |
939 | dev_err(dev, "unsupported clock rate\n"); | |
940 | return -EINVAL; | |
941 | } | |
942 | ||
943 | clk_set_parent(ick, xck); | |
944 | clk_set_rate(ick, xrate); | |
945 | ||
946 | bpfmd = fsi->chan_num * 32; | |
947 | ackmd = xrate / rate; | |
948 | ||
949 | dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate); | |
950 | ||
951 | ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); | |
952 | if (ret < 0) | |
953 | dev_err(dev, "%s failed", __func__); | |
954 | ||
955 | return ret; | |
956 | } | |
957 | ||
958 | static int fsi_clk_set_rate_cpg(struct device *dev, | |
6cbdbffb | 959 | struct fsi_priv *fsi) |
ab6f6d85 KM |
960 | { |
961 | struct clk *ick = fsi->clock.ick; | |
962 | struct clk *div = fsi->clock.div; | |
6cbdbffb | 963 | unsigned long rate = fsi->clock.rate; |
ab6f6d85 KM |
964 | unsigned long target = 0; /* 12288000 or 11289600 */ |
965 | unsigned long actual, cout; | |
966 | unsigned long diff, min; | |
967 | unsigned long best_cout, best_act; | |
968 | int adj; | |
969 | int ackmd, bpfmd; | |
970 | int ret = -EINVAL; | |
971 | ||
972 | if (!(12288000 % rate)) | |
973 | target = 12288000; | |
974 | if (!(11289600 % rate)) | |
975 | target = 11289600; | |
976 | if (!target) { | |
977 | dev_err(dev, "unsupported rate\n"); | |
978 | return ret; | |
979 | } | |
980 | ||
981 | bpfmd = fsi->chan_num * 32; | |
982 | ackmd = target / rate; | |
983 | ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); | |
984 | if (ret < 0) { | |
985 | dev_err(dev, "%s failed", __func__); | |
986 | return ret; | |
987 | } | |
988 | ||
989 | /* | |
990 | * The clock flow is | |
991 | * | |
992 | * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec] | |
993 | * | |
994 | * But, it needs to find best match of CPG and FSI_DIV | |
995 | * combination, since it is difficult to generate correct | |
996 | * frequency of audio clock from ick clock only. | |
997 | * Because ick is created from its parent clock. | |
998 | * | |
999 | * target = rate x [512/256/128/64]fs | |
1000 | * cout = round(target x adjustment) | |
1001 | * actual = cout / adjustment (by FSI-DIV) ~= target | |
1002 | * audio = actual | |
1003 | */ | |
1004 | min = ~0; | |
1005 | best_cout = 0; | |
1006 | best_act = 0; | |
1007 | for (adj = 1; adj < 0xffff; adj++) { | |
1008 | ||
1009 | cout = target * adj; | |
1010 | if (cout > 100000000) /* max clock = 100MHz */ | |
1011 | break; | |
1012 | ||
1013 | /* cout/actual audio clock */ | |
1014 | cout = clk_round_rate(ick, cout); | |
1015 | actual = cout / adj; | |
1016 | ||
1017 | /* find best frequency */ | |
1018 | diff = abs(actual - target); | |
1019 | if (diff < min) { | |
1020 | min = diff; | |
1021 | best_cout = cout; | |
1022 | best_act = actual; | |
1023 | } | |
1024 | } | |
1025 | ||
1026 | ret = clk_set_rate(ick, best_cout); | |
1027 | if (ret < 0) { | |
1028 | dev_err(dev, "ick clock failed\n"); | |
1029 | return -EIO; | |
1030 | } | |
1031 | ||
1032 | ret = clk_set_rate(div, clk_round_rate(div, best_act)); | |
1033 | if (ret < 0) { | |
1034 | dev_err(dev, "div clock failed\n"); | |
1035 | return -EIO; | |
1036 | } | |
1037 | ||
1038 | dev_dbg(dev, "ick/div = %ld/%ld\n", | |
1039 | clk_get_rate(ick), clk_get_rate(div)); | |
1040 | ||
1041 | return ret; | |
1042 | } | |
1043 | ||
1f5e2a31 | 1044 | /* |
1b0ca1a0 | 1045 | * pio data transfer handler |
1f5e2a31 | 1046 | */ |
1b0ca1a0 KM |
1047 | static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples) |
1048 | { | |
1b0ca1a0 KM |
1049 | int i; |
1050 | ||
2522acd2 | 1051 | if (fsi_is_enable_stream(fsi)) { |
766812e6 KM |
1052 | /* |
1053 | * stream mode | |
1054 | * see | |
1055 | * fsi_pio_push_init() | |
1056 | */ | |
1057 | u32 *buf = (u32 *)_buf; | |
1058 | ||
1059 | for (i = 0; i < samples / 2; i++) | |
1060 | fsi_reg_write(fsi, DODT, buf[i]); | |
1061 | } else { | |
1062 | /* normal mode */ | |
1063 | u16 *buf = (u16 *)_buf; | |
1064 | ||
1065 | for (i = 0; i < samples; i++) | |
1066 | fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8)); | |
1067 | } | |
1b0ca1a0 KM |
1068 | } |
1069 | ||
1070 | static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples) | |
1071 | { | |
1072 | u16 *buf = (u16 *)_buf; | |
1073 | int i; | |
1074 | ||
1075 | for (i = 0; i < samples; i++) | |
1076 | *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); | |
1077 | } | |
1078 | ||
1079 | static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples) | |
1080 | { | |
1081 | u32 *buf = (u32 *)_buf; | |
1082 | int i; | |
1083 | ||
1084 | for (i = 0; i < samples; i++) | |
1085 | fsi_reg_write(fsi, DODT, *(buf + i)); | |
1086 | } | |
1087 | ||
1088 | static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples) | |
1089 | { | |
1090 | u32 *buf = (u32 *)_buf; | |
1091 | int i; | |
1092 | ||
1093 | for (i = 0; i < samples; i++) | |
1094 | *(buf + i) = fsi_reg_read(fsi, DIDT); | |
1095 | } | |
1096 | ||
1097 | static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io) | |
1098 | { | |
1099 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
1100 | ||
1101 | return runtime->dma_area + | |
1102 | samples_to_bytes(runtime, io->buff_sample_pos); | |
1103 | } | |
1104 | ||
1105 | static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io, | |
95b0cf05 KM |
1106 | void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples), |
1107 | void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples), | |
1108 | int samples) | |
a4d7d550 KM |
1109 | { |
1110 | struct snd_pcm_runtime *runtime; | |
376cf38a | 1111 | struct snd_pcm_substream *substream; |
95b0cf05 | 1112 | u8 *buf; |
b9fde18c | 1113 | int over_period; |
a4d7d550 | 1114 | |
97df8187 | 1115 | if (!fsi_stream_is_working(fsi, io)) |
a4d7d550 KM |
1116 | return -EINVAL; |
1117 | ||
1c418d1f | 1118 | over_period = 0; |
93193c2b | 1119 | substream = io->substream; |
1c418d1f | 1120 | runtime = substream->runtime; |
a4d7d550 KM |
1121 | |
1122 | /* FSI FIFO has limit. | |
1123 | * So, this driver can not send periods data at a time | |
1124 | */ | |
2e651baf KM |
1125 | if (io->buff_sample_pos >= |
1126 | io->period_samples * (io->period_pos + 1)) { | |
a4d7d550 | 1127 | |
1c418d1f | 1128 | over_period = 1; |
2e651baf | 1129 | io->period_pos = (io->period_pos + 1) % runtime->periods; |
a4d7d550 | 1130 | |
2e651baf KM |
1131 | if (0 == io->period_pos) |
1132 | io->buff_sample_pos = 0; | |
a4d7d550 KM |
1133 | } |
1134 | ||
95b0cf05 KM |
1135 | buf = fsi_pio_get_area(fsi, io); |
1136 | ||
376cf38a KM |
1137 | switch (io->sample_width) { |
1138 | case 2: | |
95b0cf05 | 1139 | run16(fsi, buf, samples); |
376cf38a KM |
1140 | break; |
1141 | case 4: | |
95b0cf05 | 1142 | run32(fsi, buf, samples); |
376cf38a KM |
1143 | break; |
1144 | default: | |
1145 | return -EINVAL; | |
d8b33534 | 1146 | } |
a4d7d550 | 1147 | |
2e651baf KM |
1148 | /* update buff_sample_pos */ |
1149 | io->buff_sample_pos += samples; | |
a4d7d550 | 1150 | |
1c418d1f | 1151 | if (over_period) |
a4d7d550 KM |
1152 | snd_pcm_period_elapsed(substream); |
1153 | ||
47fc9a0a | 1154 | return 0; |
a4d7d550 KM |
1155 | } |
1156 | ||
5e97313a | 1157 | static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io) |
07102f3c | 1158 | { |
376cf38a KM |
1159 | int sample_residues; /* samples in FSI fifo */ |
1160 | int sample_space; /* ALSA free samples space */ | |
1161 | int samples; | |
376cf38a | 1162 | |
7b1b3331 | 1163 | sample_residues = fsi_get_current_fifo_samples(fsi, io); |
376cf38a KM |
1164 | sample_space = io->buff_sample_capa - io->buff_sample_pos; |
1165 | ||
1166 | samples = min(sample_residues, sample_space); | |
1167 | ||
1b0ca1a0 | 1168 | return fsi_pio_transfer(fsi, io, |
d78629e2 KM |
1169 | fsi_pio_pop16, |
1170 | fsi_pio_pop32, | |
376cf38a | 1171 | samples); |
d8b33534 | 1172 | } |
07102f3c | 1173 | |
5e97313a | 1174 | static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io) |
d8b33534 | 1175 | { |
376cf38a KM |
1176 | int sample_residues; /* ALSA residue samples */ |
1177 | int sample_space; /* FSI fifo free samples space */ | |
1178 | int samples; | |
376cf38a KM |
1179 | |
1180 | sample_residues = io->buff_sample_capa - io->buff_sample_pos; | |
1181 | sample_space = io->fifo_sample_capa - | |
7b1b3331 | 1182 | fsi_get_current_fifo_samples(fsi, io); |
376cf38a KM |
1183 | |
1184 | samples = min(sample_residues, sample_space); | |
1185 | ||
1b0ca1a0 | 1186 | return fsi_pio_transfer(fsi, io, |
d78629e2 KM |
1187 | fsi_pio_push16, |
1188 | fsi_pio_push32, | |
376cf38a | 1189 | samples); |
07102f3c KM |
1190 | } |
1191 | ||
180346ed KM |
1192 | static void fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, |
1193 | int enable) | |
1194 | { | |
1195 | struct fsi_master *master = fsi_get_master(fsi); | |
1196 | u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; | |
1197 | ||
1198 | if (enable) | |
1199 | fsi_irq_enable(fsi, io); | |
1200 | else | |
1201 | fsi_irq_disable(fsi, io); | |
1202 | ||
1203 | if (fsi_is_clk_master(fsi)) | |
1204 | fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); | |
1205 | } | |
1206 | ||
766812e6 KM |
1207 | static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io) |
1208 | { | |
766812e6 KM |
1209 | /* |
1210 | * we can use 16bit stream mode | |
1211 | * when "playback" and "16bit data" | |
1212 | * and platform allows "stream mode" | |
1213 | * see | |
1214 | * fsi_pio_push16() | |
1215 | */ | |
2522acd2 | 1216 | if (fsi_is_enable_stream(fsi)) |
766812e6 KM |
1217 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | |
1218 | BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); | |
1219 | else | |
1220 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | | |
1221 | BUSOP_SET(16, PACKAGE_24BITBUS_BACK); | |
1222 | return 0; | |
1223 | } | |
1224 | ||
1225 | static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io) | |
1226 | { | |
1227 | /* | |
1228 | * always 24bit bus, package back when "capture" | |
1229 | */ | |
1230 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | | |
1231 | BUSOP_SET(16, PACKAGE_24BITBUS_BACK); | |
1232 | return 0; | |
1233 | } | |
1234 | ||
5e97313a | 1235 | static struct fsi_stream_handler fsi_pio_push_handler = { |
766812e6 | 1236 | .init = fsi_pio_push_init, |
5e97313a | 1237 | .transfer = fsi_pio_push, |
180346ed | 1238 | .start_stop = fsi_pio_start_stop, |
5e97313a KM |
1239 | }; |
1240 | ||
1241 | static struct fsi_stream_handler fsi_pio_pop_handler = { | |
766812e6 | 1242 | .init = fsi_pio_pop_init, |
5e97313a | 1243 | .transfer = fsi_pio_pop, |
180346ed | 1244 | .start_stop = fsi_pio_start_stop, |
5e97313a KM |
1245 | }; |
1246 | ||
a4d7d550 KM |
1247 | static irqreturn_t fsi_interrupt(int irq, void *data) |
1248 | { | |
71f6e064 | 1249 | struct fsi_master *master = data; |
10ea76cc | 1250 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
1251 | |
1252 | /* clear irq status */ | |
feb58cff KM |
1253 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
1254 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 | 1255 | |
cf6edd00 | 1256 | if (int_st & AB_IO(1, AO_SHIFT)) |
5e97313a | 1257 | fsi_stream_transfer(&master->fsia.playback); |
cf6edd00 | 1258 | if (int_st & AB_IO(1, BO_SHIFT)) |
5e97313a | 1259 | fsi_stream_transfer(&master->fsib.playback); |
cf6edd00 | 1260 | if (int_st & AB_IO(1, AI_SHIFT)) |
5e97313a | 1261 | fsi_stream_transfer(&master->fsia.capture); |
cf6edd00 | 1262 | if (int_st & AB_IO(1, BI_SHIFT)) |
5e97313a | 1263 | fsi_stream_transfer(&master->fsib.capture); |
1ec9bc35 KM |
1264 | |
1265 | fsi_count_fifo_err(&master->fsia); | |
1266 | fsi_count_fifo_err(&master->fsib); | |
a4d7d550 | 1267 | |
48d78e58 KM |
1268 | fsi_irq_clear_status(&master->fsia); |
1269 | fsi_irq_clear_status(&master->fsib); | |
a4d7d550 KM |
1270 | |
1271 | return IRQ_HANDLED; | |
1272 | } | |
1273 | ||
7da9ced6 KM |
1274 | /* |
1275 | * dma data transfer handler | |
1276 | */ | |
1277 | static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io) | |
1278 | { | |
1279 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
1280 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); | |
1281 | enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? | |
1282 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1283 | ||
766812e6 KM |
1284 | /* |
1285 | * 24bit data : 24bit bus / package in back | |
1286 | * 16bit data : 16bit bus / stream mode | |
1287 | */ | |
1288 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | | |
1289 | BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); | |
1290 | ||
7da9ced6 KM |
1291 | io->dma = dma_map_single(dai->dev, runtime->dma_area, |
1292 | snd_pcm_lib_buffer_bytes(io->substream), dir); | |
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | static int fsi_dma_quit(struct fsi_priv *fsi, struct fsi_stream *io) | |
1297 | { | |
1298 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); | |
1299 | enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? | |
1300 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1301 | ||
1302 | dma_unmap_single(dai->dev, io->dma, | |
1303 | snd_pcm_lib_buffer_bytes(io->substream), dir); | |
1304 | return 0; | |
1305 | } | |
1306 | ||
4a1b09b7 KM |
1307 | static dma_addr_t fsi_dma_get_area(struct fsi_stream *io) |
1308 | { | |
1309 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
1310 | ||
1311 | return io->dma + samples_to_bytes(runtime, io->buff_sample_pos); | |
1312 | } | |
1313 | ||
7da9ced6 KM |
1314 | static void fsi_dma_complete(void *data) |
1315 | { | |
1316 | struct fsi_stream *io = (struct fsi_stream *)data; | |
1317 | struct fsi_priv *fsi = fsi_stream_to_priv(io); | |
1318 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
1319 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); | |
1320 | enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? | |
1321 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1322 | ||
4a1b09b7 | 1323 | dma_sync_single_for_cpu(dai->dev, fsi_dma_get_area(io), |
7da9ced6 KM |
1324 | samples_to_bytes(runtime, io->period_samples), dir); |
1325 | ||
1326 | io->buff_sample_pos += io->period_samples; | |
1327 | io->period_pos++; | |
1328 | ||
1329 | if (io->period_pos >= runtime->periods) { | |
1330 | io->period_pos = 0; | |
1331 | io->buff_sample_pos = 0; | |
1332 | } | |
1333 | ||
1334 | fsi_count_fifo_err(fsi); | |
1335 | fsi_stream_transfer(io); | |
1336 | ||
1337 | snd_pcm_period_elapsed(io->substream); | |
1338 | } | |
1339 | ||
57451e43 | 1340 | static void fsi_dma_do_work(struct work_struct *work) |
7da9ced6 | 1341 | { |
57451e43 | 1342 | struct fsi_stream *io = container_of(work, struct fsi_stream, work); |
7da9ced6 | 1343 | struct fsi_priv *fsi = fsi_stream_to_priv(io); |
7da9ced6 KM |
1344 | struct snd_soc_dai *dai; |
1345 | struct dma_async_tx_descriptor *desc; | |
7da9ced6 KM |
1346 | struct snd_pcm_runtime *runtime; |
1347 | enum dma_data_direction dir; | |
7da9ced6 KM |
1348 | int is_play = fsi_stream_is_play(fsi, io); |
1349 | int len; | |
1350 | dma_addr_t buf; | |
1351 | ||
1352 | if (!fsi_stream_is_working(fsi, io)) | |
1353 | return; | |
1354 | ||
1355 | dai = fsi_get_dai(io->substream); | |
7da9ced6 KM |
1356 | runtime = io->substream->runtime; |
1357 | dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1358 | len = samples_to_bytes(runtime, io->period_samples); | |
1359 | buf = fsi_dma_get_area(io); | |
1360 | ||
4a1b09b7 | 1361 | dma_sync_single_for_device(dai->dev, buf, len, dir); |
7da9ced6 | 1362 | |
5514efdf KM |
1363 | desc = dmaengine_prep_slave_single(io->chan, buf, len, dir, |
1364 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
7da9ced6 | 1365 | if (!desc) { |
cdf27f37 | 1366 | dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n"); |
7da9ced6 KM |
1367 | return; |
1368 | } | |
1369 | ||
1370 | desc->callback = fsi_dma_complete; | |
1371 | desc->callback_param = io; | |
1372 | ||
5514efdf | 1373 | if (dmaengine_submit(desc) < 0) { |
7da9ced6 KM |
1374 | dev_err(dai->dev, "tx_submit() fail\n"); |
1375 | return; | |
1376 | } | |
1377 | ||
5514efdf | 1378 | dma_async_issue_pending(io->chan); |
7da9ced6 KM |
1379 | |
1380 | /* | |
1381 | * FIXME | |
1382 | * | |
1383 | * In DMAEngine case, codec and FSI cannot be started simultaneously | |
57451e43 | 1384 | * since FSI is using the scheduler work queue. |
7da9ced6 KM |
1385 | * Therefore, in capture case, probably FSI FIFO will have got |
1386 | * overflow error in this point. | |
1387 | * in that case, DMA cannot start transfer until error was cleared. | |
1388 | */ | |
1389 | if (!is_play) { | |
1390 | if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) { | |
1391 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
1392 | fsi_reg_write(fsi, DIFF_ST, 0); | |
1393 | } | |
1394 | } | |
1395 | } | |
1396 | ||
1397 | static bool fsi_dma_filter(struct dma_chan *chan, void *param) | |
1398 | { | |
1399 | struct sh_dmae_slave *slave = param; | |
1400 | ||
1401 | chan->private = slave; | |
1402 | ||
1403 | return true; | |
1404 | } | |
1405 | ||
1406 | static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io) | |
1407 | { | |
57451e43 | 1408 | schedule_work(&io->work); |
7da9ced6 KM |
1409 | |
1410 | return 0; | |
1411 | } | |
1412 | ||
1413 | static void fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, | |
1414 | int start) | |
1415 | { | |
e42bb9bf KM |
1416 | struct fsi_master *master = fsi_get_master(fsi); |
1417 | u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; | |
766812e6 | 1418 | u32 enable = start ? DMA_ON : 0; |
7da9ced6 | 1419 | |
766812e6 | 1420 | fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable); |
e42bb9bf | 1421 | |
fbe42f66 KM |
1422 | dmaengine_terminate_all(io->chan); |
1423 | ||
e42bb9bf KM |
1424 | if (fsi_is_clk_master(fsi)) |
1425 | fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); | |
7da9ced6 KM |
1426 | } |
1427 | ||
b1226dc5 | 1428 | static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev) |
7da9ced6 KM |
1429 | { |
1430 | dma_cap_mask_t mask; | |
1431 | ||
1432 | dma_cap_zero(mask); | |
1433 | dma_cap_set(DMA_SLAVE, mask); | |
1434 | ||
1435 | io->chan = dma_request_channel(mask, fsi_dma_filter, &io->slave); | |
b1226dc5 KM |
1436 | if (!io->chan) { |
1437 | ||
1438 | /* switch to PIO handler */ | |
1439 | if (fsi_stream_is_play(fsi, io)) | |
1440 | fsi->playback.handler = &fsi_pio_push_handler; | |
1441 | else | |
1442 | fsi->capture.handler = &fsi_pio_pop_handler; | |
1443 | ||
1444 | dev_info(dev, "switch handler (dma => pio)\n"); | |
1445 | ||
1446 | /* probe again */ | |
1447 | return fsi_stream_probe(fsi, dev); | |
1448 | } | |
7da9ced6 | 1449 | |
57451e43 | 1450 | INIT_WORK(&io->work, fsi_dma_do_work); |
7da9ced6 KM |
1451 | |
1452 | return 0; | |
1453 | } | |
1454 | ||
1455 | static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io) | |
1456 | { | |
57451e43 | 1457 | cancel_work_sync(&io->work); |
7da9ced6 KM |
1458 | |
1459 | fsi_stream_stop(fsi, io); | |
1460 | ||
1461 | if (io->chan) | |
1462 | dma_release_channel(io->chan); | |
1463 | ||
1464 | io->chan = NULL; | |
1465 | return 0; | |
1466 | } | |
1467 | ||
1468 | static struct fsi_stream_handler fsi_dma_push_handler = { | |
1469 | .init = fsi_dma_init, | |
1470 | .quit = fsi_dma_quit, | |
1471 | .probe = fsi_dma_probe, | |
1472 | .transfer = fsi_dma_transfer, | |
1473 | .remove = fsi_dma_remove, | |
1474 | .start_stop = fsi_dma_push_start_stop, | |
1475 | }; | |
1476 | ||
c8fe2574 KM |
1477 | /* |
1478 | * dai ops | |
1479 | */ | |
b49e8027 | 1480 | static void fsi_fifo_init(struct fsi_priv *fsi, |
938e2a8d | 1481 | struct fsi_stream *io, |
b49e8027 KM |
1482 | struct device *dev) |
1483 | { | |
1484 | struct fsi_master *master = fsi_get_master(fsi); | |
938e2a8d | 1485 | int is_play = fsi_stream_is_play(fsi, io); |
b49e8027 KM |
1486 | u32 shift, i; |
1487 | int frame_capa; | |
1488 | ||
1489 | /* get on-chip RAM capacity */ | |
1490 | shift = fsi_master_read(master, FIFO_SZ); | |
938e2a8d | 1491 | shift >>= fsi_get_port_shift(fsi, io); |
b49e8027 KM |
1492 | shift &= FIFO_SZ_MASK; |
1493 | frame_capa = 256 << shift; | |
1494 | dev_dbg(dev, "fifo = %d words\n", frame_capa); | |
1495 | ||
1496 | /* | |
1497 | * The maximum number of sample data varies depending | |
1498 | * on the number of channels selected for the format. | |
1499 | * | |
1500 | * FIFOs are used in 4-channel units in 3-channel mode | |
1501 | * and in 8-channel units in 5- to 7-channel mode | |
1502 | * meaning that more FIFOs than the required size of DPRAM | |
1503 | * are used. | |
1504 | * | |
1505 | * ex) if 256 words of DP-RAM is connected | |
1506 | * 1 channel: 256 (256 x 1 = 256) | |
1507 | * 2 channels: 128 (128 x 2 = 256) | |
1508 | * 3 channels: 64 ( 64 x 3 = 192) | |
1509 | * 4 channels: 64 ( 64 x 4 = 256) | |
1510 | * 5 channels: 32 ( 32 x 5 = 160) | |
1511 | * 6 channels: 32 ( 32 x 6 = 192) | |
1512 | * 7 channels: 32 ( 32 x 7 = 224) | |
1513 | * 8 channels: 32 ( 32 x 8 = 256) | |
1514 | */ | |
1515 | for (i = 1; i < fsi->chan_num; i <<= 1) | |
1516 | frame_capa >>= 1; | |
1517 | dev_dbg(dev, "%d channel %d store\n", | |
1518 | fsi->chan_num, frame_capa); | |
1519 | ||
1520 | io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); | |
1521 | ||
1522 | /* | |
1523 | * set interrupt generation factor | |
1524 | * clear FIFO | |
1525 | */ | |
1526 | if (is_play) { | |
1527 | fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); | |
1528 | fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); | |
1529 | } else { | |
1530 | fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); | |
1531 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
1532 | } | |
1533 | } | |
a4d7d550 | 1534 | |
23ca8533 | 1535 | static int fsi_hw_startup(struct fsi_priv *fsi, |
938e2a8d | 1536 | struct fsi_stream *io, |
23ca8533 | 1537 | struct device *dev) |
a4d7d550 | 1538 | { |
9478e0b6 | 1539 | u32 data = 0; |
a4d7d550 | 1540 | |
9478e0b6 KM |
1541 | /* clock setting */ |
1542 | if (fsi_is_clk_master(fsi)) | |
1543 | data = DIMD | DOMD; | |
1544 | ||
1545 | fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); | |
a4d7d550 KM |
1546 | |
1547 | /* clock inversion (CKG2) */ | |
1548 | data = 0; | |
3449f5fa KM |
1549 | if (fsi->bit_clk_inv) |
1550 | data |= (1 << 0); | |
1551 | if (fsi->lr_clk_inv) | |
1552 | data |= (1 << 4); | |
1553 | if (fsi_is_clk_master(fsi)) | |
1554 | data <<= 8; | |
a4d7d550 KM |
1555 | fsi_reg_write(fsi, CKG2, data); |
1556 | ||
9478e0b6 KM |
1557 | /* spdif ? */ |
1558 | if (fsi_is_spdif(fsi)) { | |
1559 | fsi_spdif_clk_ctrl(fsi, 1); | |
1560 | fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); | |
1561 | } | |
1562 | ||
65ff03f4 | 1563 | /* |
766812e6 | 1564 | * get bus settings |
65ff03f4 | 1565 | */ |
766812e6 KM |
1566 | data = 0; |
1567 | switch (io->sample_width) { | |
1568 | case 2: | |
1569 | data = BUSOP_GET(16, io->bus_option); | |
1570 | break; | |
1571 | case 4: | |
1572 | data = BUSOP_GET(24, io->bus_option); | |
1573 | break; | |
65ff03f4 | 1574 | } |
766812e6 | 1575 | fsi_format_bus_setup(fsi, io, data, dev); |
65ff03f4 | 1576 | |
10ea76cc | 1577 | /* irq clear */ |
938e2a8d | 1578 | fsi_irq_disable(fsi, io); |
10ea76cc KM |
1579 | fsi_irq_clear_status(fsi); |
1580 | ||
1581 | /* fifo init */ | |
938e2a8d | 1582 | fsi_fifo_init(fsi, io, dev); |
a4d7d550 | 1583 | |
ddeb2d70 KM |
1584 | /* start master clock */ |
1585 | if (fsi_is_clk_master(fsi)) | |
6cbdbffb | 1586 | return fsi_clk_enable(dev, fsi); |
ddeb2d70 | 1587 | |
a68a3b4e | 1588 | return 0; |
a4d7d550 KM |
1589 | } |
1590 | ||
80b4addc | 1591 | static int fsi_hw_shutdown(struct fsi_priv *fsi, |
23ca8533 KM |
1592 | struct device *dev) |
1593 | { | |
ddeb2d70 | 1594 | /* stop master clock */ |
23ca8533 | 1595 | if (fsi_is_clk_master(fsi)) |
6cbdbffb | 1596 | return fsi_clk_disable(dev, fsi); |
80b4addc KM |
1597 | |
1598 | return 0; | |
23ca8533 KM |
1599 | } |
1600 | ||
1601 | static int fsi_dai_startup(struct snd_pcm_substream *substream, | |
1602 | struct snd_soc_dai *dai) | |
1603 | { | |
1604 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
23ca8533 | 1605 | |
ab6f6d85 | 1606 | fsi_clk_invalid(fsi); |
f33238e9 KM |
1607 | |
1608 | return 0; | |
23ca8533 KM |
1609 | } |
1610 | ||
a4d7d550 KM |
1611 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, |
1612 | struct snd_soc_dai *dai) | |
1613 | { | |
71f6e064 | 1614 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 | 1615 | |
ab6f6d85 | 1616 | fsi_clk_invalid(fsi); |
a4d7d550 KM |
1617 | } |
1618 | ||
1619 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
1620 | struct snd_soc_dai *dai) | |
1621 | { | |
71f6e064 | 1622 | struct fsi_priv *fsi = fsi_get_priv(substream); |
938e2a8d | 1623 | struct fsi_stream *io = fsi_stream_get(fsi, substream); |
a4d7d550 KM |
1624 | int ret = 0; |
1625 | ||
a4d7d550 KM |
1626 | switch (cmd) { |
1627 | case SNDRV_PCM_TRIGGER_START: | |
938e2a8d | 1628 | fsi_stream_init(fsi, io, substream); |
80b4addc KM |
1629 | if (!ret) |
1630 | ret = fsi_hw_startup(fsi, io, dai->dev); | |
1631 | if (!ret) | |
1632 | ret = fsi_stream_transfer(io); | |
1633 | if (!ret) | |
180346ed | 1634 | fsi_stream_start(fsi, io); |
a4d7d550 KM |
1635 | break; |
1636 | case SNDRV_PCM_TRIGGER_STOP: | |
80b4addc KM |
1637 | if (!ret) |
1638 | ret = fsi_hw_shutdown(fsi, dai->dev); | |
180346ed | 1639 | fsi_stream_stop(fsi, io); |
938e2a8d | 1640 | fsi_stream_quit(fsi, io); |
a4d7d550 KM |
1641 | break; |
1642 | } | |
1643 | ||
1644 | return ret; | |
1645 | } | |
1646 | ||
f17c13ca KM |
1647 | static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) |
1648 | { | |
f17c13ca KM |
1649 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
1650 | case SND_SOC_DAIFMT_I2S: | |
9c59dd34 | 1651 | fsi->fmt = CR_I2S; |
f17c13ca KM |
1652 | fsi->chan_num = 2; |
1653 | break; | |
1654 | case SND_SOC_DAIFMT_LEFT_J: | |
9c59dd34 | 1655 | fsi->fmt = CR_PCM; |
f17c13ca KM |
1656 | fsi->chan_num = 2; |
1657 | break; | |
1658 | default: | |
1659 | return -EINVAL; | |
1660 | } | |
1661 | ||
f17c13ca KM |
1662 | return 0; |
1663 | } | |
1664 | ||
1665 | static int fsi_set_fmt_spdif(struct fsi_priv *fsi) | |
1666 | { | |
1667 | struct fsi_master *master = fsi_get_master(fsi); | |
f17c13ca | 1668 | |
284c6f65 | 1669 | if (fsi_version(master) < 2) |
f17c13ca KM |
1670 | return -EINVAL; |
1671 | ||
766812e6 | 1672 | fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM; |
f17c13ca | 1673 | fsi->chan_num = 2; |
f17c13ca | 1674 | |
f17c13ca KM |
1675 | return 0; |
1676 | } | |
1677 | ||
4d805f7b KM |
1678 | static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
1679 | { | |
1680 | struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); | |
4d805f7b KM |
1681 | int ret; |
1682 | ||
4d805f7b KM |
1683 | /* set master/slave audio interface */ |
1684 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1685 | case SND_SOC_DAIFMT_CBM_CFM: | |
6a9ebad8 | 1686 | fsi->clk_master = 1; |
4d805f7b KM |
1687 | break; |
1688 | case SND_SOC_DAIFMT_CBS_CFS: | |
1689 | break; | |
1690 | default: | |
9478e0b6 | 1691 | return -EINVAL; |
4d805f7b | 1692 | } |
6a9ebad8 | 1693 | |
3449f5fa KM |
1694 | /* set clock inversion */ |
1695 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1696 | case SND_SOC_DAIFMT_NB_IF: | |
1697 | fsi->bit_clk_inv = 0; | |
1698 | fsi->lr_clk_inv = 1; | |
f17c13ca | 1699 | break; |
3449f5fa KM |
1700 | case SND_SOC_DAIFMT_IB_NF: |
1701 | fsi->bit_clk_inv = 1; | |
1702 | fsi->lr_clk_inv = 0; | |
f17c13ca | 1703 | break; |
3449f5fa KM |
1704 | case SND_SOC_DAIFMT_IB_IF: |
1705 | fsi->bit_clk_inv = 1; | |
1706 | fsi->lr_clk_inv = 1; | |
1707 | break; | |
1708 | case SND_SOC_DAIFMT_NB_NF: | |
f17c13ca | 1709 | default: |
3449f5fa KM |
1710 | fsi->bit_clk_inv = 0; |
1711 | fsi->lr_clk_inv = 0; | |
1712 | break; | |
1713 | } | |
1714 | ||
ab6f6d85 | 1715 | if (fsi_is_clk_master(fsi)) { |
ab6340c4 | 1716 | if (fsi->clk_cpg) |
ab6f6d85 KM |
1717 | fsi_clk_init(dai->dev, fsi, 0, 1, 1, |
1718 | fsi_clk_set_rate_cpg); | |
ab6340c4 KM |
1719 | else |
1720 | fsi_clk_init(dai->dev, fsi, 1, 1, 0, | |
1721 | fsi_clk_set_rate_external); | |
f17c13ca | 1722 | } |
4d805f7b | 1723 | |
f17c13ca | 1724 | /* set format */ |
c2052def | 1725 | if (fsi_is_spdif(fsi)) |
f17c13ca | 1726 | ret = fsi_set_fmt_spdif(fsi); |
c2052def KM |
1727 | else |
1728 | ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); | |
4d805f7b | 1729 | |
4d805f7b KM |
1730 | return ret; |
1731 | } | |
1732 | ||
ccad7b44 KM |
1733 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
1734 | struct snd_pcm_hw_params *params, | |
1735 | struct snd_soc_dai *dai) | |
1736 | { | |
1737 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
ccad7b44 | 1738 | |
6cbdbffb KM |
1739 | if (fsi_is_clk_master(fsi)) |
1740 | fsi_clk_valid(fsi, params_rate(params)); | |
ccad7b44 | 1741 | |
ddeb2d70 | 1742 | return 0; |
ccad7b44 KM |
1743 | } |
1744 | ||
85e7652d | 1745 | static const struct snd_soc_dai_ops fsi_dai_ops = { |
a4d7d550 KM |
1746 | .startup = fsi_dai_startup, |
1747 | .shutdown = fsi_dai_shutdown, | |
1748 | .trigger = fsi_dai_trigger, | |
4d805f7b | 1749 | .set_fmt = fsi_dai_set_fmt, |
ccad7b44 | 1750 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
1751 | }; |
1752 | ||
c8fe2574 KM |
1753 | /* |
1754 | * pcm ops | |
1755 | */ | |
a4d7d550 | 1756 | |
a4d7d550 KM |
1757 | static struct snd_pcm_hardware fsi_pcm_hardware = { |
1758 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
1759 | SNDRV_PCM_INFO_MMAP | | |
1760 | SNDRV_PCM_INFO_MMAP_VALID | | |
1761 | SNDRV_PCM_INFO_PAUSE, | |
1762 | .formats = FSI_FMTS, | |
1763 | .rates = FSI_RATES, | |
1764 | .rate_min = 8000, | |
1765 | .rate_max = 192000, | |
2a8c8a56 | 1766 | .channels_min = 2, |
a4d7d550 KM |
1767 | .channels_max = 2, |
1768 | .buffer_bytes_max = 64 * 1024, | |
1769 | .period_bytes_min = 32, | |
1770 | .period_bytes_max = 8192, | |
1771 | .periods_min = 1, | |
1772 | .periods_max = 32, | |
1773 | .fifo_size = 256, | |
1774 | }; | |
1775 | ||
1776 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
1777 | { | |
1778 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1779 | int ret = 0; | |
1780 | ||
1781 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
1782 | ||
1783 | ret = snd_pcm_hw_constraint_integer(runtime, | |
1784 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1785 | ||
1786 | return ret; | |
1787 | } | |
1788 | ||
1789 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
1790 | struct snd_pcm_hw_params *hw_params) | |
1791 | { | |
1792 | return snd_pcm_lib_malloc_pages(substream, | |
1793 | params_buffer_bytes(hw_params)); | |
1794 | } | |
1795 | ||
1796 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
1797 | { | |
1798 | return snd_pcm_lib_free_pages(substream); | |
1799 | } | |
1800 | ||
1801 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
1802 | { | |
71f6e064 | 1803 | struct fsi_priv *fsi = fsi_get_priv(substream); |
938e2a8d | 1804 | struct fsi_stream *io = fsi_stream_get(fsi, substream); |
a4d7d550 | 1805 | |
1987877d | 1806 | return fsi_sample2frame(fsi, io->buff_sample_pos); |
a4d7d550 KM |
1807 | } |
1808 | ||
1809 | static struct snd_pcm_ops fsi_pcm_ops = { | |
1810 | .open = fsi_pcm_open, | |
1811 | .ioctl = snd_pcm_lib_ioctl, | |
1812 | .hw_params = fsi_hw_params, | |
1813 | .hw_free = fsi_hw_free, | |
1814 | .pointer = fsi_pointer, | |
1815 | }; | |
1816 | ||
c8fe2574 KM |
1817 | /* |
1818 | * snd_soc_platform | |
1819 | */ | |
a4d7d550 | 1820 | |
a4d7d550 KM |
1821 | #define PREALLOC_BUFFER (32 * 1024) |
1822 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1823 | ||
1824 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1825 | { | |
1826 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1827 | } | |
1828 | ||
552d1ef6 | 1829 | static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd) |
a4d7d550 | 1830 | { |
552d1ef6 LG |
1831 | struct snd_pcm *pcm = rtd->pcm; |
1832 | ||
a4d7d550 KM |
1833 | /* |
1834 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1835 | * in MMAP mode (i.e. aplay -M) | |
1836 | */ | |
1837 | return snd_pcm_lib_preallocate_pages_for_all( | |
1838 | pcm, | |
1839 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1840 | snd_dma_continuous_data(GFP_KERNEL), | |
1841 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1842 | } | |
1843 | ||
c8fe2574 KM |
1844 | /* |
1845 | * alsa struct | |
1846 | */ | |
a4d7d550 | 1847 | |
f0fba2ad | 1848 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1849 | { |
f0fba2ad | 1850 | .name = "fsia-dai", |
a4d7d550 KM |
1851 | .playback = { |
1852 | .rates = FSI_RATES, | |
1853 | .formats = FSI_FMTS, | |
2a8c8a56 KM |
1854 | .channels_min = 2, |
1855 | .channels_max = 2, | |
a4d7d550 | 1856 | }, |
07102f3c KM |
1857 | .capture = { |
1858 | .rates = FSI_RATES, | |
1859 | .formats = FSI_FMTS, | |
2a8c8a56 KM |
1860 | .channels_min = 2, |
1861 | .channels_max = 2, | |
07102f3c | 1862 | }, |
a4d7d550 KM |
1863 | .ops = &fsi_dai_ops, |
1864 | }, | |
1865 | { | |
f0fba2ad | 1866 | .name = "fsib-dai", |
a4d7d550 KM |
1867 | .playback = { |
1868 | .rates = FSI_RATES, | |
1869 | .formats = FSI_FMTS, | |
2a8c8a56 KM |
1870 | .channels_min = 2, |
1871 | .channels_max = 2, | |
a4d7d550 | 1872 | }, |
07102f3c KM |
1873 | .capture = { |
1874 | .rates = FSI_RATES, | |
1875 | .formats = FSI_FMTS, | |
2a8c8a56 KM |
1876 | .channels_min = 2, |
1877 | .channels_max = 2, | |
07102f3c | 1878 | }, |
a4d7d550 KM |
1879 | .ops = &fsi_dai_ops, |
1880 | }, | |
1881 | }; | |
a4d7d550 | 1882 | |
f0fba2ad LG |
1883 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1884 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1885 | .pcm_new = fsi_pcm_new, |
1886 | .pcm_free = fsi_pcm_free, | |
1887 | }; | |
a4d7d550 | 1888 | |
c8fe2574 KM |
1889 | /* |
1890 | * platform function | |
1891 | */ | |
9e7b6d60 KM |
1892 | static void fsi_of_parse(char *name, |
1893 | struct device_node *np, | |
1894 | struct sh_fsi_port_info *info, | |
1895 | struct device *dev) | |
1896 | { | |
1897 | int i; | |
1898 | char prop[128]; | |
1899 | unsigned long flags = 0; | |
1900 | struct { | |
1901 | char *name; | |
1902 | unsigned int val; | |
1903 | } of_parse_property[] = { | |
1904 | { "spdif-connection", SH_FSI_FMT_SPDIF }, | |
1905 | { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE }, | |
1906 | { "use-internal-clock", SH_FSI_CLK_CPG }, | |
1907 | }; | |
1908 | ||
1909 | for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) { | |
1910 | sprintf(prop, "%s,%s", name, of_parse_property[i].name); | |
1911 | if (of_get_property(np, prop, NULL)) | |
1912 | flags |= of_parse_property[i].val; | |
1913 | } | |
1914 | info->flags = flags; | |
1915 | ||
1916 | dev_dbg(dev, "%s flags : %lx\n", name, info->flags); | |
1917 | } | |
1918 | ||
c2052def KM |
1919 | static void fsi_port_info_init(struct fsi_priv *fsi, |
1920 | struct sh_fsi_port_info *info) | |
1921 | { | |
1922 | if (info->flags & SH_FSI_FMT_SPDIF) | |
1923 | fsi->spdif = 1; | |
ab6340c4 KM |
1924 | |
1925 | if (info->flags & SH_FSI_CLK_CPG) | |
1926 | fsi->clk_cpg = 1; | |
2522acd2 KM |
1927 | |
1928 | if (info->flags & SH_FSI_ENABLE_STREAM_MODE) | |
1929 | fsi->enable_stream = 1; | |
c2052def KM |
1930 | } |
1931 | ||
943fdadc KM |
1932 | static void fsi_handler_init(struct fsi_priv *fsi, |
1933 | struct sh_fsi_port_info *info) | |
5e97313a KM |
1934 | { |
1935 | fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */ | |
1936 | fsi->playback.priv = fsi; | |
1937 | fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */ | |
1938 | fsi->capture.priv = fsi; | |
7da9ced6 | 1939 | |
943fdadc KM |
1940 | if (info->tx_id) { |
1941 | fsi->playback.slave.shdma_slave.slave_id = info->tx_id; | |
b8373147 | 1942 | fsi->playback.handler = &fsi_dma_push_handler; |
7da9ced6 | 1943 | } |
5e97313a | 1944 | } |
a4d7d550 | 1945 | |
9e7b6d60 | 1946 | static struct of_device_id fsi_of_match[]; |
a4d7d550 KM |
1947 | static int fsi_probe(struct platform_device *pdev) |
1948 | { | |
71f6e064 | 1949 | struct fsi_master *master; |
9e7b6d60 | 1950 | struct device_node *np = pdev->dev.of_node; |
fd974e52 | 1951 | struct sh_fsi_platform_info info; |
9e7b6d60 | 1952 | const struct fsi_core *core; |
40f9118b | 1953 | struct fsi_priv *fsi; |
a4d7d550 | 1954 | struct resource *res; |
a4d7d550 KM |
1955 | unsigned int irq; |
1956 | int ret; | |
1957 | ||
fd974e52 | 1958 | memset(&info, 0, sizeof(info)); |
943fdadc | 1959 | |
9e7b6d60 KM |
1960 | core = NULL; |
1961 | if (np) { | |
1962 | const struct of_device_id *of_id; | |
1963 | ||
1964 | of_id = of_match_device(fsi_of_match, &pdev->dev); | |
1965 | if (of_id) { | |
1966 | core = of_id->data; | |
1967 | fsi_of_parse("fsia", np, &info.port_a, &pdev->dev); | |
1968 | fsi_of_parse("fsib", np, &info.port_b, &pdev->dev); | |
1969 | } | |
1970 | } else { | |
1971 | const struct platform_device_id *id_entry = pdev->id_entry; | |
1972 | if (id_entry) | |
1973 | core = (struct fsi_core *)id_entry->driver_data; | |
1974 | ||
1975 | if (pdev->dev.platform_data) | |
1976 | memcpy(&info, pdev->dev.platform_data, sizeof(info)); | |
1977 | } | |
1978 | ||
1979 | if (!core) { | |
cc780d38 KM |
1980 | dev_err(&pdev->dev, "unknown fsi device\n"); |
1981 | return -ENODEV; | |
1982 | } | |
1983 | ||
a4d7d550 KM |
1984 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1985 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 1986 | if (!res || (int)irq <= 0) { |
a4d7d550 | 1987 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
6ac4262f | 1988 | return -ENODEV; |
a4d7d550 KM |
1989 | } |
1990 | ||
6ac4262f | 1991 | master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); |
a4d7d550 KM |
1992 | if (!master) { |
1993 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
6ac4262f | 1994 | return -ENOMEM; |
a4d7d550 KM |
1995 | } |
1996 | ||
6ac4262f KM |
1997 | master->base = devm_ioremap_nocache(&pdev->dev, |
1998 | res->start, resource_size(res)); | |
a4d7d550 | 1999 | if (!master->base) { |
a4d7d550 | 2000 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); |
6ac4262f | 2001 | return -ENXIO; |
a4d7d550 KM |
2002 | } |
2003 | ||
3bc28070 | 2004 | /* master setting */ |
a4d7d550 | 2005 | master->irq = irq; |
9e7b6d60 | 2006 | master->core = core; |
3bc28070 KM |
2007 | spin_lock_init(&master->lock); |
2008 | ||
2009 | /* FSI A setting */ | |
40f9118b KM |
2010 | fsi = &master->fsia; |
2011 | fsi->base = master->base; | |
2012 | fsi->master = master; | |
fd974e52 KM |
2013 | fsi_port_info_init(fsi, &info.port_a); |
2014 | fsi_handler_init(fsi, &info.port_a); | |
40f9118b | 2015 | ret = fsi_stream_probe(fsi, &pdev->dev); |
5e97313a KM |
2016 | if (ret < 0) { |
2017 | dev_err(&pdev->dev, "FSIA stream probe failed\n"); | |
6ac4262f | 2018 | return ret; |
5e97313a | 2019 | } |
3bc28070 KM |
2020 | |
2021 | /* FSI B setting */ | |
40f9118b KM |
2022 | fsi = &master->fsib; |
2023 | fsi->base = master->base + 0x40; | |
2024 | fsi->master = master; | |
fd974e52 KM |
2025 | fsi_port_info_init(fsi, &info.port_b); |
2026 | fsi_handler_init(fsi, &info.port_b); | |
40f9118b | 2027 | ret = fsi_stream_probe(fsi, &pdev->dev); |
5e97313a KM |
2028 | if (ret < 0) { |
2029 | dev_err(&pdev->dev, "FSIB stream probe failed\n"); | |
2030 | goto exit_fsia; | |
2031 | } | |
a4d7d550 | 2032 | |
785d1c45 | 2033 | pm_runtime_enable(&pdev->dev); |
f0fba2ad | 2034 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 2035 | |
1ddd8286 | 2036 | ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0, |
9e7b6d60 | 2037 | dev_name(&pdev->dev), master); |
a4d7d550 KM |
2038 | if (ret) { |
2039 | dev_err(&pdev->dev, "irq request err\n"); | |
5e97313a | 2040 | goto exit_fsib; |
a4d7d550 KM |
2041 | } |
2042 | ||
f0fba2ad | 2043 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
2044 | if (ret < 0) { |
2045 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1ddd8286 | 2046 | goto exit_fsib; |
a4d7d550 KM |
2047 | } |
2048 | ||
0b5ec87d KM |
2049 | ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai, |
2050 | ARRAY_SIZE(fsi_soc_dai)); | |
2051 | if (ret < 0) { | |
2052 | dev_err(&pdev->dev, "cannot snd dai register\n"); | |
2053 | goto exit_snd_soc; | |
2054 | } | |
a4d7d550 | 2055 | |
0b5ec87d KM |
2056 | return ret; |
2057 | ||
2058 | exit_snd_soc: | |
2059 | snd_soc_unregister_platform(&pdev->dev); | |
5e97313a | 2060 | exit_fsib: |
c35e005f | 2061 | pm_runtime_disable(&pdev->dev); |
5e97313a KM |
2062 | fsi_stream_remove(&master->fsib); |
2063 | exit_fsia: | |
2064 | fsi_stream_remove(&master->fsia); | |
6ac4262f | 2065 | |
a4d7d550 KM |
2066 | return ret; |
2067 | } | |
2068 | ||
2069 | static int fsi_remove(struct platform_device *pdev) | |
2070 | { | |
71f6e064 KM |
2071 | struct fsi_master *master; |
2072 | ||
f0fba2ad | 2073 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 2074 | |
785d1c45 | 2075 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 2076 | |
d985f27e KM |
2077 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); |
2078 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 | 2079 | |
5e97313a KM |
2080 | fsi_stream_remove(&master->fsia); |
2081 | fsi_stream_remove(&master->fsib); | |
2082 | ||
a4d7d550 KM |
2083 | return 0; |
2084 | } | |
2085 | ||
106c79ec | 2086 | static void __fsi_suspend(struct fsi_priv *fsi, |
938e2a8d | 2087 | struct fsi_stream *io, |
4f56cde1 | 2088 | struct device *dev) |
106c79ec | 2089 | { |
938e2a8d | 2090 | if (!fsi_stream_is_working(fsi, io)) |
cda828ca | 2091 | return; |
106c79ec | 2092 | |
180346ed | 2093 | fsi_stream_stop(fsi, io); |
41bba151 | 2094 | fsi_hw_shutdown(fsi, dev); |
106c79ec KM |
2095 | } |
2096 | ||
2097 | static void __fsi_resume(struct fsi_priv *fsi, | |
938e2a8d | 2098 | struct fsi_stream *io, |
4f56cde1 | 2099 | struct device *dev) |
106c79ec | 2100 | { |
938e2a8d | 2101 | if (!fsi_stream_is_working(fsi, io)) |
cda828ca | 2102 | return; |
106c79ec | 2103 | |
938e2a8d | 2104 | fsi_hw_startup(fsi, io, dev); |
180346ed | 2105 | fsi_stream_start(fsi, io); |
106c79ec KM |
2106 | } |
2107 | ||
2108 | static int fsi_suspend(struct device *dev) | |
2109 | { | |
2110 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
2111 | struct fsi_priv *fsia = &master->fsia; |
2112 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 2113 | |
938e2a8d KM |
2114 | __fsi_suspend(fsia, &fsia->playback, dev); |
2115 | __fsi_suspend(fsia, &fsia->capture, dev); | |
106c79ec | 2116 | |
938e2a8d KM |
2117 | __fsi_suspend(fsib, &fsib->playback, dev); |
2118 | __fsi_suspend(fsib, &fsib->capture, dev); | |
106c79ec KM |
2119 | |
2120 | return 0; | |
2121 | } | |
2122 | ||
2123 | static int fsi_resume(struct device *dev) | |
2124 | { | |
2125 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
2126 | struct fsi_priv *fsia = &master->fsia; |
2127 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 2128 | |
938e2a8d KM |
2129 | __fsi_resume(fsia, &fsia->playback, dev); |
2130 | __fsi_resume(fsia, &fsia->capture, dev); | |
106c79ec | 2131 | |
938e2a8d KM |
2132 | __fsi_resume(fsib, &fsib->playback, dev); |
2133 | __fsi_resume(fsib, &fsib->capture, dev); | |
106c79ec KM |
2134 | |
2135 | return 0; | |
2136 | } | |
2137 | ||
785d1c45 | 2138 | static struct dev_pm_ops fsi_pm_ops = { |
106c79ec KM |
2139 | .suspend = fsi_suspend, |
2140 | .resume = fsi_resume, | |
785d1c45 KM |
2141 | }; |
2142 | ||
73b92c1f KM |
2143 | static struct fsi_core fsi1_core = { |
2144 | .ver = 1, | |
2145 | ||
2146 | /* Interrupt */ | |
cc780d38 KM |
2147 | .int_st = INT_ST, |
2148 | .iemsk = IEMSK, | |
2149 | .imsk = IMSK, | |
2150 | }; | |
2151 | ||
73b92c1f KM |
2152 | static struct fsi_core fsi2_core = { |
2153 | .ver = 2, | |
2154 | ||
2155 | /* Interrupt */ | |
cc780d38 KM |
2156 | .int_st = CPU_INT_ST, |
2157 | .iemsk = CPU_IEMSK, | |
2158 | .imsk = CPU_IMSK, | |
2b0e7302 KM |
2159 | .a_mclk = A_MST_CTLR, |
2160 | .b_mclk = B_MST_CTLR, | |
cc780d38 KM |
2161 | }; |
2162 | ||
e43fc6af | 2163 | static struct of_device_id fsi_of_match[] = { |
9e7b6d60 KM |
2164 | { .compatible = "renesas,sh_fsi", .data = &fsi1_core}, |
2165 | { .compatible = "renesas,sh_fsi2", .data = &fsi2_core}, | |
2166 | {}, | |
2167 | }; | |
2168 | MODULE_DEVICE_TABLE(of, fsi_of_match); | |
2169 | ||
cc780d38 | 2170 | static struct platform_device_id fsi_id_table[] = { |
73b92c1f KM |
2171 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
2172 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
05c69450 | 2173 | {}, |
cc780d38 | 2174 | }; |
d85a6d7b | 2175 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 2176 | |
a4d7d550 KM |
2177 | static struct platform_driver fsi_driver = { |
2178 | .driver = { | |
f0fba2ad | 2179 | .name = "fsi-pcm-audio", |
785d1c45 | 2180 | .pm = &fsi_pm_ops, |
9e7b6d60 | 2181 | .of_match_table = fsi_of_match, |
a4d7d550 KM |
2182 | }, |
2183 | .probe = fsi_probe, | |
2184 | .remove = fsi_remove, | |
cc780d38 | 2185 | .id_table = fsi_id_table, |
a4d7d550 KM |
2186 | }; |
2187 | ||
cb5e8738 | 2188 | module_platform_driver(fsi_driver); |
a4d7d550 KM |
2189 | |
2190 | MODULE_LICENSE("GPL"); | |
2191 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
2192 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); | |
b3c27b51 | 2193 | MODULE_ALIAS("platform:fsi-pcm-audio"); |