Commit | Line | Data |
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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
785d1c45 | 16 | #include <linux/pm_runtime.h> |
a4d7d550 | 17 | #include <linux/io.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
da155d5b | 19 | #include <linux/module.h> |
a4d7d550 | 20 | #include <sound/soc.h> |
a4d7d550 | 21 | #include <sound/sh_fsi.h> |
a4d7d550 | 22 | |
e8c8b631 KM |
23 | /* PortA/PortB register */ |
24 | #define REG_DO_FMT 0x0000 | |
25 | #define REG_DOFF_CTL 0x0004 | |
26 | #define REG_DOFF_ST 0x0008 | |
27 | #define REG_DI_FMT 0x000C | |
28 | #define REG_DIFF_CTL 0x0010 | |
29 | #define REG_DIFF_ST 0x0014 | |
30 | #define REG_CKG1 0x0018 | |
31 | #define REG_CKG2 0x001C | |
32 | #define REG_DIDT 0x0020 | |
33 | #define REG_DODT 0x0024 | |
34 | #define REG_MUTE_ST 0x0028 | |
65ff03f4 | 35 | #define REG_OUT_DMAC 0x002C |
e8c8b631 | 36 | #define REG_OUT_SEL 0x0030 |
65ff03f4 | 37 | #define REG_IN_DMAC 0x0038 |
cc780d38 | 38 | |
43fa95ca KM |
39 | /* master register */ |
40 | #define MST_CLK_RST 0x0210 | |
41 | #define MST_SOFT_RST 0x0214 | |
42 | #define MST_FIFO_SZ 0x0218 | |
43 | ||
44 | /* core register (depend on FSI version) */ | |
3bc28070 KM |
45 | #define A_MST_CTLR 0x0180 |
46 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
47 | #define CPU_INT_ST 0x01F4 |
48 | #define CPU_IEMSK 0x01F8 | |
49 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
50 | #define INT_ST 0x0200 |
51 | #define IEMSK 0x0204 | |
52 | #define IMSK 0x0208 | |
a4d7d550 KM |
53 | |
54 | /* DO_FMT */ | |
55 | /* DI_FMT */ | |
f7d711e3 KM |
56 | #define CR_BWS_24 (0x0 << 20) /* FSI2 */ |
57 | #define CR_BWS_16 (0x1 << 20) /* FSI2 */ | |
58 | #define CR_BWS_20 (0x2 << 20) /* FSI2 */ | |
59 | ||
60 | #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ | |
61 | #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ | |
62 | #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ | |
63 | ||
a7ffb52b KM |
64 | #define CR_MONO (0x0 << 4) |
65 | #define CR_MONO_D (0x1 << 4) | |
66 | #define CR_PCM (0x2 << 4) | |
67 | #define CR_I2S (0x3 << 4) | |
68 | #define CR_TDM (0x4 << 4) | |
69 | #define CR_TDM_D (0x5 << 4) | |
a4d7d550 KM |
70 | |
71 | /* DOFF_CTL */ | |
72 | /* DIFF_CTL */ | |
73 | #define IRQ_HALF 0x00100000 | |
74 | #define FIFO_CLR 0x00000001 | |
75 | ||
76 | /* DOFF_ST */ | |
77 | #define ERR_OVER 0x00000010 | |
78 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 79 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 80 | |
ccad7b44 KM |
81 | /* CKG1 */ |
82 | #define ACKMD_MASK 0x00007000 | |
83 | #define BPFMD_MASK 0x00000700 | |
4d805f7b KM |
84 | #define DIMD (1 << 4) |
85 | #define DOMD (1 << 0) | |
ccad7b44 | 86 | |
3bc28070 KM |
87 | /* A/B MST_CTLR */ |
88 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
89 | #define SE (1 << 0) /* Fix the master clock */ | |
90 | ||
a4d7d550 | 91 | /* CLK_RST */ |
1f5e2a31 KM |
92 | #define CRB (1 << 4) |
93 | #define CRA (1 << 0) | |
a4d7d550 | 94 | |
cf6edd00 KM |
95 | /* IO SHIFT / MACRO */ |
96 | #define BI_SHIFT 12 | |
97 | #define BO_SHIFT 8 | |
98 | #define AI_SHIFT 4 | |
99 | #define AO_SHIFT 0 | |
100 | #define AB_IO(param, shift) (param << shift) | |
a4d7d550 | 101 | |
feb58cff KM |
102 | /* SOFT_RST */ |
103 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
104 | #define PASR (1 << 8) /* Port A Software Reset */ | |
105 | #define IR (1 << 4) /* Interrupt Reset */ | |
106 | #define FSISR (1 << 0) /* Software Reset */ | |
107 | ||
f7d711e3 KM |
108 | /* OUT_SEL (FSI2) */ |
109 | #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ | |
110 | /* 1: Biphase and serial */ | |
111 | ||
4a942b45 | 112 | /* FIFO_SZ */ |
cf6edd00 | 113 | #define FIFO_SZ_MASK 0x7 |
4a942b45 | 114 | |
a4d7d550 KM |
115 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
116 | ||
117 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
118 | ||
d7c5762b KM |
119 | typedef int (*set_rate_func)(struct device *dev, int is_porta, int rate, int enable); |
120 | ||
5bfb9ad0 KM |
121 | /* |
122 | * FSI driver use below type name for variable | |
123 | * | |
5bfb9ad0 | 124 | * xxx_num : number of data |
2e651baf KM |
125 | * xxx_pos : position of data |
126 | * xxx_capa : capacity of data | |
127 | */ | |
128 | ||
129 | /* | |
130 | * period/frame/sample image | |
131 | * | |
132 | * ex) PCM (2ch) | |
133 | * | |
134 | * period pos period pos | |
135 | * [n] [n + 1] | |
136 | * |<-------------------- period--------------------->| | |
137 | * ==|============================================ ... =|== | |
138 | * | | | |
139 | * ||<----- frame ----->|<------ frame ----->| ... | | |
140 | * |+--------------------+--------------------+- ... | | |
141 | * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | | |
142 | * |+--------------------+--------------------+- ... | | |
143 | * ==|============================================ ... =|== | |
144 | */ | |
145 | ||
146 | /* | |
147 | * FSI FIFO image | |
148 | * | |
149 | * | | | |
150 | * | | | |
151 | * | [ sample ] | | |
152 | * | [ sample ] | | |
153 | * | [ sample ] | | |
154 | * | [ sample ] | | |
155 | * --> go to codecs | |
5bfb9ad0 KM |
156 | */ |
157 | ||
c8fe2574 KM |
158 | /* |
159 | * struct | |
160 | */ | |
a4d7d550 | 161 | |
93193c2b | 162 | struct fsi_stream { |
a4d7d550 KM |
163 | struct snd_pcm_substream *substream; |
164 | ||
2e651baf KM |
165 | int fifo_sample_capa; /* sample capacity of FSI FIFO */ |
166 | int buff_sample_capa; /* sample capacity of ALSA buffer */ | |
167 | int buff_sample_pos; /* sample position of ALSA buffer */ | |
168 | int period_samples; /* sample number / 1 period */ | |
169 | int period_pos; /* current period position */ | |
c1e6f10e | 170 | int sample_width; /* sample width */ |
1ec9bc35 KM |
171 | |
172 | int uerr_num; | |
173 | int oerr_num; | |
93193c2b KM |
174 | }; |
175 | ||
176 | struct fsi_priv { | |
177 | void __iomem *base; | |
178 | struct fsi_master *master; | |
179 | ||
180 | struct fsi_stream playback; | |
181 | struct fsi_stream capture; | |
3bc28070 | 182 | |
9478e0b6 KM |
183 | u32 do_fmt; |
184 | u32 di_fmt; | |
185 | ||
6a9ebad8 KM |
186 | int chan_num:16; |
187 | int clk_master:1; | |
9478e0b6 | 188 | int spdif:1; |
6a9ebad8 | 189 | |
d4bc99b9 | 190 | long rate; |
a4d7d550 KM |
191 | }; |
192 | ||
73b92c1f KM |
193 | struct fsi_core { |
194 | int ver; | |
195 | ||
cc780d38 KM |
196 | u32 int_st; |
197 | u32 iemsk; | |
198 | u32 imsk; | |
2b0e7302 KM |
199 | u32 a_mclk; |
200 | u32 b_mclk; | |
cc780d38 KM |
201 | }; |
202 | ||
a4d7d550 KM |
203 | struct fsi_master { |
204 | void __iomem *base; | |
205 | int irq; | |
a4d7d550 KM |
206 | struct fsi_priv fsia; |
207 | struct fsi_priv fsib; | |
73b92c1f | 208 | struct fsi_core *core; |
a4d7d550 | 209 | struct sh_fsi_platform_info *info; |
8fc176d5 | 210 | spinlock_t lock; |
a4d7d550 KM |
211 | }; |
212 | ||
c8fe2574 KM |
213 | /* |
214 | * basic read write function | |
215 | */ | |
a4d7d550 | 216 | |
ca7aceef | 217 | static void __fsi_reg_write(u32 __iomem *reg, u32 data) |
a4d7d550 KM |
218 | { |
219 | /* valid data area is 24bit */ | |
220 | data &= 0x00ffffff; | |
221 | ||
0f69d978 | 222 | __raw_writel(data, reg); |
a4d7d550 KM |
223 | } |
224 | ||
ca7aceef | 225 | static u32 __fsi_reg_read(u32 __iomem *reg) |
a4d7d550 | 226 | { |
0f69d978 | 227 | return __raw_readl(reg); |
a4d7d550 KM |
228 | } |
229 | ||
ca7aceef | 230 | static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) |
a4d7d550 KM |
231 | { |
232 | u32 val = __fsi_reg_read(reg); | |
233 | ||
234 | val &= ~mask; | |
235 | val |= data & mask; | |
236 | ||
0f69d978 | 237 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
238 | } |
239 | ||
e8c8b631 | 240 | #define fsi_reg_write(p, r, d)\ |
8918b843 | 241 | __fsi_reg_write((p->base + REG_##r), d) |
a4d7d550 | 242 | |
e8c8b631 | 243 | #define fsi_reg_read(p, r)\ |
8918b843 | 244 | __fsi_reg_read((p->base + REG_##r)) |
a4d7d550 | 245 | |
e8c8b631 | 246 | #define fsi_reg_mask_set(p, r, m, d)\ |
8918b843 | 247 | __fsi_reg_mask_set((p->base + REG_##r), m, d) |
a4d7d550 | 248 | |
43fa95ca KM |
249 | #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) |
250 | #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) | |
251 | static u32 _fsi_master_read(struct fsi_master *master, u32 reg) | |
a4d7d550 | 252 | { |
8fc176d5 KM |
253 | u32 ret; |
254 | unsigned long flags; | |
255 | ||
8fc176d5 | 256 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 257 | ret = __fsi_reg_read(master->base + reg); |
8fc176d5 KM |
258 | spin_unlock_irqrestore(&master->lock, flags); |
259 | ||
260 | return ret; | |
a4d7d550 KM |
261 | } |
262 | ||
43fa95ca KM |
263 | #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) |
264 | #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) | |
265 | static void _fsi_master_mask_set(struct fsi_master *master, | |
71f6e064 | 266 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 267 | { |
8fc176d5 KM |
268 | unsigned long flags; |
269 | ||
8fc176d5 | 270 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 271 | __fsi_reg_mask_set(master->base + reg, mask, data); |
8fc176d5 | 272 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
273 | } |
274 | ||
c8fe2574 KM |
275 | /* |
276 | * basic function | |
277 | */ | |
a4d7d550 | 278 | |
71f6e064 | 279 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 280 | { |
71f6e064 | 281 | return fsi->master; |
a4d7d550 KM |
282 | } |
283 | ||
6a9ebad8 KM |
284 | static int fsi_is_clk_master(struct fsi_priv *fsi) |
285 | { | |
286 | return fsi->clk_master; | |
287 | } | |
288 | ||
a4d7d550 KM |
289 | static int fsi_is_port_a(struct fsi_priv *fsi) |
290 | { | |
71f6e064 KM |
291 | return fsi->master->base == fsi->base; |
292 | } | |
a4d7d550 | 293 | |
9478e0b6 KM |
294 | static int fsi_is_spdif(struct fsi_priv *fsi) |
295 | { | |
296 | return fsi->spdif; | |
297 | } | |
298 | ||
142e8174 | 299 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
300 | { |
301 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 302 | |
f0fba2ad | 303 | return rtd->cpu_dai; |
142e8174 KM |
304 | } |
305 | ||
0d032c19 | 306 | static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) |
142e8174 | 307 | { |
f0fba2ad | 308 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 309 | |
f0fba2ad LG |
310 | if (dai->id == 0) |
311 | return &master->fsia; | |
312 | else | |
313 | return &master->fsib; | |
a4d7d550 KM |
314 | } |
315 | ||
0d032c19 KM |
316 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) |
317 | { | |
318 | return fsi_get_priv_frm_dai(fsi_get_dai(substream)); | |
319 | } | |
320 | ||
d7c5762b KM |
321 | static set_rate_func fsi_get_info_set_rate(struct fsi_master *master) |
322 | { | |
323 | if (!master->info) | |
324 | return NULL; | |
325 | ||
326 | return master->info->set_rate; | |
327 | } | |
328 | ||
a4d7d550 KM |
329 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) |
330 | { | |
331 | int is_porta = fsi_is_port_a(fsi); | |
71f6e064 | 332 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 333 | |
d7c5762b KM |
334 | if (!master->info) |
335 | return 0; | |
336 | ||
a4d7d550 KM |
337 | return is_porta ? master->info->porta_flags : |
338 | master->info->portb_flags; | |
339 | } | |
340 | ||
93193c2b KM |
341 | static inline int fsi_stream_is_play(int stream) |
342 | { | |
343 | return stream == SNDRV_PCM_STREAM_PLAYBACK; | |
344 | } | |
345 | ||
00545785 KM |
346 | static inline int fsi_is_play(struct snd_pcm_substream *substream) |
347 | { | |
93193c2b KM |
348 | return fsi_stream_is_play(substream->stream); |
349 | } | |
350 | ||
351 | static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi, | |
352 | int is_play) | |
353 | { | |
354 | return is_play ? &fsi->playback : &fsi->capture; | |
00545785 KM |
355 | } |
356 | ||
cf6edd00 | 357 | static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
358 | { |
359 | int is_porta = fsi_is_port_a(fsi); | |
cf6edd00 | 360 | u32 shift; |
a4d7d550 KM |
361 | |
362 | if (is_porta) | |
cf6edd00 | 363 | shift = is_play ? AO_SHIFT : AI_SHIFT; |
a4d7d550 | 364 | else |
cf6edd00 | 365 | shift = is_play ? BO_SHIFT : BI_SHIFT; |
a4d7d550 | 366 | |
cf6edd00 | 367 | return shift; |
a4d7d550 KM |
368 | } |
369 | ||
2e651baf KM |
370 | static int fsi_frame2sample(struct fsi_priv *fsi, int frames) |
371 | { | |
372 | return frames * fsi->chan_num; | |
373 | } | |
374 | ||
375 | static int fsi_sample2frame(struct fsi_priv *fsi, int samples) | |
376 | { | |
377 | return samples / fsi->chan_num; | |
378 | } | |
379 | ||
cda828ca KM |
380 | static int fsi_stream_is_working(struct fsi_priv *fsi, |
381 | int is_play) | |
382 | { | |
383 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
384 | struct fsi_master *master = fsi_get_master(fsi); | |
385 | unsigned long flags; | |
386 | int ret; | |
387 | ||
388 | spin_lock_irqsave(&master->lock, flags); | |
389 | ret = !!io->substream; | |
390 | spin_unlock_irqrestore(&master->lock, flags); | |
391 | ||
392 | return ret; | |
393 | } | |
394 | ||
a4d7d550 | 395 | static void fsi_stream_push(struct fsi_priv *fsi, |
93193c2b | 396 | int is_play, |
0ffe296a | 397 | struct snd_pcm_substream *substream) |
a4d7d550 | 398 | { |
93193c2b | 399 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
0ffe296a | 400 | struct snd_pcm_runtime *runtime = substream->runtime; |
2da65892 KM |
401 | struct fsi_master *master = fsi_get_master(fsi); |
402 | unsigned long flags; | |
93193c2b | 403 | |
2da65892 | 404 | spin_lock_irqsave(&master->lock, flags); |
93193c2b | 405 | io->substream = substream; |
2e651baf KM |
406 | io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); |
407 | io->buff_sample_pos = 0; | |
408 | io->period_samples = fsi_frame2sample(fsi, runtime->period_size); | |
409 | io->period_pos = 0; | |
c1e6f10e | 410 | io->sample_width = samples_to_bytes(runtime, 1); |
1ec9bc35 KM |
411 | io->oerr_num = -1; /* ignore 1st err */ |
412 | io->uerr_num = -1; /* ignore 1st err */ | |
2da65892 | 413 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
414 | } |
415 | ||
93193c2b | 416 | static void fsi_stream_pop(struct fsi_priv *fsi, int is_play) |
a4d7d550 | 417 | { |
93193c2b | 418 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
1ec9bc35 | 419 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); |
2da65892 KM |
420 | struct fsi_master *master = fsi_get_master(fsi); |
421 | unsigned long flags; | |
1ec9bc35 | 422 | |
2da65892 | 423 | spin_lock_irqsave(&master->lock, flags); |
1ec9bc35 KM |
424 | |
425 | if (io->oerr_num > 0) | |
426 | dev_err(dai->dev, "over_run = %d\n", io->oerr_num); | |
427 | ||
428 | if (io->uerr_num > 0) | |
429 | dev_err(dai->dev, "under_run = %d\n", io->uerr_num); | |
93193c2b KM |
430 | |
431 | io->substream = NULL; | |
2e651baf KM |
432 | io->buff_sample_capa = 0; |
433 | io->buff_sample_pos = 0; | |
434 | io->period_samples = 0; | |
435 | io->period_pos = 0; | |
c1e6f10e | 436 | io->sample_width = 0; |
1ec9bc35 KM |
437 | io->oerr_num = 0; |
438 | io->uerr_num = 0; | |
2da65892 | 439 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
440 | } |
441 | ||
2e651baf | 442 | static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
443 | { |
444 | u32 status; | |
2e651baf | 445 | int frames; |
a4d7d550 | 446 | |
e8c8b631 KM |
447 | status = is_play ? |
448 | fsi_reg_read(fsi, DOFF_ST) : | |
449 | fsi_reg_read(fsi, DIFF_ST); | |
450 | ||
2e651baf | 451 | frames = 0x1ff & (status >> 8); |
5bfb9ad0 | 452 | |
2e651baf | 453 | return fsi_frame2sample(fsi, frames); |
cca1b235 KM |
454 | } |
455 | ||
1ec9bc35 KM |
456 | static void fsi_count_fifo_err(struct fsi_priv *fsi) |
457 | { | |
458 | u32 ostatus = fsi_reg_read(fsi, DOFF_ST); | |
459 | u32 istatus = fsi_reg_read(fsi, DIFF_ST); | |
460 | ||
461 | if (ostatus & ERR_OVER) | |
462 | fsi->playback.oerr_num++; | |
463 | ||
464 | if (ostatus & ERR_UNDER) | |
465 | fsi->playback.uerr_num++; | |
466 | ||
467 | if (istatus & ERR_OVER) | |
468 | fsi->capture.oerr_num++; | |
469 | ||
470 | if (istatus & ERR_UNDER) | |
471 | fsi->capture.uerr_num++; | |
472 | ||
473 | fsi_reg_write(fsi, DOFF_ST, 0); | |
474 | fsi_reg_write(fsi, DIFF_ST, 0); | |
475 | } | |
476 | ||
b9fde18c KM |
477 | /* |
478 | * dma function | |
479 | */ | |
480 | ||
93193c2b | 481 | static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream) |
c79eab3e | 482 | { |
93193c2b KM |
483 | int is_play = fsi_stream_is_play(stream); |
484 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
2e651baf | 485 | struct snd_pcm_runtime *runtime = io->substream->runtime; |
93193c2b | 486 | |
2e651baf KM |
487 | return runtime->dma_area + |
488 | samples_to_bytes(runtime, io->buff_sample_pos); | |
c79eab3e KM |
489 | } |
490 | ||
5bfb9ad0 | 491 | static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
492 | { |
493 | u16 *start; | |
494 | int i; | |
495 | ||
93193c2b | 496 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
b9fde18c | 497 | |
5bfb9ad0 | 498 | for (i = 0; i < num; i++) |
b9fde18c KM |
499 | fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8)); |
500 | } | |
501 | ||
5bfb9ad0 | 502 | static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
503 | { |
504 | u16 *start; | |
505 | int i; | |
506 | ||
93193c2b KM |
507 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
508 | ||
b9fde18c | 509 | |
5bfb9ad0 | 510 | for (i = 0; i < num; i++) |
b9fde18c KM |
511 | *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); |
512 | } | |
513 | ||
5bfb9ad0 | 514 | static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
515 | { |
516 | u32 *start; | |
517 | int i; | |
518 | ||
93193c2b KM |
519 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
520 | ||
b9fde18c | 521 | |
5bfb9ad0 | 522 | for (i = 0; i < num; i++) |
b9fde18c KM |
523 | fsi_reg_write(fsi, DODT, *(start + i)); |
524 | } | |
525 | ||
5bfb9ad0 | 526 | static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
527 | { |
528 | u32 *start; | |
529 | int i; | |
530 | ||
93193c2b | 531 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
b9fde18c | 532 | |
5bfb9ad0 | 533 | for (i = 0; i < num; i++) |
b9fde18c KM |
534 | *(start + i) = fsi_reg_read(fsi, DIDT); |
535 | } | |
536 | ||
c8fe2574 KM |
537 | /* |
538 | * irq function | |
539 | */ | |
a4d7d550 | 540 | |
a4d7d550 KM |
541 | static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) |
542 | { | |
cf6edd00 | 543 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 544 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 545 | |
43fa95ca KM |
546 | fsi_core_mask_set(master, imsk, data, data); |
547 | fsi_core_mask_set(master, iemsk, data, data); | |
a4d7d550 KM |
548 | } |
549 | ||
550 | static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | |
551 | { | |
cf6edd00 | 552 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 553 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 554 | |
43fa95ca KM |
555 | fsi_core_mask_set(master, imsk, data, 0); |
556 | fsi_core_mask_set(master, iemsk, data, 0); | |
a4d7d550 KM |
557 | } |
558 | ||
10ea76cc KM |
559 | static u32 fsi_irq_get_status(struct fsi_master *master) |
560 | { | |
43fa95ca | 561 | return fsi_core_read(master, int_st); |
10ea76cc KM |
562 | } |
563 | ||
10ea76cc KM |
564 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
565 | { | |
566 | u32 data = 0; | |
567 | struct fsi_master *master = fsi_get_master(fsi); | |
568 | ||
cf6edd00 KM |
569 | data |= AB_IO(1, fsi_get_port_shift(fsi, 0)); |
570 | data |= AB_IO(1, fsi_get_port_shift(fsi, 1)); | |
10ea76cc KM |
571 | |
572 | /* clear interrupt factor */ | |
43fa95ca | 573 | fsi_core_mask_set(master, int_st, data, 0); |
10ea76cc KM |
574 | } |
575 | ||
c8fe2574 KM |
576 | /* |
577 | * SPDIF master clock function | |
578 | * | |
579 | * These functions are used later FSI2 | |
580 | */ | |
3bc28070 KM |
581 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
582 | { | |
583 | struct fsi_master *master = fsi_get_master(fsi); | |
2b0e7302 | 584 | u32 mask, val; |
3bc28070 KM |
585 | |
586 | if (master->core->ver < 2) { | |
587 | pr_err("fsi: register access err (%s)\n", __func__); | |
588 | return; | |
589 | } | |
590 | ||
2b0e7302 KM |
591 | mask = BP | SE; |
592 | val = enable ? mask : 0; | |
593 | ||
594 | fsi_is_port_a(fsi) ? | |
43fa95ca KM |
595 | fsi_core_mask_set(master, a_mclk, mask, val) : |
596 | fsi_core_mask_set(master, b_mclk, mask, val); | |
3bc28070 KM |
597 | } |
598 | ||
c8fe2574 | 599 | /* |
1f5e2a31 | 600 | * clock function |
c8fe2574 | 601 | */ |
4f56cde1 KM |
602 | static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi, |
603 | long rate, int enable) | |
604 | { | |
605 | struct fsi_master *master = fsi_get_master(fsi); | |
606 | set_rate_func set_rate = fsi_get_info_set_rate(master); | |
607 | int fsi_ver = master->core->ver; | |
608 | int ret; | |
609 | ||
610 | ret = set_rate(dev, fsi_is_port_a(fsi), rate, enable); | |
611 | if (ret < 0) /* error */ | |
612 | return ret; | |
613 | ||
614 | if (!enable) | |
615 | return 0; | |
616 | ||
617 | if (ret > 0) { | |
618 | u32 data = 0; | |
619 | ||
620 | switch (ret & SH_FSI_ACKMD_MASK) { | |
621 | default: | |
622 | /* FALL THROUGH */ | |
623 | case SH_FSI_ACKMD_512: | |
624 | data |= (0x0 << 12); | |
625 | break; | |
626 | case SH_FSI_ACKMD_256: | |
627 | data |= (0x1 << 12); | |
628 | break; | |
629 | case SH_FSI_ACKMD_128: | |
630 | data |= (0x2 << 12); | |
631 | break; | |
632 | case SH_FSI_ACKMD_64: | |
633 | data |= (0x3 << 12); | |
634 | break; | |
635 | case SH_FSI_ACKMD_32: | |
636 | if (fsi_ver < 2) | |
637 | dev_err(dev, "unsupported ACKMD\n"); | |
638 | else | |
639 | data |= (0x4 << 12); | |
640 | break; | |
641 | } | |
642 | ||
643 | switch (ret & SH_FSI_BPFMD_MASK) { | |
644 | default: | |
645 | /* FALL THROUGH */ | |
646 | case SH_FSI_BPFMD_32: | |
647 | data |= (0x0 << 8); | |
648 | break; | |
649 | case SH_FSI_BPFMD_64: | |
650 | data |= (0x1 << 8); | |
651 | break; | |
652 | case SH_FSI_BPFMD_128: | |
653 | data |= (0x2 << 8); | |
654 | break; | |
655 | case SH_FSI_BPFMD_256: | |
656 | data |= (0x3 << 8); | |
657 | break; | |
658 | case SH_FSI_BPFMD_512: | |
659 | data |= (0x4 << 8); | |
660 | break; | |
661 | case SH_FSI_BPFMD_16: | |
662 | if (fsi_ver < 2) | |
663 | dev_err(dev, "unsupported ACKMD\n"); | |
664 | else | |
665 | data |= (0x7 << 8); | |
666 | break; | |
667 | } | |
668 | ||
669 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
670 | udelay(10); | |
671 | ret = 0; | |
672 | } | |
673 | ||
674 | return ret; | |
4f56cde1 KM |
675 | } |
676 | ||
1ddddd36 KM |
677 | #define fsi_port_start(f, i) __fsi_port_clk_ctrl(f, i, 1) |
678 | #define fsi_port_stop(f, i) __fsi_port_clk_ctrl(f, i, 0) | |
679 | static void __fsi_port_clk_ctrl(struct fsi_priv *fsi, int is_play, int enable) | |
a4d7d550 | 680 | { |
71f6e064 | 681 | struct fsi_master *master = fsi_get_master(fsi); |
1f5e2a31 | 682 | u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; |
a4d7d550 | 683 | |
1ddddd36 KM |
684 | if (enable) |
685 | fsi_irq_enable(fsi, is_play); | |
686 | else | |
687 | fsi_irq_disable(fsi, is_play); | |
688 | ||
cda828ca | 689 | if (fsi_is_clk_master(fsi)) |
1f5e2a31 | 690 | fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); |
a4d7d550 KM |
691 | } |
692 | ||
1f5e2a31 KM |
693 | /* |
694 | * ctrl function | |
695 | */ | |
4a942b45 KM |
696 | static void fsi_fifo_init(struct fsi_priv *fsi, |
697 | int is_play, | |
23ca8533 | 698 | struct device *dev) |
a4d7d550 | 699 | { |
4a942b45 | 700 | struct fsi_master *master = fsi_get_master(fsi); |
93193c2b | 701 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
e8c8b631 | 702 | u32 shift, i; |
2e651baf | 703 | int frame_capa; |
a4d7d550 | 704 | |
4a942b45 KM |
705 | /* get on-chip RAM capacity */ |
706 | shift = fsi_master_read(master, FIFO_SZ); | |
cf6edd00 KM |
707 | shift >>= fsi_get_port_shift(fsi, is_play); |
708 | shift &= FIFO_SZ_MASK; | |
2e651baf | 709 | frame_capa = 256 << shift; |
23ca8533 | 710 | dev_dbg(dev, "fifo = %d words\n", frame_capa); |
a4d7d550 | 711 | |
4a942b45 KM |
712 | /* |
713 | * The maximum number of sample data varies depending | |
714 | * on the number of channels selected for the format. | |
715 | * | |
716 | * FIFOs are used in 4-channel units in 3-channel mode | |
717 | * and in 8-channel units in 5- to 7-channel mode | |
718 | * meaning that more FIFOs than the required size of DPRAM | |
719 | * are used. | |
720 | * | |
721 | * ex) if 256 words of DP-RAM is connected | |
722 | * 1 channel: 256 (256 x 1 = 256) | |
723 | * 2 channels: 128 (128 x 2 = 256) | |
724 | * 3 channels: 64 ( 64 x 3 = 192) | |
725 | * 4 channels: 64 ( 64 x 4 = 256) | |
726 | * 5 channels: 32 ( 32 x 5 = 160) | |
727 | * 6 channels: 32 ( 32 x 6 = 192) | |
728 | * 7 channels: 32 ( 32 x 7 = 224) | |
729 | * 8 channels: 32 ( 32 x 8 = 256) | |
730 | */ | |
160afa7f | 731 | for (i = 1; i < fsi->chan_num; i <<= 1) |
2e651baf | 732 | frame_capa >>= 1; |
23ca8533 | 733 | dev_dbg(dev, "%d channel %d store\n", |
2e651baf KM |
734 | fsi->chan_num, frame_capa); |
735 | ||
736 | io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); | |
a4d7d550 | 737 | |
e8c8b631 KM |
738 | /* |
739 | * set interrupt generation factor | |
740 | * clear FIFO | |
741 | */ | |
742 | if (is_play) { | |
743 | fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); | |
744 | fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); | |
745 | } else { | |
746 | fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); | |
747 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
748 | } | |
a4d7d550 KM |
749 | } |
750 | ||
1ec9bc35 | 751 | static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream) |
a4d7d550 KM |
752 | { |
753 | struct snd_pcm_runtime *runtime; | |
754 | struct snd_pcm_substream *substream = NULL; | |
93193c2b KM |
755 | int is_play = fsi_stream_is_play(stream); |
756 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
2e651baf | 757 | int sample_residues; |
2e651baf KM |
758 | int samples; |
759 | int samples_max; | |
b9fde18c | 760 | int over_period; |
d8b33534 | 761 | void (*fn)(struct fsi_priv *fsi, int size); |
a4d7d550 KM |
762 | |
763 | if (!fsi || | |
93193c2b KM |
764 | !io->substream || |
765 | !io->substream->runtime) | |
a4d7d550 KM |
766 | return -EINVAL; |
767 | ||
1c418d1f | 768 | over_period = 0; |
93193c2b | 769 | substream = io->substream; |
1c418d1f | 770 | runtime = substream->runtime; |
a4d7d550 KM |
771 | |
772 | /* FSI FIFO has limit. | |
773 | * So, this driver can not send periods data at a time | |
774 | */ | |
2e651baf KM |
775 | if (io->buff_sample_pos >= |
776 | io->period_samples * (io->period_pos + 1)) { | |
a4d7d550 | 777 | |
1c418d1f | 778 | over_period = 1; |
2e651baf | 779 | io->period_pos = (io->period_pos + 1) % runtime->periods; |
a4d7d550 | 780 | |
2e651baf KM |
781 | if (0 == io->period_pos) |
782 | io->buff_sample_pos = 0; | |
a4d7d550 KM |
783 | } |
784 | ||
2e651baf KM |
785 | /* get number of residue samples */ |
786 | sample_residues = io->buff_sample_capa - io->buff_sample_pos; | |
d8b33534 KM |
787 | |
788 | if (is_play) { | |
789 | /* | |
790 | * for play-back | |
791 | * | |
2e651baf KM |
792 | * samples_max : number of FSI fifo free samples space |
793 | * samples : number of ALSA residue samples | |
d8b33534 | 794 | */ |
2e651baf KM |
795 | samples_max = io->fifo_sample_capa; |
796 | samples_max -= fsi_get_current_fifo_samples(fsi, is_play); | |
d8b33534 | 797 | |
2e651baf | 798 | samples = sample_residues; |
d8b33534 | 799 | |
c1e6f10e | 800 | switch (io->sample_width) { |
d8b33534 KM |
801 | case 2: |
802 | fn = fsi_dma_soft_push16; | |
803 | break; | |
804 | case 4: | |
805 | fn = fsi_dma_soft_push32; | |
806 | break; | |
807 | default: | |
808 | return -EINVAL; | |
809 | } | |
810 | } else { | |
811 | /* | |
812 | * for capture | |
813 | * | |
2e651baf KM |
814 | * samples_max : number of ALSA free samples space |
815 | * samples : number of samples in FSI fifo | |
d8b33534 | 816 | */ |
2e651baf KM |
817 | samples_max = sample_residues; |
818 | samples = fsi_get_current_fifo_samples(fsi, is_play); | |
d8b33534 | 819 | |
c1e6f10e | 820 | switch (io->sample_width) { |
d8b33534 KM |
821 | case 2: |
822 | fn = fsi_dma_soft_pop16; | |
823 | break; | |
824 | case 4: | |
825 | fn = fsi_dma_soft_pop32; | |
826 | break; | |
827 | default: | |
828 | return -EINVAL; | |
829 | } | |
830 | } | |
a4d7d550 | 831 | |
2e651baf | 832 | samples = min(samples, samples_max); |
a4d7d550 | 833 | |
2e651baf | 834 | fn(fsi, samples); |
a4d7d550 | 835 | |
2e651baf KM |
836 | /* update buff_sample_pos */ |
837 | io->buff_sample_pos += samples; | |
a4d7d550 | 838 | |
1c418d1f | 839 | if (over_period) |
a4d7d550 KM |
840 | snd_pcm_period_elapsed(substream); |
841 | ||
47fc9a0a | 842 | return 0; |
a4d7d550 KM |
843 | } |
844 | ||
1ec9bc35 | 845 | static int fsi_data_pop(struct fsi_priv *fsi) |
07102f3c | 846 | { |
1ec9bc35 | 847 | return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE); |
d8b33534 | 848 | } |
07102f3c | 849 | |
1ec9bc35 | 850 | static int fsi_data_push(struct fsi_priv *fsi) |
d8b33534 | 851 | { |
1ec9bc35 | 852 | return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
07102f3c KM |
853 | } |
854 | ||
a4d7d550 KM |
855 | static irqreturn_t fsi_interrupt(int irq, void *data) |
856 | { | |
71f6e064 | 857 | struct fsi_master *master = data; |
10ea76cc | 858 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
859 | |
860 | /* clear irq status */ | |
feb58cff KM |
861 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
862 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 | 863 | |
cf6edd00 | 864 | if (int_st & AB_IO(1, AO_SHIFT)) |
1ec9bc35 | 865 | fsi_data_push(&master->fsia); |
cf6edd00 | 866 | if (int_st & AB_IO(1, BO_SHIFT)) |
1ec9bc35 | 867 | fsi_data_push(&master->fsib); |
cf6edd00 | 868 | if (int_st & AB_IO(1, AI_SHIFT)) |
1ec9bc35 | 869 | fsi_data_pop(&master->fsia); |
cf6edd00 | 870 | if (int_st & AB_IO(1, BI_SHIFT)) |
1ec9bc35 KM |
871 | fsi_data_pop(&master->fsib); |
872 | ||
873 | fsi_count_fifo_err(&master->fsia); | |
874 | fsi_count_fifo_err(&master->fsib); | |
a4d7d550 | 875 | |
48d78e58 KM |
876 | fsi_irq_clear_status(&master->fsia); |
877 | fsi_irq_clear_status(&master->fsib); | |
a4d7d550 KM |
878 | |
879 | return IRQ_HANDLED; | |
880 | } | |
881 | ||
c8fe2574 KM |
882 | /* |
883 | * dai ops | |
884 | */ | |
a4d7d550 | 885 | |
23ca8533 KM |
886 | static int fsi_hw_startup(struct fsi_priv *fsi, |
887 | int is_play, | |
888 | struct device *dev) | |
a4d7d550 | 889 | { |
65ff03f4 KM |
890 | struct fsi_master *master = fsi_get_master(fsi); |
891 | int fsi_ver = master->core->ver; | |
93193c2b | 892 | u32 flags = fsi_get_info_flags(fsi); |
9478e0b6 | 893 | u32 data = 0; |
a4d7d550 | 894 | |
9478e0b6 KM |
895 | /* clock setting */ |
896 | if (fsi_is_clk_master(fsi)) | |
897 | data = DIMD | DOMD; | |
898 | ||
899 | fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); | |
a4d7d550 KM |
900 | |
901 | /* clock inversion (CKG2) */ | |
902 | data = 0; | |
b427b44c KM |
903 | if (SH_FSI_LRM_INV & flags) |
904 | data |= 1 << 12; | |
905 | if (SH_FSI_BRM_INV & flags) | |
906 | data |= 1 << 8; | |
907 | if (SH_FSI_LRS_INV & flags) | |
908 | data |= 1 << 4; | |
909 | if (SH_FSI_BRS_INV & flags) | |
910 | data |= 1 << 0; | |
911 | ||
a4d7d550 KM |
912 | fsi_reg_write(fsi, CKG2, data); |
913 | ||
9478e0b6 KM |
914 | /* set format */ |
915 | fsi_reg_write(fsi, DO_FMT, fsi->do_fmt); | |
916 | fsi_reg_write(fsi, DI_FMT, fsi->di_fmt); | |
917 | ||
918 | /* spdif ? */ | |
919 | if (fsi_is_spdif(fsi)) { | |
920 | fsi_spdif_clk_ctrl(fsi, 1); | |
921 | fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); | |
922 | } | |
923 | ||
65ff03f4 KM |
924 | /* |
925 | * FIXME | |
926 | * | |
927 | * FSI driver assumed that data package is in-back. | |
928 | * FSI2 chip can select it. | |
929 | */ | |
930 | if (fsi_ver >= 2) { | |
931 | fsi_reg_write(fsi, OUT_DMAC, (1 << 4)); | |
932 | fsi_reg_write(fsi, IN_DMAC, (1 << 4)); | |
933 | } | |
934 | ||
10ea76cc KM |
935 | /* irq clear */ |
936 | fsi_irq_disable(fsi, is_play); | |
937 | fsi_irq_clear_status(fsi); | |
938 | ||
939 | /* fifo init */ | |
23ca8533 | 940 | fsi_fifo_init(fsi, is_play, dev); |
a4d7d550 | 941 | |
a68a3b4e | 942 | return 0; |
a4d7d550 KM |
943 | } |
944 | ||
23ca8533 KM |
945 | static void fsi_hw_shutdown(struct fsi_priv *fsi, |
946 | int is_play, | |
947 | struct device *dev) | |
948 | { | |
949 | if (fsi_is_clk_master(fsi)) | |
950 | fsi_set_master_clk(dev, fsi, fsi->rate, 0); | |
23ca8533 KM |
951 | } |
952 | ||
953 | static int fsi_dai_startup(struct snd_pcm_substream *substream, | |
954 | struct snd_soc_dai *dai) | |
955 | { | |
956 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
957 | int is_play = fsi_is_play(substream); | |
958 | ||
959 | return fsi_hw_startup(fsi, is_play, dai->dev); | |
960 | } | |
961 | ||
a4d7d550 KM |
962 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, |
963 | struct snd_soc_dai *dai) | |
964 | { | |
71f6e064 | 965 | struct fsi_priv *fsi = fsi_get_priv(substream); |
23ca8533 | 966 | int is_play = fsi_is_play(substream); |
a4d7d550 | 967 | |
23ca8533 | 968 | fsi_hw_shutdown(fsi, is_play, dai->dev); |
d4bc99b9 | 969 | fsi->rate = 0; |
a4d7d550 KM |
970 | } |
971 | ||
972 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
973 | struct snd_soc_dai *dai) | |
974 | { | |
71f6e064 | 975 | struct fsi_priv *fsi = fsi_get_priv(substream); |
00545785 | 976 | int is_play = fsi_is_play(substream); |
a4d7d550 KM |
977 | int ret = 0; |
978 | ||
a4d7d550 KM |
979 | switch (cmd) { |
980 | case SNDRV_PCM_TRIGGER_START: | |
0ffe296a | 981 | fsi_stream_push(fsi, is_play, substream); |
1ec9bc35 | 982 | ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi); |
1ddddd36 | 983 | fsi_port_start(fsi, is_play); |
a4d7d550 KM |
984 | break; |
985 | case SNDRV_PCM_TRIGGER_STOP: | |
1ddddd36 | 986 | fsi_port_stop(fsi, is_play); |
93193c2b | 987 | fsi_stream_pop(fsi, is_play); |
a4d7d550 KM |
988 | break; |
989 | } | |
990 | ||
991 | return ret; | |
992 | } | |
993 | ||
f17c13ca KM |
994 | static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) |
995 | { | |
996 | u32 data = 0; | |
997 | ||
998 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
999 | case SND_SOC_DAIFMT_I2S: | |
1000 | data = CR_I2S; | |
1001 | fsi->chan_num = 2; | |
1002 | break; | |
1003 | case SND_SOC_DAIFMT_LEFT_J: | |
1004 | data = CR_PCM; | |
1005 | fsi->chan_num = 2; | |
1006 | break; | |
1007 | default: | |
1008 | return -EINVAL; | |
1009 | } | |
1010 | ||
9478e0b6 KM |
1011 | fsi->do_fmt = data; |
1012 | fsi->di_fmt = data; | |
f17c13ca KM |
1013 | |
1014 | return 0; | |
1015 | } | |
1016 | ||
1017 | static int fsi_set_fmt_spdif(struct fsi_priv *fsi) | |
1018 | { | |
1019 | struct fsi_master *master = fsi_get_master(fsi); | |
1020 | u32 data = 0; | |
1021 | ||
1022 | if (master->core->ver < 2) | |
1023 | return -EINVAL; | |
1024 | ||
1025 | data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM; | |
1026 | fsi->chan_num = 2; | |
9478e0b6 | 1027 | fsi->spdif = 1; |
f17c13ca | 1028 | |
9478e0b6 KM |
1029 | fsi->do_fmt = data; |
1030 | fsi->di_fmt = data; | |
f17c13ca KM |
1031 | |
1032 | return 0; | |
1033 | } | |
1034 | ||
4d805f7b KM |
1035 | static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
1036 | { | |
1037 | struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); | |
6a9ebad8 KM |
1038 | struct fsi_master *master = fsi_get_master(fsi); |
1039 | set_rate_func set_rate = fsi_get_info_set_rate(master); | |
f17c13ca | 1040 | u32 flags = fsi_get_info_flags(fsi); |
4d805f7b KM |
1041 | int ret; |
1042 | ||
4d805f7b KM |
1043 | /* set master/slave audio interface */ |
1044 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1045 | case SND_SOC_DAIFMT_CBM_CFM: | |
6a9ebad8 | 1046 | fsi->clk_master = 1; |
4d805f7b KM |
1047 | break; |
1048 | case SND_SOC_DAIFMT_CBS_CFS: | |
1049 | break; | |
1050 | default: | |
9478e0b6 | 1051 | return -EINVAL; |
4d805f7b | 1052 | } |
6a9ebad8 KM |
1053 | |
1054 | if (fsi_is_clk_master(fsi) && !set_rate) { | |
1055 | dev_err(dai->dev, "platform doesn't have set_rate\n"); | |
9478e0b6 | 1056 | return -EINVAL; |
6a9ebad8 KM |
1057 | } |
1058 | ||
f17c13ca KM |
1059 | /* set format */ |
1060 | switch (flags & SH_FSI_FMT_MASK) { | |
1061 | case SH_FSI_FMT_DAI: | |
1062 | ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); | |
1063 | break; | |
1064 | case SH_FSI_FMT_SPDIF: | |
1065 | ret = fsi_set_fmt_spdif(fsi); | |
1066 | break; | |
1067 | default: | |
1068 | ret = -EINVAL; | |
1069 | } | |
4d805f7b | 1070 | |
4d805f7b KM |
1071 | return ret; |
1072 | } | |
1073 | ||
ccad7b44 KM |
1074 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
1075 | struct snd_pcm_hw_params *params, | |
1076 | struct snd_soc_dai *dai) | |
1077 | { | |
1078 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
d4bc99b9 | 1079 | long rate = params_rate(params); |
ccad7b44 KM |
1080 | int ret; |
1081 | ||
6a9ebad8 | 1082 | if (!fsi_is_clk_master(fsi)) |
ccad7b44 KM |
1083 | return 0; |
1084 | ||
4f56cde1 KM |
1085 | ret = fsi_set_master_clk(dai->dev, fsi, rate, 1); |
1086 | if (ret < 0) | |
d4bc99b9 | 1087 | return ret; |
ccad7b44 | 1088 | |
d4bc99b9 | 1089 | fsi->rate = rate; |
ccad7b44 KM |
1090 | |
1091 | return ret; | |
ccad7b44 KM |
1092 | } |
1093 | ||
85e7652d | 1094 | static const struct snd_soc_dai_ops fsi_dai_ops = { |
a4d7d550 KM |
1095 | .startup = fsi_dai_startup, |
1096 | .shutdown = fsi_dai_shutdown, | |
1097 | .trigger = fsi_dai_trigger, | |
4d805f7b | 1098 | .set_fmt = fsi_dai_set_fmt, |
ccad7b44 | 1099 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
1100 | }; |
1101 | ||
c8fe2574 KM |
1102 | /* |
1103 | * pcm ops | |
1104 | */ | |
a4d7d550 | 1105 | |
a4d7d550 KM |
1106 | static struct snd_pcm_hardware fsi_pcm_hardware = { |
1107 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
1108 | SNDRV_PCM_INFO_MMAP | | |
1109 | SNDRV_PCM_INFO_MMAP_VALID | | |
1110 | SNDRV_PCM_INFO_PAUSE, | |
1111 | .formats = FSI_FMTS, | |
1112 | .rates = FSI_RATES, | |
1113 | .rate_min = 8000, | |
1114 | .rate_max = 192000, | |
1115 | .channels_min = 1, | |
1116 | .channels_max = 2, | |
1117 | .buffer_bytes_max = 64 * 1024, | |
1118 | .period_bytes_min = 32, | |
1119 | .period_bytes_max = 8192, | |
1120 | .periods_min = 1, | |
1121 | .periods_max = 32, | |
1122 | .fifo_size = 256, | |
1123 | }; | |
1124 | ||
1125 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
1126 | { | |
1127 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1128 | int ret = 0; | |
1129 | ||
1130 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
1131 | ||
1132 | ret = snd_pcm_hw_constraint_integer(runtime, | |
1133 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1134 | ||
1135 | return ret; | |
1136 | } | |
1137 | ||
1138 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
1139 | struct snd_pcm_hw_params *hw_params) | |
1140 | { | |
1141 | return snd_pcm_lib_malloc_pages(substream, | |
1142 | params_buffer_bytes(hw_params)); | |
1143 | } | |
1144 | ||
1145 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
1146 | { | |
1147 | return snd_pcm_lib_free_pages(substream); | |
1148 | } | |
1149 | ||
1150 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
1151 | { | |
71f6e064 | 1152 | struct fsi_priv *fsi = fsi_get_priv(substream); |
93193c2b | 1153 | struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream)); |
2e651baf | 1154 | int samples_pos = io->buff_sample_pos - 1; |
a4d7d550 | 1155 | |
2e651baf KM |
1156 | if (samples_pos < 0) |
1157 | samples_pos = 0; | |
a4d7d550 | 1158 | |
2e651baf | 1159 | return fsi_sample2frame(fsi, samples_pos); |
a4d7d550 KM |
1160 | } |
1161 | ||
1162 | static struct snd_pcm_ops fsi_pcm_ops = { | |
1163 | .open = fsi_pcm_open, | |
1164 | .ioctl = snd_pcm_lib_ioctl, | |
1165 | .hw_params = fsi_hw_params, | |
1166 | .hw_free = fsi_hw_free, | |
1167 | .pointer = fsi_pointer, | |
1168 | }; | |
1169 | ||
c8fe2574 KM |
1170 | /* |
1171 | * snd_soc_platform | |
1172 | */ | |
a4d7d550 | 1173 | |
a4d7d550 KM |
1174 | #define PREALLOC_BUFFER (32 * 1024) |
1175 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1176 | ||
1177 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1178 | { | |
1179 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1180 | } | |
1181 | ||
552d1ef6 | 1182 | static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd) |
a4d7d550 | 1183 | { |
552d1ef6 LG |
1184 | struct snd_pcm *pcm = rtd->pcm; |
1185 | ||
a4d7d550 KM |
1186 | /* |
1187 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1188 | * in MMAP mode (i.e. aplay -M) | |
1189 | */ | |
1190 | return snd_pcm_lib_preallocate_pages_for_all( | |
1191 | pcm, | |
1192 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1193 | snd_dma_continuous_data(GFP_KERNEL), | |
1194 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1195 | } | |
1196 | ||
c8fe2574 KM |
1197 | /* |
1198 | * alsa struct | |
1199 | */ | |
a4d7d550 | 1200 | |
f0fba2ad | 1201 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1202 | { |
f0fba2ad | 1203 | .name = "fsia-dai", |
a4d7d550 KM |
1204 | .playback = { |
1205 | .rates = FSI_RATES, | |
1206 | .formats = FSI_FMTS, | |
1207 | .channels_min = 1, | |
1208 | .channels_max = 8, | |
1209 | }, | |
07102f3c KM |
1210 | .capture = { |
1211 | .rates = FSI_RATES, | |
1212 | .formats = FSI_FMTS, | |
1213 | .channels_min = 1, | |
1214 | .channels_max = 8, | |
1215 | }, | |
a4d7d550 KM |
1216 | .ops = &fsi_dai_ops, |
1217 | }, | |
1218 | { | |
f0fba2ad | 1219 | .name = "fsib-dai", |
a4d7d550 KM |
1220 | .playback = { |
1221 | .rates = FSI_RATES, | |
1222 | .formats = FSI_FMTS, | |
1223 | .channels_min = 1, | |
1224 | .channels_max = 8, | |
1225 | }, | |
07102f3c KM |
1226 | .capture = { |
1227 | .rates = FSI_RATES, | |
1228 | .formats = FSI_FMTS, | |
1229 | .channels_min = 1, | |
1230 | .channels_max = 8, | |
1231 | }, | |
a4d7d550 KM |
1232 | .ops = &fsi_dai_ops, |
1233 | }, | |
1234 | }; | |
a4d7d550 | 1235 | |
f0fba2ad LG |
1236 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1237 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1238 | .pcm_new = fsi_pcm_new, |
1239 | .pcm_free = fsi_pcm_free, | |
1240 | }; | |
a4d7d550 | 1241 | |
c8fe2574 KM |
1242 | /* |
1243 | * platform function | |
1244 | */ | |
a4d7d550 | 1245 | |
a4d7d550 KM |
1246 | static int fsi_probe(struct platform_device *pdev) |
1247 | { | |
71f6e064 | 1248 | struct fsi_master *master; |
cc780d38 | 1249 | const struct platform_device_id *id_entry; |
a4d7d550 | 1250 | struct resource *res; |
a4d7d550 KM |
1251 | unsigned int irq; |
1252 | int ret; | |
1253 | ||
cc780d38 KM |
1254 | id_entry = pdev->id_entry; |
1255 | if (!id_entry) { | |
1256 | dev_err(&pdev->dev, "unknown fsi device\n"); | |
1257 | return -ENODEV; | |
1258 | } | |
1259 | ||
a4d7d550 KM |
1260 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1261 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 1262 | if (!res || (int)irq <= 0) { |
a4d7d550 KM |
1263 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
1264 | ret = -ENODEV; | |
1265 | goto exit; | |
1266 | } | |
1267 | ||
1268 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
1269 | if (!master) { | |
1270 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
1271 | ret = -ENOMEM; | |
1272 | goto exit; | |
1273 | } | |
1274 | ||
1275 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
1276 | if (!master->base) { | |
1277 | ret = -ENXIO; | |
1278 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
1279 | goto exit_kfree; | |
1280 | } | |
1281 | ||
3bc28070 | 1282 | /* master setting */ |
a4d7d550 KM |
1283 | master->irq = irq; |
1284 | master->info = pdev->dev.platform_data; | |
3bc28070 KM |
1285 | master->core = (struct fsi_core *)id_entry->driver_data; |
1286 | spin_lock_init(&master->lock); | |
1287 | ||
1288 | /* FSI A setting */ | |
a4d7d550 | 1289 | master->fsia.base = master->base; |
71f6e064 | 1290 | master->fsia.master = master; |
3bc28070 KM |
1291 | |
1292 | /* FSI B setting */ | |
a4d7d550 | 1293 | master->fsib.base = master->base + 0x40; |
71f6e064 | 1294 | master->fsib.master = master; |
a4d7d550 | 1295 | |
785d1c45 | 1296 | pm_runtime_enable(&pdev->dev); |
f0fba2ad | 1297 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 1298 | |
88e24c3a | 1299 | ret = request_irq(irq, &fsi_interrupt, 0, |
cc780d38 | 1300 | id_entry->name, master); |
a4d7d550 KM |
1301 | if (ret) { |
1302 | dev_err(&pdev->dev, "irq request err\n"); | |
9ddc9aa9 | 1303 | goto exit_iounmap; |
a4d7d550 KM |
1304 | } |
1305 | ||
f0fba2ad | 1306 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
1307 | if (ret < 0) { |
1308 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1309 | goto exit_free_irq; | |
1310 | } | |
1311 | ||
0b5ec87d KM |
1312 | ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai, |
1313 | ARRAY_SIZE(fsi_soc_dai)); | |
1314 | if (ret < 0) { | |
1315 | dev_err(&pdev->dev, "cannot snd dai register\n"); | |
1316 | goto exit_snd_soc; | |
1317 | } | |
a4d7d550 | 1318 | |
0b5ec87d KM |
1319 | return ret; |
1320 | ||
1321 | exit_snd_soc: | |
1322 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 KM |
1323 | exit_free_irq: |
1324 | free_irq(irq, master); | |
a4d7d550 KM |
1325 | exit_iounmap: |
1326 | iounmap(master->base); | |
785d1c45 | 1327 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
1328 | exit_kfree: |
1329 | kfree(master); | |
1330 | master = NULL; | |
1331 | exit: | |
1332 | return ret; | |
1333 | } | |
1334 | ||
1335 | static int fsi_remove(struct platform_device *pdev) | |
1336 | { | |
71f6e064 KM |
1337 | struct fsi_master *master; |
1338 | ||
f0fba2ad | 1339 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 1340 | |
d985f27e | 1341 | free_irq(master->irq, master); |
785d1c45 | 1342 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 1343 | |
d985f27e KM |
1344 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); |
1345 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 KM |
1346 | |
1347 | iounmap(master->base); | |
1348 | kfree(master); | |
71f6e064 | 1349 | |
a4d7d550 KM |
1350 | return 0; |
1351 | } | |
1352 | ||
106c79ec | 1353 | static void __fsi_suspend(struct fsi_priv *fsi, |
cda828ca | 1354 | int is_play, |
4f56cde1 | 1355 | struct device *dev) |
106c79ec | 1356 | { |
cda828ca KM |
1357 | if (!fsi_stream_is_working(fsi, is_play)) |
1358 | return; | |
106c79ec | 1359 | |
cda828ca KM |
1360 | fsi_port_stop(fsi, is_play); |
1361 | fsi_hw_shutdown(fsi, is_play, dev); | |
106c79ec KM |
1362 | } |
1363 | ||
1364 | static void __fsi_resume(struct fsi_priv *fsi, | |
cda828ca | 1365 | int is_play, |
4f56cde1 | 1366 | struct device *dev) |
106c79ec | 1367 | { |
cda828ca KM |
1368 | if (!fsi_stream_is_working(fsi, is_play)) |
1369 | return; | |
106c79ec | 1370 | |
cda828ca KM |
1371 | fsi_hw_startup(fsi, is_play, dev); |
1372 | ||
1373 | if (fsi_is_clk_master(fsi) && fsi->rate) | |
4f56cde1 | 1374 | fsi_set_master_clk(dev, fsi, fsi->rate, 1); |
cda828ca KM |
1375 | |
1376 | fsi_port_start(fsi, is_play); | |
1377 | ||
106c79ec KM |
1378 | } |
1379 | ||
1380 | static int fsi_suspend(struct device *dev) | |
1381 | { | |
1382 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
1383 | struct fsi_priv *fsia = &master->fsia; |
1384 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 1385 | |
cda828ca KM |
1386 | __fsi_suspend(fsia, 1, dev); |
1387 | __fsi_suspend(fsia, 0, dev); | |
106c79ec | 1388 | |
cda828ca KM |
1389 | __fsi_suspend(fsib, 1, dev); |
1390 | __fsi_suspend(fsib, 0, dev); | |
106c79ec KM |
1391 | |
1392 | return 0; | |
1393 | } | |
1394 | ||
1395 | static int fsi_resume(struct device *dev) | |
1396 | { | |
1397 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
1398 | struct fsi_priv *fsia = &master->fsia; |
1399 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 1400 | |
cda828ca KM |
1401 | __fsi_resume(fsia, 1, dev); |
1402 | __fsi_resume(fsia, 0, dev); | |
106c79ec | 1403 | |
cda828ca KM |
1404 | __fsi_resume(fsib, 1, dev); |
1405 | __fsi_resume(fsib, 0, dev); | |
106c79ec KM |
1406 | |
1407 | return 0; | |
1408 | } | |
1409 | ||
785d1c45 | 1410 | static struct dev_pm_ops fsi_pm_ops = { |
106c79ec KM |
1411 | .suspend = fsi_suspend, |
1412 | .resume = fsi_resume, | |
785d1c45 KM |
1413 | }; |
1414 | ||
73b92c1f KM |
1415 | static struct fsi_core fsi1_core = { |
1416 | .ver = 1, | |
1417 | ||
1418 | /* Interrupt */ | |
cc780d38 KM |
1419 | .int_st = INT_ST, |
1420 | .iemsk = IEMSK, | |
1421 | .imsk = IMSK, | |
1422 | }; | |
1423 | ||
73b92c1f KM |
1424 | static struct fsi_core fsi2_core = { |
1425 | .ver = 2, | |
1426 | ||
1427 | /* Interrupt */ | |
cc780d38 KM |
1428 | .int_st = CPU_INT_ST, |
1429 | .iemsk = CPU_IEMSK, | |
1430 | .imsk = CPU_IMSK, | |
2b0e7302 KM |
1431 | .a_mclk = A_MST_CTLR, |
1432 | .b_mclk = B_MST_CTLR, | |
cc780d38 KM |
1433 | }; |
1434 | ||
1435 | static struct platform_device_id fsi_id_table[] = { | |
73b92c1f KM |
1436 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
1437 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
05c69450 | 1438 | {}, |
cc780d38 | 1439 | }; |
d85a6d7b | 1440 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 1441 | |
a4d7d550 KM |
1442 | static struct platform_driver fsi_driver = { |
1443 | .driver = { | |
f0fba2ad | 1444 | .name = "fsi-pcm-audio", |
785d1c45 | 1445 | .pm = &fsi_pm_ops, |
a4d7d550 KM |
1446 | }, |
1447 | .probe = fsi_probe, | |
1448 | .remove = fsi_remove, | |
cc780d38 | 1449 | .id_table = fsi_id_table, |
a4d7d550 KM |
1450 | }; |
1451 | ||
cb5e8738 | 1452 | module_platform_driver(fsi_driver); |
a4d7d550 KM |
1453 | |
1454 | MODULE_LICENSE("GPL"); | |
1455 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1456 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); | |
b3c27b51 | 1457 | MODULE_ALIAS("platform:fsi-pcm-audio"); |