Commit | Line | Data |
---|---|---|
a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
7da9ced6 | 16 | #include <linux/dma-mapping.h> |
785d1c45 | 17 | #include <linux/pm_runtime.h> |
a4d7d550 | 18 | #include <linux/io.h> |
7da9ced6 KM |
19 | #include <linux/scatterlist.h> |
20 | #include <linux/sh_dma.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
da155d5b | 22 | #include <linux/module.h> |
a4d7d550 | 23 | #include <sound/soc.h> |
ab6f6d85 | 24 | #include <sound/pcm_params.h> |
a4d7d550 | 25 | #include <sound/sh_fsi.h> |
a4d7d550 | 26 | |
e8c8b631 KM |
27 | /* PortA/PortB register */ |
28 | #define REG_DO_FMT 0x0000 | |
29 | #define REG_DOFF_CTL 0x0004 | |
30 | #define REG_DOFF_ST 0x0008 | |
31 | #define REG_DI_FMT 0x000C | |
32 | #define REG_DIFF_CTL 0x0010 | |
33 | #define REG_DIFF_ST 0x0014 | |
34 | #define REG_CKG1 0x0018 | |
35 | #define REG_CKG2 0x001C | |
36 | #define REG_DIDT 0x0020 | |
37 | #define REG_DODT 0x0024 | |
38 | #define REG_MUTE_ST 0x0028 | |
65ff03f4 | 39 | #define REG_OUT_DMAC 0x002C |
e8c8b631 | 40 | #define REG_OUT_SEL 0x0030 |
65ff03f4 | 41 | #define REG_IN_DMAC 0x0038 |
cc780d38 | 42 | |
43fa95ca KM |
43 | /* master register */ |
44 | #define MST_CLK_RST 0x0210 | |
45 | #define MST_SOFT_RST 0x0214 | |
46 | #define MST_FIFO_SZ 0x0218 | |
47 | ||
48 | /* core register (depend on FSI version) */ | |
3bc28070 KM |
49 | #define A_MST_CTLR 0x0180 |
50 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
51 | #define CPU_INT_ST 0x01F4 |
52 | #define CPU_IEMSK 0x01F8 | |
53 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
54 | #define INT_ST 0x0200 |
55 | #define IEMSK 0x0204 | |
56 | #define IMSK 0x0208 | |
a4d7d550 KM |
57 | |
58 | /* DO_FMT */ | |
59 | /* DI_FMT */ | |
7da9ced6 | 60 | #define CR_BWS_MASK (0x3 << 20) /* FSI2 */ |
f7d711e3 KM |
61 | #define CR_BWS_24 (0x0 << 20) /* FSI2 */ |
62 | #define CR_BWS_16 (0x1 << 20) /* FSI2 */ | |
63 | #define CR_BWS_20 (0x2 << 20) /* FSI2 */ | |
64 | ||
65 | #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ | |
66 | #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ | |
67 | #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ | |
68 | ||
a7ffb52b KM |
69 | #define CR_MONO (0x0 << 4) |
70 | #define CR_MONO_D (0x1 << 4) | |
71 | #define CR_PCM (0x2 << 4) | |
72 | #define CR_I2S (0x3 << 4) | |
73 | #define CR_TDM (0x4 << 4) | |
74 | #define CR_TDM_D (0x5 << 4) | |
a4d7d550 | 75 | |
7da9ced6 KM |
76 | /* OUT_DMAC */ |
77 | /* IN_DMAC */ | |
78 | #define VDMD_MASK (0x3 << 4) | |
79 | #define VDMD_FRONT (0x0 << 4) /* Package in front */ | |
80 | #define VDMD_BACK (0x1 << 4) /* Package in back */ | |
81 | #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */ | |
82 | ||
83 | #define DMA_ON (0x1 << 0) | |
84 | ||
a4d7d550 KM |
85 | /* DOFF_CTL */ |
86 | /* DIFF_CTL */ | |
87 | #define IRQ_HALF 0x00100000 | |
88 | #define FIFO_CLR 0x00000001 | |
89 | ||
90 | /* DOFF_ST */ | |
91 | #define ERR_OVER 0x00000010 | |
92 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 93 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 94 | |
ccad7b44 KM |
95 | /* CKG1 */ |
96 | #define ACKMD_MASK 0x00007000 | |
97 | #define BPFMD_MASK 0x00000700 | |
4d805f7b KM |
98 | #define DIMD (1 << 4) |
99 | #define DOMD (1 << 0) | |
ccad7b44 | 100 | |
3bc28070 KM |
101 | /* A/B MST_CTLR */ |
102 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
103 | #define SE (1 << 0) /* Fix the master clock */ | |
104 | ||
a4d7d550 | 105 | /* CLK_RST */ |
1f5e2a31 KM |
106 | #define CRB (1 << 4) |
107 | #define CRA (1 << 0) | |
a4d7d550 | 108 | |
cf6edd00 KM |
109 | /* IO SHIFT / MACRO */ |
110 | #define BI_SHIFT 12 | |
111 | #define BO_SHIFT 8 | |
112 | #define AI_SHIFT 4 | |
113 | #define AO_SHIFT 0 | |
114 | #define AB_IO(param, shift) (param << shift) | |
a4d7d550 | 115 | |
feb58cff KM |
116 | /* SOFT_RST */ |
117 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
118 | #define PASR (1 << 8) /* Port A Software Reset */ | |
119 | #define IR (1 << 4) /* Interrupt Reset */ | |
120 | #define FSISR (1 << 0) /* Software Reset */ | |
121 | ||
f7d711e3 KM |
122 | /* OUT_SEL (FSI2) */ |
123 | #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ | |
124 | /* 1: Biphase and serial */ | |
125 | ||
4a942b45 | 126 | /* FIFO_SZ */ |
cf6edd00 | 127 | #define FIFO_SZ_MASK 0x7 |
4a942b45 | 128 | |
a4d7d550 KM |
129 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
130 | ||
131 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
132 | ||
fec691e7 | 133 | typedef int (*set_rate_func)(struct device *dev, int rate, int enable); |
d7c5762b | 134 | |
766812e6 KM |
135 | /* |
136 | * bus options | |
137 | * | |
138 | * 0x000000BA | |
139 | * | |
140 | * A : sample widtht 16bit setting | |
141 | * B : sample widtht 24bit setting | |
142 | */ | |
143 | ||
144 | #define SHIFT_16DATA 0 | |
145 | #define SHIFT_24DATA 4 | |
146 | ||
147 | #define PACKAGE_24BITBUS_BACK 0 | |
148 | #define PACKAGE_24BITBUS_FRONT 1 | |
149 | #define PACKAGE_16BITBUS_STREAM 2 | |
150 | ||
151 | #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA) | |
152 | #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF) | |
153 | ||
5bfb9ad0 KM |
154 | /* |
155 | * FSI driver use below type name for variable | |
156 | * | |
5bfb9ad0 | 157 | * xxx_num : number of data |
2e651baf KM |
158 | * xxx_pos : position of data |
159 | * xxx_capa : capacity of data | |
160 | */ | |
161 | ||
162 | /* | |
163 | * period/frame/sample image | |
164 | * | |
165 | * ex) PCM (2ch) | |
166 | * | |
167 | * period pos period pos | |
168 | * [n] [n + 1] | |
169 | * |<-------------------- period--------------------->| | |
170 | * ==|============================================ ... =|== | |
171 | * | | | |
172 | * ||<----- frame ----->|<------ frame ----->| ... | | |
173 | * |+--------------------+--------------------+- ... | | |
174 | * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | | |
175 | * |+--------------------+--------------------+- ... | | |
176 | * ==|============================================ ... =|== | |
177 | */ | |
178 | ||
179 | /* | |
180 | * FSI FIFO image | |
181 | * | |
182 | * | | | |
183 | * | | | |
184 | * | [ sample ] | | |
185 | * | [ sample ] | | |
186 | * | [ sample ] | | |
187 | * | [ sample ] | | |
188 | * --> go to codecs | |
5bfb9ad0 KM |
189 | */ |
190 | ||
ab6f6d85 KM |
191 | /* |
192 | * FSI clock | |
193 | * | |
194 | * FSIxCLK [CPG] (ick) -------> | | |
195 | * |-> FSI_DIV (div)-> FSI2 | |
196 | * FSIxCK [external] (xck) ---> | | |
197 | */ | |
198 | ||
c8fe2574 KM |
199 | /* |
200 | * struct | |
201 | */ | |
a4d7d550 | 202 | |
5e97313a | 203 | struct fsi_stream_handler; |
93193c2b | 204 | struct fsi_stream { |
a4d7d550 | 205 | |
5e97313a KM |
206 | /* |
207 | * these are initialized by fsi_stream_init() | |
208 | */ | |
209 | struct snd_pcm_substream *substream; | |
2e651baf KM |
210 | int fifo_sample_capa; /* sample capacity of FSI FIFO */ |
211 | int buff_sample_capa; /* sample capacity of ALSA buffer */ | |
212 | int buff_sample_pos; /* sample position of ALSA buffer */ | |
213 | int period_samples; /* sample number / 1 period */ | |
214 | int period_pos; /* current period position */ | |
c1e6f10e | 215 | int sample_width; /* sample width */ |
1ec9bc35 KM |
216 | int uerr_num; |
217 | int oerr_num; | |
5e97313a | 218 | |
766812e6 KM |
219 | /* |
220 | * bus options | |
221 | */ | |
222 | u32 bus_option; | |
223 | ||
5e97313a KM |
224 | /* |
225 | * thse are initialized by fsi_handler_init() | |
226 | */ | |
227 | struct fsi_stream_handler *handler; | |
228 | struct fsi_priv *priv; | |
7da9ced6 KM |
229 | |
230 | /* | |
231 | * these are for DMAEngine | |
232 | */ | |
233 | struct dma_chan *chan; | |
234 | struct sh_dmae_slave slave; /* see fsi_handler_init() */ | |
235 | struct tasklet_struct tasklet; | |
236 | dma_addr_t dma; | |
93193c2b KM |
237 | }; |
238 | ||
ab6f6d85 KM |
239 | struct fsi_clk { |
240 | /* see [FSI clock] */ | |
241 | struct clk *own; | |
242 | struct clk *xck; | |
243 | struct clk *ick; | |
244 | struct clk *div; | |
245 | int (*set_rate)(struct device *dev, | |
246 | struct fsi_priv *fsi, | |
247 | unsigned long rate); | |
248 | ||
249 | unsigned long rate; | |
250 | unsigned int count; | |
251 | }; | |
252 | ||
93193c2b KM |
253 | struct fsi_priv { |
254 | void __iomem *base; | |
255 | struct fsi_master *master; | |
fec691e7 | 256 | struct sh_fsi_port_info *info; |
93193c2b KM |
257 | |
258 | struct fsi_stream playback; | |
259 | struct fsi_stream capture; | |
3bc28070 | 260 | |
ab6f6d85 KM |
261 | struct fsi_clk clock; |
262 | ||
9c59dd34 | 263 | u32 fmt; |
9478e0b6 | 264 | |
6a9ebad8 KM |
265 | int chan_num:16; |
266 | int clk_master:1; | |
9478e0b6 | 267 | int spdif:1; |
6a9ebad8 | 268 | |
d4bc99b9 | 269 | long rate; |
a4d7d550 KM |
270 | }; |
271 | ||
5e97313a | 272 | struct fsi_stream_handler { |
83344027 KM |
273 | int (*init)(struct fsi_priv *fsi, struct fsi_stream *io); |
274 | int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io); | |
b1226dc5 | 275 | int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev); |
5e97313a KM |
276 | int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io); |
277 | int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io); | |
180346ed KM |
278 | void (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io, |
279 | int enable); | |
5e97313a KM |
280 | }; |
281 | #define fsi_stream_handler_call(io, func, args...) \ | |
282 | (!(io) ? -ENODEV : \ | |
283 | !((io)->handler->func) ? 0 : \ | |
284 | (io)->handler->func(args)) | |
285 | ||
73b92c1f KM |
286 | struct fsi_core { |
287 | int ver; | |
288 | ||
cc780d38 KM |
289 | u32 int_st; |
290 | u32 iemsk; | |
291 | u32 imsk; | |
2b0e7302 KM |
292 | u32 a_mclk; |
293 | u32 b_mclk; | |
cc780d38 KM |
294 | }; |
295 | ||
a4d7d550 KM |
296 | struct fsi_master { |
297 | void __iomem *base; | |
298 | int irq; | |
a4d7d550 KM |
299 | struct fsi_priv fsia; |
300 | struct fsi_priv fsib; | |
73b92c1f | 301 | struct fsi_core *core; |
8fc176d5 | 302 | spinlock_t lock; |
a4d7d550 KM |
303 | }; |
304 | ||
7b1b3331 KM |
305 | static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io); |
306 | ||
c8fe2574 KM |
307 | /* |
308 | * basic read write function | |
309 | */ | |
a4d7d550 | 310 | |
ca7aceef | 311 | static void __fsi_reg_write(u32 __iomem *reg, u32 data) |
a4d7d550 KM |
312 | { |
313 | /* valid data area is 24bit */ | |
314 | data &= 0x00ffffff; | |
315 | ||
0f69d978 | 316 | __raw_writel(data, reg); |
a4d7d550 KM |
317 | } |
318 | ||
ca7aceef | 319 | static u32 __fsi_reg_read(u32 __iomem *reg) |
a4d7d550 | 320 | { |
0f69d978 | 321 | return __raw_readl(reg); |
a4d7d550 KM |
322 | } |
323 | ||
ca7aceef | 324 | static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) |
a4d7d550 KM |
325 | { |
326 | u32 val = __fsi_reg_read(reg); | |
327 | ||
328 | val &= ~mask; | |
329 | val |= data & mask; | |
330 | ||
0f69d978 | 331 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
332 | } |
333 | ||
e8c8b631 | 334 | #define fsi_reg_write(p, r, d)\ |
8918b843 | 335 | __fsi_reg_write((p->base + REG_##r), d) |
a4d7d550 | 336 | |
e8c8b631 | 337 | #define fsi_reg_read(p, r)\ |
8918b843 | 338 | __fsi_reg_read((p->base + REG_##r)) |
a4d7d550 | 339 | |
e8c8b631 | 340 | #define fsi_reg_mask_set(p, r, m, d)\ |
8918b843 | 341 | __fsi_reg_mask_set((p->base + REG_##r), m, d) |
a4d7d550 | 342 | |
43fa95ca KM |
343 | #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) |
344 | #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) | |
345 | static u32 _fsi_master_read(struct fsi_master *master, u32 reg) | |
a4d7d550 | 346 | { |
8fc176d5 KM |
347 | u32 ret; |
348 | unsigned long flags; | |
349 | ||
8fc176d5 | 350 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 351 | ret = __fsi_reg_read(master->base + reg); |
8fc176d5 KM |
352 | spin_unlock_irqrestore(&master->lock, flags); |
353 | ||
354 | return ret; | |
a4d7d550 KM |
355 | } |
356 | ||
43fa95ca KM |
357 | #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) |
358 | #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) | |
359 | static void _fsi_master_mask_set(struct fsi_master *master, | |
71f6e064 | 360 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 361 | { |
8fc176d5 KM |
362 | unsigned long flags; |
363 | ||
8fc176d5 | 364 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 365 | __fsi_reg_mask_set(master->base + reg, mask, data); |
8fc176d5 | 366 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
367 | } |
368 | ||
c8fe2574 KM |
369 | /* |
370 | * basic function | |
371 | */ | |
284c6f65 KM |
372 | static int fsi_version(struct fsi_master *master) |
373 | { | |
374 | return master->core->ver; | |
375 | } | |
a4d7d550 | 376 | |
71f6e064 | 377 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 378 | { |
71f6e064 | 379 | return fsi->master; |
a4d7d550 KM |
380 | } |
381 | ||
6a9ebad8 KM |
382 | static int fsi_is_clk_master(struct fsi_priv *fsi) |
383 | { | |
384 | return fsi->clk_master; | |
385 | } | |
386 | ||
a4d7d550 KM |
387 | static int fsi_is_port_a(struct fsi_priv *fsi) |
388 | { | |
71f6e064 KM |
389 | return fsi->master->base == fsi->base; |
390 | } | |
a4d7d550 | 391 | |
9478e0b6 KM |
392 | static int fsi_is_spdif(struct fsi_priv *fsi) |
393 | { | |
394 | return fsi->spdif; | |
395 | } | |
396 | ||
a449e467 KM |
397 | static int fsi_is_play(struct snd_pcm_substream *substream) |
398 | { | |
399 | return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
400 | } | |
401 | ||
142e8174 | 402 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
403 | { |
404 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 405 | |
f0fba2ad | 406 | return rtd->cpu_dai; |
142e8174 KM |
407 | } |
408 | ||
0d032c19 | 409 | static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) |
142e8174 | 410 | { |
f0fba2ad | 411 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 412 | |
f0fba2ad LG |
413 | if (dai->id == 0) |
414 | return &master->fsia; | |
415 | else | |
416 | return &master->fsib; | |
a4d7d550 KM |
417 | } |
418 | ||
0d032c19 KM |
419 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) |
420 | { | |
421 | return fsi_get_priv_frm_dai(fsi_get_dai(substream)); | |
422 | } | |
423 | ||
fec691e7 | 424 | static set_rate_func fsi_get_info_set_rate(struct fsi_priv *fsi) |
d7c5762b | 425 | { |
fec691e7 | 426 | if (!fsi->info) |
d7c5762b KM |
427 | return NULL; |
428 | ||
fec691e7 | 429 | return fsi->info->set_rate; |
d7c5762b KM |
430 | } |
431 | ||
a4d7d550 KM |
432 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) |
433 | { | |
fec691e7 | 434 | if (!fsi->info) |
d7c5762b KM |
435 | return 0; |
436 | ||
fec691e7 | 437 | return fsi->info->flags; |
a4d7d550 KM |
438 | } |
439 | ||
938e2a8d | 440 | static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 441 | { |
938e2a8d | 442 | int is_play = fsi_stream_is_play(fsi, io); |
a4d7d550 | 443 | int is_porta = fsi_is_port_a(fsi); |
cf6edd00 | 444 | u32 shift; |
a4d7d550 KM |
445 | |
446 | if (is_porta) | |
cf6edd00 | 447 | shift = is_play ? AO_SHIFT : AI_SHIFT; |
a4d7d550 | 448 | else |
cf6edd00 | 449 | shift = is_play ? BO_SHIFT : BI_SHIFT; |
a4d7d550 | 450 | |
cf6edd00 | 451 | return shift; |
a4d7d550 KM |
452 | } |
453 | ||
2e651baf KM |
454 | static int fsi_frame2sample(struct fsi_priv *fsi, int frames) |
455 | { | |
456 | return frames * fsi->chan_num; | |
457 | } | |
458 | ||
459 | static int fsi_sample2frame(struct fsi_priv *fsi, int samples) | |
460 | { | |
461 | return samples / fsi->chan_num; | |
462 | } | |
463 | ||
7b1b3331 KM |
464 | static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, |
465 | struct fsi_stream *io) | |
4e62d84d | 466 | { |
7b1b3331 | 467 | int is_play = fsi_stream_is_play(fsi, io); |
4e62d84d KM |
468 | u32 status; |
469 | int frames; | |
470 | ||
471 | status = is_play ? | |
472 | fsi_reg_read(fsi, DOFF_ST) : | |
473 | fsi_reg_read(fsi, DIFF_ST); | |
474 | ||
475 | frames = 0x1ff & (status >> 8); | |
476 | ||
477 | return fsi_frame2sample(fsi, frames); | |
478 | } | |
479 | ||
480 | static void fsi_count_fifo_err(struct fsi_priv *fsi) | |
481 | { | |
482 | u32 ostatus = fsi_reg_read(fsi, DOFF_ST); | |
483 | u32 istatus = fsi_reg_read(fsi, DIFF_ST); | |
484 | ||
485 | if (ostatus & ERR_OVER) | |
486 | fsi->playback.oerr_num++; | |
487 | ||
488 | if (ostatus & ERR_UNDER) | |
489 | fsi->playback.uerr_num++; | |
490 | ||
491 | if (istatus & ERR_OVER) | |
492 | fsi->capture.oerr_num++; | |
493 | ||
494 | if (istatus & ERR_UNDER) | |
495 | fsi->capture.uerr_num++; | |
496 | ||
497 | fsi_reg_write(fsi, DOFF_ST, 0); | |
498 | fsi_reg_write(fsi, DIFF_ST, 0); | |
499 | } | |
500 | ||
501 | /* | |
502 | * fsi_stream_xx() function | |
503 | */ | |
a449e467 KM |
504 | static inline int fsi_stream_is_play(struct fsi_priv *fsi, |
505 | struct fsi_stream *io) | |
4e62d84d | 506 | { |
a449e467 | 507 | return &fsi->playback == io; |
4e62d84d KM |
508 | } |
509 | ||
510 | static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi, | |
938e2a8d | 511 | struct snd_pcm_substream *substream) |
4e62d84d | 512 | { |
938e2a8d | 513 | return fsi_is_play(substream) ? &fsi->playback : &fsi->capture; |
4e62d84d KM |
514 | } |
515 | ||
cda828ca | 516 | static int fsi_stream_is_working(struct fsi_priv *fsi, |
938e2a8d | 517 | struct fsi_stream *io) |
cda828ca | 518 | { |
cda828ca KM |
519 | struct fsi_master *master = fsi_get_master(fsi); |
520 | unsigned long flags; | |
521 | int ret; | |
522 | ||
523 | spin_lock_irqsave(&master->lock, flags); | |
97df8187 | 524 | ret = !!(io->substream && io->substream->runtime); |
cda828ca KM |
525 | spin_unlock_irqrestore(&master->lock, flags); |
526 | ||
527 | return ret; | |
528 | } | |
529 | ||
5e97313a KM |
530 | static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io) |
531 | { | |
532 | return io->priv; | |
533 | } | |
534 | ||
8c415295 | 535 | static void fsi_stream_init(struct fsi_priv *fsi, |
938e2a8d | 536 | struct fsi_stream *io, |
0ffe296a | 537 | struct snd_pcm_substream *substream) |
a4d7d550 | 538 | { |
0ffe296a | 539 | struct snd_pcm_runtime *runtime = substream->runtime; |
2da65892 KM |
540 | struct fsi_master *master = fsi_get_master(fsi); |
541 | unsigned long flags; | |
93193c2b | 542 | |
2da65892 | 543 | spin_lock_irqsave(&master->lock, flags); |
93193c2b | 544 | io->substream = substream; |
2e651baf KM |
545 | io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); |
546 | io->buff_sample_pos = 0; | |
547 | io->period_samples = fsi_frame2sample(fsi, runtime->period_size); | |
548 | io->period_pos = 0; | |
c1e6f10e | 549 | io->sample_width = samples_to_bytes(runtime, 1); |
766812e6 | 550 | io->bus_option = 0; |
1ec9bc35 KM |
551 | io->oerr_num = -1; /* ignore 1st err */ |
552 | io->uerr_num = -1; /* ignore 1st err */ | |
83344027 | 553 | fsi_stream_handler_call(io, init, fsi, io); |
2da65892 | 554 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
555 | } |
556 | ||
938e2a8d | 557 | static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 558 | { |
1ec9bc35 | 559 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); |
2da65892 KM |
560 | struct fsi_master *master = fsi_get_master(fsi); |
561 | unsigned long flags; | |
1ec9bc35 | 562 | |
2da65892 | 563 | spin_lock_irqsave(&master->lock, flags); |
1ec9bc35 KM |
564 | |
565 | if (io->oerr_num > 0) | |
566 | dev_err(dai->dev, "over_run = %d\n", io->oerr_num); | |
567 | ||
568 | if (io->uerr_num > 0) | |
569 | dev_err(dai->dev, "under_run = %d\n", io->uerr_num); | |
93193c2b | 570 | |
83344027 | 571 | fsi_stream_handler_call(io, quit, fsi, io); |
93193c2b | 572 | io->substream = NULL; |
2e651baf KM |
573 | io->buff_sample_capa = 0; |
574 | io->buff_sample_pos = 0; | |
575 | io->period_samples = 0; | |
576 | io->period_pos = 0; | |
c1e6f10e | 577 | io->sample_width = 0; |
766812e6 | 578 | io->bus_option = 0; |
1ec9bc35 KM |
579 | io->oerr_num = 0; |
580 | io->uerr_num = 0; | |
2da65892 | 581 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
582 | } |
583 | ||
5e97313a KM |
584 | static int fsi_stream_transfer(struct fsi_stream *io) |
585 | { | |
586 | struct fsi_priv *fsi = fsi_stream_to_priv(io); | |
587 | if (!fsi) | |
588 | return -EIO; | |
589 | ||
590 | return fsi_stream_handler_call(io, transfer, fsi, io); | |
591 | } | |
592 | ||
180346ed KM |
593 | #define fsi_stream_start(fsi, io)\ |
594 | fsi_stream_handler_call(io, start_stop, fsi, io, 1) | |
595 | ||
596 | #define fsi_stream_stop(fsi, io)\ | |
597 | fsi_stream_handler_call(io, start_stop, fsi, io, 0) | |
598 | ||
b1226dc5 | 599 | static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev) |
5e97313a KM |
600 | { |
601 | struct fsi_stream *io; | |
602 | int ret1, ret2; | |
603 | ||
604 | io = &fsi->playback; | |
b1226dc5 | 605 | ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev); |
5e97313a KM |
606 | |
607 | io = &fsi->capture; | |
b1226dc5 | 608 | ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev); |
5e97313a KM |
609 | |
610 | if (ret1 < 0) | |
611 | return ret1; | |
612 | if (ret2 < 0) | |
613 | return ret2; | |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
618 | static int fsi_stream_remove(struct fsi_priv *fsi) | |
619 | { | |
620 | struct fsi_stream *io; | |
621 | int ret1, ret2; | |
622 | ||
623 | io = &fsi->playback; | |
624 | ret1 = fsi_stream_handler_call(io, remove, fsi, io); | |
625 | ||
626 | io = &fsi->capture; | |
627 | ret2 = fsi_stream_handler_call(io, remove, fsi, io); | |
628 | ||
629 | if (ret1 < 0) | |
630 | return ret1; | |
631 | if (ret2 < 0) | |
632 | return ret2; | |
633 | ||
634 | return 0; | |
635 | } | |
636 | ||
766812e6 KM |
637 | /* |
638 | * format/bus/dma setting | |
639 | */ | |
640 | static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io, | |
641 | u32 bus, struct device *dev) | |
642 | { | |
643 | struct fsi_master *master = fsi_get_master(fsi); | |
644 | int is_play = fsi_stream_is_play(fsi, io); | |
645 | u32 fmt = fsi->fmt; | |
646 | ||
647 | if (fsi_version(master) >= 2) { | |
648 | u32 dma = 0; | |
649 | ||
650 | /* | |
651 | * FSI2 needs DMA/Bus setting | |
652 | */ | |
653 | switch (bus) { | |
654 | case PACKAGE_24BITBUS_FRONT: | |
655 | fmt |= CR_BWS_24; | |
656 | dma |= VDMD_FRONT; | |
657 | dev_dbg(dev, "24bit bus / package in front\n"); | |
658 | break; | |
659 | case PACKAGE_16BITBUS_STREAM: | |
660 | fmt |= CR_BWS_16; | |
661 | dma |= VDMD_STREAM; | |
662 | dev_dbg(dev, "16bit bus / stream mode\n"); | |
663 | break; | |
664 | case PACKAGE_24BITBUS_BACK: | |
665 | default: | |
666 | fmt |= CR_BWS_24; | |
667 | dma |= VDMD_BACK; | |
668 | dev_dbg(dev, "24bit bus / package in back\n"); | |
669 | break; | |
670 | } | |
671 | ||
672 | if (is_play) | |
673 | fsi_reg_write(fsi, OUT_DMAC, dma); | |
674 | else | |
675 | fsi_reg_write(fsi, IN_DMAC, dma); | |
676 | } | |
677 | ||
678 | if (is_play) | |
679 | fsi_reg_write(fsi, DO_FMT, fmt); | |
680 | else | |
681 | fsi_reg_write(fsi, DI_FMT, fmt); | |
682 | } | |
683 | ||
c8fe2574 KM |
684 | /* |
685 | * irq function | |
686 | */ | |
a4d7d550 | 687 | |
938e2a8d | 688 | static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 689 | { |
938e2a8d | 690 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); |
71f6e064 | 691 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 692 | |
43fa95ca KM |
693 | fsi_core_mask_set(master, imsk, data, data); |
694 | fsi_core_mask_set(master, iemsk, data, data); | |
a4d7d550 KM |
695 | } |
696 | ||
938e2a8d | 697 | static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 698 | { |
938e2a8d | 699 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); |
71f6e064 | 700 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 701 | |
43fa95ca KM |
702 | fsi_core_mask_set(master, imsk, data, 0); |
703 | fsi_core_mask_set(master, iemsk, data, 0); | |
a4d7d550 KM |
704 | } |
705 | ||
10ea76cc KM |
706 | static u32 fsi_irq_get_status(struct fsi_master *master) |
707 | { | |
43fa95ca | 708 | return fsi_core_read(master, int_st); |
10ea76cc KM |
709 | } |
710 | ||
10ea76cc KM |
711 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
712 | { | |
713 | u32 data = 0; | |
714 | struct fsi_master *master = fsi_get_master(fsi); | |
715 | ||
938e2a8d KM |
716 | data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback)); |
717 | data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture)); | |
10ea76cc KM |
718 | |
719 | /* clear interrupt factor */ | |
43fa95ca | 720 | fsi_core_mask_set(master, int_st, data, 0); |
10ea76cc KM |
721 | } |
722 | ||
c8fe2574 KM |
723 | /* |
724 | * SPDIF master clock function | |
725 | * | |
726 | * These functions are used later FSI2 | |
727 | */ | |
3bc28070 KM |
728 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
729 | { | |
730 | struct fsi_master *master = fsi_get_master(fsi); | |
2b0e7302 | 731 | u32 mask, val; |
3bc28070 | 732 | |
2b0e7302 KM |
733 | mask = BP | SE; |
734 | val = enable ? mask : 0; | |
735 | ||
736 | fsi_is_port_a(fsi) ? | |
43fa95ca KM |
737 | fsi_core_mask_set(master, a_mclk, mask, val) : |
738 | fsi_core_mask_set(master, b_mclk, mask, val); | |
3bc28070 KM |
739 | } |
740 | ||
c8fe2574 | 741 | /* |
1f5e2a31 | 742 | * clock function |
c8fe2574 | 743 | */ |
ab6f6d85 KM |
744 | static int fsi_clk_init(struct device *dev, |
745 | struct fsi_priv *fsi, | |
746 | int xck, | |
747 | int ick, | |
748 | int div, | |
749 | int (*set_rate)(struct device *dev, | |
750 | struct fsi_priv *fsi, | |
751 | unsigned long rate)) | |
752 | { | |
753 | struct fsi_clk *clock = &fsi->clock; | |
754 | int is_porta = fsi_is_port_a(fsi); | |
755 | ||
756 | clock->xck = NULL; | |
757 | clock->ick = NULL; | |
758 | clock->div = NULL; | |
759 | clock->rate = 0; | |
760 | clock->count = 0; | |
761 | clock->set_rate = set_rate; | |
762 | ||
763 | clock->own = devm_clk_get(dev, NULL); | |
764 | if (IS_ERR(clock->own)) | |
765 | return -EINVAL; | |
766 | ||
767 | /* external clock */ | |
768 | if (xck) { | |
769 | clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb"); | |
770 | if (IS_ERR(clock->xck)) { | |
771 | dev_err(dev, "can't get xck clock\n"); | |
772 | return -EINVAL; | |
773 | } | |
774 | if (clock->xck == clock->own) { | |
775 | dev_err(dev, "cpu doesn't support xck clock\n"); | |
776 | return -EINVAL; | |
777 | } | |
778 | } | |
779 | ||
780 | /* FSIACLK/FSIBCLK */ | |
781 | if (ick) { | |
782 | clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb"); | |
783 | if (IS_ERR(clock->ick)) { | |
784 | dev_err(dev, "can't get ick clock\n"); | |
785 | return -EINVAL; | |
786 | } | |
787 | if (clock->ick == clock->own) { | |
788 | dev_err(dev, "cpu doesn't support ick clock\n"); | |
789 | return -EINVAL; | |
790 | } | |
791 | } | |
792 | ||
793 | /* FSI-DIV */ | |
794 | if (div) { | |
795 | clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb"); | |
796 | if (IS_ERR(clock->div)) { | |
797 | dev_err(dev, "can't get div clock\n"); | |
798 | return -EINVAL; | |
799 | } | |
800 | if (clock->div == clock->own) { | |
801 | dev_err(dev, "cpu doens't support div clock\n"); | |
802 | return -EINVAL; | |
803 | } | |
804 | } | |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
809 | #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0) | |
810 | static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate) | |
811 | { | |
812 | fsi->clock.rate = rate; | |
813 | } | |
814 | ||
815 | static int fsi_clk_is_valid(struct fsi_priv *fsi) | |
816 | { | |
817 | return fsi->clock.set_rate && | |
818 | fsi->clock.rate; | |
819 | } | |
820 | ||
821 | static int fsi_clk_enable(struct device *dev, | |
822 | struct fsi_priv *fsi, | |
823 | unsigned long rate) | |
824 | { | |
825 | struct fsi_clk *clock = &fsi->clock; | |
826 | int ret = -EINVAL; | |
827 | ||
828 | if (!fsi_clk_is_valid(fsi)) | |
829 | return ret; | |
830 | ||
831 | if (0 == clock->count) { | |
832 | ret = clock->set_rate(dev, fsi, rate); | |
833 | if (ret < 0) { | |
834 | fsi_clk_invalid(fsi); | |
835 | return ret; | |
836 | } | |
837 | ||
838 | if (clock->xck) | |
839 | clk_enable(clock->xck); | |
840 | if (clock->ick) | |
841 | clk_enable(clock->ick); | |
842 | if (clock->div) | |
843 | clk_enable(clock->div); | |
844 | ||
845 | clock->count++; | |
846 | } | |
847 | ||
848 | return ret; | |
849 | } | |
850 | ||
851 | static int fsi_clk_disable(struct device *dev, | |
852 | struct fsi_priv *fsi) | |
853 | { | |
854 | struct fsi_clk *clock = &fsi->clock; | |
855 | ||
856 | if (!fsi_clk_is_valid(fsi)) | |
857 | return -EINVAL; | |
858 | ||
859 | if (1 == clock->count--) { | |
860 | if (clock->xck) | |
861 | clk_disable(clock->xck); | |
862 | if (clock->ick) | |
863 | clk_disable(clock->ick); | |
864 | if (clock->div) | |
865 | clk_disable(clock->div); | |
866 | } | |
867 | ||
868 | return 0; | |
869 | } | |
870 | ||
871 | static int fsi_clk_set_ackbpf(struct device *dev, | |
872 | struct fsi_priv *fsi, | |
873 | int ackmd, int bpfmd) | |
874 | { | |
875 | u32 data = 0; | |
876 | ||
877 | /* check ackmd/bpfmd relationship */ | |
878 | if (bpfmd > ackmd) { | |
879 | dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd); | |
880 | return -EINVAL; | |
881 | } | |
882 | ||
883 | /* ACKMD */ | |
884 | switch (ackmd) { | |
885 | case 512: | |
886 | data |= (0x0 << 12); | |
887 | break; | |
888 | case 256: | |
889 | data |= (0x1 << 12); | |
890 | break; | |
891 | case 128: | |
892 | data |= (0x2 << 12); | |
893 | break; | |
894 | case 64: | |
895 | data |= (0x3 << 12); | |
896 | break; | |
897 | case 32: | |
898 | data |= (0x4 << 12); | |
899 | break; | |
900 | default: | |
901 | dev_err(dev, "unsupported ackmd (%d)\n", ackmd); | |
902 | return -EINVAL; | |
903 | } | |
904 | ||
905 | /* BPFMD */ | |
906 | switch (bpfmd) { | |
907 | case 32: | |
908 | data |= (0x0 << 8); | |
909 | break; | |
910 | case 64: | |
911 | data |= (0x1 << 8); | |
912 | break; | |
913 | case 128: | |
914 | data |= (0x2 << 8); | |
915 | break; | |
916 | case 256: | |
917 | data |= (0x3 << 8); | |
918 | break; | |
919 | case 512: | |
920 | data |= (0x4 << 8); | |
921 | break; | |
922 | case 16: | |
923 | data |= (0x7 << 8); | |
924 | break; | |
925 | default: | |
926 | dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd); | |
927 | return -EINVAL; | |
928 | } | |
929 | ||
930 | dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd); | |
931 | ||
932 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
933 | udelay(10); | |
934 | ||
935 | return 0; | |
936 | } | |
937 | ||
938 | static int fsi_clk_set_rate_external(struct device *dev, | |
939 | struct fsi_priv *fsi, | |
940 | unsigned long rate) | |
941 | { | |
942 | struct clk *xck = fsi->clock.xck; | |
943 | struct clk *ick = fsi->clock.ick; | |
944 | unsigned long xrate; | |
945 | int ackmd, bpfmd; | |
946 | int ret = 0; | |
947 | ||
948 | /* check clock rate */ | |
949 | xrate = clk_get_rate(xck); | |
950 | if (xrate % rate) { | |
951 | dev_err(dev, "unsupported clock rate\n"); | |
952 | return -EINVAL; | |
953 | } | |
954 | ||
955 | clk_set_parent(ick, xck); | |
956 | clk_set_rate(ick, xrate); | |
957 | ||
958 | bpfmd = fsi->chan_num * 32; | |
959 | ackmd = xrate / rate; | |
960 | ||
961 | dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate); | |
962 | ||
963 | ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); | |
964 | if (ret < 0) | |
965 | dev_err(dev, "%s failed", __func__); | |
966 | ||
967 | return ret; | |
968 | } | |
969 | ||
970 | static int fsi_clk_set_rate_cpg(struct device *dev, | |
971 | struct fsi_priv *fsi, | |
972 | unsigned long rate) | |
973 | { | |
974 | struct clk *ick = fsi->clock.ick; | |
975 | struct clk *div = fsi->clock.div; | |
976 | unsigned long target = 0; /* 12288000 or 11289600 */ | |
977 | unsigned long actual, cout; | |
978 | unsigned long diff, min; | |
979 | unsigned long best_cout, best_act; | |
980 | int adj; | |
981 | int ackmd, bpfmd; | |
982 | int ret = -EINVAL; | |
983 | ||
984 | if (!(12288000 % rate)) | |
985 | target = 12288000; | |
986 | if (!(11289600 % rate)) | |
987 | target = 11289600; | |
988 | if (!target) { | |
989 | dev_err(dev, "unsupported rate\n"); | |
990 | return ret; | |
991 | } | |
992 | ||
993 | bpfmd = fsi->chan_num * 32; | |
994 | ackmd = target / rate; | |
995 | ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); | |
996 | if (ret < 0) { | |
997 | dev_err(dev, "%s failed", __func__); | |
998 | return ret; | |
999 | } | |
1000 | ||
1001 | /* | |
1002 | * The clock flow is | |
1003 | * | |
1004 | * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec] | |
1005 | * | |
1006 | * But, it needs to find best match of CPG and FSI_DIV | |
1007 | * combination, since it is difficult to generate correct | |
1008 | * frequency of audio clock from ick clock only. | |
1009 | * Because ick is created from its parent clock. | |
1010 | * | |
1011 | * target = rate x [512/256/128/64]fs | |
1012 | * cout = round(target x adjustment) | |
1013 | * actual = cout / adjustment (by FSI-DIV) ~= target | |
1014 | * audio = actual | |
1015 | */ | |
1016 | min = ~0; | |
1017 | best_cout = 0; | |
1018 | best_act = 0; | |
1019 | for (adj = 1; adj < 0xffff; adj++) { | |
1020 | ||
1021 | cout = target * adj; | |
1022 | if (cout > 100000000) /* max clock = 100MHz */ | |
1023 | break; | |
1024 | ||
1025 | /* cout/actual audio clock */ | |
1026 | cout = clk_round_rate(ick, cout); | |
1027 | actual = cout / adj; | |
1028 | ||
1029 | /* find best frequency */ | |
1030 | diff = abs(actual - target); | |
1031 | if (diff < min) { | |
1032 | min = diff; | |
1033 | best_cout = cout; | |
1034 | best_act = actual; | |
1035 | } | |
1036 | } | |
1037 | ||
1038 | ret = clk_set_rate(ick, best_cout); | |
1039 | if (ret < 0) { | |
1040 | dev_err(dev, "ick clock failed\n"); | |
1041 | return -EIO; | |
1042 | } | |
1043 | ||
1044 | ret = clk_set_rate(div, clk_round_rate(div, best_act)); | |
1045 | if (ret < 0) { | |
1046 | dev_err(dev, "div clock failed\n"); | |
1047 | return -EIO; | |
1048 | } | |
1049 | ||
1050 | dev_dbg(dev, "ick/div = %ld/%ld\n", | |
1051 | clk_get_rate(ick), clk_get_rate(div)); | |
1052 | ||
1053 | return ret; | |
1054 | } | |
1055 | ||
4f56cde1 KM |
1056 | static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi, |
1057 | long rate, int enable) | |
1058 | { | |
fec691e7 | 1059 | set_rate_func set_rate = fsi_get_info_set_rate(fsi); |
4f56cde1 KM |
1060 | int ret; |
1061 | ||
ab6f6d85 KM |
1062 | /* |
1063 | * CAUTION | |
1064 | * | |
1065 | * set_rate will be deleted | |
1066 | */ | |
1067 | if (!set_rate) { | |
1068 | if (enable) | |
1069 | return fsi_clk_enable(dev, fsi, rate); | |
1070 | else | |
1071 | return fsi_clk_disable(dev, fsi); | |
1072 | } | |
fec691e7 KM |
1073 | |
1074 | ret = set_rate(dev, rate, enable); | |
4f56cde1 KM |
1075 | if (ret < 0) /* error */ |
1076 | return ret; | |
1077 | ||
1078 | if (!enable) | |
1079 | return 0; | |
1080 | ||
1081 | if (ret > 0) { | |
1082 | u32 data = 0; | |
1083 | ||
1084 | switch (ret & SH_FSI_ACKMD_MASK) { | |
1085 | default: | |
1086 | /* FALL THROUGH */ | |
1087 | case SH_FSI_ACKMD_512: | |
1088 | data |= (0x0 << 12); | |
1089 | break; | |
1090 | case SH_FSI_ACKMD_256: | |
1091 | data |= (0x1 << 12); | |
1092 | break; | |
1093 | case SH_FSI_ACKMD_128: | |
1094 | data |= (0x2 << 12); | |
1095 | break; | |
1096 | case SH_FSI_ACKMD_64: | |
1097 | data |= (0x3 << 12); | |
1098 | break; | |
1099 | case SH_FSI_ACKMD_32: | |
284c6f65 | 1100 | data |= (0x4 << 12); |
4f56cde1 KM |
1101 | break; |
1102 | } | |
1103 | ||
1104 | switch (ret & SH_FSI_BPFMD_MASK) { | |
1105 | default: | |
1106 | /* FALL THROUGH */ | |
1107 | case SH_FSI_BPFMD_32: | |
1108 | data |= (0x0 << 8); | |
1109 | break; | |
1110 | case SH_FSI_BPFMD_64: | |
1111 | data |= (0x1 << 8); | |
1112 | break; | |
1113 | case SH_FSI_BPFMD_128: | |
1114 | data |= (0x2 << 8); | |
1115 | break; | |
1116 | case SH_FSI_BPFMD_256: | |
1117 | data |= (0x3 << 8); | |
1118 | break; | |
1119 | case SH_FSI_BPFMD_512: | |
1120 | data |= (0x4 << 8); | |
1121 | break; | |
1122 | case SH_FSI_BPFMD_16: | |
284c6f65 | 1123 | data |= (0x7 << 8); |
4f56cde1 KM |
1124 | break; |
1125 | } | |
1126 | ||
1127 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
1128 | udelay(10); | |
1129 | ret = 0; | |
1130 | } | |
1131 | ||
1132 | return ret; | |
4f56cde1 KM |
1133 | } |
1134 | ||
1f5e2a31 | 1135 | /* |
1b0ca1a0 | 1136 | * pio data transfer handler |
1f5e2a31 | 1137 | */ |
1b0ca1a0 KM |
1138 | static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples) |
1139 | { | |
766812e6 | 1140 | u32 enable_stream = fsi_get_info_flags(fsi) & SH_FSI_ENABLE_STREAM_MODE; |
1b0ca1a0 KM |
1141 | int i; |
1142 | ||
766812e6 KM |
1143 | if (enable_stream) { |
1144 | /* | |
1145 | * stream mode | |
1146 | * see | |
1147 | * fsi_pio_push_init() | |
1148 | */ | |
1149 | u32 *buf = (u32 *)_buf; | |
1150 | ||
1151 | for (i = 0; i < samples / 2; i++) | |
1152 | fsi_reg_write(fsi, DODT, buf[i]); | |
1153 | } else { | |
1154 | /* normal mode */ | |
1155 | u16 *buf = (u16 *)_buf; | |
1156 | ||
1157 | for (i = 0; i < samples; i++) | |
1158 | fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8)); | |
1159 | } | |
1b0ca1a0 KM |
1160 | } |
1161 | ||
1162 | static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples) | |
1163 | { | |
1164 | u16 *buf = (u16 *)_buf; | |
1165 | int i; | |
1166 | ||
1167 | for (i = 0; i < samples; i++) | |
1168 | *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); | |
1169 | } | |
1170 | ||
1171 | static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples) | |
1172 | { | |
1173 | u32 *buf = (u32 *)_buf; | |
1174 | int i; | |
1175 | ||
1176 | for (i = 0; i < samples; i++) | |
1177 | fsi_reg_write(fsi, DODT, *(buf + i)); | |
1178 | } | |
1179 | ||
1180 | static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples) | |
1181 | { | |
1182 | u32 *buf = (u32 *)_buf; | |
1183 | int i; | |
1184 | ||
1185 | for (i = 0; i < samples; i++) | |
1186 | *(buf + i) = fsi_reg_read(fsi, DIDT); | |
1187 | } | |
1188 | ||
1189 | static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io) | |
1190 | { | |
1191 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
1192 | ||
1193 | return runtime->dma_area + | |
1194 | samples_to_bytes(runtime, io->buff_sample_pos); | |
1195 | } | |
1196 | ||
1197 | static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io, | |
95b0cf05 KM |
1198 | void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples), |
1199 | void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples), | |
1200 | int samples) | |
a4d7d550 KM |
1201 | { |
1202 | struct snd_pcm_runtime *runtime; | |
376cf38a | 1203 | struct snd_pcm_substream *substream; |
95b0cf05 | 1204 | u8 *buf; |
b9fde18c | 1205 | int over_period; |
a4d7d550 | 1206 | |
97df8187 | 1207 | if (!fsi_stream_is_working(fsi, io)) |
a4d7d550 KM |
1208 | return -EINVAL; |
1209 | ||
1c418d1f | 1210 | over_period = 0; |
93193c2b | 1211 | substream = io->substream; |
1c418d1f | 1212 | runtime = substream->runtime; |
a4d7d550 KM |
1213 | |
1214 | /* FSI FIFO has limit. | |
1215 | * So, this driver can not send periods data at a time | |
1216 | */ | |
2e651baf KM |
1217 | if (io->buff_sample_pos >= |
1218 | io->period_samples * (io->period_pos + 1)) { | |
a4d7d550 | 1219 | |
1c418d1f | 1220 | over_period = 1; |
2e651baf | 1221 | io->period_pos = (io->period_pos + 1) % runtime->periods; |
a4d7d550 | 1222 | |
2e651baf KM |
1223 | if (0 == io->period_pos) |
1224 | io->buff_sample_pos = 0; | |
a4d7d550 KM |
1225 | } |
1226 | ||
95b0cf05 KM |
1227 | buf = fsi_pio_get_area(fsi, io); |
1228 | ||
376cf38a KM |
1229 | switch (io->sample_width) { |
1230 | case 2: | |
95b0cf05 | 1231 | run16(fsi, buf, samples); |
376cf38a KM |
1232 | break; |
1233 | case 4: | |
95b0cf05 | 1234 | run32(fsi, buf, samples); |
376cf38a KM |
1235 | break; |
1236 | default: | |
1237 | return -EINVAL; | |
d8b33534 | 1238 | } |
a4d7d550 | 1239 | |
2e651baf KM |
1240 | /* update buff_sample_pos */ |
1241 | io->buff_sample_pos += samples; | |
a4d7d550 | 1242 | |
1c418d1f | 1243 | if (over_period) |
a4d7d550 KM |
1244 | snd_pcm_period_elapsed(substream); |
1245 | ||
47fc9a0a | 1246 | return 0; |
a4d7d550 KM |
1247 | } |
1248 | ||
5e97313a | 1249 | static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io) |
07102f3c | 1250 | { |
376cf38a KM |
1251 | int sample_residues; /* samples in FSI fifo */ |
1252 | int sample_space; /* ALSA free samples space */ | |
1253 | int samples; | |
376cf38a | 1254 | |
7b1b3331 | 1255 | sample_residues = fsi_get_current_fifo_samples(fsi, io); |
376cf38a KM |
1256 | sample_space = io->buff_sample_capa - io->buff_sample_pos; |
1257 | ||
1258 | samples = min(sample_residues, sample_space); | |
1259 | ||
1b0ca1a0 | 1260 | return fsi_pio_transfer(fsi, io, |
d78629e2 KM |
1261 | fsi_pio_pop16, |
1262 | fsi_pio_pop32, | |
376cf38a | 1263 | samples); |
d8b33534 | 1264 | } |
07102f3c | 1265 | |
5e97313a | 1266 | static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io) |
d8b33534 | 1267 | { |
376cf38a KM |
1268 | int sample_residues; /* ALSA residue samples */ |
1269 | int sample_space; /* FSI fifo free samples space */ | |
1270 | int samples; | |
376cf38a KM |
1271 | |
1272 | sample_residues = io->buff_sample_capa - io->buff_sample_pos; | |
1273 | sample_space = io->fifo_sample_capa - | |
7b1b3331 | 1274 | fsi_get_current_fifo_samples(fsi, io); |
376cf38a KM |
1275 | |
1276 | samples = min(sample_residues, sample_space); | |
1277 | ||
1b0ca1a0 | 1278 | return fsi_pio_transfer(fsi, io, |
d78629e2 KM |
1279 | fsi_pio_push16, |
1280 | fsi_pio_push32, | |
376cf38a | 1281 | samples); |
07102f3c KM |
1282 | } |
1283 | ||
180346ed KM |
1284 | static void fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, |
1285 | int enable) | |
1286 | { | |
1287 | struct fsi_master *master = fsi_get_master(fsi); | |
1288 | u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; | |
1289 | ||
1290 | if (enable) | |
1291 | fsi_irq_enable(fsi, io); | |
1292 | else | |
1293 | fsi_irq_disable(fsi, io); | |
1294 | ||
1295 | if (fsi_is_clk_master(fsi)) | |
1296 | fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); | |
1297 | } | |
1298 | ||
766812e6 KM |
1299 | static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io) |
1300 | { | |
1301 | u32 enable_stream = fsi_get_info_flags(fsi) & SH_FSI_ENABLE_STREAM_MODE; | |
1302 | ||
1303 | /* | |
1304 | * we can use 16bit stream mode | |
1305 | * when "playback" and "16bit data" | |
1306 | * and platform allows "stream mode" | |
1307 | * see | |
1308 | * fsi_pio_push16() | |
1309 | */ | |
1310 | if (enable_stream) | |
1311 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | | |
1312 | BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); | |
1313 | else | |
1314 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | | |
1315 | BUSOP_SET(16, PACKAGE_24BITBUS_BACK); | |
1316 | return 0; | |
1317 | } | |
1318 | ||
1319 | static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io) | |
1320 | { | |
1321 | /* | |
1322 | * always 24bit bus, package back when "capture" | |
1323 | */ | |
1324 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | | |
1325 | BUSOP_SET(16, PACKAGE_24BITBUS_BACK); | |
1326 | return 0; | |
1327 | } | |
1328 | ||
5e97313a | 1329 | static struct fsi_stream_handler fsi_pio_push_handler = { |
766812e6 | 1330 | .init = fsi_pio_push_init, |
5e97313a | 1331 | .transfer = fsi_pio_push, |
180346ed | 1332 | .start_stop = fsi_pio_start_stop, |
5e97313a KM |
1333 | }; |
1334 | ||
1335 | static struct fsi_stream_handler fsi_pio_pop_handler = { | |
766812e6 | 1336 | .init = fsi_pio_pop_init, |
5e97313a | 1337 | .transfer = fsi_pio_pop, |
180346ed | 1338 | .start_stop = fsi_pio_start_stop, |
5e97313a KM |
1339 | }; |
1340 | ||
a4d7d550 KM |
1341 | static irqreturn_t fsi_interrupt(int irq, void *data) |
1342 | { | |
71f6e064 | 1343 | struct fsi_master *master = data; |
10ea76cc | 1344 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
1345 | |
1346 | /* clear irq status */ | |
feb58cff KM |
1347 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
1348 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 | 1349 | |
cf6edd00 | 1350 | if (int_st & AB_IO(1, AO_SHIFT)) |
5e97313a | 1351 | fsi_stream_transfer(&master->fsia.playback); |
cf6edd00 | 1352 | if (int_st & AB_IO(1, BO_SHIFT)) |
5e97313a | 1353 | fsi_stream_transfer(&master->fsib.playback); |
cf6edd00 | 1354 | if (int_st & AB_IO(1, AI_SHIFT)) |
5e97313a | 1355 | fsi_stream_transfer(&master->fsia.capture); |
cf6edd00 | 1356 | if (int_st & AB_IO(1, BI_SHIFT)) |
5e97313a | 1357 | fsi_stream_transfer(&master->fsib.capture); |
1ec9bc35 KM |
1358 | |
1359 | fsi_count_fifo_err(&master->fsia); | |
1360 | fsi_count_fifo_err(&master->fsib); | |
a4d7d550 | 1361 | |
48d78e58 KM |
1362 | fsi_irq_clear_status(&master->fsia); |
1363 | fsi_irq_clear_status(&master->fsib); | |
a4d7d550 KM |
1364 | |
1365 | return IRQ_HANDLED; | |
1366 | } | |
1367 | ||
7da9ced6 KM |
1368 | /* |
1369 | * dma data transfer handler | |
1370 | */ | |
1371 | static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io) | |
1372 | { | |
1373 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
1374 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); | |
1375 | enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? | |
1376 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1377 | ||
766812e6 KM |
1378 | /* |
1379 | * 24bit data : 24bit bus / package in back | |
1380 | * 16bit data : 16bit bus / stream mode | |
1381 | */ | |
1382 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | | |
1383 | BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); | |
1384 | ||
7da9ced6 KM |
1385 | io->dma = dma_map_single(dai->dev, runtime->dma_area, |
1386 | snd_pcm_lib_buffer_bytes(io->substream), dir); | |
1387 | return 0; | |
1388 | } | |
1389 | ||
1390 | static int fsi_dma_quit(struct fsi_priv *fsi, struct fsi_stream *io) | |
1391 | { | |
1392 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); | |
1393 | enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? | |
1394 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1395 | ||
1396 | dma_unmap_single(dai->dev, io->dma, | |
1397 | snd_pcm_lib_buffer_bytes(io->substream), dir); | |
1398 | return 0; | |
1399 | } | |
1400 | ||
4a1b09b7 KM |
1401 | static dma_addr_t fsi_dma_get_area(struct fsi_stream *io) |
1402 | { | |
1403 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
1404 | ||
1405 | return io->dma + samples_to_bytes(runtime, io->buff_sample_pos); | |
1406 | } | |
1407 | ||
7da9ced6 KM |
1408 | static void fsi_dma_complete(void *data) |
1409 | { | |
1410 | struct fsi_stream *io = (struct fsi_stream *)data; | |
1411 | struct fsi_priv *fsi = fsi_stream_to_priv(io); | |
1412 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
1413 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); | |
1414 | enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? | |
1415 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1416 | ||
4a1b09b7 | 1417 | dma_sync_single_for_cpu(dai->dev, fsi_dma_get_area(io), |
7da9ced6 KM |
1418 | samples_to_bytes(runtime, io->period_samples), dir); |
1419 | ||
1420 | io->buff_sample_pos += io->period_samples; | |
1421 | io->period_pos++; | |
1422 | ||
1423 | if (io->period_pos >= runtime->periods) { | |
1424 | io->period_pos = 0; | |
1425 | io->buff_sample_pos = 0; | |
1426 | } | |
1427 | ||
1428 | fsi_count_fifo_err(fsi); | |
1429 | fsi_stream_transfer(io); | |
1430 | ||
1431 | snd_pcm_period_elapsed(io->substream); | |
1432 | } | |
1433 | ||
7da9ced6 KM |
1434 | static void fsi_dma_do_tasklet(unsigned long data) |
1435 | { | |
1436 | struct fsi_stream *io = (struct fsi_stream *)data; | |
1437 | struct fsi_priv *fsi = fsi_stream_to_priv(io); | |
7da9ced6 KM |
1438 | struct snd_soc_dai *dai; |
1439 | struct dma_async_tx_descriptor *desc; | |
7da9ced6 KM |
1440 | struct snd_pcm_runtime *runtime; |
1441 | enum dma_data_direction dir; | |
7da9ced6 KM |
1442 | int is_play = fsi_stream_is_play(fsi, io); |
1443 | int len; | |
1444 | dma_addr_t buf; | |
1445 | ||
1446 | if (!fsi_stream_is_working(fsi, io)) | |
1447 | return; | |
1448 | ||
1449 | dai = fsi_get_dai(io->substream); | |
7da9ced6 KM |
1450 | runtime = io->substream->runtime; |
1451 | dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1452 | len = samples_to_bytes(runtime, io->period_samples); | |
1453 | buf = fsi_dma_get_area(io); | |
1454 | ||
4a1b09b7 | 1455 | dma_sync_single_for_device(dai->dev, buf, len, dir); |
7da9ced6 | 1456 | |
5514efdf KM |
1457 | desc = dmaengine_prep_slave_single(io->chan, buf, len, dir, |
1458 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
7da9ced6 | 1459 | if (!desc) { |
cdf27f37 | 1460 | dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n"); |
7da9ced6 KM |
1461 | return; |
1462 | } | |
1463 | ||
1464 | desc->callback = fsi_dma_complete; | |
1465 | desc->callback_param = io; | |
1466 | ||
5514efdf | 1467 | if (dmaengine_submit(desc) < 0) { |
7da9ced6 KM |
1468 | dev_err(dai->dev, "tx_submit() fail\n"); |
1469 | return; | |
1470 | } | |
1471 | ||
5514efdf | 1472 | dma_async_issue_pending(io->chan); |
7da9ced6 KM |
1473 | |
1474 | /* | |
1475 | * FIXME | |
1476 | * | |
1477 | * In DMAEngine case, codec and FSI cannot be started simultaneously | |
1478 | * since FSI is using tasklet. | |
1479 | * Therefore, in capture case, probably FSI FIFO will have got | |
1480 | * overflow error in this point. | |
1481 | * in that case, DMA cannot start transfer until error was cleared. | |
1482 | */ | |
1483 | if (!is_play) { | |
1484 | if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) { | |
1485 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
1486 | fsi_reg_write(fsi, DIFF_ST, 0); | |
1487 | } | |
1488 | } | |
1489 | } | |
1490 | ||
1491 | static bool fsi_dma_filter(struct dma_chan *chan, void *param) | |
1492 | { | |
1493 | struct sh_dmae_slave *slave = param; | |
1494 | ||
1495 | chan->private = slave; | |
1496 | ||
1497 | return true; | |
1498 | } | |
1499 | ||
1500 | static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io) | |
1501 | { | |
1502 | tasklet_schedule(&io->tasklet); | |
1503 | ||
1504 | return 0; | |
1505 | } | |
1506 | ||
1507 | static void fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, | |
1508 | int start) | |
1509 | { | |
e42bb9bf KM |
1510 | struct fsi_master *master = fsi_get_master(fsi); |
1511 | u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; | |
766812e6 | 1512 | u32 enable = start ? DMA_ON : 0; |
7da9ced6 | 1513 | |
766812e6 | 1514 | fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable); |
e42bb9bf | 1515 | |
fbe42f66 KM |
1516 | dmaengine_terminate_all(io->chan); |
1517 | ||
e42bb9bf KM |
1518 | if (fsi_is_clk_master(fsi)) |
1519 | fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); | |
7da9ced6 KM |
1520 | } |
1521 | ||
b1226dc5 | 1522 | static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev) |
7da9ced6 KM |
1523 | { |
1524 | dma_cap_mask_t mask; | |
1525 | ||
1526 | dma_cap_zero(mask); | |
1527 | dma_cap_set(DMA_SLAVE, mask); | |
1528 | ||
1529 | io->chan = dma_request_channel(mask, fsi_dma_filter, &io->slave); | |
b1226dc5 KM |
1530 | if (!io->chan) { |
1531 | ||
1532 | /* switch to PIO handler */ | |
1533 | if (fsi_stream_is_play(fsi, io)) | |
1534 | fsi->playback.handler = &fsi_pio_push_handler; | |
1535 | else | |
1536 | fsi->capture.handler = &fsi_pio_pop_handler; | |
1537 | ||
1538 | dev_info(dev, "switch handler (dma => pio)\n"); | |
1539 | ||
1540 | /* probe again */ | |
1541 | return fsi_stream_probe(fsi, dev); | |
1542 | } | |
7da9ced6 KM |
1543 | |
1544 | tasklet_init(&io->tasklet, fsi_dma_do_tasklet, (unsigned long)io); | |
1545 | ||
1546 | return 0; | |
1547 | } | |
1548 | ||
1549 | static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io) | |
1550 | { | |
1551 | tasklet_kill(&io->tasklet); | |
1552 | ||
1553 | fsi_stream_stop(fsi, io); | |
1554 | ||
1555 | if (io->chan) | |
1556 | dma_release_channel(io->chan); | |
1557 | ||
1558 | io->chan = NULL; | |
1559 | return 0; | |
1560 | } | |
1561 | ||
1562 | static struct fsi_stream_handler fsi_dma_push_handler = { | |
1563 | .init = fsi_dma_init, | |
1564 | .quit = fsi_dma_quit, | |
1565 | .probe = fsi_dma_probe, | |
1566 | .transfer = fsi_dma_transfer, | |
1567 | .remove = fsi_dma_remove, | |
1568 | .start_stop = fsi_dma_push_start_stop, | |
1569 | }; | |
1570 | ||
c8fe2574 KM |
1571 | /* |
1572 | * dai ops | |
1573 | */ | |
b49e8027 | 1574 | static void fsi_fifo_init(struct fsi_priv *fsi, |
938e2a8d | 1575 | struct fsi_stream *io, |
b49e8027 KM |
1576 | struct device *dev) |
1577 | { | |
1578 | struct fsi_master *master = fsi_get_master(fsi); | |
938e2a8d | 1579 | int is_play = fsi_stream_is_play(fsi, io); |
b49e8027 KM |
1580 | u32 shift, i; |
1581 | int frame_capa; | |
1582 | ||
1583 | /* get on-chip RAM capacity */ | |
1584 | shift = fsi_master_read(master, FIFO_SZ); | |
938e2a8d | 1585 | shift >>= fsi_get_port_shift(fsi, io); |
b49e8027 KM |
1586 | shift &= FIFO_SZ_MASK; |
1587 | frame_capa = 256 << shift; | |
1588 | dev_dbg(dev, "fifo = %d words\n", frame_capa); | |
1589 | ||
1590 | /* | |
1591 | * The maximum number of sample data varies depending | |
1592 | * on the number of channels selected for the format. | |
1593 | * | |
1594 | * FIFOs are used in 4-channel units in 3-channel mode | |
1595 | * and in 8-channel units in 5- to 7-channel mode | |
1596 | * meaning that more FIFOs than the required size of DPRAM | |
1597 | * are used. | |
1598 | * | |
1599 | * ex) if 256 words of DP-RAM is connected | |
1600 | * 1 channel: 256 (256 x 1 = 256) | |
1601 | * 2 channels: 128 (128 x 2 = 256) | |
1602 | * 3 channels: 64 ( 64 x 3 = 192) | |
1603 | * 4 channels: 64 ( 64 x 4 = 256) | |
1604 | * 5 channels: 32 ( 32 x 5 = 160) | |
1605 | * 6 channels: 32 ( 32 x 6 = 192) | |
1606 | * 7 channels: 32 ( 32 x 7 = 224) | |
1607 | * 8 channels: 32 ( 32 x 8 = 256) | |
1608 | */ | |
1609 | for (i = 1; i < fsi->chan_num; i <<= 1) | |
1610 | frame_capa >>= 1; | |
1611 | dev_dbg(dev, "%d channel %d store\n", | |
1612 | fsi->chan_num, frame_capa); | |
1613 | ||
1614 | io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); | |
1615 | ||
1616 | /* | |
1617 | * set interrupt generation factor | |
1618 | * clear FIFO | |
1619 | */ | |
1620 | if (is_play) { | |
1621 | fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); | |
1622 | fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); | |
1623 | } else { | |
1624 | fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); | |
1625 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
1626 | } | |
1627 | } | |
a4d7d550 | 1628 | |
23ca8533 | 1629 | static int fsi_hw_startup(struct fsi_priv *fsi, |
938e2a8d | 1630 | struct fsi_stream *io, |
23ca8533 | 1631 | struct device *dev) |
a4d7d550 | 1632 | { |
93193c2b | 1633 | u32 flags = fsi_get_info_flags(fsi); |
9478e0b6 | 1634 | u32 data = 0; |
a4d7d550 | 1635 | |
9478e0b6 KM |
1636 | /* clock setting */ |
1637 | if (fsi_is_clk_master(fsi)) | |
1638 | data = DIMD | DOMD; | |
1639 | ||
1640 | fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); | |
a4d7d550 KM |
1641 | |
1642 | /* clock inversion (CKG2) */ | |
1643 | data = 0; | |
b427b44c KM |
1644 | if (SH_FSI_LRM_INV & flags) |
1645 | data |= 1 << 12; | |
1646 | if (SH_FSI_BRM_INV & flags) | |
1647 | data |= 1 << 8; | |
1648 | if (SH_FSI_LRS_INV & flags) | |
1649 | data |= 1 << 4; | |
1650 | if (SH_FSI_BRS_INV & flags) | |
1651 | data |= 1 << 0; | |
1652 | ||
a4d7d550 KM |
1653 | fsi_reg_write(fsi, CKG2, data); |
1654 | ||
9478e0b6 KM |
1655 | /* spdif ? */ |
1656 | if (fsi_is_spdif(fsi)) { | |
1657 | fsi_spdif_clk_ctrl(fsi, 1); | |
1658 | fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); | |
1659 | } | |
1660 | ||
65ff03f4 | 1661 | /* |
766812e6 | 1662 | * get bus settings |
65ff03f4 | 1663 | */ |
766812e6 KM |
1664 | data = 0; |
1665 | switch (io->sample_width) { | |
1666 | case 2: | |
1667 | data = BUSOP_GET(16, io->bus_option); | |
1668 | break; | |
1669 | case 4: | |
1670 | data = BUSOP_GET(24, io->bus_option); | |
1671 | break; | |
65ff03f4 | 1672 | } |
766812e6 | 1673 | fsi_format_bus_setup(fsi, io, data, dev); |
65ff03f4 | 1674 | |
10ea76cc | 1675 | /* irq clear */ |
938e2a8d | 1676 | fsi_irq_disable(fsi, io); |
10ea76cc KM |
1677 | fsi_irq_clear_status(fsi); |
1678 | ||
1679 | /* fifo init */ | |
938e2a8d | 1680 | fsi_fifo_init(fsi, io, dev); |
a4d7d550 | 1681 | |
ddeb2d70 KM |
1682 | /* start master clock */ |
1683 | if (fsi_is_clk_master(fsi)) | |
80b4addc | 1684 | return fsi_set_master_clk(dev, fsi, fsi->rate, 1); |
ddeb2d70 | 1685 | |
a68a3b4e | 1686 | return 0; |
a4d7d550 KM |
1687 | } |
1688 | ||
80b4addc | 1689 | static int fsi_hw_shutdown(struct fsi_priv *fsi, |
23ca8533 KM |
1690 | struct device *dev) |
1691 | { | |
ddeb2d70 | 1692 | /* stop master clock */ |
23ca8533 | 1693 | if (fsi_is_clk_master(fsi)) |
80b4addc KM |
1694 | return fsi_set_master_clk(dev, fsi, fsi->rate, 0); |
1695 | ||
1696 | return 0; | |
23ca8533 KM |
1697 | } |
1698 | ||
1699 | static int fsi_dai_startup(struct snd_pcm_substream *substream, | |
1700 | struct snd_soc_dai *dai) | |
1701 | { | |
1702 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
23ca8533 | 1703 | |
ab6f6d85 | 1704 | fsi_clk_invalid(fsi); |
f33238e9 KM |
1705 | fsi->rate = 0; |
1706 | ||
1707 | return 0; | |
23ca8533 KM |
1708 | } |
1709 | ||
a4d7d550 KM |
1710 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, |
1711 | struct snd_soc_dai *dai) | |
1712 | { | |
71f6e064 | 1713 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 | 1714 | |
ab6f6d85 | 1715 | fsi_clk_invalid(fsi); |
d4bc99b9 | 1716 | fsi->rate = 0; |
a4d7d550 KM |
1717 | } |
1718 | ||
1719 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
1720 | struct snd_soc_dai *dai) | |
1721 | { | |
71f6e064 | 1722 | struct fsi_priv *fsi = fsi_get_priv(substream); |
938e2a8d | 1723 | struct fsi_stream *io = fsi_stream_get(fsi, substream); |
a4d7d550 KM |
1724 | int ret = 0; |
1725 | ||
a4d7d550 KM |
1726 | switch (cmd) { |
1727 | case SNDRV_PCM_TRIGGER_START: | |
938e2a8d | 1728 | fsi_stream_init(fsi, io, substream); |
80b4addc KM |
1729 | if (!ret) |
1730 | ret = fsi_hw_startup(fsi, io, dai->dev); | |
1731 | if (!ret) | |
1732 | ret = fsi_stream_transfer(io); | |
1733 | if (!ret) | |
180346ed | 1734 | fsi_stream_start(fsi, io); |
a4d7d550 KM |
1735 | break; |
1736 | case SNDRV_PCM_TRIGGER_STOP: | |
80b4addc KM |
1737 | if (!ret) |
1738 | ret = fsi_hw_shutdown(fsi, dai->dev); | |
180346ed | 1739 | fsi_stream_stop(fsi, io); |
938e2a8d | 1740 | fsi_stream_quit(fsi, io); |
a4d7d550 KM |
1741 | break; |
1742 | } | |
1743 | ||
1744 | return ret; | |
1745 | } | |
1746 | ||
f17c13ca KM |
1747 | static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) |
1748 | { | |
f17c13ca KM |
1749 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
1750 | case SND_SOC_DAIFMT_I2S: | |
9c59dd34 | 1751 | fsi->fmt = CR_I2S; |
f17c13ca KM |
1752 | fsi->chan_num = 2; |
1753 | break; | |
1754 | case SND_SOC_DAIFMT_LEFT_J: | |
9c59dd34 | 1755 | fsi->fmt = CR_PCM; |
f17c13ca KM |
1756 | fsi->chan_num = 2; |
1757 | break; | |
1758 | default: | |
1759 | return -EINVAL; | |
1760 | } | |
1761 | ||
f17c13ca KM |
1762 | return 0; |
1763 | } | |
1764 | ||
1765 | static int fsi_set_fmt_spdif(struct fsi_priv *fsi) | |
1766 | { | |
1767 | struct fsi_master *master = fsi_get_master(fsi); | |
f17c13ca | 1768 | |
284c6f65 | 1769 | if (fsi_version(master) < 2) |
f17c13ca KM |
1770 | return -EINVAL; |
1771 | ||
766812e6 | 1772 | fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM; |
f17c13ca | 1773 | fsi->chan_num = 2; |
f17c13ca | 1774 | |
f17c13ca KM |
1775 | return 0; |
1776 | } | |
1777 | ||
4d805f7b KM |
1778 | static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
1779 | { | |
1780 | struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); | |
fec691e7 | 1781 | set_rate_func set_rate = fsi_get_info_set_rate(fsi); |
f17c13ca | 1782 | u32 flags = fsi_get_info_flags(fsi); |
4d805f7b KM |
1783 | int ret; |
1784 | ||
4d805f7b KM |
1785 | /* set master/slave audio interface */ |
1786 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1787 | case SND_SOC_DAIFMT_CBM_CFM: | |
6a9ebad8 | 1788 | fsi->clk_master = 1; |
4d805f7b KM |
1789 | break; |
1790 | case SND_SOC_DAIFMT_CBS_CFS: | |
1791 | break; | |
1792 | default: | |
9478e0b6 | 1793 | return -EINVAL; |
4d805f7b | 1794 | } |
6a9ebad8 | 1795 | |
ab6f6d85 KM |
1796 | if (fsi_is_clk_master(fsi)) { |
1797 | /* | |
1798 | * CAUTION | |
1799 | * | |
1800 | * set_rate will be deleted | |
1801 | */ | |
1802 | if (set_rate) | |
1803 | dev_warn(dai->dev, "set_rate will be removed soon\n"); | |
1804 | ||
1805 | switch (flags & SH_FSI_CLK_MASK) { | |
1806 | case SH_FSI_CLK_EXTERNAL: | |
1807 | fsi_clk_init(dai->dev, fsi, 1, 1, 0, | |
1808 | fsi_clk_set_rate_external); | |
1809 | break; | |
1810 | case SH_FSI_CLK_CPG: | |
1811 | fsi_clk_init(dai->dev, fsi, 0, 1, 1, | |
1812 | fsi_clk_set_rate_cpg); | |
1813 | break; | |
1814 | } | |
6a9ebad8 KM |
1815 | } |
1816 | ||
f17c13ca | 1817 | /* set format */ |
c2052def | 1818 | if (fsi_is_spdif(fsi)) |
f17c13ca | 1819 | ret = fsi_set_fmt_spdif(fsi); |
c2052def KM |
1820 | else |
1821 | ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); | |
4d805f7b | 1822 | |
4d805f7b KM |
1823 | return ret; |
1824 | } | |
1825 | ||
ccad7b44 KM |
1826 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
1827 | struct snd_pcm_hw_params *params, | |
1828 | struct snd_soc_dai *dai) | |
1829 | { | |
1830 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
ccad7b44 | 1831 | |
ab6f6d85 | 1832 | if (fsi_is_clk_master(fsi)) { |
ddeb2d70 | 1833 | fsi->rate = params_rate(params); |
ab6f6d85 KM |
1834 | fsi_clk_valid(fsi, fsi->rate); |
1835 | } | |
ccad7b44 | 1836 | |
ddeb2d70 | 1837 | return 0; |
ccad7b44 KM |
1838 | } |
1839 | ||
85e7652d | 1840 | static const struct snd_soc_dai_ops fsi_dai_ops = { |
a4d7d550 KM |
1841 | .startup = fsi_dai_startup, |
1842 | .shutdown = fsi_dai_shutdown, | |
1843 | .trigger = fsi_dai_trigger, | |
4d805f7b | 1844 | .set_fmt = fsi_dai_set_fmt, |
ccad7b44 | 1845 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
1846 | }; |
1847 | ||
c8fe2574 KM |
1848 | /* |
1849 | * pcm ops | |
1850 | */ | |
a4d7d550 | 1851 | |
a4d7d550 KM |
1852 | static struct snd_pcm_hardware fsi_pcm_hardware = { |
1853 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
1854 | SNDRV_PCM_INFO_MMAP | | |
1855 | SNDRV_PCM_INFO_MMAP_VALID | | |
1856 | SNDRV_PCM_INFO_PAUSE, | |
1857 | .formats = FSI_FMTS, | |
1858 | .rates = FSI_RATES, | |
1859 | .rate_min = 8000, | |
1860 | .rate_max = 192000, | |
2a8c8a56 | 1861 | .channels_min = 2, |
a4d7d550 KM |
1862 | .channels_max = 2, |
1863 | .buffer_bytes_max = 64 * 1024, | |
1864 | .period_bytes_min = 32, | |
1865 | .period_bytes_max = 8192, | |
1866 | .periods_min = 1, | |
1867 | .periods_max = 32, | |
1868 | .fifo_size = 256, | |
1869 | }; | |
1870 | ||
1871 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
1872 | { | |
1873 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1874 | int ret = 0; | |
1875 | ||
1876 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
1877 | ||
1878 | ret = snd_pcm_hw_constraint_integer(runtime, | |
1879 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1880 | ||
1881 | return ret; | |
1882 | } | |
1883 | ||
1884 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
1885 | struct snd_pcm_hw_params *hw_params) | |
1886 | { | |
1887 | return snd_pcm_lib_malloc_pages(substream, | |
1888 | params_buffer_bytes(hw_params)); | |
1889 | } | |
1890 | ||
1891 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
1892 | { | |
1893 | return snd_pcm_lib_free_pages(substream); | |
1894 | } | |
1895 | ||
1896 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
1897 | { | |
71f6e064 | 1898 | struct fsi_priv *fsi = fsi_get_priv(substream); |
938e2a8d | 1899 | struct fsi_stream *io = fsi_stream_get(fsi, substream); |
a4d7d550 | 1900 | |
1987877d | 1901 | return fsi_sample2frame(fsi, io->buff_sample_pos); |
a4d7d550 KM |
1902 | } |
1903 | ||
1904 | static struct snd_pcm_ops fsi_pcm_ops = { | |
1905 | .open = fsi_pcm_open, | |
1906 | .ioctl = snd_pcm_lib_ioctl, | |
1907 | .hw_params = fsi_hw_params, | |
1908 | .hw_free = fsi_hw_free, | |
1909 | .pointer = fsi_pointer, | |
1910 | }; | |
1911 | ||
c8fe2574 KM |
1912 | /* |
1913 | * snd_soc_platform | |
1914 | */ | |
a4d7d550 | 1915 | |
a4d7d550 KM |
1916 | #define PREALLOC_BUFFER (32 * 1024) |
1917 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1918 | ||
1919 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1920 | { | |
1921 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1922 | } | |
1923 | ||
552d1ef6 | 1924 | static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd) |
a4d7d550 | 1925 | { |
552d1ef6 LG |
1926 | struct snd_pcm *pcm = rtd->pcm; |
1927 | ||
a4d7d550 KM |
1928 | /* |
1929 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1930 | * in MMAP mode (i.e. aplay -M) | |
1931 | */ | |
1932 | return snd_pcm_lib_preallocate_pages_for_all( | |
1933 | pcm, | |
1934 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1935 | snd_dma_continuous_data(GFP_KERNEL), | |
1936 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1937 | } | |
1938 | ||
c8fe2574 KM |
1939 | /* |
1940 | * alsa struct | |
1941 | */ | |
a4d7d550 | 1942 | |
f0fba2ad | 1943 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1944 | { |
f0fba2ad | 1945 | .name = "fsia-dai", |
a4d7d550 KM |
1946 | .playback = { |
1947 | .rates = FSI_RATES, | |
1948 | .formats = FSI_FMTS, | |
2a8c8a56 KM |
1949 | .channels_min = 2, |
1950 | .channels_max = 2, | |
a4d7d550 | 1951 | }, |
07102f3c KM |
1952 | .capture = { |
1953 | .rates = FSI_RATES, | |
1954 | .formats = FSI_FMTS, | |
2a8c8a56 KM |
1955 | .channels_min = 2, |
1956 | .channels_max = 2, | |
07102f3c | 1957 | }, |
a4d7d550 KM |
1958 | .ops = &fsi_dai_ops, |
1959 | }, | |
1960 | { | |
f0fba2ad | 1961 | .name = "fsib-dai", |
a4d7d550 KM |
1962 | .playback = { |
1963 | .rates = FSI_RATES, | |
1964 | .formats = FSI_FMTS, | |
2a8c8a56 KM |
1965 | .channels_min = 2, |
1966 | .channels_max = 2, | |
a4d7d550 | 1967 | }, |
07102f3c KM |
1968 | .capture = { |
1969 | .rates = FSI_RATES, | |
1970 | .formats = FSI_FMTS, | |
2a8c8a56 KM |
1971 | .channels_min = 2, |
1972 | .channels_max = 2, | |
07102f3c | 1973 | }, |
a4d7d550 KM |
1974 | .ops = &fsi_dai_ops, |
1975 | }, | |
1976 | }; | |
a4d7d550 | 1977 | |
f0fba2ad LG |
1978 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1979 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1980 | .pcm_new = fsi_pcm_new, |
1981 | .pcm_free = fsi_pcm_free, | |
1982 | }; | |
a4d7d550 | 1983 | |
c8fe2574 KM |
1984 | /* |
1985 | * platform function | |
1986 | */ | |
c2052def KM |
1987 | static void fsi_port_info_init(struct fsi_priv *fsi, |
1988 | struct sh_fsi_port_info *info) | |
1989 | { | |
1990 | if (info->flags & SH_FSI_FMT_SPDIF) | |
1991 | fsi->spdif = 1; | |
1992 | } | |
1993 | ||
943fdadc KM |
1994 | static void fsi_handler_init(struct fsi_priv *fsi, |
1995 | struct sh_fsi_port_info *info) | |
5e97313a KM |
1996 | { |
1997 | fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */ | |
1998 | fsi->playback.priv = fsi; | |
1999 | fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */ | |
2000 | fsi->capture.priv = fsi; | |
7da9ced6 | 2001 | |
943fdadc KM |
2002 | if (info->tx_id) { |
2003 | fsi->playback.slave.shdma_slave.slave_id = info->tx_id; | |
b8373147 | 2004 | fsi->playback.handler = &fsi_dma_push_handler; |
7da9ced6 | 2005 | } |
5e97313a | 2006 | } |
a4d7d550 | 2007 | |
a4d7d550 KM |
2008 | static int fsi_probe(struct platform_device *pdev) |
2009 | { | |
71f6e064 | 2010 | struct fsi_master *master; |
cc780d38 | 2011 | const struct platform_device_id *id_entry; |
fec691e7 | 2012 | struct sh_fsi_platform_info *info = pdev->dev.platform_data; |
943fdadc | 2013 | struct sh_fsi_port_info nul_info, *pinfo; |
40f9118b | 2014 | struct fsi_priv *fsi; |
a4d7d550 | 2015 | struct resource *res; |
a4d7d550 KM |
2016 | unsigned int irq; |
2017 | int ret; | |
2018 | ||
943fdadc KM |
2019 | nul_info.flags = 0; |
2020 | nul_info.tx_id = 0; | |
2021 | nul_info.rx_id = 0; | |
2022 | ||
cc780d38 KM |
2023 | id_entry = pdev->id_entry; |
2024 | if (!id_entry) { | |
2025 | dev_err(&pdev->dev, "unknown fsi device\n"); | |
2026 | return -ENODEV; | |
2027 | } | |
2028 | ||
a4d7d550 KM |
2029 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2030 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 2031 | if (!res || (int)irq <= 0) { |
a4d7d550 | 2032 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
6ac4262f | 2033 | return -ENODEV; |
a4d7d550 KM |
2034 | } |
2035 | ||
6ac4262f | 2036 | master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); |
a4d7d550 KM |
2037 | if (!master) { |
2038 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
6ac4262f | 2039 | return -ENOMEM; |
a4d7d550 KM |
2040 | } |
2041 | ||
6ac4262f KM |
2042 | master->base = devm_ioremap_nocache(&pdev->dev, |
2043 | res->start, resource_size(res)); | |
a4d7d550 | 2044 | if (!master->base) { |
a4d7d550 | 2045 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); |
6ac4262f | 2046 | return -ENXIO; |
a4d7d550 KM |
2047 | } |
2048 | ||
3bc28070 | 2049 | /* master setting */ |
a4d7d550 | 2050 | master->irq = irq; |
3bc28070 KM |
2051 | master->core = (struct fsi_core *)id_entry->driver_data; |
2052 | spin_lock_init(&master->lock); | |
2053 | ||
2054 | /* FSI A setting */ | |
943fdadc | 2055 | pinfo = (info) ? &info->port_a : &nul_info; |
40f9118b KM |
2056 | fsi = &master->fsia; |
2057 | fsi->base = master->base; | |
2058 | fsi->master = master; | |
943fdadc | 2059 | fsi->info = pinfo; |
c2052def | 2060 | fsi_port_info_init(fsi, pinfo); |
943fdadc | 2061 | fsi_handler_init(fsi, pinfo); |
40f9118b | 2062 | ret = fsi_stream_probe(fsi, &pdev->dev); |
5e97313a KM |
2063 | if (ret < 0) { |
2064 | dev_err(&pdev->dev, "FSIA stream probe failed\n"); | |
6ac4262f | 2065 | return ret; |
5e97313a | 2066 | } |
3bc28070 KM |
2067 | |
2068 | /* FSI B setting */ | |
943fdadc | 2069 | pinfo = (info) ? &info->port_b : &nul_info; |
40f9118b KM |
2070 | fsi = &master->fsib; |
2071 | fsi->base = master->base + 0x40; | |
2072 | fsi->master = master; | |
943fdadc | 2073 | fsi->info = pinfo; |
c2052def | 2074 | fsi_port_info_init(fsi, pinfo); |
943fdadc | 2075 | fsi_handler_init(fsi, pinfo); |
40f9118b | 2076 | ret = fsi_stream_probe(fsi, &pdev->dev); |
5e97313a KM |
2077 | if (ret < 0) { |
2078 | dev_err(&pdev->dev, "FSIB stream probe failed\n"); | |
2079 | goto exit_fsia; | |
2080 | } | |
a4d7d550 | 2081 | |
785d1c45 | 2082 | pm_runtime_enable(&pdev->dev); |
f0fba2ad | 2083 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 2084 | |
1ddd8286 | 2085 | ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0, |
cc780d38 | 2086 | id_entry->name, master); |
a4d7d550 KM |
2087 | if (ret) { |
2088 | dev_err(&pdev->dev, "irq request err\n"); | |
5e97313a | 2089 | goto exit_fsib; |
a4d7d550 KM |
2090 | } |
2091 | ||
f0fba2ad | 2092 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
2093 | if (ret < 0) { |
2094 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1ddd8286 | 2095 | goto exit_fsib; |
a4d7d550 KM |
2096 | } |
2097 | ||
0b5ec87d KM |
2098 | ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai, |
2099 | ARRAY_SIZE(fsi_soc_dai)); | |
2100 | if (ret < 0) { | |
2101 | dev_err(&pdev->dev, "cannot snd dai register\n"); | |
2102 | goto exit_snd_soc; | |
2103 | } | |
a4d7d550 | 2104 | |
0b5ec87d KM |
2105 | return ret; |
2106 | ||
2107 | exit_snd_soc: | |
2108 | snd_soc_unregister_platform(&pdev->dev); | |
5e97313a | 2109 | exit_fsib: |
c35e005f | 2110 | pm_runtime_disable(&pdev->dev); |
5e97313a KM |
2111 | fsi_stream_remove(&master->fsib); |
2112 | exit_fsia: | |
2113 | fsi_stream_remove(&master->fsia); | |
6ac4262f | 2114 | |
a4d7d550 KM |
2115 | return ret; |
2116 | } | |
2117 | ||
2118 | static int fsi_remove(struct platform_device *pdev) | |
2119 | { | |
71f6e064 KM |
2120 | struct fsi_master *master; |
2121 | ||
f0fba2ad | 2122 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 2123 | |
785d1c45 | 2124 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 2125 | |
d985f27e KM |
2126 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); |
2127 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 | 2128 | |
5e97313a KM |
2129 | fsi_stream_remove(&master->fsia); |
2130 | fsi_stream_remove(&master->fsib); | |
2131 | ||
a4d7d550 KM |
2132 | return 0; |
2133 | } | |
2134 | ||
106c79ec | 2135 | static void __fsi_suspend(struct fsi_priv *fsi, |
938e2a8d | 2136 | struct fsi_stream *io, |
4f56cde1 | 2137 | struct device *dev) |
106c79ec | 2138 | { |
938e2a8d | 2139 | if (!fsi_stream_is_working(fsi, io)) |
cda828ca | 2140 | return; |
106c79ec | 2141 | |
180346ed | 2142 | fsi_stream_stop(fsi, io); |
41bba151 | 2143 | fsi_hw_shutdown(fsi, dev); |
106c79ec KM |
2144 | } |
2145 | ||
2146 | static void __fsi_resume(struct fsi_priv *fsi, | |
938e2a8d | 2147 | struct fsi_stream *io, |
4f56cde1 | 2148 | struct device *dev) |
106c79ec | 2149 | { |
938e2a8d | 2150 | if (!fsi_stream_is_working(fsi, io)) |
cda828ca | 2151 | return; |
106c79ec | 2152 | |
938e2a8d | 2153 | fsi_hw_startup(fsi, io, dev); |
180346ed | 2154 | fsi_stream_start(fsi, io); |
106c79ec KM |
2155 | } |
2156 | ||
2157 | static int fsi_suspend(struct device *dev) | |
2158 | { | |
2159 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
2160 | struct fsi_priv *fsia = &master->fsia; |
2161 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 2162 | |
938e2a8d KM |
2163 | __fsi_suspend(fsia, &fsia->playback, dev); |
2164 | __fsi_suspend(fsia, &fsia->capture, dev); | |
106c79ec | 2165 | |
938e2a8d KM |
2166 | __fsi_suspend(fsib, &fsib->playback, dev); |
2167 | __fsi_suspend(fsib, &fsib->capture, dev); | |
106c79ec KM |
2168 | |
2169 | return 0; | |
2170 | } | |
2171 | ||
2172 | static int fsi_resume(struct device *dev) | |
2173 | { | |
2174 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
2175 | struct fsi_priv *fsia = &master->fsia; |
2176 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 2177 | |
938e2a8d KM |
2178 | __fsi_resume(fsia, &fsia->playback, dev); |
2179 | __fsi_resume(fsia, &fsia->capture, dev); | |
106c79ec | 2180 | |
938e2a8d KM |
2181 | __fsi_resume(fsib, &fsib->playback, dev); |
2182 | __fsi_resume(fsib, &fsib->capture, dev); | |
106c79ec KM |
2183 | |
2184 | return 0; | |
2185 | } | |
2186 | ||
785d1c45 | 2187 | static struct dev_pm_ops fsi_pm_ops = { |
106c79ec KM |
2188 | .suspend = fsi_suspend, |
2189 | .resume = fsi_resume, | |
785d1c45 KM |
2190 | }; |
2191 | ||
73b92c1f KM |
2192 | static struct fsi_core fsi1_core = { |
2193 | .ver = 1, | |
2194 | ||
2195 | /* Interrupt */ | |
cc780d38 KM |
2196 | .int_st = INT_ST, |
2197 | .iemsk = IEMSK, | |
2198 | .imsk = IMSK, | |
2199 | }; | |
2200 | ||
73b92c1f KM |
2201 | static struct fsi_core fsi2_core = { |
2202 | .ver = 2, | |
2203 | ||
2204 | /* Interrupt */ | |
cc780d38 KM |
2205 | .int_st = CPU_INT_ST, |
2206 | .iemsk = CPU_IEMSK, | |
2207 | .imsk = CPU_IMSK, | |
2b0e7302 KM |
2208 | .a_mclk = A_MST_CTLR, |
2209 | .b_mclk = B_MST_CTLR, | |
cc780d38 KM |
2210 | }; |
2211 | ||
2212 | static struct platform_device_id fsi_id_table[] = { | |
73b92c1f KM |
2213 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
2214 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
05c69450 | 2215 | {}, |
cc780d38 | 2216 | }; |
d85a6d7b | 2217 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 2218 | |
a4d7d550 KM |
2219 | static struct platform_driver fsi_driver = { |
2220 | .driver = { | |
f0fba2ad | 2221 | .name = "fsi-pcm-audio", |
785d1c45 | 2222 | .pm = &fsi_pm_ops, |
a4d7d550 KM |
2223 | }, |
2224 | .probe = fsi_probe, | |
2225 | .remove = fsi_remove, | |
cc780d38 | 2226 | .id_table = fsi_id_table, |
a4d7d550 KM |
2227 | }; |
2228 | ||
cb5e8738 | 2229 | module_platform_driver(fsi_driver); |
a4d7d550 KM |
2230 | |
2231 | MODULE_LICENSE("GPL"); | |
2232 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
2233 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); | |
b3c27b51 | 2234 | MODULE_ALIAS("platform:fsi-pcm-audio"); |