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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
785d1c45 | 16 | #include <linux/pm_runtime.h> |
a4d7d550 | 17 | #include <linux/io.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
a4d7d550 | 19 | #include <sound/soc.h> |
a4d7d550 | 20 | #include <sound/sh_fsi.h> |
a4d7d550 KM |
21 | |
22 | #define DO_FMT 0x0000 | |
23 | #define DOFF_CTL 0x0004 | |
24 | #define DOFF_ST 0x0008 | |
25 | #define DI_FMT 0x000C | |
26 | #define DIFF_CTL 0x0010 | |
27 | #define DIFF_ST 0x0014 | |
28 | #define CKG1 0x0018 | |
29 | #define CKG2 0x001C | |
30 | #define DIDT 0x0020 | |
31 | #define DODT 0x0024 | |
32 | #define MUTE_ST 0x0028 | |
3bc28070 KM |
33 | #define OUT_SEL 0x0030 |
34 | #define REG_END OUT_SEL | |
cc780d38 | 35 | |
3bc28070 KM |
36 | #define A_MST_CTLR 0x0180 |
37 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
38 | #define CPU_INT_ST 0x01F4 |
39 | #define CPU_IEMSK 0x01F8 | |
40 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
41 | #define INT_ST 0x0200 |
42 | #define IEMSK 0x0204 | |
43 | #define IMSK 0x0208 | |
44 | #define MUTE 0x020C | |
45 | #define CLK_RST 0x0210 | |
46 | #define SOFT_RST 0x0214 | |
4a942b45 | 47 | #define FIFO_SZ 0x0218 |
3bc28070 | 48 | #define MREG_START A_MST_CTLR |
4a942b45 | 49 | #define MREG_END FIFO_SZ |
a4d7d550 KM |
50 | |
51 | /* DO_FMT */ | |
52 | /* DI_FMT */ | |
a7ffb52b KM |
53 | #define CR_MONO (0x0 << 4) |
54 | #define CR_MONO_D (0x1 << 4) | |
55 | #define CR_PCM (0x2 << 4) | |
56 | #define CR_I2S (0x3 << 4) | |
57 | #define CR_TDM (0x4 << 4) | |
58 | #define CR_TDM_D (0x5 << 4) | |
3bc28070 | 59 | #define CR_SPDIF 0x00100120 |
a4d7d550 KM |
60 | |
61 | /* DOFF_CTL */ | |
62 | /* DIFF_CTL */ | |
63 | #define IRQ_HALF 0x00100000 | |
64 | #define FIFO_CLR 0x00000001 | |
65 | ||
66 | /* DOFF_ST */ | |
67 | #define ERR_OVER 0x00000010 | |
68 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 69 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 70 | |
ccad7b44 KM |
71 | /* CKG1 */ |
72 | #define ACKMD_MASK 0x00007000 | |
73 | #define BPFMD_MASK 0x00000700 | |
74 | ||
3bc28070 KM |
75 | /* A/B MST_CTLR */ |
76 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
77 | #define SE (1 << 0) /* Fix the master clock */ | |
78 | ||
a4d7d550 KM |
79 | /* CLK_RST */ |
80 | #define B_CLK 0x00000010 | |
81 | #define A_CLK 0x00000001 | |
82 | ||
cf6edd00 KM |
83 | /* IO SHIFT / MACRO */ |
84 | #define BI_SHIFT 12 | |
85 | #define BO_SHIFT 8 | |
86 | #define AI_SHIFT 4 | |
87 | #define AO_SHIFT 0 | |
88 | #define AB_IO(param, shift) (param << shift) | |
a4d7d550 | 89 | |
feb58cff KM |
90 | /* SOFT_RST */ |
91 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
92 | #define PASR (1 << 8) /* Port A Software Reset */ | |
93 | #define IR (1 << 4) /* Interrupt Reset */ | |
94 | #define FSISR (1 << 0) /* Software Reset */ | |
95 | ||
4a942b45 | 96 | /* FIFO_SZ */ |
cf6edd00 | 97 | #define FIFO_SZ_MASK 0x7 |
4a942b45 | 98 | |
a4d7d550 KM |
99 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
100 | ||
101 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
102 | ||
5bfb9ad0 KM |
103 | /* |
104 | * FSI driver use below type name for variable | |
105 | * | |
106 | * xxx_len : data length | |
107 | * xxx_width : data width | |
108 | * xxx_offset : data offset | |
109 | * xxx_num : number of data | |
110 | */ | |
111 | ||
c8fe2574 KM |
112 | /* |
113 | * struct | |
114 | */ | |
a4d7d550 | 115 | |
93193c2b | 116 | struct fsi_stream { |
a4d7d550 KM |
117 | struct snd_pcm_substream *substream; |
118 | ||
5bfb9ad0 KM |
119 | int fifo_max_num; |
120 | int chan_num; | |
a4d7d550 | 121 | |
5bfb9ad0 KM |
122 | int buff_offset; |
123 | int buff_len; | |
a4d7d550 | 124 | int period_len; |
5bfb9ad0 | 125 | int period_num; |
93193c2b KM |
126 | }; |
127 | ||
128 | struct fsi_priv { | |
129 | void __iomem *base; | |
130 | struct fsi_master *master; | |
131 | ||
132 | struct fsi_stream playback; | |
133 | struct fsi_stream capture; | |
3bc28070 | 134 | |
d4bc99b9 KM |
135 | long rate; |
136 | ||
3bc28070 | 137 | u32 mst_ctrl; |
a4d7d550 KM |
138 | }; |
139 | ||
73b92c1f KM |
140 | struct fsi_core { |
141 | int ver; | |
142 | ||
cc780d38 KM |
143 | u32 int_st; |
144 | u32 iemsk; | |
145 | u32 imsk; | |
146 | }; | |
147 | ||
a4d7d550 KM |
148 | struct fsi_master { |
149 | void __iomem *base; | |
150 | int irq; | |
a4d7d550 KM |
151 | struct fsi_priv fsia; |
152 | struct fsi_priv fsib; | |
73b92c1f | 153 | struct fsi_core *core; |
a4d7d550 | 154 | struct sh_fsi_platform_info *info; |
8fc176d5 | 155 | spinlock_t lock; |
a4d7d550 KM |
156 | }; |
157 | ||
c8fe2574 KM |
158 | /* |
159 | * basic read write function | |
160 | */ | |
a4d7d550 | 161 | |
0f69d978 | 162 | static void __fsi_reg_write(u32 reg, u32 data) |
a4d7d550 KM |
163 | { |
164 | /* valid data area is 24bit */ | |
165 | data &= 0x00ffffff; | |
166 | ||
0f69d978 | 167 | __raw_writel(data, reg); |
a4d7d550 KM |
168 | } |
169 | ||
170 | static u32 __fsi_reg_read(u32 reg) | |
171 | { | |
0f69d978 | 172 | return __raw_readl(reg); |
a4d7d550 KM |
173 | } |
174 | ||
0f69d978 | 175 | static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data) |
a4d7d550 KM |
176 | { |
177 | u32 val = __fsi_reg_read(reg); | |
178 | ||
179 | val &= ~mask; | |
180 | val |= data & mask; | |
181 | ||
0f69d978 | 182 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
183 | } |
184 | ||
0f69d978 | 185 | static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data) |
a4d7d550 | 186 | { |
d7854147 KM |
187 | if (reg > REG_END) { |
188 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 189 | return; |
d7854147 | 190 | } |
a4d7d550 | 191 | |
0f69d978 | 192 | __fsi_reg_write((u32)(fsi->base + reg), data); |
a4d7d550 KM |
193 | } |
194 | ||
195 | static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg) | |
196 | { | |
d7854147 KM |
197 | if (reg > REG_END) { |
198 | pr_err("fsi: register access err (%s)\n", __func__); | |
a4d7d550 | 199 | return 0; |
d7854147 | 200 | } |
a4d7d550 KM |
201 | |
202 | return __fsi_reg_read((u32)(fsi->base + reg)); | |
203 | } | |
204 | ||
0f69d978 | 205 | static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data) |
a4d7d550 | 206 | { |
d7854147 KM |
207 | if (reg > REG_END) { |
208 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 209 | return; |
d7854147 | 210 | } |
a4d7d550 | 211 | |
0f69d978 | 212 | __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data); |
a4d7d550 KM |
213 | } |
214 | ||
0f69d978 | 215 | static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data) |
a4d7d550 | 216 | { |
8fc176d5 KM |
217 | unsigned long flags; |
218 | ||
a4d7d550 | 219 | if ((reg < MREG_START) || |
d7854147 KM |
220 | (reg > MREG_END)) { |
221 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 222 | return; |
d7854147 | 223 | } |
a4d7d550 | 224 | |
8fc176d5 | 225 | spin_lock_irqsave(&master->lock, flags); |
0f69d978 | 226 | __fsi_reg_write((u32)(master->base + reg), data); |
8fc176d5 | 227 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
228 | } |
229 | ||
71f6e064 | 230 | static u32 fsi_master_read(struct fsi_master *master, u32 reg) |
a4d7d550 | 231 | { |
8fc176d5 KM |
232 | u32 ret; |
233 | unsigned long flags; | |
234 | ||
a4d7d550 | 235 | if ((reg < MREG_START) || |
d7854147 KM |
236 | (reg > MREG_END)) { |
237 | pr_err("fsi: register access err (%s)\n", __func__); | |
a4d7d550 | 238 | return 0; |
d7854147 | 239 | } |
a4d7d550 | 240 | |
8fc176d5 KM |
241 | spin_lock_irqsave(&master->lock, flags); |
242 | ret = __fsi_reg_read((u32)(master->base + reg)); | |
243 | spin_unlock_irqrestore(&master->lock, flags); | |
244 | ||
245 | return ret; | |
a4d7d550 KM |
246 | } |
247 | ||
0f69d978 | 248 | static void fsi_master_mask_set(struct fsi_master *master, |
71f6e064 | 249 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 250 | { |
8fc176d5 KM |
251 | unsigned long flags; |
252 | ||
a4d7d550 | 253 | if ((reg < MREG_START) || |
d7854147 KM |
254 | (reg > MREG_END)) { |
255 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 256 | return; |
d7854147 | 257 | } |
a4d7d550 | 258 | |
8fc176d5 | 259 | spin_lock_irqsave(&master->lock, flags); |
0f69d978 | 260 | __fsi_reg_mask_set((u32)(master->base + reg), mask, data); |
8fc176d5 | 261 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
262 | } |
263 | ||
c8fe2574 KM |
264 | /* |
265 | * basic function | |
266 | */ | |
a4d7d550 | 267 | |
71f6e064 | 268 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 269 | { |
71f6e064 | 270 | return fsi->master; |
a4d7d550 KM |
271 | } |
272 | ||
273 | static int fsi_is_port_a(struct fsi_priv *fsi) | |
274 | { | |
71f6e064 KM |
275 | return fsi->master->base == fsi->base; |
276 | } | |
a4d7d550 | 277 | |
142e8174 | 278 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
279 | { |
280 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 281 | |
f0fba2ad | 282 | return rtd->cpu_dai; |
142e8174 KM |
283 | } |
284 | ||
285 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) | |
286 | { | |
287 | struct snd_soc_dai *dai = fsi_get_dai(substream); | |
f0fba2ad | 288 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 289 | |
f0fba2ad LG |
290 | if (dai->id == 0) |
291 | return &master->fsia; | |
292 | else | |
293 | return &master->fsib; | |
a4d7d550 KM |
294 | } |
295 | ||
296 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) | |
297 | { | |
298 | int is_porta = fsi_is_port_a(fsi); | |
71f6e064 | 299 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
300 | |
301 | return is_porta ? master->info->porta_flags : | |
302 | master->info->portb_flags; | |
303 | } | |
304 | ||
93193c2b KM |
305 | static inline int fsi_stream_is_play(int stream) |
306 | { | |
307 | return stream == SNDRV_PCM_STREAM_PLAYBACK; | |
308 | } | |
309 | ||
00545785 KM |
310 | static inline int fsi_is_play(struct snd_pcm_substream *substream) |
311 | { | |
93193c2b KM |
312 | return fsi_stream_is_play(substream->stream); |
313 | } | |
314 | ||
315 | static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi, | |
316 | int is_play) | |
317 | { | |
318 | return is_play ? &fsi->playback : &fsi->capture; | |
00545785 KM |
319 | } |
320 | ||
a4d7d550 KM |
321 | static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play) |
322 | { | |
323 | u32 mode; | |
324 | u32 flags = fsi_get_info_flags(fsi); | |
325 | ||
326 | mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE; | |
327 | ||
328 | /* return | |
329 | * 1 : master mode | |
330 | * 0 : slave mode | |
331 | */ | |
332 | ||
333 | return (mode & flags) != mode; | |
334 | } | |
335 | ||
cf6edd00 | 336 | static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
337 | { |
338 | int is_porta = fsi_is_port_a(fsi); | |
cf6edd00 | 339 | u32 shift; |
a4d7d550 KM |
340 | |
341 | if (is_porta) | |
cf6edd00 | 342 | shift = is_play ? AO_SHIFT : AI_SHIFT; |
a4d7d550 | 343 | else |
cf6edd00 | 344 | shift = is_play ? BO_SHIFT : BI_SHIFT; |
a4d7d550 | 345 | |
cf6edd00 | 346 | return shift; |
a4d7d550 KM |
347 | } |
348 | ||
349 | static void fsi_stream_push(struct fsi_priv *fsi, | |
93193c2b | 350 | int is_play, |
a4d7d550 KM |
351 | struct snd_pcm_substream *substream, |
352 | u32 buffer_len, | |
353 | u32 period_len) | |
354 | { | |
93193c2b KM |
355 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
356 | ||
357 | io->substream = substream; | |
358 | io->buff_len = buffer_len; | |
359 | io->buff_offset = 0; | |
360 | io->period_len = period_len; | |
361 | io->period_num = 0; | |
a4d7d550 KM |
362 | } |
363 | ||
93193c2b | 364 | static void fsi_stream_pop(struct fsi_priv *fsi, int is_play) |
a4d7d550 | 365 | { |
93193c2b KM |
366 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
367 | ||
368 | io->substream = NULL; | |
369 | io->buff_len = 0; | |
370 | io->buff_offset = 0; | |
371 | io->period_len = 0; | |
372 | io->period_num = 0; | |
a4d7d550 KM |
373 | } |
374 | ||
5bfb9ad0 | 375 | static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
376 | { |
377 | u32 status; | |
378 | u32 reg = is_play ? DOFF_ST : DIFF_ST; | |
93193c2b | 379 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
5bfb9ad0 | 380 | int data_num; |
a4d7d550 KM |
381 | |
382 | status = fsi_reg_read(fsi, reg); | |
5bfb9ad0 | 383 | data_num = 0x1ff & (status >> 8); |
93193c2b | 384 | data_num *= io->chan_num; |
5bfb9ad0 KM |
385 | |
386 | return data_num; | |
387 | } | |
a4d7d550 | 388 | |
5bfb9ad0 KM |
389 | static int fsi_len2num(int len, int width) |
390 | { | |
391 | return len / width; | |
392 | } | |
393 | ||
394 | #define fsi_num2offset(a, b) fsi_num2len(a, b) | |
395 | static int fsi_num2len(int num, int width) | |
396 | { | |
397 | return num * width; | |
a4d7d550 KM |
398 | } |
399 | ||
93193c2b | 400 | static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play) |
cca1b235 | 401 | { |
93193c2b KM |
402 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
403 | struct snd_pcm_substream *substream = io->substream; | |
cca1b235 KM |
404 | struct snd_pcm_runtime *runtime = substream->runtime; |
405 | ||
93193c2b | 406 | return frames_to_bytes(runtime, 1) / io->chan_num; |
cca1b235 KM |
407 | } |
408 | ||
b9fde18c KM |
409 | /* |
410 | * dma function | |
411 | */ | |
412 | ||
93193c2b | 413 | static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream) |
c79eab3e | 414 | { |
93193c2b KM |
415 | int is_play = fsi_stream_is_play(stream); |
416 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
417 | ||
418 | return io->substream->runtime->dma_area + io->buff_offset; | |
c79eab3e KM |
419 | } |
420 | ||
5bfb9ad0 | 421 | static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
422 | { |
423 | u16 *start; | |
424 | int i; | |
425 | ||
93193c2b | 426 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
b9fde18c | 427 | |
5bfb9ad0 | 428 | for (i = 0; i < num; i++) |
b9fde18c KM |
429 | fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8)); |
430 | } | |
431 | ||
5bfb9ad0 | 432 | static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
433 | { |
434 | u16 *start; | |
435 | int i; | |
436 | ||
93193c2b KM |
437 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
438 | ||
b9fde18c | 439 | |
5bfb9ad0 | 440 | for (i = 0; i < num; i++) |
b9fde18c KM |
441 | *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); |
442 | } | |
443 | ||
5bfb9ad0 | 444 | static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
445 | { |
446 | u32 *start; | |
447 | int i; | |
448 | ||
93193c2b KM |
449 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
450 | ||
b9fde18c | 451 | |
5bfb9ad0 | 452 | for (i = 0; i < num; i++) |
b9fde18c KM |
453 | fsi_reg_write(fsi, DODT, *(start + i)); |
454 | } | |
455 | ||
5bfb9ad0 | 456 | static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
457 | { |
458 | u32 *start; | |
459 | int i; | |
460 | ||
93193c2b | 461 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
b9fde18c | 462 | |
5bfb9ad0 | 463 | for (i = 0; i < num; i++) |
b9fde18c KM |
464 | *(start + i) = fsi_reg_read(fsi, DIDT); |
465 | } | |
466 | ||
c8fe2574 KM |
467 | /* |
468 | * irq function | |
469 | */ | |
a4d7d550 | 470 | |
a4d7d550 KM |
471 | static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) |
472 | { | |
cf6edd00 | 473 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 474 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 475 | |
73b92c1f KM |
476 | fsi_master_mask_set(master, master->core->imsk, data, data); |
477 | fsi_master_mask_set(master, master->core->iemsk, data, data); | |
a4d7d550 KM |
478 | } |
479 | ||
480 | static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | |
481 | { | |
cf6edd00 | 482 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 483 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 484 | |
73b92c1f KM |
485 | fsi_master_mask_set(master, master->core->imsk, data, 0); |
486 | fsi_master_mask_set(master, master->core->iemsk, data, 0); | |
a4d7d550 KM |
487 | } |
488 | ||
10ea76cc KM |
489 | static u32 fsi_irq_get_status(struct fsi_master *master) |
490 | { | |
73b92c1f | 491 | return fsi_master_read(master, master->core->int_st); |
10ea76cc KM |
492 | } |
493 | ||
494 | static void fsi_irq_clear_all_status(struct fsi_master *master) | |
495 | { | |
73b92c1f | 496 | fsi_master_write(master, master->core->int_st, 0); |
a4d7d550 KM |
497 | } |
498 | ||
10ea76cc KM |
499 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
500 | { | |
501 | u32 data = 0; | |
502 | struct fsi_master *master = fsi_get_master(fsi); | |
503 | ||
cf6edd00 KM |
504 | data |= AB_IO(1, fsi_get_port_shift(fsi, 0)); |
505 | data |= AB_IO(1, fsi_get_port_shift(fsi, 1)); | |
10ea76cc KM |
506 | |
507 | /* clear interrupt factor */ | |
73b92c1f | 508 | fsi_master_mask_set(master, master->core->int_st, data, 0); |
10ea76cc KM |
509 | } |
510 | ||
c8fe2574 KM |
511 | /* |
512 | * SPDIF master clock function | |
513 | * | |
514 | * These functions are used later FSI2 | |
515 | */ | |
3bc28070 KM |
516 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
517 | { | |
518 | struct fsi_master *master = fsi_get_master(fsi); | |
519 | u32 val = BP | SE; | |
520 | ||
521 | if (master->core->ver < 2) { | |
522 | pr_err("fsi: register access err (%s)\n", __func__); | |
523 | return; | |
524 | } | |
525 | ||
526 | if (enable) | |
527 | fsi_master_mask_set(master, fsi->mst_ctrl, val, val); | |
528 | else | |
529 | fsi_master_mask_set(master, fsi->mst_ctrl, val, 0); | |
530 | } | |
531 | ||
c8fe2574 KM |
532 | /* |
533 | * ctrl function | |
534 | */ | |
10ea76cc | 535 | |
a4d7d550 KM |
536 | static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable) |
537 | { | |
538 | u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4); | |
71f6e064 | 539 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
540 | |
541 | if (enable) | |
71f6e064 | 542 | fsi_master_mask_set(master, CLK_RST, val, val); |
a4d7d550 | 543 | else |
71f6e064 | 544 | fsi_master_mask_set(master, CLK_RST, val, 0); |
a4d7d550 KM |
545 | } |
546 | ||
4a942b45 KM |
547 | static void fsi_fifo_init(struct fsi_priv *fsi, |
548 | int is_play, | |
549 | struct snd_soc_dai *dai) | |
a4d7d550 | 550 | { |
4a942b45 | 551 | struct fsi_master *master = fsi_get_master(fsi); |
93193c2b | 552 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
4a942b45 | 553 | u32 ctrl, shift, i; |
a4d7d550 | 554 | |
4a942b45 KM |
555 | /* get on-chip RAM capacity */ |
556 | shift = fsi_master_read(master, FIFO_SZ); | |
cf6edd00 KM |
557 | shift >>= fsi_get_port_shift(fsi, is_play); |
558 | shift &= FIFO_SZ_MASK; | |
93193c2b KM |
559 | io->fifo_max_num = 256 << shift; |
560 | dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num); | |
a4d7d550 | 561 | |
4a942b45 KM |
562 | /* |
563 | * The maximum number of sample data varies depending | |
564 | * on the number of channels selected for the format. | |
565 | * | |
566 | * FIFOs are used in 4-channel units in 3-channel mode | |
567 | * and in 8-channel units in 5- to 7-channel mode | |
568 | * meaning that more FIFOs than the required size of DPRAM | |
569 | * are used. | |
570 | * | |
571 | * ex) if 256 words of DP-RAM is connected | |
572 | * 1 channel: 256 (256 x 1 = 256) | |
573 | * 2 channels: 128 (128 x 2 = 256) | |
574 | * 3 channels: 64 ( 64 x 3 = 192) | |
575 | * 4 channels: 64 ( 64 x 4 = 256) | |
576 | * 5 channels: 32 ( 32 x 5 = 160) | |
577 | * 6 channels: 32 ( 32 x 6 = 192) | |
578 | * 7 channels: 32 ( 32 x 7 = 224) | |
579 | * 8 channels: 32 ( 32 x 8 = 256) | |
580 | */ | |
93193c2b KM |
581 | for (i = 1; i < io->chan_num; i <<= 1) |
582 | io->fifo_max_num >>= 1; | |
5bfb9ad0 | 583 | dev_dbg(dai->dev, "%d channel %d store\n", |
93193c2b | 584 | io->chan_num, io->fifo_max_num); |
a4d7d550 | 585 | |
a4d7d550 | 586 | ctrl = is_play ? DOFF_CTL : DIFF_CTL; |
a4d7d550 KM |
587 | |
588 | /* set interrupt generation factor */ | |
589 | fsi_reg_write(fsi, ctrl, IRQ_HALF); | |
590 | ||
591 | /* clear FIFO */ | |
592 | fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR); | |
a4d7d550 KM |
593 | } |
594 | ||
71f6e064 | 595 | static void fsi_soft_all_reset(struct fsi_master *master) |
a4d7d550 | 596 | { |
a4d7d550 | 597 | /* port AB reset */ |
feb58cff | 598 | fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0); |
a4d7d550 KM |
599 | mdelay(10); |
600 | ||
601 | /* soft reset */ | |
feb58cff KM |
602 | fsi_master_mask_set(master, SOFT_RST, FSISR, 0); |
603 | fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR); | |
a4d7d550 KM |
604 | mdelay(10); |
605 | } | |
606 | ||
93193c2b | 607 | static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int startup, int stream) |
a4d7d550 KM |
608 | { |
609 | struct snd_pcm_runtime *runtime; | |
610 | struct snd_pcm_substream *substream = NULL; | |
93193c2b KM |
611 | int is_play = fsi_stream_is_play(stream); |
612 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
d8b33534 KM |
613 | u32 status_reg = is_play ? DOFF_ST : DIFF_ST; |
614 | int data_residue_num; | |
615 | int data_num; | |
616 | int data_num_max; | |
5bfb9ad0 | 617 | int ch_width; |
b9fde18c | 618 | int over_period; |
d8b33534 | 619 | void (*fn)(struct fsi_priv *fsi, int size); |
a4d7d550 KM |
620 | |
621 | if (!fsi || | |
93193c2b KM |
622 | !io->substream || |
623 | !io->substream->runtime) | |
a4d7d550 KM |
624 | return -EINVAL; |
625 | ||
1c418d1f | 626 | over_period = 0; |
93193c2b | 627 | substream = io->substream; |
1c418d1f | 628 | runtime = substream->runtime; |
a4d7d550 KM |
629 | |
630 | /* FSI FIFO has limit. | |
631 | * So, this driver can not send periods data at a time | |
632 | */ | |
93193c2b KM |
633 | if (io->buff_offset >= |
634 | fsi_num2offset(io->period_num + 1, io->period_len)) { | |
a4d7d550 | 635 | |
1c418d1f | 636 | over_period = 1; |
93193c2b | 637 | io->period_num = (io->period_num + 1) % runtime->periods; |
a4d7d550 | 638 | |
93193c2b KM |
639 | if (0 == io->period_num) |
640 | io->buff_offset = 0; | |
a4d7d550 KM |
641 | } |
642 | ||
643 | /* get 1 channel data width */ | |
93193c2b | 644 | ch_width = fsi_get_frame_width(fsi, is_play); |
a4d7d550 | 645 | |
d8b33534 | 646 | /* get residue data number of alsa */ |
93193c2b | 647 | data_residue_num = fsi_len2num(io->buff_len - io->buff_offset, |
d8b33534 KM |
648 | ch_width); |
649 | ||
650 | if (is_play) { | |
651 | /* | |
652 | * for play-back | |
653 | * | |
654 | * data_num_max : number of FSI fifo free space | |
655 | * data_num : number of ALSA residue data | |
656 | */ | |
93193c2b | 657 | data_num_max = io->fifo_max_num * io->chan_num; |
d8b33534 KM |
658 | data_num_max -= fsi_get_fifo_data_num(fsi, is_play); |
659 | ||
660 | data_num = data_residue_num; | |
661 | ||
662 | switch (ch_width) { | |
663 | case 2: | |
664 | fn = fsi_dma_soft_push16; | |
665 | break; | |
666 | case 4: | |
667 | fn = fsi_dma_soft_push32; | |
668 | break; | |
669 | default: | |
670 | return -EINVAL; | |
671 | } | |
672 | } else { | |
673 | /* | |
674 | * for capture | |
675 | * | |
676 | * data_num_max : number of ALSA free space | |
677 | * data_num : number of data in FSI fifo | |
678 | */ | |
679 | data_num_max = data_residue_num; | |
680 | data_num = fsi_get_fifo_data_num(fsi, is_play); | |
681 | ||
682 | switch (ch_width) { | |
683 | case 2: | |
684 | fn = fsi_dma_soft_pop16; | |
685 | break; | |
686 | case 4: | |
687 | fn = fsi_dma_soft_pop32; | |
688 | break; | |
689 | default: | |
690 | return -EINVAL; | |
691 | } | |
692 | } | |
a4d7d550 | 693 | |
d8b33534 | 694 | data_num = min(data_num, data_num_max); |
a4d7d550 | 695 | |
d8b33534 | 696 | fn(fsi, data_num); |
a4d7d550 | 697 | |
d8b33534 | 698 | /* update buff_offset */ |
93193c2b | 699 | io->buff_offset += fsi_num2offset(data_num, ch_width); |
a4d7d550 | 700 | |
d8b33534 | 701 | /* check fifo status */ |
47fc9a0a | 702 | if (!startup) { |
59c3b003 | 703 | struct snd_soc_dai *dai = fsi_get_dai(substream); |
75eda968 | 704 | u32 status = fsi_reg_read(fsi, status_reg); |
47fc9a0a KM |
705 | |
706 | if (status & ERR_OVER) | |
707 | dev_err(dai->dev, "over run\n"); | |
708 | if (status & ERR_UNDER) | |
709 | dev_err(dai->dev, "under run\n"); | |
59c3b003 | 710 | } |
d8b33534 | 711 | fsi_reg_write(fsi, status_reg, 0); |
59c3b003 | 712 | |
d8b33534 KM |
713 | /* re-enable irq */ |
714 | fsi_irq_enable(fsi, is_play); | |
a4d7d550 | 715 | |
1c418d1f | 716 | if (over_period) |
a4d7d550 KM |
717 | snd_pcm_period_elapsed(substream); |
718 | ||
47fc9a0a | 719 | return 0; |
a4d7d550 KM |
720 | } |
721 | ||
47fc9a0a | 722 | static int fsi_data_pop(struct fsi_priv *fsi, int startup) |
07102f3c | 723 | { |
93193c2b | 724 | return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_CAPTURE); |
d8b33534 | 725 | } |
07102f3c | 726 | |
d8b33534 KM |
727 | static int fsi_data_push(struct fsi_priv *fsi, int startup) |
728 | { | |
93193c2b | 729 | return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_PLAYBACK); |
07102f3c KM |
730 | } |
731 | ||
a4d7d550 KM |
732 | static irqreturn_t fsi_interrupt(int irq, void *data) |
733 | { | |
71f6e064 | 734 | struct fsi_master *master = data; |
10ea76cc | 735 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
736 | |
737 | /* clear irq status */ | |
feb58cff KM |
738 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
739 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 | 740 | |
cf6edd00 | 741 | if (int_st & AB_IO(1, AO_SHIFT)) |
47fc9a0a | 742 | fsi_data_push(&master->fsia, 0); |
cf6edd00 | 743 | if (int_st & AB_IO(1, BO_SHIFT)) |
47fc9a0a | 744 | fsi_data_push(&master->fsib, 0); |
cf6edd00 | 745 | if (int_st & AB_IO(1, AI_SHIFT)) |
47fc9a0a | 746 | fsi_data_pop(&master->fsia, 0); |
cf6edd00 | 747 | if (int_st & AB_IO(1, BI_SHIFT)) |
47fc9a0a | 748 | fsi_data_pop(&master->fsib, 0); |
a4d7d550 | 749 | |
10ea76cc | 750 | fsi_irq_clear_all_status(master); |
a4d7d550 KM |
751 | |
752 | return IRQ_HANDLED; | |
753 | } | |
754 | ||
c8fe2574 KM |
755 | /* |
756 | * dai ops | |
757 | */ | |
a4d7d550 | 758 | |
a4d7d550 KM |
759 | static int fsi_dai_startup(struct snd_pcm_substream *substream, |
760 | struct snd_soc_dai *dai) | |
761 | { | |
71f6e064 | 762 | struct fsi_priv *fsi = fsi_get_priv(substream); |
3bc28070 | 763 | struct fsi_master *master = fsi_get_master(fsi); |
93193c2b KM |
764 | struct fsi_stream *io; |
765 | u32 flags = fsi_get_info_flags(fsi); | |
a4d7d550 KM |
766 | u32 fmt; |
767 | u32 reg; | |
768 | u32 data; | |
00545785 | 769 | int is_play = fsi_is_play(substream); |
a4d7d550 | 770 | int is_master; |
a4d7d550 | 771 | |
93193c2b KM |
772 | io = fsi_get_stream(fsi, is_play); |
773 | ||
785d1c45 | 774 | pm_runtime_get_sync(dai->dev); |
a4d7d550 KM |
775 | |
776 | /* CKG1 */ | |
777 | data = is_play ? (1 << 0) : (1 << 4); | |
778 | is_master = fsi_is_master_mode(fsi, is_play); | |
779 | if (is_master) | |
780 | fsi_reg_mask_set(fsi, CKG1, data, data); | |
781 | else | |
782 | fsi_reg_mask_set(fsi, CKG1, data, 0); | |
783 | ||
784 | /* clock inversion (CKG2) */ | |
785 | data = 0; | |
b427b44c KM |
786 | if (SH_FSI_LRM_INV & flags) |
787 | data |= 1 << 12; | |
788 | if (SH_FSI_BRM_INV & flags) | |
789 | data |= 1 << 8; | |
790 | if (SH_FSI_LRS_INV & flags) | |
791 | data |= 1 << 4; | |
792 | if (SH_FSI_BRS_INV & flags) | |
793 | data |= 1 << 0; | |
794 | ||
a4d7d550 KM |
795 | fsi_reg_write(fsi, CKG2, data); |
796 | ||
797 | /* do fmt, di fmt */ | |
798 | data = 0; | |
799 | reg = is_play ? DO_FMT : DI_FMT; | |
800 | fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags); | |
801 | switch (fmt) { | |
802 | case SH_FSI_FMT_MONO: | |
a7ffb52b | 803 | data = CR_MONO; |
93193c2b | 804 | io->chan_num = 1; |
a4d7d550 KM |
805 | break; |
806 | case SH_FSI_FMT_MONO_DELAY: | |
a7ffb52b | 807 | data = CR_MONO_D; |
93193c2b | 808 | io->chan_num = 1; |
a4d7d550 KM |
809 | break; |
810 | case SH_FSI_FMT_PCM: | |
a7ffb52b | 811 | data = CR_PCM; |
93193c2b | 812 | io->chan_num = 2; |
a4d7d550 KM |
813 | break; |
814 | case SH_FSI_FMT_I2S: | |
a7ffb52b | 815 | data = CR_I2S; |
93193c2b | 816 | io->chan_num = 2; |
a4d7d550 KM |
817 | break; |
818 | case SH_FSI_FMT_TDM: | |
93193c2b | 819 | io->chan_num = is_play ? |
a4d7d550 | 820 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); |
93193c2b | 821 | data = CR_TDM | (io->chan_num - 1); |
a4d7d550 KM |
822 | break; |
823 | case SH_FSI_FMT_TDM_DELAY: | |
93193c2b | 824 | io->chan_num = is_play ? |
a4d7d550 | 825 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); |
93193c2b | 826 | data = CR_TDM_D | (io->chan_num - 1); |
a4d7d550 | 827 | break; |
3bc28070 KM |
828 | case SH_FSI_FMT_SPDIF: |
829 | if (master->core->ver < 2) { | |
830 | dev_err(dai->dev, "This FSI can not use SPDIF\n"); | |
831 | return -EINVAL; | |
832 | } | |
833 | data = CR_SPDIF; | |
93193c2b | 834 | io->chan_num = 2; |
3bc28070 KM |
835 | fsi_spdif_clk_ctrl(fsi, 1); |
836 | fsi_reg_mask_set(fsi, OUT_SEL, 0x0010, 0x0010); | |
837 | break; | |
a4d7d550 KM |
838 | default: |
839 | dev_err(dai->dev, "unknown format.\n"); | |
840 | return -EINVAL; | |
841 | } | |
a4d7d550 | 842 | fsi_reg_write(fsi, reg, data); |
a4d7d550 | 843 | |
10ea76cc KM |
844 | /* irq clear */ |
845 | fsi_irq_disable(fsi, is_play); | |
846 | fsi_irq_clear_status(fsi); | |
847 | ||
848 | /* fifo init */ | |
4a942b45 | 849 | fsi_fifo_init(fsi, is_play, dai); |
a4d7d550 | 850 | |
a68a3b4e | 851 | return 0; |
a4d7d550 KM |
852 | } |
853 | ||
854 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, | |
855 | struct snd_soc_dai *dai) | |
856 | { | |
71f6e064 | 857 | struct fsi_priv *fsi = fsi_get_priv(substream); |
00545785 | 858 | int is_play = fsi_is_play(substream); |
d4bc99b9 KM |
859 | struct fsi_master *master = fsi_get_master(fsi); |
860 | int (*set_rate)(struct device *dev, int is_porta, int rate, int enable); | |
a4d7d550 KM |
861 | |
862 | fsi_irq_disable(fsi, is_play); | |
863 | fsi_clk_ctrl(fsi, 0); | |
864 | ||
d4bc99b9 KM |
865 | set_rate = master->info->set_rate; |
866 | if (set_rate && fsi->rate) | |
867 | set_rate(dai->dev, fsi_is_port_a(fsi), fsi->rate, 0); | |
868 | fsi->rate = 0; | |
869 | ||
785d1c45 | 870 | pm_runtime_put_sync(dai->dev); |
a4d7d550 KM |
871 | } |
872 | ||
873 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
874 | struct snd_soc_dai *dai) | |
875 | { | |
71f6e064 | 876 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 | 877 | struct snd_pcm_runtime *runtime = substream->runtime; |
00545785 | 878 | int is_play = fsi_is_play(substream); |
a4d7d550 KM |
879 | int ret = 0; |
880 | ||
a4d7d550 KM |
881 | switch (cmd) { |
882 | case SNDRV_PCM_TRIGGER_START: | |
93193c2b | 883 | fsi_stream_push(fsi, is_play, substream, |
a4d7d550 KM |
884 | frames_to_bytes(runtime, runtime->buffer_size), |
885 | frames_to_bytes(runtime, runtime->period_size)); | |
47fc9a0a | 886 | ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1); |
a4d7d550 KM |
887 | break; |
888 | case SNDRV_PCM_TRIGGER_STOP: | |
889 | fsi_irq_disable(fsi, is_play); | |
93193c2b | 890 | fsi_stream_pop(fsi, is_play); |
a4d7d550 KM |
891 | break; |
892 | } | |
893 | ||
894 | return ret; | |
895 | } | |
896 | ||
ccad7b44 KM |
897 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
898 | struct snd_pcm_hw_params *params, | |
899 | struct snd_soc_dai *dai) | |
900 | { | |
901 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
902 | struct fsi_master *master = fsi_get_master(fsi); | |
d4bc99b9 | 903 | int (*set_rate)(struct device *dev, int is_porta, int rate, int enable); |
ccad7b44 | 904 | int fsi_ver = master->core->ver; |
00545785 | 905 | int is_play = fsi_is_play(substream); |
d4bc99b9 | 906 | long rate = params_rate(params); |
ccad7b44 KM |
907 | int ret; |
908 | ||
909 | /* if slave mode, set_rate is not needed */ | |
910 | if (!fsi_is_master_mode(fsi, is_play)) | |
911 | return 0; | |
912 | ||
913 | /* it is error if no set_rate */ | |
d4bc99b9 | 914 | set_rate = master->info->set_rate; |
ccad7b44 KM |
915 | if (!set_rate) |
916 | return -EIO; | |
917 | ||
d4bc99b9 KM |
918 | ret = set_rate(dai->dev, fsi_is_port_a(fsi), rate, 1); |
919 | if (ret < 0) /* error */ | |
920 | return ret; | |
921 | ||
922 | fsi->rate = rate; | |
ccad7b44 KM |
923 | if (ret > 0) { |
924 | u32 data = 0; | |
925 | ||
926 | switch (ret & SH_FSI_ACKMD_MASK) { | |
927 | default: | |
928 | /* FALL THROUGH */ | |
929 | case SH_FSI_ACKMD_512: | |
930 | data |= (0x0 << 12); | |
931 | break; | |
932 | case SH_FSI_ACKMD_256: | |
933 | data |= (0x1 << 12); | |
934 | break; | |
935 | case SH_FSI_ACKMD_128: | |
936 | data |= (0x2 << 12); | |
937 | break; | |
938 | case SH_FSI_ACKMD_64: | |
939 | data |= (0x3 << 12); | |
940 | break; | |
941 | case SH_FSI_ACKMD_32: | |
942 | if (fsi_ver < 2) | |
943 | dev_err(dai->dev, "unsupported ACKMD\n"); | |
944 | else | |
945 | data |= (0x4 << 12); | |
946 | break; | |
947 | } | |
948 | ||
949 | switch (ret & SH_FSI_BPFMD_MASK) { | |
950 | default: | |
951 | /* FALL THROUGH */ | |
952 | case SH_FSI_BPFMD_32: | |
953 | data |= (0x0 << 8); | |
954 | break; | |
955 | case SH_FSI_BPFMD_64: | |
956 | data |= (0x1 << 8); | |
957 | break; | |
958 | case SH_FSI_BPFMD_128: | |
959 | data |= (0x2 << 8); | |
960 | break; | |
961 | case SH_FSI_BPFMD_256: | |
962 | data |= (0x3 << 8); | |
963 | break; | |
964 | case SH_FSI_BPFMD_512: | |
965 | data |= (0x4 << 8); | |
966 | break; | |
967 | case SH_FSI_BPFMD_16: | |
968 | if (fsi_ver < 2) | |
969 | dev_err(dai->dev, "unsupported ACKMD\n"); | |
970 | else | |
971 | data |= (0x7 << 8); | |
972 | break; | |
973 | } | |
974 | ||
975 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
976 | udelay(10); | |
977 | fsi_clk_ctrl(fsi, 1); | |
978 | ret = 0; | |
979 | } | |
ccad7b44 KM |
980 | |
981 | return ret; | |
982 | ||
983 | } | |
984 | ||
a4d7d550 KM |
985 | static struct snd_soc_dai_ops fsi_dai_ops = { |
986 | .startup = fsi_dai_startup, | |
987 | .shutdown = fsi_dai_shutdown, | |
988 | .trigger = fsi_dai_trigger, | |
ccad7b44 | 989 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
990 | }; |
991 | ||
c8fe2574 KM |
992 | /* |
993 | * pcm ops | |
994 | */ | |
a4d7d550 | 995 | |
a4d7d550 KM |
996 | static struct snd_pcm_hardware fsi_pcm_hardware = { |
997 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
998 | SNDRV_PCM_INFO_MMAP | | |
999 | SNDRV_PCM_INFO_MMAP_VALID | | |
1000 | SNDRV_PCM_INFO_PAUSE, | |
1001 | .formats = FSI_FMTS, | |
1002 | .rates = FSI_RATES, | |
1003 | .rate_min = 8000, | |
1004 | .rate_max = 192000, | |
1005 | .channels_min = 1, | |
1006 | .channels_max = 2, | |
1007 | .buffer_bytes_max = 64 * 1024, | |
1008 | .period_bytes_min = 32, | |
1009 | .period_bytes_max = 8192, | |
1010 | .periods_min = 1, | |
1011 | .periods_max = 32, | |
1012 | .fifo_size = 256, | |
1013 | }; | |
1014 | ||
1015 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
1016 | { | |
1017 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1018 | int ret = 0; | |
1019 | ||
1020 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
1021 | ||
1022 | ret = snd_pcm_hw_constraint_integer(runtime, | |
1023 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1024 | ||
1025 | return ret; | |
1026 | } | |
1027 | ||
1028 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
1029 | struct snd_pcm_hw_params *hw_params) | |
1030 | { | |
1031 | return snd_pcm_lib_malloc_pages(substream, | |
1032 | params_buffer_bytes(hw_params)); | |
1033 | } | |
1034 | ||
1035 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
1036 | { | |
1037 | return snd_pcm_lib_free_pages(substream); | |
1038 | } | |
1039 | ||
1040 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
1041 | { | |
1042 | struct snd_pcm_runtime *runtime = substream->runtime; | |
71f6e064 | 1043 | struct fsi_priv *fsi = fsi_get_priv(substream); |
93193c2b | 1044 | struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream)); |
a4d7d550 KM |
1045 | long location; |
1046 | ||
93193c2b | 1047 | location = (io->buff_offset - 1); |
a4d7d550 KM |
1048 | if (location < 0) |
1049 | location = 0; | |
1050 | ||
1051 | return bytes_to_frames(runtime, location); | |
1052 | } | |
1053 | ||
1054 | static struct snd_pcm_ops fsi_pcm_ops = { | |
1055 | .open = fsi_pcm_open, | |
1056 | .ioctl = snd_pcm_lib_ioctl, | |
1057 | .hw_params = fsi_hw_params, | |
1058 | .hw_free = fsi_hw_free, | |
1059 | .pointer = fsi_pointer, | |
1060 | }; | |
1061 | ||
c8fe2574 KM |
1062 | /* |
1063 | * snd_soc_platform | |
1064 | */ | |
a4d7d550 | 1065 | |
a4d7d550 KM |
1066 | #define PREALLOC_BUFFER (32 * 1024) |
1067 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1068 | ||
1069 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1070 | { | |
1071 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1072 | } | |
1073 | ||
1074 | static int fsi_pcm_new(struct snd_card *card, | |
1075 | struct snd_soc_dai *dai, | |
1076 | struct snd_pcm *pcm) | |
1077 | { | |
1078 | /* | |
1079 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1080 | * in MMAP mode (i.e. aplay -M) | |
1081 | */ | |
1082 | return snd_pcm_lib_preallocate_pages_for_all( | |
1083 | pcm, | |
1084 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1085 | snd_dma_continuous_data(GFP_KERNEL), | |
1086 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1087 | } | |
1088 | ||
c8fe2574 KM |
1089 | /* |
1090 | * alsa struct | |
1091 | */ | |
a4d7d550 | 1092 | |
f0fba2ad | 1093 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1094 | { |
f0fba2ad | 1095 | .name = "fsia-dai", |
a4d7d550 KM |
1096 | .playback = { |
1097 | .rates = FSI_RATES, | |
1098 | .formats = FSI_FMTS, | |
1099 | .channels_min = 1, | |
1100 | .channels_max = 8, | |
1101 | }, | |
07102f3c KM |
1102 | .capture = { |
1103 | .rates = FSI_RATES, | |
1104 | .formats = FSI_FMTS, | |
1105 | .channels_min = 1, | |
1106 | .channels_max = 8, | |
1107 | }, | |
a4d7d550 KM |
1108 | .ops = &fsi_dai_ops, |
1109 | }, | |
1110 | { | |
f0fba2ad | 1111 | .name = "fsib-dai", |
a4d7d550 KM |
1112 | .playback = { |
1113 | .rates = FSI_RATES, | |
1114 | .formats = FSI_FMTS, | |
1115 | .channels_min = 1, | |
1116 | .channels_max = 8, | |
1117 | }, | |
07102f3c KM |
1118 | .capture = { |
1119 | .rates = FSI_RATES, | |
1120 | .formats = FSI_FMTS, | |
1121 | .channels_min = 1, | |
1122 | .channels_max = 8, | |
1123 | }, | |
a4d7d550 KM |
1124 | .ops = &fsi_dai_ops, |
1125 | }, | |
1126 | }; | |
a4d7d550 | 1127 | |
f0fba2ad LG |
1128 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1129 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1130 | .pcm_new = fsi_pcm_new, |
1131 | .pcm_free = fsi_pcm_free, | |
1132 | }; | |
a4d7d550 | 1133 | |
c8fe2574 KM |
1134 | /* |
1135 | * platform function | |
1136 | */ | |
a4d7d550 | 1137 | |
a4d7d550 KM |
1138 | static int fsi_probe(struct platform_device *pdev) |
1139 | { | |
71f6e064 | 1140 | struct fsi_master *master; |
cc780d38 | 1141 | const struct platform_device_id *id_entry; |
a4d7d550 | 1142 | struct resource *res; |
a4d7d550 KM |
1143 | unsigned int irq; |
1144 | int ret; | |
1145 | ||
cc780d38 KM |
1146 | id_entry = pdev->id_entry; |
1147 | if (!id_entry) { | |
1148 | dev_err(&pdev->dev, "unknown fsi device\n"); | |
1149 | return -ENODEV; | |
1150 | } | |
1151 | ||
a4d7d550 KM |
1152 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1153 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 1154 | if (!res || (int)irq <= 0) { |
a4d7d550 KM |
1155 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
1156 | ret = -ENODEV; | |
1157 | goto exit; | |
1158 | } | |
1159 | ||
1160 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
1161 | if (!master) { | |
1162 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
1163 | ret = -ENOMEM; | |
1164 | goto exit; | |
1165 | } | |
1166 | ||
1167 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
1168 | if (!master->base) { | |
1169 | ret = -ENXIO; | |
1170 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
1171 | goto exit_kfree; | |
1172 | } | |
1173 | ||
3bc28070 | 1174 | /* master setting */ |
a4d7d550 KM |
1175 | master->irq = irq; |
1176 | master->info = pdev->dev.platform_data; | |
3bc28070 KM |
1177 | master->core = (struct fsi_core *)id_entry->driver_data; |
1178 | spin_lock_init(&master->lock); | |
1179 | ||
1180 | /* FSI A setting */ | |
a4d7d550 | 1181 | master->fsia.base = master->base; |
71f6e064 | 1182 | master->fsia.master = master; |
3bc28070 KM |
1183 | master->fsia.mst_ctrl = A_MST_CTLR; |
1184 | ||
1185 | /* FSI B setting */ | |
a4d7d550 | 1186 | master->fsib.base = master->base + 0x40; |
71f6e064 | 1187 | master->fsib.master = master; |
3bc28070 | 1188 | master->fsib.mst_ctrl = B_MST_CTLR; |
a4d7d550 | 1189 | |
785d1c45 KM |
1190 | pm_runtime_enable(&pdev->dev); |
1191 | pm_runtime_resume(&pdev->dev); | |
f0fba2ad | 1192 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 1193 | |
71f6e064 | 1194 | fsi_soft_all_reset(master); |
a4d7d550 | 1195 | |
cc780d38 KM |
1196 | ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, |
1197 | id_entry->name, master); | |
a4d7d550 KM |
1198 | if (ret) { |
1199 | dev_err(&pdev->dev, "irq request err\n"); | |
9ddc9aa9 | 1200 | goto exit_iounmap; |
a4d7d550 KM |
1201 | } |
1202 | ||
f0fba2ad | 1203 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
1204 | if (ret < 0) { |
1205 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1206 | goto exit_free_irq; | |
1207 | } | |
1208 | ||
f0fba2ad | 1209 | return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); |
a4d7d550 KM |
1210 | |
1211 | exit_free_irq: | |
1212 | free_irq(irq, master); | |
a4d7d550 KM |
1213 | exit_iounmap: |
1214 | iounmap(master->base); | |
785d1c45 | 1215 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
1216 | exit_kfree: |
1217 | kfree(master); | |
1218 | master = NULL; | |
1219 | exit: | |
1220 | return ret; | |
1221 | } | |
1222 | ||
1223 | static int fsi_remove(struct platform_device *pdev) | |
1224 | { | |
71f6e064 KM |
1225 | struct fsi_master *master; |
1226 | ||
f0fba2ad | 1227 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 1228 | |
f0fba2ad LG |
1229 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); |
1230 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 | 1231 | |
785d1c45 | 1232 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 1233 | |
a4d7d550 KM |
1234 | free_irq(master->irq, master); |
1235 | ||
1236 | iounmap(master->base); | |
1237 | kfree(master); | |
71f6e064 | 1238 | |
a4d7d550 KM |
1239 | return 0; |
1240 | } | |
1241 | ||
785d1c45 KM |
1242 | static int fsi_runtime_nop(struct device *dev) |
1243 | { | |
1244 | /* Runtime PM callback shared between ->runtime_suspend() | |
1245 | * and ->runtime_resume(). Simply returns success. | |
1246 | * | |
1247 | * This driver re-initializes all registers after | |
1248 | * pm_runtime_get_sync() anyway so there is no need | |
1249 | * to save and restore registers here. | |
1250 | */ | |
1251 | return 0; | |
1252 | } | |
1253 | ||
1254 | static struct dev_pm_ops fsi_pm_ops = { | |
1255 | .runtime_suspend = fsi_runtime_nop, | |
1256 | .runtime_resume = fsi_runtime_nop, | |
1257 | }; | |
1258 | ||
73b92c1f KM |
1259 | static struct fsi_core fsi1_core = { |
1260 | .ver = 1, | |
1261 | ||
1262 | /* Interrupt */ | |
cc780d38 KM |
1263 | .int_st = INT_ST, |
1264 | .iemsk = IEMSK, | |
1265 | .imsk = IMSK, | |
1266 | }; | |
1267 | ||
73b92c1f KM |
1268 | static struct fsi_core fsi2_core = { |
1269 | .ver = 2, | |
1270 | ||
1271 | /* Interrupt */ | |
cc780d38 KM |
1272 | .int_st = CPU_INT_ST, |
1273 | .iemsk = CPU_IEMSK, | |
1274 | .imsk = CPU_IMSK, | |
1275 | }; | |
1276 | ||
1277 | static struct platform_device_id fsi_id_table[] = { | |
73b92c1f KM |
1278 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
1279 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
05c69450 | 1280 | {}, |
cc780d38 | 1281 | }; |
d85a6d7b | 1282 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 1283 | |
a4d7d550 KM |
1284 | static struct platform_driver fsi_driver = { |
1285 | .driver = { | |
f0fba2ad | 1286 | .name = "fsi-pcm-audio", |
785d1c45 | 1287 | .pm = &fsi_pm_ops, |
a4d7d550 KM |
1288 | }, |
1289 | .probe = fsi_probe, | |
1290 | .remove = fsi_remove, | |
cc780d38 | 1291 | .id_table = fsi_id_table, |
a4d7d550 KM |
1292 | }; |
1293 | ||
1294 | static int __init fsi_mobile_init(void) | |
1295 | { | |
1296 | return platform_driver_register(&fsi_driver); | |
1297 | } | |
1298 | ||
1299 | static void __exit fsi_mobile_exit(void) | |
1300 | { | |
1301 | platform_driver_unregister(&fsi_driver); | |
1302 | } | |
d85a6d7b | 1303 | |
a4d7d550 KM |
1304 | module_init(fsi_mobile_init); |
1305 | module_exit(fsi_mobile_exit); | |
1306 | ||
1307 | MODULE_LICENSE("GPL"); | |
1308 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1309 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); |