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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
785d1c45 | 16 | #include <linux/pm_runtime.h> |
a4d7d550 | 17 | #include <linux/io.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
da155d5b | 19 | #include <linux/module.h> |
a4d7d550 | 20 | #include <sound/soc.h> |
a4d7d550 | 21 | #include <sound/sh_fsi.h> |
a4d7d550 | 22 | |
e8c8b631 KM |
23 | /* PortA/PortB register */ |
24 | #define REG_DO_FMT 0x0000 | |
25 | #define REG_DOFF_CTL 0x0004 | |
26 | #define REG_DOFF_ST 0x0008 | |
27 | #define REG_DI_FMT 0x000C | |
28 | #define REG_DIFF_CTL 0x0010 | |
29 | #define REG_DIFF_ST 0x0014 | |
30 | #define REG_CKG1 0x0018 | |
31 | #define REG_CKG2 0x001C | |
32 | #define REG_DIDT 0x0020 | |
33 | #define REG_DODT 0x0024 | |
34 | #define REG_MUTE_ST 0x0028 | |
65ff03f4 | 35 | #define REG_OUT_DMAC 0x002C |
e8c8b631 | 36 | #define REG_OUT_SEL 0x0030 |
65ff03f4 | 37 | #define REG_IN_DMAC 0x0038 |
cc780d38 | 38 | |
43fa95ca KM |
39 | /* master register */ |
40 | #define MST_CLK_RST 0x0210 | |
41 | #define MST_SOFT_RST 0x0214 | |
42 | #define MST_FIFO_SZ 0x0218 | |
43 | ||
44 | /* core register (depend on FSI version) */ | |
3bc28070 KM |
45 | #define A_MST_CTLR 0x0180 |
46 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
47 | #define CPU_INT_ST 0x01F4 |
48 | #define CPU_IEMSK 0x01F8 | |
49 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
50 | #define INT_ST 0x0200 |
51 | #define IEMSK 0x0204 | |
52 | #define IMSK 0x0208 | |
a4d7d550 KM |
53 | |
54 | /* DO_FMT */ | |
55 | /* DI_FMT */ | |
f7d711e3 KM |
56 | #define CR_BWS_24 (0x0 << 20) /* FSI2 */ |
57 | #define CR_BWS_16 (0x1 << 20) /* FSI2 */ | |
58 | #define CR_BWS_20 (0x2 << 20) /* FSI2 */ | |
59 | ||
60 | #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ | |
61 | #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ | |
62 | #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ | |
63 | ||
a7ffb52b KM |
64 | #define CR_MONO (0x0 << 4) |
65 | #define CR_MONO_D (0x1 << 4) | |
66 | #define CR_PCM (0x2 << 4) | |
67 | #define CR_I2S (0x3 << 4) | |
68 | #define CR_TDM (0x4 << 4) | |
69 | #define CR_TDM_D (0x5 << 4) | |
a4d7d550 KM |
70 | |
71 | /* DOFF_CTL */ | |
72 | /* DIFF_CTL */ | |
73 | #define IRQ_HALF 0x00100000 | |
74 | #define FIFO_CLR 0x00000001 | |
75 | ||
76 | /* DOFF_ST */ | |
77 | #define ERR_OVER 0x00000010 | |
78 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 79 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 80 | |
ccad7b44 KM |
81 | /* CKG1 */ |
82 | #define ACKMD_MASK 0x00007000 | |
83 | #define BPFMD_MASK 0x00000700 | |
4d805f7b KM |
84 | #define DIMD (1 << 4) |
85 | #define DOMD (1 << 0) | |
ccad7b44 | 86 | |
3bc28070 KM |
87 | /* A/B MST_CTLR */ |
88 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
89 | #define SE (1 << 0) /* Fix the master clock */ | |
90 | ||
a4d7d550 | 91 | /* CLK_RST */ |
1f5e2a31 KM |
92 | #define CRB (1 << 4) |
93 | #define CRA (1 << 0) | |
a4d7d550 | 94 | |
cf6edd00 KM |
95 | /* IO SHIFT / MACRO */ |
96 | #define BI_SHIFT 12 | |
97 | #define BO_SHIFT 8 | |
98 | #define AI_SHIFT 4 | |
99 | #define AO_SHIFT 0 | |
100 | #define AB_IO(param, shift) (param << shift) | |
a4d7d550 | 101 | |
feb58cff KM |
102 | /* SOFT_RST */ |
103 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
104 | #define PASR (1 << 8) /* Port A Software Reset */ | |
105 | #define IR (1 << 4) /* Interrupt Reset */ | |
106 | #define FSISR (1 << 0) /* Software Reset */ | |
107 | ||
f7d711e3 KM |
108 | /* OUT_SEL (FSI2) */ |
109 | #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ | |
110 | /* 1: Biphase and serial */ | |
111 | ||
4a942b45 | 112 | /* FIFO_SZ */ |
cf6edd00 | 113 | #define FIFO_SZ_MASK 0x7 |
4a942b45 | 114 | |
a4d7d550 KM |
115 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
116 | ||
117 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
118 | ||
d7c5762b KM |
119 | typedef int (*set_rate_func)(struct device *dev, int is_porta, int rate, int enable); |
120 | ||
5bfb9ad0 KM |
121 | /* |
122 | * FSI driver use below type name for variable | |
123 | * | |
5bfb9ad0 | 124 | * xxx_num : number of data |
2e651baf KM |
125 | * xxx_pos : position of data |
126 | * xxx_capa : capacity of data | |
127 | */ | |
128 | ||
129 | /* | |
130 | * period/frame/sample image | |
131 | * | |
132 | * ex) PCM (2ch) | |
133 | * | |
134 | * period pos period pos | |
135 | * [n] [n + 1] | |
136 | * |<-------------------- period--------------------->| | |
137 | * ==|============================================ ... =|== | |
138 | * | | | |
139 | * ||<----- frame ----->|<------ frame ----->| ... | | |
140 | * |+--------------------+--------------------+- ... | | |
141 | * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | | |
142 | * |+--------------------+--------------------+- ... | | |
143 | * ==|============================================ ... =|== | |
144 | */ | |
145 | ||
146 | /* | |
147 | * FSI FIFO image | |
148 | * | |
149 | * | | | |
150 | * | | | |
151 | * | [ sample ] | | |
152 | * | [ sample ] | | |
153 | * | [ sample ] | | |
154 | * | [ sample ] | | |
155 | * --> go to codecs | |
5bfb9ad0 KM |
156 | */ |
157 | ||
c8fe2574 KM |
158 | /* |
159 | * struct | |
160 | */ | |
a4d7d550 | 161 | |
93193c2b | 162 | struct fsi_stream { |
a4d7d550 KM |
163 | struct snd_pcm_substream *substream; |
164 | ||
2e651baf KM |
165 | int fifo_sample_capa; /* sample capacity of FSI FIFO */ |
166 | int buff_sample_capa; /* sample capacity of ALSA buffer */ | |
167 | int buff_sample_pos; /* sample position of ALSA buffer */ | |
168 | int period_samples; /* sample number / 1 period */ | |
169 | int period_pos; /* current period position */ | |
c1e6f10e | 170 | int sample_width; /* sample width */ |
1ec9bc35 KM |
171 | |
172 | int uerr_num; | |
173 | int oerr_num; | |
93193c2b KM |
174 | }; |
175 | ||
176 | struct fsi_priv { | |
177 | void __iomem *base; | |
178 | struct fsi_master *master; | |
179 | ||
180 | struct fsi_stream playback; | |
181 | struct fsi_stream capture; | |
3bc28070 | 182 | |
9478e0b6 KM |
183 | u32 do_fmt; |
184 | u32 di_fmt; | |
185 | ||
6a9ebad8 KM |
186 | int chan_num:16; |
187 | int clk_master:1; | |
9478e0b6 | 188 | int spdif:1; |
6a9ebad8 | 189 | |
d4bc99b9 | 190 | long rate; |
a4d7d550 KM |
191 | }; |
192 | ||
73b92c1f KM |
193 | struct fsi_core { |
194 | int ver; | |
195 | ||
cc780d38 KM |
196 | u32 int_st; |
197 | u32 iemsk; | |
198 | u32 imsk; | |
2b0e7302 KM |
199 | u32 a_mclk; |
200 | u32 b_mclk; | |
cc780d38 KM |
201 | }; |
202 | ||
a4d7d550 KM |
203 | struct fsi_master { |
204 | void __iomem *base; | |
205 | int irq; | |
a4d7d550 KM |
206 | struct fsi_priv fsia; |
207 | struct fsi_priv fsib; | |
73b92c1f | 208 | struct fsi_core *core; |
a4d7d550 | 209 | struct sh_fsi_platform_info *info; |
8fc176d5 | 210 | spinlock_t lock; |
a4d7d550 KM |
211 | }; |
212 | ||
c8fe2574 KM |
213 | /* |
214 | * basic read write function | |
215 | */ | |
a4d7d550 | 216 | |
ca7aceef | 217 | static void __fsi_reg_write(u32 __iomem *reg, u32 data) |
a4d7d550 KM |
218 | { |
219 | /* valid data area is 24bit */ | |
220 | data &= 0x00ffffff; | |
221 | ||
0f69d978 | 222 | __raw_writel(data, reg); |
a4d7d550 KM |
223 | } |
224 | ||
ca7aceef | 225 | static u32 __fsi_reg_read(u32 __iomem *reg) |
a4d7d550 | 226 | { |
0f69d978 | 227 | return __raw_readl(reg); |
a4d7d550 KM |
228 | } |
229 | ||
ca7aceef | 230 | static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) |
a4d7d550 KM |
231 | { |
232 | u32 val = __fsi_reg_read(reg); | |
233 | ||
234 | val &= ~mask; | |
235 | val |= data & mask; | |
236 | ||
0f69d978 | 237 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
238 | } |
239 | ||
e8c8b631 | 240 | #define fsi_reg_write(p, r, d)\ |
8918b843 | 241 | __fsi_reg_write((p->base + REG_##r), d) |
a4d7d550 | 242 | |
e8c8b631 | 243 | #define fsi_reg_read(p, r)\ |
8918b843 | 244 | __fsi_reg_read((p->base + REG_##r)) |
a4d7d550 | 245 | |
e8c8b631 | 246 | #define fsi_reg_mask_set(p, r, m, d)\ |
8918b843 | 247 | __fsi_reg_mask_set((p->base + REG_##r), m, d) |
a4d7d550 | 248 | |
43fa95ca KM |
249 | #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) |
250 | #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) | |
251 | static u32 _fsi_master_read(struct fsi_master *master, u32 reg) | |
a4d7d550 | 252 | { |
8fc176d5 KM |
253 | u32 ret; |
254 | unsigned long flags; | |
255 | ||
8fc176d5 | 256 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 257 | ret = __fsi_reg_read(master->base + reg); |
8fc176d5 KM |
258 | spin_unlock_irqrestore(&master->lock, flags); |
259 | ||
260 | return ret; | |
a4d7d550 KM |
261 | } |
262 | ||
43fa95ca KM |
263 | #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) |
264 | #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) | |
265 | static void _fsi_master_mask_set(struct fsi_master *master, | |
71f6e064 | 266 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 267 | { |
8fc176d5 KM |
268 | unsigned long flags; |
269 | ||
8fc176d5 | 270 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 271 | __fsi_reg_mask_set(master->base + reg, mask, data); |
8fc176d5 | 272 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
273 | } |
274 | ||
c8fe2574 KM |
275 | /* |
276 | * basic function | |
277 | */ | |
a4d7d550 | 278 | |
71f6e064 | 279 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 280 | { |
71f6e064 | 281 | return fsi->master; |
a4d7d550 KM |
282 | } |
283 | ||
6a9ebad8 KM |
284 | static int fsi_is_clk_master(struct fsi_priv *fsi) |
285 | { | |
286 | return fsi->clk_master; | |
287 | } | |
288 | ||
a4d7d550 KM |
289 | static int fsi_is_port_a(struct fsi_priv *fsi) |
290 | { | |
71f6e064 KM |
291 | return fsi->master->base == fsi->base; |
292 | } | |
a4d7d550 | 293 | |
9478e0b6 KM |
294 | static int fsi_is_spdif(struct fsi_priv *fsi) |
295 | { | |
296 | return fsi->spdif; | |
297 | } | |
298 | ||
142e8174 | 299 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
300 | { |
301 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 302 | |
f0fba2ad | 303 | return rtd->cpu_dai; |
142e8174 KM |
304 | } |
305 | ||
0d032c19 | 306 | static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) |
142e8174 | 307 | { |
f0fba2ad | 308 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 309 | |
f0fba2ad LG |
310 | if (dai->id == 0) |
311 | return &master->fsia; | |
312 | else | |
313 | return &master->fsib; | |
a4d7d550 KM |
314 | } |
315 | ||
0d032c19 KM |
316 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) |
317 | { | |
318 | return fsi_get_priv_frm_dai(fsi_get_dai(substream)); | |
319 | } | |
320 | ||
d7c5762b KM |
321 | static set_rate_func fsi_get_info_set_rate(struct fsi_master *master) |
322 | { | |
323 | if (!master->info) | |
324 | return NULL; | |
325 | ||
326 | return master->info->set_rate; | |
327 | } | |
328 | ||
a4d7d550 KM |
329 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) |
330 | { | |
331 | int is_porta = fsi_is_port_a(fsi); | |
71f6e064 | 332 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 333 | |
d7c5762b KM |
334 | if (!master->info) |
335 | return 0; | |
336 | ||
a4d7d550 KM |
337 | return is_porta ? master->info->porta_flags : |
338 | master->info->portb_flags; | |
339 | } | |
340 | ||
cf6edd00 | 341 | static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
342 | { |
343 | int is_porta = fsi_is_port_a(fsi); | |
cf6edd00 | 344 | u32 shift; |
a4d7d550 KM |
345 | |
346 | if (is_porta) | |
cf6edd00 | 347 | shift = is_play ? AO_SHIFT : AI_SHIFT; |
a4d7d550 | 348 | else |
cf6edd00 | 349 | shift = is_play ? BO_SHIFT : BI_SHIFT; |
a4d7d550 | 350 | |
cf6edd00 | 351 | return shift; |
a4d7d550 KM |
352 | } |
353 | ||
2e651baf KM |
354 | static int fsi_frame2sample(struct fsi_priv *fsi, int frames) |
355 | { | |
356 | return frames * fsi->chan_num; | |
357 | } | |
358 | ||
359 | static int fsi_sample2frame(struct fsi_priv *fsi, int samples) | |
360 | { | |
361 | return samples / fsi->chan_num; | |
362 | } | |
363 | ||
4e62d84d KM |
364 | static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, int is_play) |
365 | { | |
366 | u32 status; | |
367 | int frames; | |
368 | ||
369 | status = is_play ? | |
370 | fsi_reg_read(fsi, DOFF_ST) : | |
371 | fsi_reg_read(fsi, DIFF_ST); | |
372 | ||
373 | frames = 0x1ff & (status >> 8); | |
374 | ||
375 | return fsi_frame2sample(fsi, frames); | |
376 | } | |
377 | ||
378 | static void fsi_count_fifo_err(struct fsi_priv *fsi) | |
379 | { | |
380 | u32 ostatus = fsi_reg_read(fsi, DOFF_ST); | |
381 | u32 istatus = fsi_reg_read(fsi, DIFF_ST); | |
382 | ||
383 | if (ostatus & ERR_OVER) | |
384 | fsi->playback.oerr_num++; | |
385 | ||
386 | if (ostatus & ERR_UNDER) | |
387 | fsi->playback.uerr_num++; | |
388 | ||
389 | if (istatus & ERR_OVER) | |
390 | fsi->capture.oerr_num++; | |
391 | ||
392 | if (istatus & ERR_UNDER) | |
393 | fsi->capture.uerr_num++; | |
394 | ||
395 | fsi_reg_write(fsi, DOFF_ST, 0); | |
396 | fsi_reg_write(fsi, DIFF_ST, 0); | |
397 | } | |
398 | ||
399 | /* | |
400 | * fsi_stream_xx() function | |
401 | */ | |
402 | #define fsi_is_play(substream) fsi_stream_is_play(substream->stream) | |
403 | static inline int fsi_stream_is_play(int stream) | |
404 | { | |
405 | return stream == SNDRV_PCM_STREAM_PLAYBACK; | |
406 | } | |
407 | ||
408 | static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi, | |
409 | int is_play) | |
410 | { | |
411 | return is_play ? &fsi->playback : &fsi->capture; | |
412 | } | |
413 | ||
cda828ca KM |
414 | static int fsi_stream_is_working(struct fsi_priv *fsi, |
415 | int is_play) | |
416 | { | |
4e62d84d | 417 | struct fsi_stream *io = fsi_stream_get(fsi, is_play); |
cda828ca KM |
418 | struct fsi_master *master = fsi_get_master(fsi); |
419 | unsigned long flags; | |
420 | int ret; | |
421 | ||
422 | spin_lock_irqsave(&master->lock, flags); | |
423 | ret = !!io->substream; | |
424 | spin_unlock_irqrestore(&master->lock, flags); | |
425 | ||
426 | return ret; | |
427 | } | |
428 | ||
a4d7d550 | 429 | static void fsi_stream_push(struct fsi_priv *fsi, |
93193c2b | 430 | int is_play, |
0ffe296a | 431 | struct snd_pcm_substream *substream) |
a4d7d550 | 432 | { |
4e62d84d | 433 | struct fsi_stream *io = fsi_stream_get(fsi, is_play); |
0ffe296a | 434 | struct snd_pcm_runtime *runtime = substream->runtime; |
2da65892 KM |
435 | struct fsi_master *master = fsi_get_master(fsi); |
436 | unsigned long flags; | |
93193c2b | 437 | |
2da65892 | 438 | spin_lock_irqsave(&master->lock, flags); |
93193c2b | 439 | io->substream = substream; |
2e651baf KM |
440 | io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); |
441 | io->buff_sample_pos = 0; | |
442 | io->period_samples = fsi_frame2sample(fsi, runtime->period_size); | |
443 | io->period_pos = 0; | |
c1e6f10e | 444 | io->sample_width = samples_to_bytes(runtime, 1); |
1ec9bc35 KM |
445 | io->oerr_num = -1; /* ignore 1st err */ |
446 | io->uerr_num = -1; /* ignore 1st err */ | |
2da65892 | 447 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
448 | } |
449 | ||
93193c2b | 450 | static void fsi_stream_pop(struct fsi_priv *fsi, int is_play) |
a4d7d550 | 451 | { |
4e62d84d | 452 | struct fsi_stream *io = fsi_stream_get(fsi, is_play); |
1ec9bc35 | 453 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); |
2da65892 KM |
454 | struct fsi_master *master = fsi_get_master(fsi); |
455 | unsigned long flags; | |
1ec9bc35 | 456 | |
2da65892 | 457 | spin_lock_irqsave(&master->lock, flags); |
1ec9bc35 KM |
458 | |
459 | if (io->oerr_num > 0) | |
460 | dev_err(dai->dev, "over_run = %d\n", io->oerr_num); | |
461 | ||
462 | if (io->uerr_num > 0) | |
463 | dev_err(dai->dev, "under_run = %d\n", io->uerr_num); | |
93193c2b KM |
464 | |
465 | io->substream = NULL; | |
2e651baf KM |
466 | io->buff_sample_capa = 0; |
467 | io->buff_sample_pos = 0; | |
468 | io->period_samples = 0; | |
469 | io->period_pos = 0; | |
c1e6f10e | 470 | io->sample_width = 0; |
1ec9bc35 KM |
471 | io->oerr_num = 0; |
472 | io->uerr_num = 0; | |
2da65892 | 473 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
474 | } |
475 | ||
b9fde18c | 476 | /* |
d78629e2 | 477 | * pio function |
b9fde18c KM |
478 | */ |
479 | ||
d78629e2 | 480 | static u8 *fsi_pio_get_area(struct fsi_priv *fsi, int stream) |
c79eab3e | 481 | { |
93193c2b | 482 | int is_play = fsi_stream_is_play(stream); |
4e62d84d | 483 | struct fsi_stream *io = fsi_stream_get(fsi, is_play); |
2e651baf | 484 | struct snd_pcm_runtime *runtime = io->substream->runtime; |
93193c2b | 485 | |
2e651baf KM |
486 | return runtime->dma_area + |
487 | samples_to_bytes(runtime, io->buff_sample_pos); | |
c79eab3e KM |
488 | } |
489 | ||
d78629e2 | 490 | static void fsi_pio_push16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
491 | { |
492 | u16 *start; | |
493 | int i; | |
494 | ||
d78629e2 | 495 | start = (u16 *)fsi_pio_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
b9fde18c | 496 | |
5bfb9ad0 | 497 | for (i = 0; i < num; i++) |
b9fde18c KM |
498 | fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8)); |
499 | } | |
500 | ||
d78629e2 | 501 | static void fsi_pio_pop16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
502 | { |
503 | u16 *start; | |
504 | int i; | |
505 | ||
d78629e2 | 506 | start = (u16 *)fsi_pio_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
93193c2b | 507 | |
b9fde18c | 508 | |
5bfb9ad0 | 509 | for (i = 0; i < num; i++) |
b9fde18c KM |
510 | *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); |
511 | } | |
512 | ||
d78629e2 | 513 | static void fsi_pio_push32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
514 | { |
515 | u32 *start; | |
516 | int i; | |
517 | ||
d78629e2 | 518 | start = (u32 *)fsi_pio_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
93193c2b | 519 | |
b9fde18c | 520 | |
5bfb9ad0 | 521 | for (i = 0; i < num; i++) |
b9fde18c KM |
522 | fsi_reg_write(fsi, DODT, *(start + i)); |
523 | } | |
524 | ||
d78629e2 | 525 | static void fsi_pio_pop32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
526 | { |
527 | u32 *start; | |
528 | int i; | |
529 | ||
d78629e2 | 530 | start = (u32 *)fsi_pio_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
b9fde18c | 531 | |
5bfb9ad0 | 532 | for (i = 0; i < num; i++) |
b9fde18c KM |
533 | *(start + i) = fsi_reg_read(fsi, DIDT); |
534 | } | |
535 | ||
c8fe2574 KM |
536 | /* |
537 | * irq function | |
538 | */ | |
a4d7d550 | 539 | |
a4d7d550 KM |
540 | static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) |
541 | { | |
cf6edd00 | 542 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 543 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 544 | |
43fa95ca KM |
545 | fsi_core_mask_set(master, imsk, data, data); |
546 | fsi_core_mask_set(master, iemsk, data, data); | |
a4d7d550 KM |
547 | } |
548 | ||
549 | static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | |
550 | { | |
cf6edd00 | 551 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 552 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 553 | |
43fa95ca KM |
554 | fsi_core_mask_set(master, imsk, data, 0); |
555 | fsi_core_mask_set(master, iemsk, data, 0); | |
a4d7d550 KM |
556 | } |
557 | ||
10ea76cc KM |
558 | static u32 fsi_irq_get_status(struct fsi_master *master) |
559 | { | |
43fa95ca | 560 | return fsi_core_read(master, int_st); |
10ea76cc KM |
561 | } |
562 | ||
10ea76cc KM |
563 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
564 | { | |
565 | u32 data = 0; | |
566 | struct fsi_master *master = fsi_get_master(fsi); | |
567 | ||
cf6edd00 KM |
568 | data |= AB_IO(1, fsi_get_port_shift(fsi, 0)); |
569 | data |= AB_IO(1, fsi_get_port_shift(fsi, 1)); | |
10ea76cc KM |
570 | |
571 | /* clear interrupt factor */ | |
43fa95ca | 572 | fsi_core_mask_set(master, int_st, data, 0); |
10ea76cc KM |
573 | } |
574 | ||
c8fe2574 KM |
575 | /* |
576 | * SPDIF master clock function | |
577 | * | |
578 | * These functions are used later FSI2 | |
579 | */ | |
3bc28070 KM |
580 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
581 | { | |
582 | struct fsi_master *master = fsi_get_master(fsi); | |
2b0e7302 | 583 | u32 mask, val; |
3bc28070 KM |
584 | |
585 | if (master->core->ver < 2) { | |
586 | pr_err("fsi: register access err (%s)\n", __func__); | |
587 | return; | |
588 | } | |
589 | ||
2b0e7302 KM |
590 | mask = BP | SE; |
591 | val = enable ? mask : 0; | |
592 | ||
593 | fsi_is_port_a(fsi) ? | |
43fa95ca KM |
594 | fsi_core_mask_set(master, a_mclk, mask, val) : |
595 | fsi_core_mask_set(master, b_mclk, mask, val); | |
3bc28070 KM |
596 | } |
597 | ||
c8fe2574 | 598 | /* |
1f5e2a31 | 599 | * clock function |
c8fe2574 | 600 | */ |
4f56cde1 KM |
601 | static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi, |
602 | long rate, int enable) | |
603 | { | |
604 | struct fsi_master *master = fsi_get_master(fsi); | |
605 | set_rate_func set_rate = fsi_get_info_set_rate(master); | |
606 | int fsi_ver = master->core->ver; | |
607 | int ret; | |
608 | ||
609 | ret = set_rate(dev, fsi_is_port_a(fsi), rate, enable); | |
610 | if (ret < 0) /* error */ | |
611 | return ret; | |
612 | ||
613 | if (!enable) | |
614 | return 0; | |
615 | ||
616 | if (ret > 0) { | |
617 | u32 data = 0; | |
618 | ||
619 | switch (ret & SH_FSI_ACKMD_MASK) { | |
620 | default: | |
621 | /* FALL THROUGH */ | |
622 | case SH_FSI_ACKMD_512: | |
623 | data |= (0x0 << 12); | |
624 | break; | |
625 | case SH_FSI_ACKMD_256: | |
626 | data |= (0x1 << 12); | |
627 | break; | |
628 | case SH_FSI_ACKMD_128: | |
629 | data |= (0x2 << 12); | |
630 | break; | |
631 | case SH_FSI_ACKMD_64: | |
632 | data |= (0x3 << 12); | |
633 | break; | |
634 | case SH_FSI_ACKMD_32: | |
635 | if (fsi_ver < 2) | |
636 | dev_err(dev, "unsupported ACKMD\n"); | |
637 | else | |
638 | data |= (0x4 << 12); | |
639 | break; | |
640 | } | |
641 | ||
642 | switch (ret & SH_FSI_BPFMD_MASK) { | |
643 | default: | |
644 | /* FALL THROUGH */ | |
645 | case SH_FSI_BPFMD_32: | |
646 | data |= (0x0 << 8); | |
647 | break; | |
648 | case SH_FSI_BPFMD_64: | |
649 | data |= (0x1 << 8); | |
650 | break; | |
651 | case SH_FSI_BPFMD_128: | |
652 | data |= (0x2 << 8); | |
653 | break; | |
654 | case SH_FSI_BPFMD_256: | |
655 | data |= (0x3 << 8); | |
656 | break; | |
657 | case SH_FSI_BPFMD_512: | |
658 | data |= (0x4 << 8); | |
659 | break; | |
660 | case SH_FSI_BPFMD_16: | |
661 | if (fsi_ver < 2) | |
662 | dev_err(dev, "unsupported ACKMD\n"); | |
663 | else | |
664 | data |= (0x7 << 8); | |
665 | break; | |
666 | } | |
667 | ||
668 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
669 | udelay(10); | |
670 | ret = 0; | |
671 | } | |
672 | ||
673 | return ret; | |
4f56cde1 KM |
674 | } |
675 | ||
1ddddd36 KM |
676 | #define fsi_port_start(f, i) __fsi_port_clk_ctrl(f, i, 1) |
677 | #define fsi_port_stop(f, i) __fsi_port_clk_ctrl(f, i, 0) | |
678 | static void __fsi_port_clk_ctrl(struct fsi_priv *fsi, int is_play, int enable) | |
a4d7d550 | 679 | { |
71f6e064 | 680 | struct fsi_master *master = fsi_get_master(fsi); |
1f5e2a31 | 681 | u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; |
a4d7d550 | 682 | |
1ddddd36 KM |
683 | if (enable) |
684 | fsi_irq_enable(fsi, is_play); | |
685 | else | |
686 | fsi_irq_disable(fsi, is_play); | |
687 | ||
cda828ca | 688 | if (fsi_is_clk_master(fsi)) |
1f5e2a31 | 689 | fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); |
a4d7d550 KM |
690 | } |
691 | ||
1f5e2a31 KM |
692 | /* |
693 | * ctrl function | |
694 | */ | |
4a942b45 KM |
695 | static void fsi_fifo_init(struct fsi_priv *fsi, |
696 | int is_play, | |
23ca8533 | 697 | struct device *dev) |
a4d7d550 | 698 | { |
4a942b45 | 699 | struct fsi_master *master = fsi_get_master(fsi); |
4e62d84d | 700 | struct fsi_stream *io = fsi_stream_get(fsi, is_play); |
e8c8b631 | 701 | u32 shift, i; |
2e651baf | 702 | int frame_capa; |
a4d7d550 | 703 | |
4a942b45 KM |
704 | /* get on-chip RAM capacity */ |
705 | shift = fsi_master_read(master, FIFO_SZ); | |
cf6edd00 KM |
706 | shift >>= fsi_get_port_shift(fsi, is_play); |
707 | shift &= FIFO_SZ_MASK; | |
2e651baf | 708 | frame_capa = 256 << shift; |
23ca8533 | 709 | dev_dbg(dev, "fifo = %d words\n", frame_capa); |
a4d7d550 | 710 | |
4a942b45 KM |
711 | /* |
712 | * The maximum number of sample data varies depending | |
713 | * on the number of channels selected for the format. | |
714 | * | |
715 | * FIFOs are used in 4-channel units in 3-channel mode | |
716 | * and in 8-channel units in 5- to 7-channel mode | |
717 | * meaning that more FIFOs than the required size of DPRAM | |
718 | * are used. | |
719 | * | |
720 | * ex) if 256 words of DP-RAM is connected | |
721 | * 1 channel: 256 (256 x 1 = 256) | |
722 | * 2 channels: 128 (128 x 2 = 256) | |
723 | * 3 channels: 64 ( 64 x 3 = 192) | |
724 | * 4 channels: 64 ( 64 x 4 = 256) | |
725 | * 5 channels: 32 ( 32 x 5 = 160) | |
726 | * 6 channels: 32 ( 32 x 6 = 192) | |
727 | * 7 channels: 32 ( 32 x 7 = 224) | |
728 | * 8 channels: 32 ( 32 x 8 = 256) | |
729 | */ | |
160afa7f | 730 | for (i = 1; i < fsi->chan_num; i <<= 1) |
2e651baf | 731 | frame_capa >>= 1; |
23ca8533 | 732 | dev_dbg(dev, "%d channel %d store\n", |
2e651baf KM |
733 | fsi->chan_num, frame_capa); |
734 | ||
735 | io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); | |
a4d7d550 | 736 | |
e8c8b631 KM |
737 | /* |
738 | * set interrupt generation factor | |
739 | * clear FIFO | |
740 | */ | |
741 | if (is_play) { | |
742 | fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); | |
743 | fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); | |
744 | } else { | |
745 | fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); | |
746 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
747 | } | |
a4d7d550 KM |
748 | } |
749 | ||
376cf38a KM |
750 | static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, struct fsi_stream *io, |
751 | void (*run16)(struct fsi_priv *fsi, int size), | |
752 | void (*run32)(struct fsi_priv *fsi, int size), | |
753 | int samples) | |
a4d7d550 KM |
754 | { |
755 | struct snd_pcm_runtime *runtime; | |
376cf38a | 756 | struct snd_pcm_substream *substream; |
b9fde18c | 757 | int over_period; |
a4d7d550 KM |
758 | |
759 | if (!fsi || | |
93193c2b KM |
760 | !io->substream || |
761 | !io->substream->runtime) | |
a4d7d550 KM |
762 | return -EINVAL; |
763 | ||
1c418d1f | 764 | over_period = 0; |
93193c2b | 765 | substream = io->substream; |
1c418d1f | 766 | runtime = substream->runtime; |
a4d7d550 KM |
767 | |
768 | /* FSI FIFO has limit. | |
769 | * So, this driver can not send periods data at a time | |
770 | */ | |
2e651baf KM |
771 | if (io->buff_sample_pos >= |
772 | io->period_samples * (io->period_pos + 1)) { | |
a4d7d550 | 773 | |
1c418d1f | 774 | over_period = 1; |
2e651baf | 775 | io->period_pos = (io->period_pos + 1) % runtime->periods; |
a4d7d550 | 776 | |
2e651baf KM |
777 | if (0 == io->period_pos) |
778 | io->buff_sample_pos = 0; | |
a4d7d550 KM |
779 | } |
780 | ||
376cf38a KM |
781 | switch (io->sample_width) { |
782 | case 2: | |
783 | run16(fsi, samples); | |
784 | break; | |
785 | case 4: | |
786 | run32(fsi, samples); | |
787 | break; | |
788 | default: | |
789 | return -EINVAL; | |
d8b33534 | 790 | } |
a4d7d550 | 791 | |
2e651baf KM |
792 | /* update buff_sample_pos */ |
793 | io->buff_sample_pos += samples; | |
a4d7d550 | 794 | |
1c418d1f | 795 | if (over_period) |
a4d7d550 KM |
796 | snd_pcm_period_elapsed(substream); |
797 | ||
47fc9a0a | 798 | return 0; |
a4d7d550 KM |
799 | } |
800 | ||
1ec9bc35 | 801 | static int fsi_data_pop(struct fsi_priv *fsi) |
07102f3c | 802 | { |
376cf38a KM |
803 | int is_play = fsi_stream_is_play(SNDRV_PCM_STREAM_CAPTURE); |
804 | int sample_residues; /* samples in FSI fifo */ | |
805 | int sample_space; /* ALSA free samples space */ | |
806 | int samples; | |
807 | struct fsi_stream *io = fsi_stream_get(fsi, is_play); | |
808 | ||
809 | sample_residues = fsi_get_current_fifo_samples(fsi, is_play); | |
810 | sample_space = io->buff_sample_capa - io->buff_sample_pos; | |
811 | ||
812 | samples = min(sample_residues, sample_space); | |
813 | ||
814 | return fsi_fifo_data_ctrl(fsi, io, | |
d78629e2 KM |
815 | fsi_pio_pop16, |
816 | fsi_pio_pop32, | |
376cf38a | 817 | samples); |
d8b33534 | 818 | } |
07102f3c | 819 | |
1ec9bc35 | 820 | static int fsi_data_push(struct fsi_priv *fsi) |
d8b33534 | 821 | { |
376cf38a KM |
822 | int is_play = fsi_stream_is_play(SNDRV_PCM_STREAM_PLAYBACK); |
823 | int sample_residues; /* ALSA residue samples */ | |
824 | int sample_space; /* FSI fifo free samples space */ | |
825 | int samples; | |
826 | struct fsi_stream *io = fsi_stream_get(fsi, is_play); | |
827 | ||
828 | sample_residues = io->buff_sample_capa - io->buff_sample_pos; | |
829 | sample_space = io->fifo_sample_capa - | |
830 | fsi_get_current_fifo_samples(fsi, is_play); | |
831 | ||
832 | samples = min(sample_residues, sample_space); | |
833 | ||
834 | return fsi_fifo_data_ctrl(fsi, io, | |
d78629e2 KM |
835 | fsi_pio_push16, |
836 | fsi_pio_push32, | |
376cf38a | 837 | samples); |
07102f3c KM |
838 | } |
839 | ||
a4d7d550 KM |
840 | static irqreturn_t fsi_interrupt(int irq, void *data) |
841 | { | |
71f6e064 | 842 | struct fsi_master *master = data; |
10ea76cc | 843 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
844 | |
845 | /* clear irq status */ | |
feb58cff KM |
846 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
847 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 | 848 | |
cf6edd00 | 849 | if (int_st & AB_IO(1, AO_SHIFT)) |
1ec9bc35 | 850 | fsi_data_push(&master->fsia); |
cf6edd00 | 851 | if (int_st & AB_IO(1, BO_SHIFT)) |
1ec9bc35 | 852 | fsi_data_push(&master->fsib); |
cf6edd00 | 853 | if (int_st & AB_IO(1, AI_SHIFT)) |
1ec9bc35 | 854 | fsi_data_pop(&master->fsia); |
cf6edd00 | 855 | if (int_st & AB_IO(1, BI_SHIFT)) |
1ec9bc35 KM |
856 | fsi_data_pop(&master->fsib); |
857 | ||
858 | fsi_count_fifo_err(&master->fsia); | |
859 | fsi_count_fifo_err(&master->fsib); | |
a4d7d550 | 860 | |
48d78e58 KM |
861 | fsi_irq_clear_status(&master->fsia); |
862 | fsi_irq_clear_status(&master->fsib); | |
a4d7d550 KM |
863 | |
864 | return IRQ_HANDLED; | |
865 | } | |
866 | ||
c8fe2574 KM |
867 | /* |
868 | * dai ops | |
869 | */ | |
a4d7d550 | 870 | |
23ca8533 KM |
871 | static int fsi_hw_startup(struct fsi_priv *fsi, |
872 | int is_play, | |
873 | struct device *dev) | |
a4d7d550 | 874 | { |
65ff03f4 KM |
875 | struct fsi_master *master = fsi_get_master(fsi); |
876 | int fsi_ver = master->core->ver; | |
93193c2b | 877 | u32 flags = fsi_get_info_flags(fsi); |
9478e0b6 | 878 | u32 data = 0; |
a4d7d550 | 879 | |
9478e0b6 KM |
880 | /* clock setting */ |
881 | if (fsi_is_clk_master(fsi)) | |
882 | data = DIMD | DOMD; | |
883 | ||
884 | fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); | |
a4d7d550 KM |
885 | |
886 | /* clock inversion (CKG2) */ | |
887 | data = 0; | |
b427b44c KM |
888 | if (SH_FSI_LRM_INV & flags) |
889 | data |= 1 << 12; | |
890 | if (SH_FSI_BRM_INV & flags) | |
891 | data |= 1 << 8; | |
892 | if (SH_FSI_LRS_INV & flags) | |
893 | data |= 1 << 4; | |
894 | if (SH_FSI_BRS_INV & flags) | |
895 | data |= 1 << 0; | |
896 | ||
a4d7d550 KM |
897 | fsi_reg_write(fsi, CKG2, data); |
898 | ||
9478e0b6 KM |
899 | /* set format */ |
900 | fsi_reg_write(fsi, DO_FMT, fsi->do_fmt); | |
901 | fsi_reg_write(fsi, DI_FMT, fsi->di_fmt); | |
902 | ||
903 | /* spdif ? */ | |
904 | if (fsi_is_spdif(fsi)) { | |
905 | fsi_spdif_clk_ctrl(fsi, 1); | |
906 | fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); | |
907 | } | |
908 | ||
65ff03f4 KM |
909 | /* |
910 | * FIXME | |
911 | * | |
912 | * FSI driver assumed that data package is in-back. | |
913 | * FSI2 chip can select it. | |
914 | */ | |
915 | if (fsi_ver >= 2) { | |
916 | fsi_reg_write(fsi, OUT_DMAC, (1 << 4)); | |
917 | fsi_reg_write(fsi, IN_DMAC, (1 << 4)); | |
918 | } | |
919 | ||
10ea76cc KM |
920 | /* irq clear */ |
921 | fsi_irq_disable(fsi, is_play); | |
922 | fsi_irq_clear_status(fsi); | |
923 | ||
924 | /* fifo init */ | |
23ca8533 | 925 | fsi_fifo_init(fsi, is_play, dev); |
a4d7d550 | 926 | |
a68a3b4e | 927 | return 0; |
a4d7d550 KM |
928 | } |
929 | ||
23ca8533 KM |
930 | static void fsi_hw_shutdown(struct fsi_priv *fsi, |
931 | int is_play, | |
932 | struct device *dev) | |
933 | { | |
934 | if (fsi_is_clk_master(fsi)) | |
935 | fsi_set_master_clk(dev, fsi, fsi->rate, 0); | |
23ca8533 KM |
936 | } |
937 | ||
938 | static int fsi_dai_startup(struct snd_pcm_substream *substream, | |
939 | struct snd_soc_dai *dai) | |
940 | { | |
941 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
942 | int is_play = fsi_is_play(substream); | |
943 | ||
944 | return fsi_hw_startup(fsi, is_play, dai->dev); | |
945 | } | |
946 | ||
a4d7d550 KM |
947 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, |
948 | struct snd_soc_dai *dai) | |
949 | { | |
71f6e064 | 950 | struct fsi_priv *fsi = fsi_get_priv(substream); |
23ca8533 | 951 | int is_play = fsi_is_play(substream); |
a4d7d550 | 952 | |
23ca8533 | 953 | fsi_hw_shutdown(fsi, is_play, dai->dev); |
d4bc99b9 | 954 | fsi->rate = 0; |
a4d7d550 KM |
955 | } |
956 | ||
957 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
958 | struct snd_soc_dai *dai) | |
959 | { | |
71f6e064 | 960 | struct fsi_priv *fsi = fsi_get_priv(substream); |
00545785 | 961 | int is_play = fsi_is_play(substream); |
a4d7d550 KM |
962 | int ret = 0; |
963 | ||
a4d7d550 KM |
964 | switch (cmd) { |
965 | case SNDRV_PCM_TRIGGER_START: | |
0ffe296a | 966 | fsi_stream_push(fsi, is_play, substream); |
1ec9bc35 | 967 | ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi); |
1ddddd36 | 968 | fsi_port_start(fsi, is_play); |
a4d7d550 KM |
969 | break; |
970 | case SNDRV_PCM_TRIGGER_STOP: | |
1ddddd36 | 971 | fsi_port_stop(fsi, is_play); |
93193c2b | 972 | fsi_stream_pop(fsi, is_play); |
a4d7d550 KM |
973 | break; |
974 | } | |
975 | ||
976 | return ret; | |
977 | } | |
978 | ||
f17c13ca KM |
979 | static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) |
980 | { | |
981 | u32 data = 0; | |
982 | ||
983 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
984 | case SND_SOC_DAIFMT_I2S: | |
985 | data = CR_I2S; | |
986 | fsi->chan_num = 2; | |
987 | break; | |
988 | case SND_SOC_DAIFMT_LEFT_J: | |
989 | data = CR_PCM; | |
990 | fsi->chan_num = 2; | |
991 | break; | |
992 | default: | |
993 | return -EINVAL; | |
994 | } | |
995 | ||
9478e0b6 KM |
996 | fsi->do_fmt = data; |
997 | fsi->di_fmt = data; | |
f17c13ca KM |
998 | |
999 | return 0; | |
1000 | } | |
1001 | ||
1002 | static int fsi_set_fmt_spdif(struct fsi_priv *fsi) | |
1003 | { | |
1004 | struct fsi_master *master = fsi_get_master(fsi); | |
1005 | u32 data = 0; | |
1006 | ||
1007 | if (master->core->ver < 2) | |
1008 | return -EINVAL; | |
1009 | ||
1010 | data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM; | |
1011 | fsi->chan_num = 2; | |
9478e0b6 | 1012 | fsi->spdif = 1; |
f17c13ca | 1013 | |
9478e0b6 KM |
1014 | fsi->do_fmt = data; |
1015 | fsi->di_fmt = data; | |
f17c13ca KM |
1016 | |
1017 | return 0; | |
1018 | } | |
1019 | ||
4d805f7b KM |
1020 | static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
1021 | { | |
1022 | struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); | |
6a9ebad8 KM |
1023 | struct fsi_master *master = fsi_get_master(fsi); |
1024 | set_rate_func set_rate = fsi_get_info_set_rate(master); | |
f17c13ca | 1025 | u32 flags = fsi_get_info_flags(fsi); |
4d805f7b KM |
1026 | int ret; |
1027 | ||
4d805f7b KM |
1028 | /* set master/slave audio interface */ |
1029 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1030 | case SND_SOC_DAIFMT_CBM_CFM: | |
6a9ebad8 | 1031 | fsi->clk_master = 1; |
4d805f7b KM |
1032 | break; |
1033 | case SND_SOC_DAIFMT_CBS_CFS: | |
1034 | break; | |
1035 | default: | |
9478e0b6 | 1036 | return -EINVAL; |
4d805f7b | 1037 | } |
6a9ebad8 KM |
1038 | |
1039 | if (fsi_is_clk_master(fsi) && !set_rate) { | |
1040 | dev_err(dai->dev, "platform doesn't have set_rate\n"); | |
9478e0b6 | 1041 | return -EINVAL; |
6a9ebad8 KM |
1042 | } |
1043 | ||
f17c13ca KM |
1044 | /* set format */ |
1045 | switch (flags & SH_FSI_FMT_MASK) { | |
1046 | case SH_FSI_FMT_DAI: | |
1047 | ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); | |
1048 | break; | |
1049 | case SH_FSI_FMT_SPDIF: | |
1050 | ret = fsi_set_fmt_spdif(fsi); | |
1051 | break; | |
1052 | default: | |
1053 | ret = -EINVAL; | |
1054 | } | |
4d805f7b | 1055 | |
4d805f7b KM |
1056 | return ret; |
1057 | } | |
1058 | ||
ccad7b44 KM |
1059 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
1060 | struct snd_pcm_hw_params *params, | |
1061 | struct snd_soc_dai *dai) | |
1062 | { | |
1063 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
d4bc99b9 | 1064 | long rate = params_rate(params); |
ccad7b44 KM |
1065 | int ret; |
1066 | ||
6a9ebad8 | 1067 | if (!fsi_is_clk_master(fsi)) |
ccad7b44 KM |
1068 | return 0; |
1069 | ||
4f56cde1 KM |
1070 | ret = fsi_set_master_clk(dai->dev, fsi, rate, 1); |
1071 | if (ret < 0) | |
d4bc99b9 | 1072 | return ret; |
ccad7b44 | 1073 | |
d4bc99b9 | 1074 | fsi->rate = rate; |
ccad7b44 KM |
1075 | |
1076 | return ret; | |
ccad7b44 KM |
1077 | } |
1078 | ||
85e7652d | 1079 | static const struct snd_soc_dai_ops fsi_dai_ops = { |
a4d7d550 KM |
1080 | .startup = fsi_dai_startup, |
1081 | .shutdown = fsi_dai_shutdown, | |
1082 | .trigger = fsi_dai_trigger, | |
4d805f7b | 1083 | .set_fmt = fsi_dai_set_fmt, |
ccad7b44 | 1084 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
1085 | }; |
1086 | ||
c8fe2574 KM |
1087 | /* |
1088 | * pcm ops | |
1089 | */ | |
a4d7d550 | 1090 | |
a4d7d550 KM |
1091 | static struct snd_pcm_hardware fsi_pcm_hardware = { |
1092 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
1093 | SNDRV_PCM_INFO_MMAP | | |
1094 | SNDRV_PCM_INFO_MMAP_VALID | | |
1095 | SNDRV_PCM_INFO_PAUSE, | |
1096 | .formats = FSI_FMTS, | |
1097 | .rates = FSI_RATES, | |
1098 | .rate_min = 8000, | |
1099 | .rate_max = 192000, | |
1100 | .channels_min = 1, | |
1101 | .channels_max = 2, | |
1102 | .buffer_bytes_max = 64 * 1024, | |
1103 | .period_bytes_min = 32, | |
1104 | .period_bytes_max = 8192, | |
1105 | .periods_min = 1, | |
1106 | .periods_max = 32, | |
1107 | .fifo_size = 256, | |
1108 | }; | |
1109 | ||
1110 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
1111 | { | |
1112 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1113 | int ret = 0; | |
1114 | ||
1115 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
1116 | ||
1117 | ret = snd_pcm_hw_constraint_integer(runtime, | |
1118 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1119 | ||
1120 | return ret; | |
1121 | } | |
1122 | ||
1123 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
1124 | struct snd_pcm_hw_params *hw_params) | |
1125 | { | |
1126 | return snd_pcm_lib_malloc_pages(substream, | |
1127 | params_buffer_bytes(hw_params)); | |
1128 | } | |
1129 | ||
1130 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
1131 | { | |
1132 | return snd_pcm_lib_free_pages(substream); | |
1133 | } | |
1134 | ||
1135 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
1136 | { | |
71f6e064 | 1137 | struct fsi_priv *fsi = fsi_get_priv(substream); |
4e62d84d | 1138 | struct fsi_stream *io = fsi_stream_get(fsi, fsi_is_play(substream)); |
2e651baf | 1139 | int samples_pos = io->buff_sample_pos - 1; |
a4d7d550 | 1140 | |
2e651baf KM |
1141 | if (samples_pos < 0) |
1142 | samples_pos = 0; | |
a4d7d550 | 1143 | |
2e651baf | 1144 | return fsi_sample2frame(fsi, samples_pos); |
a4d7d550 KM |
1145 | } |
1146 | ||
1147 | static struct snd_pcm_ops fsi_pcm_ops = { | |
1148 | .open = fsi_pcm_open, | |
1149 | .ioctl = snd_pcm_lib_ioctl, | |
1150 | .hw_params = fsi_hw_params, | |
1151 | .hw_free = fsi_hw_free, | |
1152 | .pointer = fsi_pointer, | |
1153 | }; | |
1154 | ||
c8fe2574 KM |
1155 | /* |
1156 | * snd_soc_platform | |
1157 | */ | |
a4d7d550 | 1158 | |
a4d7d550 KM |
1159 | #define PREALLOC_BUFFER (32 * 1024) |
1160 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1161 | ||
1162 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1163 | { | |
1164 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1165 | } | |
1166 | ||
552d1ef6 | 1167 | static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd) |
a4d7d550 | 1168 | { |
552d1ef6 LG |
1169 | struct snd_pcm *pcm = rtd->pcm; |
1170 | ||
a4d7d550 KM |
1171 | /* |
1172 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1173 | * in MMAP mode (i.e. aplay -M) | |
1174 | */ | |
1175 | return snd_pcm_lib_preallocate_pages_for_all( | |
1176 | pcm, | |
1177 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1178 | snd_dma_continuous_data(GFP_KERNEL), | |
1179 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1180 | } | |
1181 | ||
c8fe2574 KM |
1182 | /* |
1183 | * alsa struct | |
1184 | */ | |
a4d7d550 | 1185 | |
f0fba2ad | 1186 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1187 | { |
f0fba2ad | 1188 | .name = "fsia-dai", |
a4d7d550 KM |
1189 | .playback = { |
1190 | .rates = FSI_RATES, | |
1191 | .formats = FSI_FMTS, | |
1192 | .channels_min = 1, | |
1193 | .channels_max = 8, | |
1194 | }, | |
07102f3c KM |
1195 | .capture = { |
1196 | .rates = FSI_RATES, | |
1197 | .formats = FSI_FMTS, | |
1198 | .channels_min = 1, | |
1199 | .channels_max = 8, | |
1200 | }, | |
a4d7d550 KM |
1201 | .ops = &fsi_dai_ops, |
1202 | }, | |
1203 | { | |
f0fba2ad | 1204 | .name = "fsib-dai", |
a4d7d550 KM |
1205 | .playback = { |
1206 | .rates = FSI_RATES, | |
1207 | .formats = FSI_FMTS, | |
1208 | .channels_min = 1, | |
1209 | .channels_max = 8, | |
1210 | }, | |
07102f3c KM |
1211 | .capture = { |
1212 | .rates = FSI_RATES, | |
1213 | .formats = FSI_FMTS, | |
1214 | .channels_min = 1, | |
1215 | .channels_max = 8, | |
1216 | }, | |
a4d7d550 KM |
1217 | .ops = &fsi_dai_ops, |
1218 | }, | |
1219 | }; | |
a4d7d550 | 1220 | |
f0fba2ad LG |
1221 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1222 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1223 | .pcm_new = fsi_pcm_new, |
1224 | .pcm_free = fsi_pcm_free, | |
1225 | }; | |
a4d7d550 | 1226 | |
c8fe2574 KM |
1227 | /* |
1228 | * platform function | |
1229 | */ | |
a4d7d550 | 1230 | |
a4d7d550 KM |
1231 | static int fsi_probe(struct platform_device *pdev) |
1232 | { | |
71f6e064 | 1233 | struct fsi_master *master; |
cc780d38 | 1234 | const struct platform_device_id *id_entry; |
a4d7d550 | 1235 | struct resource *res; |
a4d7d550 KM |
1236 | unsigned int irq; |
1237 | int ret; | |
1238 | ||
cc780d38 KM |
1239 | id_entry = pdev->id_entry; |
1240 | if (!id_entry) { | |
1241 | dev_err(&pdev->dev, "unknown fsi device\n"); | |
1242 | return -ENODEV; | |
1243 | } | |
1244 | ||
a4d7d550 KM |
1245 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1246 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 1247 | if (!res || (int)irq <= 0) { |
a4d7d550 KM |
1248 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
1249 | ret = -ENODEV; | |
1250 | goto exit; | |
1251 | } | |
1252 | ||
1253 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
1254 | if (!master) { | |
1255 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
1256 | ret = -ENOMEM; | |
1257 | goto exit; | |
1258 | } | |
1259 | ||
1260 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
1261 | if (!master->base) { | |
1262 | ret = -ENXIO; | |
1263 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
1264 | goto exit_kfree; | |
1265 | } | |
1266 | ||
3bc28070 | 1267 | /* master setting */ |
a4d7d550 KM |
1268 | master->irq = irq; |
1269 | master->info = pdev->dev.platform_data; | |
3bc28070 KM |
1270 | master->core = (struct fsi_core *)id_entry->driver_data; |
1271 | spin_lock_init(&master->lock); | |
1272 | ||
1273 | /* FSI A setting */ | |
a4d7d550 | 1274 | master->fsia.base = master->base; |
71f6e064 | 1275 | master->fsia.master = master; |
3bc28070 KM |
1276 | |
1277 | /* FSI B setting */ | |
a4d7d550 | 1278 | master->fsib.base = master->base + 0x40; |
71f6e064 | 1279 | master->fsib.master = master; |
a4d7d550 | 1280 | |
785d1c45 | 1281 | pm_runtime_enable(&pdev->dev); |
f0fba2ad | 1282 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 1283 | |
88e24c3a | 1284 | ret = request_irq(irq, &fsi_interrupt, 0, |
cc780d38 | 1285 | id_entry->name, master); |
a4d7d550 KM |
1286 | if (ret) { |
1287 | dev_err(&pdev->dev, "irq request err\n"); | |
9ddc9aa9 | 1288 | goto exit_iounmap; |
a4d7d550 KM |
1289 | } |
1290 | ||
f0fba2ad | 1291 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
1292 | if (ret < 0) { |
1293 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1294 | goto exit_free_irq; | |
1295 | } | |
1296 | ||
0b5ec87d KM |
1297 | ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai, |
1298 | ARRAY_SIZE(fsi_soc_dai)); | |
1299 | if (ret < 0) { | |
1300 | dev_err(&pdev->dev, "cannot snd dai register\n"); | |
1301 | goto exit_snd_soc; | |
1302 | } | |
a4d7d550 | 1303 | |
0b5ec87d KM |
1304 | return ret; |
1305 | ||
1306 | exit_snd_soc: | |
1307 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 KM |
1308 | exit_free_irq: |
1309 | free_irq(irq, master); | |
a4d7d550 KM |
1310 | exit_iounmap: |
1311 | iounmap(master->base); | |
785d1c45 | 1312 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
1313 | exit_kfree: |
1314 | kfree(master); | |
1315 | master = NULL; | |
1316 | exit: | |
1317 | return ret; | |
1318 | } | |
1319 | ||
1320 | static int fsi_remove(struct platform_device *pdev) | |
1321 | { | |
71f6e064 KM |
1322 | struct fsi_master *master; |
1323 | ||
f0fba2ad | 1324 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 1325 | |
d985f27e | 1326 | free_irq(master->irq, master); |
785d1c45 | 1327 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 1328 | |
d985f27e KM |
1329 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); |
1330 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 KM |
1331 | |
1332 | iounmap(master->base); | |
1333 | kfree(master); | |
71f6e064 | 1334 | |
a4d7d550 KM |
1335 | return 0; |
1336 | } | |
1337 | ||
106c79ec | 1338 | static void __fsi_suspend(struct fsi_priv *fsi, |
cda828ca | 1339 | int is_play, |
4f56cde1 | 1340 | struct device *dev) |
106c79ec | 1341 | { |
cda828ca KM |
1342 | if (!fsi_stream_is_working(fsi, is_play)) |
1343 | return; | |
106c79ec | 1344 | |
cda828ca KM |
1345 | fsi_port_stop(fsi, is_play); |
1346 | fsi_hw_shutdown(fsi, is_play, dev); | |
106c79ec KM |
1347 | } |
1348 | ||
1349 | static void __fsi_resume(struct fsi_priv *fsi, | |
cda828ca | 1350 | int is_play, |
4f56cde1 | 1351 | struct device *dev) |
106c79ec | 1352 | { |
cda828ca KM |
1353 | if (!fsi_stream_is_working(fsi, is_play)) |
1354 | return; | |
106c79ec | 1355 | |
cda828ca KM |
1356 | fsi_hw_startup(fsi, is_play, dev); |
1357 | ||
1358 | if (fsi_is_clk_master(fsi) && fsi->rate) | |
4f56cde1 | 1359 | fsi_set_master_clk(dev, fsi, fsi->rate, 1); |
cda828ca KM |
1360 | |
1361 | fsi_port_start(fsi, is_play); | |
1362 | ||
106c79ec KM |
1363 | } |
1364 | ||
1365 | static int fsi_suspend(struct device *dev) | |
1366 | { | |
1367 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
1368 | struct fsi_priv *fsia = &master->fsia; |
1369 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 1370 | |
cda828ca KM |
1371 | __fsi_suspend(fsia, 1, dev); |
1372 | __fsi_suspend(fsia, 0, dev); | |
106c79ec | 1373 | |
cda828ca KM |
1374 | __fsi_suspend(fsib, 1, dev); |
1375 | __fsi_suspend(fsib, 0, dev); | |
106c79ec KM |
1376 | |
1377 | return 0; | |
1378 | } | |
1379 | ||
1380 | static int fsi_resume(struct device *dev) | |
1381 | { | |
1382 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
1383 | struct fsi_priv *fsia = &master->fsia; |
1384 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 1385 | |
cda828ca KM |
1386 | __fsi_resume(fsia, 1, dev); |
1387 | __fsi_resume(fsia, 0, dev); | |
106c79ec | 1388 | |
cda828ca KM |
1389 | __fsi_resume(fsib, 1, dev); |
1390 | __fsi_resume(fsib, 0, dev); | |
106c79ec KM |
1391 | |
1392 | return 0; | |
1393 | } | |
1394 | ||
785d1c45 | 1395 | static struct dev_pm_ops fsi_pm_ops = { |
106c79ec KM |
1396 | .suspend = fsi_suspend, |
1397 | .resume = fsi_resume, | |
785d1c45 KM |
1398 | }; |
1399 | ||
73b92c1f KM |
1400 | static struct fsi_core fsi1_core = { |
1401 | .ver = 1, | |
1402 | ||
1403 | /* Interrupt */ | |
cc780d38 KM |
1404 | .int_st = INT_ST, |
1405 | .iemsk = IEMSK, | |
1406 | .imsk = IMSK, | |
1407 | }; | |
1408 | ||
73b92c1f KM |
1409 | static struct fsi_core fsi2_core = { |
1410 | .ver = 2, | |
1411 | ||
1412 | /* Interrupt */ | |
cc780d38 KM |
1413 | .int_st = CPU_INT_ST, |
1414 | .iemsk = CPU_IEMSK, | |
1415 | .imsk = CPU_IMSK, | |
2b0e7302 KM |
1416 | .a_mclk = A_MST_CTLR, |
1417 | .b_mclk = B_MST_CTLR, | |
cc780d38 KM |
1418 | }; |
1419 | ||
1420 | static struct platform_device_id fsi_id_table[] = { | |
73b92c1f KM |
1421 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
1422 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
05c69450 | 1423 | {}, |
cc780d38 | 1424 | }; |
d85a6d7b | 1425 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 1426 | |
a4d7d550 KM |
1427 | static struct platform_driver fsi_driver = { |
1428 | .driver = { | |
f0fba2ad | 1429 | .name = "fsi-pcm-audio", |
785d1c45 | 1430 | .pm = &fsi_pm_ops, |
a4d7d550 KM |
1431 | }, |
1432 | .probe = fsi_probe, | |
1433 | .remove = fsi_remove, | |
cc780d38 | 1434 | .id_table = fsi_id_table, |
a4d7d550 KM |
1435 | }; |
1436 | ||
cb5e8738 | 1437 | module_platform_driver(fsi_driver); |
a4d7d550 KM |
1438 | |
1439 | MODULE_LICENSE("GPL"); | |
1440 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1441 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); | |
b3c27b51 | 1442 | MODULE_ALIAS("platform:fsi-pcm-audio"); |