Commit | Line | Data |
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17a52fd6 MB |
1 | /* |
2 | * soc-cache.c -- ASoC register cache helpers | |
3 | * | |
4 | * Copyright 2009 Wolfson Microelectronics PLC. | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | ||
7084a42b | 14 | #include <linux/i2c.h> |
27ded041 | 15 | #include <linux/spi/spi.h> |
17a52fd6 | 16 | #include <sound/soc.h> |
cc28fb8e DP |
17 | #include <linux/lzo.h> |
18 | #include <linux/bitmap.h> | |
a7f387d5 | 19 | #include <linux/rbtree.h> |
17a52fd6 | 20 | |
c358e640 DP |
21 | #include <trace/events/asoc.h> |
22 | ||
30539a18 DP |
23 | #if defined(CONFIG_SPI_MASTER) |
24 | static int do_spi_write(void *control_data, const void *msg, | |
25 | int len) | |
26 | { | |
27 | struct spi_device *spi = control_data; | |
28 | struct spi_transfer t; | |
29 | struct spi_message m; | |
30 | ||
31 | if (len <= 0) | |
32 | return 0; | |
33 | ||
34 | spi_message_init(&m); | |
35 | memset(&t, 0, sizeof t); | |
36 | ||
37 | t.tx_buf = msg; | |
38 | t.len = len; | |
39 | ||
40 | spi_message_add_tail(&t, &m); | |
41 | spi_sync(spi, &m); | |
42 | ||
43 | return len; | |
44 | } | |
45 | #endif | |
46 | ||
26e9984c DP |
47 | static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg, |
48 | unsigned int value, const void *data, int len) | |
49 | { | |
50 | int ret; | |
51 | ||
52 | if (!snd_soc_codec_volatile_register(codec, reg) && | |
53 | reg < codec->driver->reg_cache_size && | |
54 | !codec->cache_bypass) { | |
55 | ret = snd_soc_cache_write(codec, reg, value); | |
56 | if (ret < 0) | |
57 | return -1; | |
58 | } | |
59 | ||
60 | if (codec->cache_only) { | |
61 | codec->cache_sync = 1; | |
62 | return 0; | |
63 | } | |
64 | ||
65 | ret = codec->hw_write(codec->control_data, data, len); | |
66 | if (ret == len) | |
67 | return 0; | |
68 | if (ret < 0) | |
69 | return ret; | |
70 | else | |
71 | return -EIO; | |
72 | } | |
73 | ||
b8cbc195 | 74 | static unsigned int do_hw_read(struct snd_soc_codec *codec, unsigned int reg) |
63b62ab0 | 75 | { |
7a30a3db DP |
76 | int ret; |
77 | unsigned int val; | |
db49c146 DP |
78 | |
79 | if (reg >= codec->driver->reg_cache_size || | |
b8cbc195 DP |
80 | snd_soc_codec_volatile_register(codec, reg) || |
81 | codec->cache_bypass) { | |
82 | if (codec->cache_only) | |
83 | return -1; | |
db49c146 | 84 | |
b8cbc195 DP |
85 | BUG_ON(!codec->hw_read); |
86 | return codec->hw_read(codec, reg); | |
db49c146 DP |
87 | } |
88 | ||
7a30a3db DP |
89 | ret = snd_soc_cache_read(codec, reg, &val); |
90 | if (ret < 0) | |
91 | return -1; | |
92 | return val; | |
63b62ab0 BS |
93 | } |
94 | ||
b8cbc195 | 95 | static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec, |
fbda1824 | 96 | unsigned int reg) |
b8cbc195 DP |
97 | { |
98 | return do_hw_read(codec, reg); | |
99 | } | |
100 | ||
63b62ab0 | 101 | static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg, |
fbda1824 | 102 | unsigned int value) |
63b62ab0 | 103 | { |
63b62ab0 | 104 | u8 data[2]; |
63b62ab0 | 105 | |
63b62ab0 BS |
106 | data[0] = (reg << 4) | ((value >> 8) & 0x000f); |
107 | data[1] = value & 0x00ff; | |
108 | ||
26e9984c | 109 | return do_hw_write(codec, reg, value, data, 2); |
63b62ab0 BS |
110 | } |
111 | ||
112 | #if defined(CONFIG_SPI_MASTER) | |
113 | static int snd_soc_4_12_spi_write(void *control_data, const char *data, | |
fbda1824 | 114 | int len) |
63b62ab0 | 115 | { |
63b62ab0 BS |
116 | u8 msg[2]; |
117 | ||
63b62ab0 BS |
118 | msg[0] = data[1]; |
119 | msg[1] = data[0]; | |
120 | ||
30539a18 | 121 | return do_spi_write(control_data, msg, len); |
63b62ab0 BS |
122 | } |
123 | #else | |
124 | #define snd_soc_4_12_spi_write NULL | |
125 | #endif | |
126 | ||
17a52fd6 MB |
127 | static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec, |
128 | unsigned int reg) | |
129 | { | |
b8cbc195 | 130 | return do_hw_read(codec, reg); |
17a52fd6 MB |
131 | } |
132 | ||
133 | static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg, | |
134 | unsigned int value) | |
135 | { | |
17a52fd6 | 136 | u8 data[2]; |
17a52fd6 | 137 | |
17a52fd6 MB |
138 | data[0] = (reg << 1) | ((value >> 8) & 0x0001); |
139 | data[1] = value & 0x00ff; | |
140 | ||
26e9984c | 141 | return do_hw_write(codec, reg, value, data, 2); |
17a52fd6 MB |
142 | } |
143 | ||
27ded041 MB |
144 | #if defined(CONFIG_SPI_MASTER) |
145 | static int snd_soc_7_9_spi_write(void *control_data, const char *data, | |
146 | int len) | |
147 | { | |
27ded041 MB |
148 | u8 msg[2]; |
149 | ||
27ded041 MB |
150 | msg[0] = data[0]; |
151 | msg[1] = data[1]; | |
152 | ||
30539a18 | 153 | return do_spi_write(control_data, msg, len); |
27ded041 MB |
154 | } |
155 | #else | |
156 | #define snd_soc_7_9_spi_write NULL | |
157 | #endif | |
158 | ||
341c9b84 JS |
159 | static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg, |
160 | unsigned int value) | |
161 | { | |
341c9b84 JS |
162 | u8 data[2]; |
163 | ||
f4bee1bb BS |
164 | reg &= 0xff; |
165 | data[0] = reg; | |
341c9b84 JS |
166 | data[1] = value & 0xff; |
167 | ||
26e9984c | 168 | return do_hw_write(codec, reg, value, data, 2); |
341c9b84 JS |
169 | } |
170 | ||
171 | static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec, | |
172 | unsigned int reg) | |
173 | { | |
b8cbc195 | 174 | return do_hw_read(codec, reg); |
341c9b84 JS |
175 | } |
176 | ||
f479fd93 DP |
177 | #if defined(CONFIG_SPI_MASTER) |
178 | static int snd_soc_8_8_spi_write(void *control_data, const char *data, | |
179 | int len) | |
180 | { | |
f479fd93 DP |
181 | u8 msg[2]; |
182 | ||
f479fd93 DP |
183 | msg[0] = data[0]; |
184 | msg[1] = data[1]; | |
185 | ||
30539a18 | 186 | return do_spi_write(control_data, msg, len); |
f479fd93 DP |
187 | } |
188 | #else | |
189 | #define snd_soc_8_8_spi_write NULL | |
190 | #endif | |
191 | ||
afa2f106 MB |
192 | static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg, |
193 | unsigned int value) | |
194 | { | |
afa2f106 MB |
195 | u8 data[3]; |
196 | ||
197 | data[0] = reg; | |
198 | data[1] = (value >> 8) & 0xff; | |
199 | data[2] = value & 0xff; | |
200 | ||
26e9984c | 201 | return do_hw_write(codec, reg, value, data, 3); |
afa2f106 MB |
202 | } |
203 | ||
204 | static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec, | |
205 | unsigned int reg) | |
206 | { | |
b8cbc195 | 207 | return do_hw_read(codec, reg); |
afa2f106 MB |
208 | } |
209 | ||
f479fd93 DP |
210 | #if defined(CONFIG_SPI_MASTER) |
211 | static int snd_soc_8_16_spi_write(void *control_data, const char *data, | |
fbda1824 | 212 | int len) |
f479fd93 | 213 | { |
f479fd93 DP |
214 | u8 msg[3]; |
215 | ||
f479fd93 DP |
216 | msg[0] = data[0]; |
217 | msg[1] = data[1]; | |
218 | msg[2] = data[2]; | |
219 | ||
30539a18 | 220 | return do_spi_write(control_data, msg, len); |
f479fd93 DP |
221 | } |
222 | #else | |
223 | #define snd_soc_8_16_spi_write NULL | |
224 | #endif | |
225 | ||
85dfcdff | 226 | #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE)) |
f3594f5c DP |
227 | static unsigned int do_i2c_read(struct snd_soc_codec *codec, |
228 | void *reg, int reglen, | |
229 | void *data, int datalen) | |
85dfcdff CC |
230 | { |
231 | struct i2c_msg xfer[2]; | |
85dfcdff CC |
232 | int ret; |
233 | struct i2c_client *client = codec->control_data; | |
234 | ||
235 | /* Write register */ | |
236 | xfer[0].addr = client->addr; | |
237 | xfer[0].flags = 0; | |
f3594f5c DP |
238 | xfer[0].len = reglen; |
239 | xfer[0].buf = reg; | |
85dfcdff CC |
240 | |
241 | /* Read data */ | |
242 | xfer[1].addr = client->addr; | |
243 | xfer[1].flags = I2C_M_RD; | |
f3594f5c DP |
244 | xfer[1].len = datalen; |
245 | xfer[1].buf = data; | |
85dfcdff CC |
246 | |
247 | ret = i2c_transfer(client->adapter, xfer, 2); | |
f3594f5c | 248 | if (ret == 2) |
85dfcdff | 249 | return 0; |
f3594f5c DP |
250 | else if (ret < 0) |
251 | return ret; | |
252 | else | |
253 | return -EIO; | |
254 | } | |
255 | #endif | |
256 | ||
257 | #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE)) | |
258 | static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec, | |
fbda1824 | 259 | unsigned int r) |
f3594f5c DP |
260 | { |
261 | u8 reg = r; | |
262 | u8 data; | |
263 | int ret; | |
85dfcdff | 264 | |
f3594f5c DP |
265 | ret = do_i2c_read(codec, ®, 1, &data, 1); |
266 | if (ret < 0) | |
267 | return 0; | |
85dfcdff CC |
268 | return data; |
269 | } | |
270 | #else | |
271 | #define snd_soc_8_8_read_i2c NULL | |
272 | #endif | |
273 | ||
17244c24 | 274 | #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE)) |
afa2f106 MB |
275 | static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec, |
276 | unsigned int r) | |
277 | { | |
afa2f106 MB |
278 | u8 reg = r; |
279 | u16 data; | |
280 | int ret; | |
afa2f106 | 281 | |
f3594f5c DP |
282 | ret = do_i2c_read(codec, ®, 1, &data, 2); |
283 | if (ret < 0) | |
afa2f106 | 284 | return 0; |
afa2f106 MB |
285 | return (data >> 8) | ((data & 0xff) << 8); |
286 | } | |
287 | #else | |
288 | #define snd_soc_8_16_read_i2c NULL | |
289 | #endif | |
17a52fd6 | 290 | |
994dc424 BS |
291 | #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE)) |
292 | static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec, | |
293 | unsigned int r) | |
294 | { | |
994dc424 BS |
295 | u16 reg = r; |
296 | u8 data; | |
297 | int ret; | |
994dc424 | 298 | |
f3594f5c DP |
299 | ret = do_i2c_read(codec, ®, 2, &data, 1); |
300 | if (ret < 0) | |
994dc424 | 301 | return 0; |
994dc424 BS |
302 | return data; |
303 | } | |
304 | #else | |
305 | #define snd_soc_16_8_read_i2c NULL | |
306 | #endif | |
307 | ||
308 | static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec, | |
fbda1824 | 309 | unsigned int reg) |
994dc424 | 310 | { |
b8cbc195 | 311 | return do_hw_read(codec, reg); |
994dc424 BS |
312 | } |
313 | ||
314 | static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg, | |
fbda1824 | 315 | unsigned int value) |
994dc424 | 316 | { |
994dc424 | 317 | u8 data[3]; |
994dc424 | 318 | |
994dc424 BS |
319 | data[0] = (reg >> 8) & 0xff; |
320 | data[1] = reg & 0xff; | |
321 | data[2] = value; | |
994dc424 | 322 | reg &= 0xff; |
8c961bcc | 323 | |
26e9984c | 324 | return do_hw_write(codec, reg, value, data, 3); |
994dc424 BS |
325 | } |
326 | ||
327 | #if defined(CONFIG_SPI_MASTER) | |
328 | static int snd_soc_16_8_spi_write(void *control_data, const char *data, | |
fbda1824 | 329 | int len) |
994dc424 | 330 | { |
994dc424 BS |
331 | u8 msg[3]; |
332 | ||
994dc424 BS |
333 | msg[0] = data[0]; |
334 | msg[1] = data[1]; | |
335 | msg[2] = data[2]; | |
336 | ||
30539a18 | 337 | return do_spi_write(control_data, msg, len); |
994dc424 BS |
338 | } |
339 | #else | |
340 | #define snd_soc_16_8_spi_write NULL | |
341 | #endif | |
342 | ||
bc6552f4 MB |
343 | #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE)) |
344 | static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec, | |
345 | unsigned int r) | |
346 | { | |
bc6552f4 MB |
347 | u16 reg = cpu_to_be16(r); |
348 | u16 data; | |
349 | int ret; | |
bc6552f4 | 350 | |
f3594f5c DP |
351 | ret = do_i2c_read(codec, ®, 2, &data, 2); |
352 | if (ret < 0) | |
bc6552f4 | 353 | return 0; |
bc6552f4 MB |
354 | return be16_to_cpu(data); |
355 | } | |
356 | #else | |
357 | #define snd_soc_16_16_read_i2c NULL | |
358 | #endif | |
359 | ||
360 | static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec, | |
361 | unsigned int reg) | |
362 | { | |
b8cbc195 | 363 | return do_hw_read(codec, reg); |
bc6552f4 MB |
364 | } |
365 | ||
366 | static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg, | |
367 | unsigned int value) | |
368 | { | |
bc6552f4 | 369 | u8 data[4]; |
bc6552f4 MB |
370 | |
371 | data[0] = (reg >> 8) & 0xff; | |
372 | data[1] = reg & 0xff; | |
373 | data[2] = (value >> 8) & 0xff; | |
374 | data[3] = value & 0xff; | |
375 | ||
26e9984c | 376 | return do_hw_write(codec, reg, value, data, 4); |
bc6552f4 | 377 | } |
994dc424 | 378 | |
f479fd93 DP |
379 | #if defined(CONFIG_SPI_MASTER) |
380 | static int snd_soc_16_16_spi_write(void *control_data, const char *data, | |
fbda1824 | 381 | int len) |
f479fd93 | 382 | { |
f479fd93 DP |
383 | u8 msg[4]; |
384 | ||
f479fd93 DP |
385 | msg[0] = data[0]; |
386 | msg[1] = data[1]; | |
387 | msg[2] = data[2]; | |
388 | msg[3] = data[3]; | |
389 | ||
30539a18 | 390 | return do_spi_write(control_data, msg, len); |
f479fd93 DP |
391 | } |
392 | #else | |
393 | #define snd_soc_16_16_spi_write NULL | |
394 | #endif | |
395 | ||
34bad69c MB |
396 | /* Primitive bulk write support for soc-cache. The data pointed to by |
397 | * `data' needs to already be in the form the hardware expects | |
398 | * including any leading register specific data. Any data written | |
399 | * through this function will not go through the cache as it only | |
400 | * handles writing to volatile or out of bounds registers. | |
5fb609d4 DP |
401 | */ |
402 | static int snd_soc_hw_bulk_write_raw(struct snd_soc_codec *codec, unsigned int reg, | |
403 | const void *data, size_t len) | |
404 | { | |
405 | int ret; | |
406 | ||
64d27069 DP |
407 | /* To ensure that we don't get out of sync with the cache, check |
408 | * whether the base register is volatile or if we've directly asked | |
409 | * to bypass the cache. Out of bounds registers are considered | |
410 | * volatile. | |
5fb609d4 | 411 | */ |
64d27069 DP |
412 | if (!codec->cache_bypass |
413 | && !snd_soc_codec_volatile_register(codec, reg) | |
5fb609d4 DP |
414 | && reg < codec->driver->reg_cache_size) |
415 | return -EINVAL; | |
416 | ||
417 | switch (codec->control_type) { | |
898f8b0b | 418 | #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE)) |
5fb609d4 DP |
419 | case SND_SOC_I2C: |
420 | ret = i2c_master_send(codec->control_data, data, len); | |
421 | break; | |
898f8b0b SY |
422 | #endif |
423 | #if defined(CONFIG_SPI_MASTER) | |
5fb609d4 DP |
424 | case SND_SOC_SPI: |
425 | ret = do_spi_write(codec->control_data, data, len); | |
426 | break; | |
898f8b0b | 427 | #endif |
5fb609d4 DP |
428 | default: |
429 | BUG(); | |
430 | } | |
431 | ||
432 | if (ret == len) | |
433 | return 0; | |
434 | if (ret < 0) | |
435 | return ret; | |
436 | else | |
437 | return -EIO; | |
438 | } | |
439 | ||
17a52fd6 MB |
440 | static struct { |
441 | int addr_bits; | |
442 | int data_bits; | |
afa2f106 | 443 | int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int); |
27ded041 | 444 | int (*spi_write)(void *, const char *, int); |
17a52fd6 | 445 | unsigned int (*read)(struct snd_soc_codec *, unsigned int); |
afa2f106 | 446 | unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int); |
17a52fd6 | 447 | } io_types[] = { |
63b62ab0 BS |
448 | { |
449 | .addr_bits = 4, .data_bits = 12, | |
450 | .write = snd_soc_4_12_write, .read = snd_soc_4_12_read, | |
451 | .spi_write = snd_soc_4_12_spi_write, | |
452 | }, | |
d62ab358 MB |
453 | { |
454 | .addr_bits = 7, .data_bits = 9, | |
455 | .write = snd_soc_7_9_write, .read = snd_soc_7_9_read, | |
8998c899 | 456 | .spi_write = snd_soc_7_9_spi_write, |
d62ab358 MB |
457 | }, |
458 | { | |
459 | .addr_bits = 8, .data_bits = 8, | |
460 | .write = snd_soc_8_8_write, .read = snd_soc_8_8_read, | |
85dfcdff | 461 | .i2c_read = snd_soc_8_8_read_i2c, |
f479fd93 | 462 | .spi_write = snd_soc_8_8_spi_write, |
d62ab358 MB |
463 | }, |
464 | { | |
465 | .addr_bits = 8, .data_bits = 16, | |
466 | .write = snd_soc_8_16_write, .read = snd_soc_8_16_read, | |
467 | .i2c_read = snd_soc_8_16_read_i2c, | |
f479fd93 | 468 | .spi_write = snd_soc_8_16_spi_write, |
d62ab358 | 469 | }, |
994dc424 BS |
470 | { |
471 | .addr_bits = 16, .data_bits = 8, | |
472 | .write = snd_soc_16_8_write, .read = snd_soc_16_8_read, | |
473 | .i2c_read = snd_soc_16_8_read_i2c, | |
474 | .spi_write = snd_soc_16_8_spi_write, | |
475 | }, | |
bc6552f4 MB |
476 | { |
477 | .addr_bits = 16, .data_bits = 16, | |
478 | .write = snd_soc_16_16_write, .read = snd_soc_16_16_read, | |
479 | .i2c_read = snd_soc_16_16_read_i2c, | |
f479fd93 | 480 | .spi_write = snd_soc_16_16_spi_write, |
bc6552f4 | 481 | }, |
17a52fd6 MB |
482 | }; |
483 | ||
484 | /** | |
485 | * snd_soc_codec_set_cache_io: Set up standard I/O functions. | |
486 | * | |
487 | * @codec: CODEC to configure. | |
17a52fd6 MB |
488 | * @addr_bits: Number of bits of register address data. |
489 | * @data_bits: Number of bits of data per register. | |
7084a42b | 490 | * @control: Control bus used. |
17a52fd6 MB |
491 | * |
492 | * Register formats are frequently shared between many I2C and SPI | |
493 | * devices. In order to promote code reuse the ASoC core provides | |
494 | * some standard implementations of CODEC read and write operations | |
495 | * which can be set up using this function. | |
496 | * | |
497 | * The caller is responsible for allocating and initialising the | |
498 | * actual cache. | |
499 | * | |
500 | * Note that at present this code cannot be used by CODECs with | |
501 | * volatile registers. | |
502 | */ | |
503 | int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec, | |
7084a42b MB |
504 | int addr_bits, int data_bits, |
505 | enum snd_soc_control_type control) | |
17a52fd6 MB |
506 | { |
507 | int i; | |
508 | ||
17a52fd6 MB |
509 | for (i = 0; i < ARRAY_SIZE(io_types); i++) |
510 | if (io_types[i].addr_bits == addr_bits && | |
511 | io_types[i].data_bits == data_bits) | |
512 | break; | |
513 | if (i == ARRAY_SIZE(io_types)) { | |
514 | printk(KERN_ERR | |
515 | "No I/O functions for %d bit address %d bit data\n", | |
516 | addr_bits, data_bits); | |
517 | return -EINVAL; | |
518 | } | |
519 | ||
c3acec26 MB |
520 | codec->write = io_types[i].write; |
521 | codec->read = io_types[i].read; | |
5fb609d4 | 522 | codec->bulk_write_raw = snd_soc_hw_bulk_write_raw; |
17a52fd6 | 523 | |
7084a42b MB |
524 | switch (control) { |
525 | case SND_SOC_CUSTOM: | |
526 | break; | |
527 | ||
528 | case SND_SOC_I2C: | |
17244c24 | 529 | #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE)) |
7084a42b MB |
530 | codec->hw_write = (hw_write_t)i2c_master_send; |
531 | #endif | |
afa2f106 MB |
532 | if (io_types[i].i2c_read) |
533 | codec->hw_read = io_types[i].i2c_read; | |
a6d14342 MB |
534 | |
535 | codec->control_data = container_of(codec->dev, | |
536 | struct i2c_client, | |
537 | dev); | |
7084a42b MB |
538 | break; |
539 | ||
540 | case SND_SOC_SPI: | |
27ded041 MB |
541 | if (io_types[i].spi_write) |
542 | codec->hw_write = io_types[i].spi_write; | |
a6d14342 MB |
543 | |
544 | codec->control_data = container_of(codec->dev, | |
545 | struct spi_device, | |
546 | dev); | |
7084a42b MB |
547 | break; |
548 | } | |
549 | ||
17a52fd6 MB |
550 | return 0; |
551 | } | |
552 | EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io); | |
7a30a3db | 553 | |
1321e883 DP |
554 | static bool snd_soc_set_cache_val(void *base, unsigned int idx, |
555 | unsigned int val, unsigned int word_size) | |
556 | { | |
557 | switch (word_size) { | |
558 | case 1: { | |
559 | u8 *cache = base; | |
560 | if (cache[idx] == val) | |
561 | return true; | |
562 | cache[idx] = val; | |
563 | break; | |
564 | } | |
565 | case 2: { | |
566 | u16 *cache = base; | |
567 | if (cache[idx] == val) | |
568 | return true; | |
569 | cache[idx] = val; | |
570 | break; | |
571 | } | |
572 | default: | |
573 | BUG(); | |
574 | } | |
575 | return false; | |
576 | } | |
577 | ||
578 | static unsigned int snd_soc_get_cache_val(const void *base, unsigned int idx, | |
579 | unsigned int word_size) | |
580 | { | |
581 | switch (word_size) { | |
582 | case 1: { | |
583 | const u8 *cache = base; | |
584 | return cache[idx]; | |
585 | } | |
586 | case 2: { | |
587 | const u16 *cache = base; | |
588 | return cache[idx]; | |
589 | } | |
590 | default: | |
591 | BUG(); | |
592 | } | |
593 | /* unreachable */ | |
594 | return -1; | |
595 | } | |
596 | ||
a7f387d5 DP |
597 | struct snd_soc_rbtree_node { |
598 | struct rb_node node; | |
599 | unsigned int reg; | |
600 | unsigned int value; | |
601 | unsigned int defval; | |
602 | } __attribute__ ((packed)); | |
603 | ||
604 | struct snd_soc_rbtree_ctx { | |
605 | struct rb_root root; | |
606 | }; | |
607 | ||
608 | static struct snd_soc_rbtree_node *snd_soc_rbtree_lookup( | |
609 | struct rb_root *root, unsigned int reg) | |
610 | { | |
611 | struct rb_node *node; | |
612 | struct snd_soc_rbtree_node *rbnode; | |
613 | ||
614 | node = root->rb_node; | |
615 | while (node) { | |
616 | rbnode = container_of(node, struct snd_soc_rbtree_node, node); | |
617 | if (rbnode->reg < reg) | |
618 | node = node->rb_left; | |
619 | else if (rbnode->reg > reg) | |
620 | node = node->rb_right; | |
621 | else | |
622 | return rbnode; | |
623 | } | |
624 | ||
625 | return NULL; | |
626 | } | |
627 | ||
a7f387d5 DP |
628 | static int snd_soc_rbtree_insert(struct rb_root *root, |
629 | struct snd_soc_rbtree_node *rbnode) | |
630 | { | |
631 | struct rb_node **new, *parent; | |
632 | struct snd_soc_rbtree_node *rbnode_tmp; | |
633 | ||
634 | parent = NULL; | |
635 | new = &root->rb_node; | |
636 | while (*new) { | |
637 | rbnode_tmp = container_of(*new, struct snd_soc_rbtree_node, | |
638 | node); | |
639 | parent = *new; | |
640 | if (rbnode_tmp->reg < rbnode->reg) | |
641 | new = &((*new)->rb_left); | |
642 | else if (rbnode_tmp->reg > rbnode->reg) | |
643 | new = &((*new)->rb_right); | |
644 | else | |
645 | return 0; | |
646 | } | |
647 | ||
648 | /* insert the node into the rbtree */ | |
649 | rb_link_node(&rbnode->node, parent, new); | |
650 | rb_insert_color(&rbnode->node, root); | |
651 | ||
652 | return 1; | |
653 | } | |
654 | ||
655 | static int snd_soc_rbtree_cache_sync(struct snd_soc_codec *codec) | |
656 | { | |
657 | struct snd_soc_rbtree_ctx *rbtree_ctx; | |
658 | struct rb_node *node; | |
659 | struct snd_soc_rbtree_node *rbnode; | |
660 | unsigned int val; | |
7a33d4ce | 661 | int ret; |
a7f387d5 DP |
662 | |
663 | rbtree_ctx = codec->reg_cache; | |
664 | for (node = rb_first(&rbtree_ctx->root); node; node = rb_next(node)) { | |
665 | rbnode = rb_entry(node, struct snd_soc_rbtree_node, node); | |
666 | if (rbnode->value == rbnode->defval) | |
667 | continue; | |
f20eda5d DP |
668 | WARN_ON(codec->writable_register && |
669 | codec->writable_register(codec, rbnode->reg)); | |
7a33d4ce DP |
670 | ret = snd_soc_cache_read(codec, rbnode->reg, &val); |
671 | if (ret) | |
672 | return ret; | |
9978007b | 673 | codec->cache_bypass = 1; |
7a33d4ce | 674 | ret = snd_soc_write(codec, rbnode->reg, val); |
9978007b | 675 | codec->cache_bypass = 0; |
7a33d4ce DP |
676 | if (ret) |
677 | return ret; | |
a7f387d5 DP |
678 | dev_dbg(codec->dev, "Synced register %#x, value = %#x\n", |
679 | rbnode->reg, val); | |
680 | } | |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
685 | static int snd_soc_rbtree_cache_write(struct snd_soc_codec *codec, | |
686 | unsigned int reg, unsigned int value) | |
687 | { | |
688 | struct snd_soc_rbtree_ctx *rbtree_ctx; | |
689 | struct snd_soc_rbtree_node *rbnode; | |
690 | ||
691 | rbtree_ctx = codec->reg_cache; | |
692 | rbnode = snd_soc_rbtree_lookup(&rbtree_ctx->root, reg); | |
693 | if (rbnode) { | |
694 | if (rbnode->value == value) | |
695 | return 0; | |
696 | rbnode->value = value; | |
697 | } else { | |
698 | /* bail out early, no need to create the rbnode yet */ | |
699 | if (!value) | |
700 | return 0; | |
701 | /* | |
702 | * for uninitialized registers whose value is changed | |
703 | * from the default zero, create an rbnode and insert | |
704 | * it into the tree. | |
705 | */ | |
706 | rbnode = kzalloc(sizeof *rbnode, GFP_KERNEL); | |
707 | if (!rbnode) | |
708 | return -ENOMEM; | |
709 | rbnode->reg = reg; | |
710 | rbnode->value = value; | |
711 | snd_soc_rbtree_insert(&rbtree_ctx->root, rbnode); | |
712 | } | |
713 | ||
714 | return 0; | |
715 | } | |
716 | ||
717 | static int snd_soc_rbtree_cache_read(struct snd_soc_codec *codec, | |
718 | unsigned int reg, unsigned int *value) | |
719 | { | |
720 | struct snd_soc_rbtree_ctx *rbtree_ctx; | |
721 | struct snd_soc_rbtree_node *rbnode; | |
722 | ||
723 | rbtree_ctx = codec->reg_cache; | |
724 | rbnode = snd_soc_rbtree_lookup(&rbtree_ctx->root, reg); | |
725 | if (rbnode) { | |
726 | *value = rbnode->value; | |
727 | } else { | |
728 | /* uninitialized registers default to 0 */ | |
729 | *value = 0; | |
730 | } | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
735 | static int snd_soc_rbtree_cache_exit(struct snd_soc_codec *codec) | |
736 | { | |
737 | struct rb_node *next; | |
738 | struct snd_soc_rbtree_ctx *rbtree_ctx; | |
739 | struct snd_soc_rbtree_node *rbtree_node; | |
740 | ||
741 | /* if we've already been called then just return */ | |
742 | rbtree_ctx = codec->reg_cache; | |
743 | if (!rbtree_ctx) | |
744 | return 0; | |
745 | ||
746 | /* free up the rbtree */ | |
747 | next = rb_first(&rbtree_ctx->root); | |
748 | while (next) { | |
749 | rbtree_node = rb_entry(next, struct snd_soc_rbtree_node, node); | |
750 | next = rb_next(&rbtree_node->node); | |
751 | rb_erase(&rbtree_node->node, &rbtree_ctx->root); | |
752 | kfree(rbtree_node); | |
753 | } | |
754 | ||
755 | /* release the resources */ | |
756 | kfree(codec->reg_cache); | |
757 | codec->reg_cache = NULL; | |
758 | ||
759 | return 0; | |
760 | } | |
761 | ||
762 | static int snd_soc_rbtree_cache_init(struct snd_soc_codec *codec) | |
763 | { | |
1321e883 | 764 | struct snd_soc_rbtree_node *rbtree_node; |
a7f387d5 | 765 | struct snd_soc_rbtree_ctx *rbtree_ctx; |
1321e883 DP |
766 | unsigned int val; |
767 | unsigned int word_size; | |
768 | int i; | |
769 | int ret; | |
a7f387d5 DP |
770 | |
771 | codec->reg_cache = kmalloc(sizeof *rbtree_ctx, GFP_KERNEL); | |
772 | if (!codec->reg_cache) | |
773 | return -ENOMEM; | |
774 | ||
775 | rbtree_ctx = codec->reg_cache; | |
776 | rbtree_ctx->root = RB_ROOT; | |
777 | ||
3335ddca | 778 | if (!codec->reg_def_copy) |
a7f387d5 DP |
779 | return 0; |
780 | ||
1321e883 DP |
781 | /* |
782 | * populate the rbtree with the initialized registers. All other | |
783 | * registers will be inserted when they are first modified. | |
784 | */ | |
785 | word_size = codec->driver->reg_word_size; | |
786 | for (i = 0; i < codec->driver->reg_cache_size; ++i) { | |
787 | val = snd_soc_get_cache_val(codec->reg_def_copy, i, word_size); | |
788 | if (!val) | |
789 | continue; | |
790 | rbtree_node = kzalloc(sizeof *rbtree_node, GFP_KERNEL); | |
791 | if (!rbtree_node) { | |
792 | ret = -ENOMEM; | |
793 | snd_soc_cache_exit(codec); | |
794 | break; | |
795 | } | |
796 | rbtree_node->reg = i; | |
797 | rbtree_node->value = val; | |
798 | rbtree_node->defval = val; | |
799 | snd_soc_rbtree_insert(&rbtree_ctx->root, rbtree_node); | |
a7f387d5 DP |
800 | } |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
68d44ee0 | 805 | #ifdef CONFIG_SND_SOC_CACHE_LZO |
cc28fb8e DP |
806 | struct snd_soc_lzo_ctx { |
807 | void *wmem; | |
808 | void *dst; | |
809 | const void *src; | |
810 | size_t src_len; | |
811 | size_t dst_len; | |
812 | size_t decompressed_size; | |
813 | unsigned long *sync_bmp; | |
814 | int sync_bmp_nbits; | |
815 | }; | |
816 | ||
817 | #define LZO_BLOCK_NUM 8 | |
818 | static int snd_soc_lzo_block_count(void) | |
819 | { | |
820 | return LZO_BLOCK_NUM; | |
821 | } | |
822 | ||
823 | static int snd_soc_lzo_prepare(struct snd_soc_lzo_ctx *lzo_ctx) | |
824 | { | |
825 | lzo_ctx->wmem = kmalloc(LZO1X_MEM_COMPRESS, GFP_KERNEL); | |
826 | if (!lzo_ctx->wmem) | |
827 | return -ENOMEM; | |
828 | return 0; | |
829 | } | |
830 | ||
831 | static int snd_soc_lzo_compress(struct snd_soc_lzo_ctx *lzo_ctx) | |
832 | { | |
833 | size_t compress_size; | |
834 | int ret; | |
835 | ||
836 | ret = lzo1x_1_compress(lzo_ctx->src, lzo_ctx->src_len, | |
837 | lzo_ctx->dst, &compress_size, lzo_ctx->wmem); | |
838 | if (ret != LZO_E_OK || compress_size > lzo_ctx->dst_len) | |
839 | return -EINVAL; | |
840 | lzo_ctx->dst_len = compress_size; | |
841 | return 0; | |
842 | } | |
843 | ||
844 | static int snd_soc_lzo_decompress(struct snd_soc_lzo_ctx *lzo_ctx) | |
845 | { | |
846 | size_t dst_len; | |
847 | int ret; | |
848 | ||
849 | dst_len = lzo_ctx->dst_len; | |
850 | ret = lzo1x_decompress_safe(lzo_ctx->src, lzo_ctx->src_len, | |
851 | lzo_ctx->dst, &dst_len); | |
852 | if (ret != LZO_E_OK || dst_len != lzo_ctx->dst_len) | |
853 | return -EINVAL; | |
854 | return 0; | |
855 | } | |
856 | ||
857 | static int snd_soc_lzo_compress_cache_block(struct snd_soc_codec *codec, | |
858 | struct snd_soc_lzo_ctx *lzo_ctx) | |
859 | { | |
860 | int ret; | |
861 | ||
862 | lzo_ctx->dst_len = lzo1x_worst_compress(PAGE_SIZE); | |
863 | lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL); | |
864 | if (!lzo_ctx->dst) { | |
865 | lzo_ctx->dst_len = 0; | |
866 | return -ENOMEM; | |
867 | } | |
868 | ||
869 | ret = snd_soc_lzo_compress(lzo_ctx); | |
870 | if (ret < 0) | |
871 | return ret; | |
872 | return 0; | |
873 | } | |
874 | ||
875 | static int snd_soc_lzo_decompress_cache_block(struct snd_soc_codec *codec, | |
876 | struct snd_soc_lzo_ctx *lzo_ctx) | |
877 | { | |
878 | int ret; | |
879 | ||
880 | lzo_ctx->dst_len = lzo_ctx->decompressed_size; | |
881 | lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL); | |
882 | if (!lzo_ctx->dst) { | |
883 | lzo_ctx->dst_len = 0; | |
884 | return -ENOMEM; | |
885 | } | |
886 | ||
887 | ret = snd_soc_lzo_decompress(lzo_ctx); | |
888 | if (ret < 0) | |
889 | return ret; | |
890 | return 0; | |
891 | } | |
892 | ||
893 | static inline int snd_soc_lzo_get_blkindex(struct snd_soc_codec *codec, | |
894 | unsigned int reg) | |
895 | { | |
001ae4c0 | 896 | const struct snd_soc_codec_driver *codec_drv; |
cc28fb8e DP |
897 | |
898 | codec_drv = codec->driver; | |
cc28fb8e | 899 | return (reg * codec_drv->reg_word_size) / |
aea170a0 | 900 | DIV_ROUND_UP(codec->reg_size, snd_soc_lzo_block_count()); |
cc28fb8e DP |
901 | } |
902 | ||
903 | static inline int snd_soc_lzo_get_blkpos(struct snd_soc_codec *codec, | |
904 | unsigned int reg) | |
905 | { | |
001ae4c0 | 906 | const struct snd_soc_codec_driver *codec_drv; |
cc28fb8e DP |
907 | |
908 | codec_drv = codec->driver; | |
aea170a0 | 909 | return reg % (DIV_ROUND_UP(codec->reg_size, snd_soc_lzo_block_count()) / |
cc28fb8e DP |
910 | codec_drv->reg_word_size); |
911 | } | |
912 | ||
913 | static inline int snd_soc_lzo_get_blksize(struct snd_soc_codec *codec) | |
914 | { | |
001ae4c0 | 915 | const struct snd_soc_codec_driver *codec_drv; |
cc28fb8e DP |
916 | |
917 | codec_drv = codec->driver; | |
aea170a0 | 918 | return DIV_ROUND_UP(codec->reg_size, snd_soc_lzo_block_count()); |
cc28fb8e DP |
919 | } |
920 | ||
921 | static int snd_soc_lzo_cache_sync(struct snd_soc_codec *codec) | |
922 | { | |
923 | struct snd_soc_lzo_ctx **lzo_blocks; | |
924 | unsigned int val; | |
925 | int i; | |
7a33d4ce | 926 | int ret; |
cc28fb8e DP |
927 | |
928 | lzo_blocks = codec->reg_cache; | |
929 | for_each_set_bit(i, lzo_blocks[0]->sync_bmp, lzo_blocks[0]->sync_bmp_nbits) { | |
f20eda5d DP |
930 | WARN_ON(codec->writable_register && |
931 | codec->writable_register(codec, i)); | |
7a33d4ce DP |
932 | ret = snd_soc_cache_read(codec, i, &val); |
933 | if (ret) | |
934 | return ret; | |
9978007b | 935 | codec->cache_bypass = 1; |
7a33d4ce | 936 | ret = snd_soc_write(codec, i, val); |
9978007b | 937 | codec->cache_bypass = 0; |
7a33d4ce DP |
938 | if (ret) |
939 | return ret; | |
cc28fb8e DP |
940 | dev_dbg(codec->dev, "Synced register %#x, value = %#x\n", |
941 | i, val); | |
942 | } | |
943 | ||
944 | return 0; | |
945 | } | |
946 | ||
947 | static int snd_soc_lzo_cache_write(struct snd_soc_codec *codec, | |
948 | unsigned int reg, unsigned int value) | |
949 | { | |
950 | struct snd_soc_lzo_ctx *lzo_block, **lzo_blocks; | |
951 | int ret, blkindex, blkpos; | |
952 | size_t blksize, tmp_dst_len; | |
953 | void *tmp_dst; | |
954 | ||
955 | /* index of the compressed lzo block */ | |
956 | blkindex = snd_soc_lzo_get_blkindex(codec, reg); | |
957 | /* register index within the decompressed block */ | |
958 | blkpos = snd_soc_lzo_get_blkpos(codec, reg); | |
959 | /* size of the compressed block */ | |
960 | blksize = snd_soc_lzo_get_blksize(codec); | |
961 | lzo_blocks = codec->reg_cache; | |
962 | lzo_block = lzo_blocks[blkindex]; | |
963 | ||
964 | /* save the pointer and length of the compressed block */ | |
965 | tmp_dst = lzo_block->dst; | |
966 | tmp_dst_len = lzo_block->dst_len; | |
967 | ||
968 | /* prepare the source to be the compressed block */ | |
969 | lzo_block->src = lzo_block->dst; | |
970 | lzo_block->src_len = lzo_block->dst_len; | |
971 | ||
972 | /* decompress the block */ | |
973 | ret = snd_soc_lzo_decompress_cache_block(codec, lzo_block); | |
974 | if (ret < 0) { | |
975 | kfree(lzo_block->dst); | |
976 | goto out; | |
977 | } | |
978 | ||
979 | /* write the new value to the cache */ | |
1321e883 DP |
980 | if (snd_soc_set_cache_val(lzo_block->dst, blkpos, value, |
981 | codec->driver->reg_word_size)) { | |
982 | kfree(lzo_block->dst); | |
983 | goto out; | |
cc28fb8e DP |
984 | } |
985 | ||
986 | /* prepare the source to be the decompressed block */ | |
987 | lzo_block->src = lzo_block->dst; | |
988 | lzo_block->src_len = lzo_block->dst_len; | |
989 | ||
990 | /* compress the block */ | |
991 | ret = snd_soc_lzo_compress_cache_block(codec, lzo_block); | |
992 | if (ret < 0) { | |
993 | kfree(lzo_block->dst); | |
994 | kfree(lzo_block->src); | |
995 | goto out; | |
996 | } | |
997 | ||
998 | /* set the bit so we know we have to sync this register */ | |
999 | set_bit(reg, lzo_block->sync_bmp); | |
1000 | kfree(tmp_dst); | |
1001 | kfree(lzo_block->src); | |
1002 | return 0; | |
1003 | out: | |
1004 | lzo_block->dst = tmp_dst; | |
1005 | lzo_block->dst_len = tmp_dst_len; | |
1006 | return ret; | |
1007 | } | |
1008 | ||
1009 | static int snd_soc_lzo_cache_read(struct snd_soc_codec *codec, | |
1010 | unsigned int reg, unsigned int *value) | |
1011 | { | |
1012 | struct snd_soc_lzo_ctx *lzo_block, **lzo_blocks; | |
1013 | int ret, blkindex, blkpos; | |
1014 | size_t blksize, tmp_dst_len; | |
1015 | void *tmp_dst; | |
1016 | ||
1017 | *value = 0; | |
1018 | /* index of the compressed lzo block */ | |
1019 | blkindex = snd_soc_lzo_get_blkindex(codec, reg); | |
1020 | /* register index within the decompressed block */ | |
1021 | blkpos = snd_soc_lzo_get_blkpos(codec, reg); | |
1022 | /* size of the compressed block */ | |
1023 | blksize = snd_soc_lzo_get_blksize(codec); | |
1024 | lzo_blocks = codec->reg_cache; | |
1025 | lzo_block = lzo_blocks[blkindex]; | |
1026 | ||
1027 | /* save the pointer and length of the compressed block */ | |
1028 | tmp_dst = lzo_block->dst; | |
1029 | tmp_dst_len = lzo_block->dst_len; | |
1030 | ||
1031 | /* prepare the source to be the compressed block */ | |
1032 | lzo_block->src = lzo_block->dst; | |
1033 | lzo_block->src_len = lzo_block->dst_len; | |
1034 | ||
1035 | /* decompress the block */ | |
1036 | ret = snd_soc_lzo_decompress_cache_block(codec, lzo_block); | |
1321e883 | 1037 | if (ret >= 0) |
cc28fb8e | 1038 | /* fetch the value from the cache */ |
1321e883 DP |
1039 | *value = snd_soc_get_cache_val(lzo_block->dst, blkpos, |
1040 | codec->driver->reg_word_size); | |
cc28fb8e DP |
1041 | |
1042 | kfree(lzo_block->dst); | |
1043 | /* restore the pointer and length of the compressed block */ | |
1044 | lzo_block->dst = tmp_dst; | |
1045 | lzo_block->dst_len = tmp_dst_len; | |
1046 | return 0; | |
1047 | } | |
1048 | ||
1049 | static int snd_soc_lzo_cache_exit(struct snd_soc_codec *codec) | |
1050 | { | |
1051 | struct snd_soc_lzo_ctx **lzo_blocks; | |
1052 | int i, blkcount; | |
1053 | ||
1054 | lzo_blocks = codec->reg_cache; | |
1055 | if (!lzo_blocks) | |
1056 | return 0; | |
1057 | ||
1058 | blkcount = snd_soc_lzo_block_count(); | |
1059 | /* | |
1060 | * the pointer to the bitmap used for syncing the cache | |
1061 | * is shared amongst all lzo_blocks. Ensure it is freed | |
1062 | * only once. | |
1063 | */ | |
1064 | if (lzo_blocks[0]) | |
1065 | kfree(lzo_blocks[0]->sync_bmp); | |
1066 | for (i = 0; i < blkcount; ++i) { | |
1067 | if (lzo_blocks[i]) { | |
1068 | kfree(lzo_blocks[i]->wmem); | |
1069 | kfree(lzo_blocks[i]->dst); | |
1070 | } | |
1071 | /* each lzo_block is a pointer returned by kmalloc or NULL */ | |
1072 | kfree(lzo_blocks[i]); | |
1073 | } | |
1074 | kfree(lzo_blocks); | |
1075 | codec->reg_cache = NULL; | |
1076 | return 0; | |
1077 | } | |
1078 | ||
1079 | static int snd_soc_lzo_cache_init(struct snd_soc_codec *codec) | |
1080 | { | |
1081 | struct snd_soc_lzo_ctx **lzo_blocks; | |
aea170a0 | 1082 | size_t bmp_size; |
001ae4c0 | 1083 | const struct snd_soc_codec_driver *codec_drv; |
cc28fb8e DP |
1084 | int ret, tofree, i, blksize, blkcount; |
1085 | const char *p, *end; | |
1086 | unsigned long *sync_bmp; | |
1087 | ||
1088 | ret = 0; | |
1089 | codec_drv = codec->driver; | |
cc28fb8e DP |
1090 | |
1091 | /* | |
1092 | * If we have not been given a default register cache | |
1093 | * then allocate a dummy zero-ed out region, compress it | |
1094 | * and remember to free it afterwards. | |
1095 | */ | |
1096 | tofree = 0; | |
3335ddca | 1097 | if (!codec->reg_def_copy) |
cc28fb8e DP |
1098 | tofree = 1; |
1099 | ||
3335ddca | 1100 | if (!codec->reg_def_copy) { |
aea170a0 | 1101 | codec->reg_def_copy = kzalloc(codec->reg_size, GFP_KERNEL); |
3335ddca | 1102 | if (!codec->reg_def_copy) |
cc28fb8e DP |
1103 | return -ENOMEM; |
1104 | } | |
1105 | ||
1106 | blkcount = snd_soc_lzo_block_count(); | |
1107 | codec->reg_cache = kzalloc(blkcount * sizeof *lzo_blocks, | |
1108 | GFP_KERNEL); | |
1109 | if (!codec->reg_cache) { | |
1110 | ret = -ENOMEM; | |
1111 | goto err_tofree; | |
1112 | } | |
1113 | lzo_blocks = codec->reg_cache; | |
1114 | ||
1115 | /* | |
1116 | * allocate a bitmap to be used when syncing the cache with | |
1117 | * the hardware. Each time a register is modified, the corresponding | |
1118 | * bit is set in the bitmap, so we know that we have to sync | |
1119 | * that register. | |
1120 | */ | |
1121 | bmp_size = codec_drv->reg_cache_size; | |
465d7fcc | 1122 | sync_bmp = kmalloc(BITS_TO_LONGS(bmp_size) * sizeof(long), |
cc28fb8e DP |
1123 | GFP_KERNEL); |
1124 | if (!sync_bmp) { | |
1125 | ret = -ENOMEM; | |
1126 | goto err; | |
1127 | } | |
09c74a9d | 1128 | bitmap_zero(sync_bmp, bmp_size); |
cc28fb8e DP |
1129 | |
1130 | /* allocate the lzo blocks and initialize them */ | |
1131 | for (i = 0; i < blkcount; ++i) { | |
1132 | lzo_blocks[i] = kzalloc(sizeof **lzo_blocks, | |
1133 | GFP_KERNEL); | |
1134 | if (!lzo_blocks[i]) { | |
1135 | kfree(sync_bmp); | |
1136 | ret = -ENOMEM; | |
1137 | goto err; | |
1138 | } | |
1139 | lzo_blocks[i]->sync_bmp = sync_bmp; | |
04f8fd17 | 1140 | lzo_blocks[i]->sync_bmp_nbits = bmp_size; |
cc28fb8e DP |
1141 | /* alloc the working space for the compressed block */ |
1142 | ret = snd_soc_lzo_prepare(lzo_blocks[i]); | |
1143 | if (ret < 0) | |
1144 | goto err; | |
1145 | } | |
1146 | ||
1147 | blksize = snd_soc_lzo_get_blksize(codec); | |
3335ddca | 1148 | p = codec->reg_def_copy; |
aea170a0 | 1149 | end = codec->reg_def_copy + codec->reg_size; |
cc28fb8e DP |
1150 | /* compress the register map and fill the lzo blocks */ |
1151 | for (i = 0; i < blkcount; ++i, p += blksize) { | |
1152 | lzo_blocks[i]->src = p; | |
1153 | if (p + blksize > end) | |
1154 | lzo_blocks[i]->src_len = end - p; | |
1155 | else | |
1156 | lzo_blocks[i]->src_len = blksize; | |
1157 | ret = snd_soc_lzo_compress_cache_block(codec, | |
1158 | lzo_blocks[i]); | |
1159 | if (ret < 0) | |
1160 | goto err; | |
1161 | lzo_blocks[i]->decompressed_size = | |
1162 | lzo_blocks[i]->src_len; | |
1163 | } | |
1164 | ||
3335ddca DP |
1165 | if (tofree) { |
1166 | kfree(codec->reg_def_copy); | |
1167 | codec->reg_def_copy = NULL; | |
1168 | } | |
cc28fb8e DP |
1169 | return 0; |
1170 | err: | |
1171 | snd_soc_cache_exit(codec); | |
1172 | err_tofree: | |
3335ddca DP |
1173 | if (tofree) { |
1174 | kfree(codec->reg_def_copy); | |
1175 | codec->reg_def_copy = NULL; | |
1176 | } | |
cc28fb8e DP |
1177 | return ret; |
1178 | } | |
68d44ee0 | 1179 | #endif |
cc28fb8e | 1180 | |
7a30a3db DP |
1181 | static int snd_soc_flat_cache_sync(struct snd_soc_codec *codec) |
1182 | { | |
1183 | int i; | |
7a33d4ce | 1184 | int ret; |
001ae4c0 | 1185 | const struct snd_soc_codec_driver *codec_drv; |
7a30a3db DP |
1186 | unsigned int val; |
1187 | ||
1188 | codec_drv = codec->driver; | |
1189 | for (i = 0; i < codec_drv->reg_cache_size; ++i) { | |
f20eda5d DP |
1190 | WARN_ON(codec->writable_register && |
1191 | codec->writable_register(codec, i)); | |
7a33d4ce DP |
1192 | ret = snd_soc_cache_read(codec, i, &val); |
1193 | if (ret) | |
1194 | return ret; | |
d779fce5 DP |
1195 | if (codec->reg_def_copy) |
1196 | if (snd_soc_get_cache_val(codec->reg_def_copy, | |
1321e883 DP |
1197 | i, codec_drv->reg_word_size) == val) |
1198 | continue; | |
7a33d4ce DP |
1199 | ret = snd_soc_write(codec, i, val); |
1200 | if (ret) | |
1201 | return ret; | |
7a30a3db DP |
1202 | dev_dbg(codec->dev, "Synced register %#x, value = %#x\n", |
1203 | i, val); | |
1204 | } | |
1205 | return 0; | |
1206 | } | |
1207 | ||
1208 | static int snd_soc_flat_cache_write(struct snd_soc_codec *codec, | |
1209 | unsigned int reg, unsigned int value) | |
1210 | { | |
1321e883 DP |
1211 | snd_soc_set_cache_val(codec->reg_cache, reg, value, |
1212 | codec->driver->reg_word_size); | |
7a30a3db DP |
1213 | return 0; |
1214 | } | |
1215 | ||
1216 | static int snd_soc_flat_cache_read(struct snd_soc_codec *codec, | |
1217 | unsigned int reg, unsigned int *value) | |
1218 | { | |
1321e883 DP |
1219 | *value = snd_soc_get_cache_val(codec->reg_cache, reg, |
1220 | codec->driver->reg_word_size); | |
7a30a3db DP |
1221 | return 0; |
1222 | } | |
1223 | ||
1224 | static int snd_soc_flat_cache_exit(struct snd_soc_codec *codec) | |
1225 | { | |
1226 | if (!codec->reg_cache) | |
1227 | return 0; | |
1228 | kfree(codec->reg_cache); | |
1229 | codec->reg_cache = NULL; | |
1230 | return 0; | |
1231 | } | |
1232 | ||
1233 | static int snd_soc_flat_cache_init(struct snd_soc_codec *codec) | |
1234 | { | |
001ae4c0 | 1235 | const struct snd_soc_codec_driver *codec_drv; |
7a30a3db DP |
1236 | |
1237 | codec_drv = codec->driver; | |
7a30a3db | 1238 | |
d779fce5 DP |
1239 | if (codec->reg_def_copy) |
1240 | codec->reg_cache = kmemdup(codec->reg_def_copy, | |
aea170a0 | 1241 | codec->reg_size, GFP_KERNEL); |
7a30a3db | 1242 | else |
aea170a0 | 1243 | codec->reg_cache = kzalloc(codec->reg_size, GFP_KERNEL); |
7a30a3db DP |
1244 | if (!codec->reg_cache) |
1245 | return -ENOMEM; | |
1246 | ||
1247 | return 0; | |
1248 | } | |
1249 | ||
1250 | /* an array of all supported compression types */ | |
1251 | static const struct snd_soc_cache_ops cache_types[] = { | |
be4fcddd | 1252 | /* Flat *must* be the first entry for fallback */ |
7a30a3db | 1253 | { |
df0701bb | 1254 | .id = SND_SOC_FLAT_COMPRESSION, |
0d735eaa | 1255 | .name = "flat", |
7a30a3db DP |
1256 | .init = snd_soc_flat_cache_init, |
1257 | .exit = snd_soc_flat_cache_exit, | |
1258 | .read = snd_soc_flat_cache_read, | |
1259 | .write = snd_soc_flat_cache_write, | |
1260 | .sync = snd_soc_flat_cache_sync | |
cc28fb8e | 1261 | }, |
68d44ee0 | 1262 | #ifdef CONFIG_SND_SOC_CACHE_LZO |
cc28fb8e DP |
1263 | { |
1264 | .id = SND_SOC_LZO_COMPRESSION, | |
0d735eaa | 1265 | .name = "LZO", |
cc28fb8e DP |
1266 | .init = snd_soc_lzo_cache_init, |
1267 | .exit = snd_soc_lzo_cache_exit, | |
1268 | .read = snd_soc_lzo_cache_read, | |
1269 | .write = snd_soc_lzo_cache_write, | |
1270 | .sync = snd_soc_lzo_cache_sync | |
a7f387d5 | 1271 | }, |
68d44ee0 | 1272 | #endif |
a7f387d5 DP |
1273 | { |
1274 | .id = SND_SOC_RBTREE_COMPRESSION, | |
0d735eaa | 1275 | .name = "rbtree", |
a7f387d5 DP |
1276 | .init = snd_soc_rbtree_cache_init, |
1277 | .exit = snd_soc_rbtree_cache_exit, | |
1278 | .read = snd_soc_rbtree_cache_read, | |
1279 | .write = snd_soc_rbtree_cache_write, | |
1280 | .sync = snd_soc_rbtree_cache_sync | |
7a30a3db DP |
1281 | } |
1282 | }; | |
1283 | ||
1284 | int snd_soc_cache_init(struct snd_soc_codec *codec) | |
1285 | { | |
1286 | int i; | |
1287 | ||
1288 | for (i = 0; i < ARRAY_SIZE(cache_types); ++i) | |
23bbce34 | 1289 | if (cache_types[i].id == codec->compress_type) |
7a30a3db | 1290 | break; |
be4fcddd MB |
1291 | |
1292 | /* Fall back to flat compression */ | |
7a30a3db | 1293 | if (i == ARRAY_SIZE(cache_types)) { |
be4fcddd MB |
1294 | dev_warn(codec->dev, "Could not match compress type: %d\n", |
1295 | codec->compress_type); | |
1296 | i = 0; | |
7a30a3db DP |
1297 | } |
1298 | ||
1299 | mutex_init(&codec->cache_rw_mutex); | |
1300 | codec->cache_ops = &cache_types[i]; | |
1301 | ||
0d735eaa DP |
1302 | if (codec->cache_ops->init) { |
1303 | if (codec->cache_ops->name) | |
1304 | dev_dbg(codec->dev, "Initializing %s cache for %s codec\n", | |
1305 | codec->cache_ops->name, codec->name); | |
7a30a3db | 1306 | return codec->cache_ops->init(codec); |
0d735eaa | 1307 | } |
acd61451 | 1308 | return -ENOSYS; |
7a30a3db DP |
1309 | } |
1310 | ||
1311 | /* | |
1312 | * NOTE: keep in mind that this function might be called | |
1313 | * multiple times. | |
1314 | */ | |
1315 | int snd_soc_cache_exit(struct snd_soc_codec *codec) | |
1316 | { | |
0d735eaa DP |
1317 | if (codec->cache_ops && codec->cache_ops->exit) { |
1318 | if (codec->cache_ops->name) | |
1319 | dev_dbg(codec->dev, "Destroying %s cache for %s codec\n", | |
1320 | codec->cache_ops->name, codec->name); | |
7a30a3db | 1321 | return codec->cache_ops->exit(codec); |
0d735eaa | 1322 | } |
acd61451 | 1323 | return -ENOSYS; |
7a30a3db DP |
1324 | } |
1325 | ||
1326 | /** | |
1327 | * snd_soc_cache_read: Fetch the value of a given register from the cache. | |
1328 | * | |
1329 | * @codec: CODEC to configure. | |
1330 | * @reg: The register index. | |
1331 | * @value: The value to be returned. | |
1332 | */ | |
1333 | int snd_soc_cache_read(struct snd_soc_codec *codec, | |
1334 | unsigned int reg, unsigned int *value) | |
1335 | { | |
1336 | int ret; | |
1337 | ||
1338 | mutex_lock(&codec->cache_rw_mutex); | |
1339 | ||
1340 | if (value && codec->cache_ops && codec->cache_ops->read) { | |
1341 | ret = codec->cache_ops->read(codec, reg, value); | |
1342 | mutex_unlock(&codec->cache_rw_mutex); | |
1343 | return ret; | |
1344 | } | |
1345 | ||
1346 | mutex_unlock(&codec->cache_rw_mutex); | |
acd61451 | 1347 | return -ENOSYS; |
7a30a3db DP |
1348 | } |
1349 | EXPORT_SYMBOL_GPL(snd_soc_cache_read); | |
1350 | ||
1351 | /** | |
1352 | * snd_soc_cache_write: Set the value of a given register in the cache. | |
1353 | * | |
1354 | * @codec: CODEC to configure. | |
1355 | * @reg: The register index. | |
1356 | * @value: The new register value. | |
1357 | */ | |
1358 | int snd_soc_cache_write(struct snd_soc_codec *codec, | |
1359 | unsigned int reg, unsigned int value) | |
1360 | { | |
1361 | int ret; | |
1362 | ||
1363 | mutex_lock(&codec->cache_rw_mutex); | |
1364 | ||
1365 | if (codec->cache_ops && codec->cache_ops->write) { | |
1366 | ret = codec->cache_ops->write(codec, reg, value); | |
1367 | mutex_unlock(&codec->cache_rw_mutex); | |
1368 | return ret; | |
1369 | } | |
1370 | ||
1371 | mutex_unlock(&codec->cache_rw_mutex); | |
acd61451 | 1372 | return -ENOSYS; |
7a30a3db DP |
1373 | } |
1374 | EXPORT_SYMBOL_GPL(snd_soc_cache_write); | |
1375 | ||
1376 | /** | |
1377 | * snd_soc_cache_sync: Sync the register cache with the hardware. | |
1378 | * | |
1379 | * @codec: CODEC to configure. | |
1380 | * | |
1381 | * Any registers that should not be synced should be marked as | |
1382 | * volatile. In general drivers can choose not to use the provided | |
1383 | * syncing functionality if they so require. | |
1384 | */ | |
1385 | int snd_soc_cache_sync(struct snd_soc_codec *codec) | |
1386 | { | |
1387 | int ret; | |
c358e640 | 1388 | const char *name; |
7a30a3db DP |
1389 | |
1390 | if (!codec->cache_sync) { | |
1391 | return 0; | |
1392 | } | |
1393 | ||
46fdaa3b | 1394 | if (!codec->cache_ops || !codec->cache_ops->sync) |
acd61451 | 1395 | return -ENOSYS; |
46fdaa3b | 1396 | |
c358e640 DP |
1397 | if (codec->cache_ops->name) |
1398 | name = codec->cache_ops->name; | |
1399 | else | |
1400 | name = "unknown"; | |
1401 | ||
46fdaa3b DC |
1402 | if (codec->cache_ops->name) |
1403 | dev_dbg(codec->dev, "Syncing %s cache for %s codec\n", | |
1404 | codec->cache_ops->name, codec->name); | |
1405 | trace_snd_soc_cache_sync(codec, name, "start"); | |
1406 | ret = codec->cache_ops->sync(codec); | |
1407 | if (!ret) | |
1408 | codec->cache_sync = 0; | |
1409 | trace_snd_soc_cache_sync(codec, name, "end"); | |
1410 | return ret; | |
7a30a3db DP |
1411 | } |
1412 | EXPORT_SYMBOL_GPL(snd_soc_cache_sync); | |
066d16c3 DP |
1413 | |
1414 | static int snd_soc_get_reg_access_index(struct snd_soc_codec *codec, | |
1415 | unsigned int reg) | |
1416 | { | |
1417 | const struct snd_soc_codec_driver *codec_drv; | |
1418 | unsigned int min, max, index; | |
1419 | ||
1420 | codec_drv = codec->driver; | |
1421 | min = 0; | |
1422 | max = codec_drv->reg_access_size - 1; | |
1423 | do { | |
1424 | index = (min + max) / 2; | |
1425 | if (codec_drv->reg_access_default[index].reg == reg) | |
1426 | return index; | |
1427 | if (codec_drv->reg_access_default[index].reg < reg) | |
1428 | min = index + 1; | |
1429 | else | |
1430 | max = index; | |
1431 | } while (min <= max); | |
1432 | return -1; | |
1433 | } | |
1434 | ||
1435 | int snd_soc_default_volatile_register(struct snd_soc_codec *codec, | |
1436 | unsigned int reg) | |
1437 | { | |
1438 | int index; | |
1439 | ||
1440 | if (reg >= codec->driver->reg_cache_size) | |
1441 | return 1; | |
1442 | index = snd_soc_get_reg_access_index(codec, reg); | |
1443 | if (index < 0) | |
1444 | return 0; | |
1445 | return codec->driver->reg_access_default[index].vol; | |
1446 | } | |
1447 | EXPORT_SYMBOL_GPL(snd_soc_default_volatile_register); | |
1448 | ||
1449 | int snd_soc_default_readable_register(struct snd_soc_codec *codec, | |
1450 | unsigned int reg) | |
1451 | { | |
1452 | int index; | |
1453 | ||
1454 | if (reg >= codec->driver->reg_cache_size) | |
1455 | return 1; | |
1456 | index = snd_soc_get_reg_access_index(codec, reg); | |
1457 | if (index < 0) | |
1458 | return 0; | |
1459 | return codec->driver->reg_access_default[index].read; | |
1460 | } | |
1461 | EXPORT_SYMBOL_GPL(snd_soc_default_readable_register); | |
8020454c DP |
1462 | |
1463 | int snd_soc_default_writable_register(struct snd_soc_codec *codec, | |
1464 | unsigned int reg) | |
1465 | { | |
1466 | int index; | |
1467 | ||
1468 | if (reg >= codec->driver->reg_cache_size) | |
1469 | return 1; | |
1470 | index = snd_soc_get_reg_access_index(codec, reg); | |
1471 | if (index < 0) | |
1472 | return 0; | |
1473 | return codec->driver->reg_access_default[index].write; | |
1474 | } | |
1475 | EXPORT_SYMBOL_GPL(snd_soc_default_writable_register); |