ASoC: soc-cache: Introduce the cache_bypass option
[deliverable/linux.git] / sound / soc / soc-cache.c
CommitLineData
17a52fd6
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1/*
2 * soc-cache.c -- ASoC register cache helpers
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
7084a42b 14#include <linux/i2c.h>
27ded041 15#include <linux/spi/spi.h>
17a52fd6 16#include <sound/soc.h>
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17#include <linux/lzo.h>
18#include <linux/bitmap.h>
a7f387d5 19#include <linux/rbtree.h>
17a52fd6 20
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21static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
22 unsigned int reg)
23{
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24 int ret;
25 unsigned int val;
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26
27 if (reg >= codec->driver->reg_cache_size ||
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28 snd_soc_codec_volatile_register(codec, reg) ||
29 codec->cache_bypass) {
db49c146
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30 if (codec->cache_only)
31 return -1;
32
5aaa062c 33 BUG_ON(!codec->hw_read);
db49c146
DP
34 return codec->hw_read(codec, reg);
35 }
36
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37 ret = snd_soc_cache_read(codec, reg, &val);
38 if (ret < 0)
39 return -1;
40 return val;
63b62ab0
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41}
42
43static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
44 unsigned int value)
45{
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46 u8 data[2];
47 int ret;
48
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49 data[0] = (reg << 4) | ((value >> 8) & 0x000f);
50 data[1] = value & 0x00ff;
51
db49c146 52 if (!snd_soc_codec_volatile_register(codec, reg) &&
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53 reg < codec->driver->reg_cache_size &&
54 !codec->cache_bypass) {
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DP
55 ret = snd_soc_cache_write(codec, reg, value);
56 if (ret < 0)
57 return -1;
58 }
8c961bcc 59
a3032b47
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60 if (codec->cache_only) {
61 codec->cache_sync = 1;
8c961bcc 62 return 0;
a3032b47 63 }
8c961bcc 64
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65 ret = codec->hw_write(codec->control_data, data, 2);
66 if (ret == 2)
67 return 0;
68 if (ret < 0)
69 return ret;
70 else
71 return -EIO;
72}
73
74#if defined(CONFIG_SPI_MASTER)
75static int snd_soc_4_12_spi_write(void *control_data, const char *data,
76 int len)
77{
78 struct spi_device *spi = control_data;
79 struct spi_transfer t;
80 struct spi_message m;
81 u8 msg[2];
82
83 if (len <= 0)
84 return 0;
85
86 msg[0] = data[1];
87 msg[1] = data[0];
88
89 spi_message_init(&m);
465d7fcc 90 memset(&t, 0, sizeof t);
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91
92 t.tx_buf = &msg[0];
93 t.len = len;
94
95 spi_message_add_tail(&t, &m);
96 spi_sync(spi, &m);
97
98 return len;
99}
100#else
101#define snd_soc_4_12_spi_write NULL
102#endif
103
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104static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
105 unsigned int reg)
106{
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107 int ret;
108 unsigned int val;
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109
110 if (reg >= codec->driver->reg_cache_size ||
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111 snd_soc_codec_volatile_register(codec, reg) ||
112 codec->cache_bypass) {
db49c146
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113 if (codec->cache_only)
114 return -1;
115
5aaa062c 116 BUG_ON(!codec->hw_read);
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117 return codec->hw_read(codec, reg);
118 }
119
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120 ret = snd_soc_cache_read(codec, reg, &val);
121 if (ret < 0)
122 return -1;
123 return val;
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124}
125
126static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
127 unsigned int value)
128{
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129 u8 data[2];
130 int ret;
131
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132 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
133 data[1] = value & 0x00ff;
134
db49c146 135 if (!snd_soc_codec_volatile_register(codec, reg) &&
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136 reg < codec->driver->reg_cache_size &&
137 !codec->cache_bypass) {
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138 ret = snd_soc_cache_write(codec, reg, value);
139 if (ret < 0)
140 return -1;
141 }
8c961bcc 142
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143 if (codec->cache_only) {
144 codec->cache_sync = 1;
8c961bcc 145 return 0;
a3032b47 146 }
8c961bcc 147
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148 ret = codec->hw_write(codec->control_data, data, 2);
149 if (ret == 2)
150 return 0;
151 if (ret < 0)
152 return ret;
153 else
154 return -EIO;
155}
156
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157#if defined(CONFIG_SPI_MASTER)
158static int snd_soc_7_9_spi_write(void *control_data, const char *data,
159 int len)
160{
161 struct spi_device *spi = control_data;
162 struct spi_transfer t;
163 struct spi_message m;
164 u8 msg[2];
165
166 if (len <= 0)
167 return 0;
168
169 msg[0] = data[0];
170 msg[1] = data[1];
171
172 spi_message_init(&m);
465d7fcc 173 memset(&t, 0, sizeof t);
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174
175 t.tx_buf = &msg[0];
176 t.len = len;
177
178 spi_message_add_tail(&t, &m);
179 spi_sync(spi, &m);
180
181 return len;
182}
183#else
184#define snd_soc_7_9_spi_write NULL
185#endif
186
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187static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
188 unsigned int value)
189{
341c9b84 190 u8 data[2];
7a30a3db 191 int ret;
341c9b84 192
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193 reg &= 0xff;
194 data[0] = reg;
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195 data[1] = value & 0xff;
196
005d65fb 197 if (!snd_soc_codec_volatile_register(codec, reg) &&
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198 reg < codec->driver->reg_cache_size &&
199 !codec->cache_bypass) {
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200 ret = snd_soc_cache_write(codec, reg, value);
201 if (ret < 0)
202 return -1;
203 }
341c9b84 204
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205 if (codec->cache_only) {
206 codec->cache_sync = 1;
8c961bcc 207 return 0;
a3032b47 208 }
8c961bcc 209
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210 if (codec->hw_write(codec->control_data, data, 2) == 2)
211 return 0;
212 else
213 return -EIO;
214}
215
216static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
217 unsigned int reg)
218{
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219 int ret;
220 unsigned int val;
db49c146 221
f4bee1bb 222 reg &= 0xff;
db49c146 223 if (reg >= codec->driver->reg_cache_size ||
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224 snd_soc_codec_volatile_register(codec, reg) ||
225 codec->cache_bypass) {
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DP
226 if (codec->cache_only)
227 return -1;
228
5aaa062c 229 BUG_ON(!codec->hw_read);
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DP
230 return codec->hw_read(codec, reg);
231 }
232
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233 ret = snd_soc_cache_read(codec, reg, &val);
234 if (ret < 0)
235 return -1;
236 return val;
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237}
238
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239#if defined(CONFIG_SPI_MASTER)
240static int snd_soc_8_8_spi_write(void *control_data, const char *data,
241 int len)
242{
243 struct spi_device *spi = control_data;
244 struct spi_transfer t;
245 struct spi_message m;
246 u8 msg[2];
247
248 if (len <= 0)
249 return 0;
250
251 msg[0] = data[0];
252 msg[1] = data[1];
253
254 spi_message_init(&m);
465d7fcc 255 memset(&t, 0, sizeof t);
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256
257 t.tx_buf = &msg[0];
258 t.len = len;
259
260 spi_message_add_tail(&t, &m);
261 spi_sync(spi, &m);
262
263 return len;
264}
265#else
266#define snd_soc_8_8_spi_write NULL
267#endif
268
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269static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
270 unsigned int value)
271{
afa2f106 272 u8 data[3];
7a30a3db 273 int ret;
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274
275 data[0] = reg;
276 data[1] = (value >> 8) & 0xff;
277 data[2] = value & 0xff;
278
3e13f65e 279 if (!snd_soc_codec_volatile_register(codec, reg) &&
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280 reg < codec->driver->reg_cache_size &&
281 !codec->cache_bypass) {
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282 ret = snd_soc_cache_write(codec, reg, value);
283 if (ret < 0)
284 return -1;
285 }
afa2f106 286
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287 if (codec->cache_only) {
288 codec->cache_sync = 1;
8c961bcc 289 return 0;
a3032b47 290 }
8c961bcc 291
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292 if (codec->hw_write(codec->control_data, data, 3) == 3)
293 return 0;
294 else
295 return -EIO;
296}
297
298static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
299 unsigned int reg)
300{
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301 int ret;
302 unsigned int val;
afa2f106 303
f0fba2ad 304 if (reg >= codec->driver->reg_cache_size ||
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305 snd_soc_codec_volatile_register(codec, reg) ||
306 codec->cache_bypass) {
8c961bcc 307 if (codec->cache_only)
391d8a04 308 return -1;
8c961bcc 309
5aaa062c 310 BUG_ON(!codec->hw_read);
afa2f106 311 return codec->hw_read(codec, reg);
8c961bcc 312 }
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313
314 ret = snd_soc_cache_read(codec, reg, &val);
315 if (ret < 0)
316 return -1;
317 return val;
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318}
319
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320#if defined(CONFIG_SPI_MASTER)
321static int snd_soc_8_16_spi_write(void *control_data, const char *data,
322 int len)
323{
324 struct spi_device *spi = control_data;
325 struct spi_transfer t;
326 struct spi_message m;
327 u8 msg[3];
328
329 if (len <= 0)
330 return 0;
331
332 msg[0] = data[0];
333 msg[1] = data[1];
334 msg[2] = data[2];
335
336 spi_message_init(&m);
465d7fcc 337 memset(&t, 0, sizeof t);
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338
339 t.tx_buf = &msg[0];
340 t.len = len;
341
342 spi_message_add_tail(&t, &m);
343 spi_sync(spi, &m);
344
345 return len;
346}
347#else
348#define snd_soc_8_16_spi_write NULL
349#endif
350
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CC
351#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
352static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
353 unsigned int r)
354{
355 struct i2c_msg xfer[2];
356 u8 reg = r;
357 u8 data;
358 int ret;
359 struct i2c_client *client = codec->control_data;
360
361 /* Write register */
362 xfer[0].addr = client->addr;
363 xfer[0].flags = 0;
364 xfer[0].len = 1;
365 xfer[0].buf = &reg;
366
367 /* Read data */
368 xfer[1].addr = client->addr;
369 xfer[1].flags = I2C_M_RD;
370 xfer[1].len = 1;
371 xfer[1].buf = &data;
372
373 ret = i2c_transfer(client->adapter, xfer, 2);
374 if (ret != 2) {
375 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
376 return 0;
377 }
378
379 return data;
380}
381#else
382#define snd_soc_8_8_read_i2c NULL
383#endif
384
17244c24 385#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
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386static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
387 unsigned int r)
388{
389 struct i2c_msg xfer[2];
390 u8 reg = r;
391 u16 data;
392 int ret;
393 struct i2c_client *client = codec->control_data;
394
395 /* Write register */
396 xfer[0].addr = client->addr;
397 xfer[0].flags = 0;
398 xfer[0].len = 1;
399 xfer[0].buf = &reg;
400
401 /* Read data */
402 xfer[1].addr = client->addr;
403 xfer[1].flags = I2C_M_RD;
404 xfer[1].len = 2;
405 xfer[1].buf = (u8 *)&data;
406
407 ret = i2c_transfer(client->adapter, xfer, 2);
408 if (ret != 2) {
409 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
410 return 0;
411 }
412
413 return (data >> 8) | ((data & 0xff) << 8);
414}
415#else
416#define snd_soc_8_16_read_i2c NULL
417#endif
17a52fd6 418
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419#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
420static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
421 unsigned int r)
422{
423 struct i2c_msg xfer[2];
424 u16 reg = r;
425 u8 data;
426 int ret;
427 struct i2c_client *client = codec->control_data;
428
429 /* Write register */
430 xfer[0].addr = client->addr;
431 xfer[0].flags = 0;
432 xfer[0].len = 2;
433 xfer[0].buf = (u8 *)&reg;
434
435 /* Read data */
436 xfer[1].addr = client->addr;
437 xfer[1].flags = I2C_M_RD;
438 xfer[1].len = 1;
439 xfer[1].buf = &data;
440
441 ret = i2c_transfer(client->adapter, xfer, 2);
442 if (ret != 2) {
443 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
444 return 0;
445 }
446
447 return data;
448}
449#else
450#define snd_soc_16_8_read_i2c NULL
451#endif
452
453static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
454 unsigned int reg)
455{
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456 int ret;
457 unsigned int val;
994dc424
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458
459 reg &= 0xff;
db49c146 460 if (reg >= codec->driver->reg_cache_size ||
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DP
461 snd_soc_codec_volatile_register(codec, reg) ||
462 codec->cache_bypass) {
db49c146
DP
463 if (codec->cache_only)
464 return -1;
465
5aaa062c 466 BUG_ON(!codec->hw_read);
db49c146
DP
467 return codec->hw_read(codec, reg);
468 }
469
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DP
470 ret = snd_soc_cache_read(codec, reg, &val);
471 if (ret < 0)
472 return -1;
473 return val;
994dc424
BS
474}
475
476static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
477 unsigned int value)
478{
994dc424
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479 u8 data[3];
480 int ret;
481
994dc424
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482 data[0] = (reg >> 8) & 0xff;
483 data[1] = reg & 0xff;
484 data[2] = value;
485
486 reg &= 0xff;
db49c146 487 if (!snd_soc_codec_volatile_register(codec, reg) &&
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488 reg < codec->driver->reg_cache_size &&
489 !codec->cache_bypass) {
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490 ret = snd_soc_cache_write(codec, reg, value);
491 if (ret < 0)
492 return -1;
493 }
8c961bcc 494
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495 if (codec->cache_only) {
496 codec->cache_sync = 1;
8c961bcc 497 return 0;
a3032b47 498 }
8c961bcc 499
994dc424
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500 ret = codec->hw_write(codec->control_data, data, 3);
501 if (ret == 3)
502 return 0;
503 if (ret < 0)
504 return ret;
505 else
506 return -EIO;
507}
508
509#if defined(CONFIG_SPI_MASTER)
510static int snd_soc_16_8_spi_write(void *control_data, const char *data,
511 int len)
512{
513 struct spi_device *spi = control_data;
514 struct spi_transfer t;
515 struct spi_message m;
516 u8 msg[3];
517
518 if (len <= 0)
519 return 0;
520
521 msg[0] = data[0];
522 msg[1] = data[1];
523 msg[2] = data[2];
524
525 spi_message_init(&m);
465d7fcc 526 memset(&t, 0, sizeof t);
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527
528 t.tx_buf = &msg[0];
529 t.len = len;
530
531 spi_message_add_tail(&t, &m);
532 spi_sync(spi, &m);
533
534 return len;
535}
536#else
537#define snd_soc_16_8_spi_write NULL
538#endif
539
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540#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
541static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
542 unsigned int r)
543{
544 struct i2c_msg xfer[2];
545 u16 reg = cpu_to_be16(r);
546 u16 data;
547 int ret;
548 struct i2c_client *client = codec->control_data;
549
550 /* Write register */
551 xfer[0].addr = client->addr;
552 xfer[0].flags = 0;
553 xfer[0].len = 2;
554 xfer[0].buf = (u8 *)&reg;
555
556 /* Read data */
557 xfer[1].addr = client->addr;
558 xfer[1].flags = I2C_M_RD;
559 xfer[1].len = 2;
560 xfer[1].buf = (u8 *)&data;
561
562 ret = i2c_transfer(client->adapter, xfer, 2);
563 if (ret != 2) {
564 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
565 return 0;
566 }
567
568 return be16_to_cpu(data);
569}
570#else
571#define snd_soc_16_16_read_i2c NULL
572#endif
573
574static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec,
575 unsigned int reg)
576{
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DP
577 int ret;
578 unsigned int val;
bc6552f4 579
f0fba2ad 580 if (reg >= codec->driver->reg_cache_size ||
dad8e7ae
DP
581 snd_soc_codec_volatile_register(codec, reg) ||
582 codec->cache_bypass) {
bc6552f4 583 if (codec->cache_only)
391d8a04 584 return -1;
bc6552f4 585
5aaa062c 586 BUG_ON(!codec->hw_read);
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587 return codec->hw_read(codec, reg);
588 }
589
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590 ret = snd_soc_cache_read(codec, reg, &val);
591 if (ret < 0)
592 return -1;
593
594 return val;
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595}
596
597static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
598 unsigned int value)
599{
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600 u8 data[4];
601 int ret;
602
603 data[0] = (reg >> 8) & 0xff;
604 data[1] = reg & 0xff;
605 data[2] = (value >> 8) & 0xff;
606 data[3] = value & 0xff;
607
db49c146 608 if (!snd_soc_codec_volatile_register(codec, reg) &&
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609 reg < codec->driver->reg_cache_size &&
610 !codec->cache_bypass) {
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DP
611 ret = snd_soc_cache_write(codec, reg, value);
612 if (ret < 0)
613 return -1;
614 }
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615
616 if (codec->cache_only) {
617 codec->cache_sync = 1;
618 return 0;
619 }
620
621 ret = codec->hw_write(codec->control_data, data, 4);
622 if (ret == 4)
623 return 0;
624 if (ret < 0)
625 return ret;
626 else
627 return -EIO;
628}
994dc424 629
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630#if defined(CONFIG_SPI_MASTER)
631static int snd_soc_16_16_spi_write(void *control_data, const char *data,
632 int len)
633{
634 struct spi_device *spi = control_data;
635 struct spi_transfer t;
636 struct spi_message m;
637 u8 msg[4];
638
639 if (len <= 0)
640 return 0;
641
642 msg[0] = data[0];
643 msg[1] = data[1];
644 msg[2] = data[2];
645 msg[3] = data[3];
646
647 spi_message_init(&m);
465d7fcc 648 memset(&t, 0, sizeof t);
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649
650 t.tx_buf = &msg[0];
651 t.len = len;
652
653 spi_message_add_tail(&t, &m);
654 spi_sync(spi, &m);
655
656 return len;
657}
658#else
659#define snd_soc_16_16_spi_write NULL
660#endif
661
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662static struct {
663 int addr_bits;
664 int data_bits;
afa2f106 665 int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
27ded041 666 int (*spi_write)(void *, const char *, int);
17a52fd6 667 unsigned int (*read)(struct snd_soc_codec *, unsigned int);
afa2f106 668 unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
17a52fd6 669} io_types[] = {
63b62ab0
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670 {
671 .addr_bits = 4, .data_bits = 12,
672 .write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
673 .spi_write = snd_soc_4_12_spi_write,
674 },
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675 {
676 .addr_bits = 7, .data_bits = 9,
677 .write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
8998c899 678 .spi_write = snd_soc_7_9_spi_write,
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679 },
680 {
681 .addr_bits = 8, .data_bits = 8,
682 .write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
85dfcdff 683 .i2c_read = snd_soc_8_8_read_i2c,
f479fd93 684 .spi_write = snd_soc_8_8_spi_write,
d62ab358
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685 },
686 {
687 .addr_bits = 8, .data_bits = 16,
688 .write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
689 .i2c_read = snd_soc_8_16_read_i2c,
f479fd93 690 .spi_write = snd_soc_8_16_spi_write,
d62ab358 691 },
994dc424
BS
692 {
693 .addr_bits = 16, .data_bits = 8,
694 .write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
695 .i2c_read = snd_soc_16_8_read_i2c,
696 .spi_write = snd_soc_16_8_spi_write,
697 },
bc6552f4
MB
698 {
699 .addr_bits = 16, .data_bits = 16,
700 .write = snd_soc_16_16_write, .read = snd_soc_16_16_read,
701 .i2c_read = snd_soc_16_16_read_i2c,
f479fd93 702 .spi_write = snd_soc_16_16_spi_write,
bc6552f4 703 },
17a52fd6
MB
704};
705
706/**
707 * snd_soc_codec_set_cache_io: Set up standard I/O functions.
708 *
709 * @codec: CODEC to configure.
710 * @type: Type of cache.
711 * @addr_bits: Number of bits of register address data.
712 * @data_bits: Number of bits of data per register.
7084a42b 713 * @control: Control bus used.
17a52fd6
MB
714 *
715 * Register formats are frequently shared between many I2C and SPI
716 * devices. In order to promote code reuse the ASoC core provides
717 * some standard implementations of CODEC read and write operations
718 * which can be set up using this function.
719 *
720 * The caller is responsible for allocating and initialising the
721 * actual cache.
722 *
723 * Note that at present this code cannot be used by CODECs with
724 * volatile registers.
725 */
726int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
7084a42b
MB
727 int addr_bits, int data_bits,
728 enum snd_soc_control_type control)
17a52fd6
MB
729{
730 int i;
731
17a52fd6
MB
732 for (i = 0; i < ARRAY_SIZE(io_types); i++)
733 if (io_types[i].addr_bits == addr_bits &&
734 io_types[i].data_bits == data_bits)
735 break;
736 if (i == ARRAY_SIZE(io_types)) {
737 printk(KERN_ERR
738 "No I/O functions for %d bit address %d bit data\n",
739 addr_bits, data_bits);
740 return -EINVAL;
741 }
742
c3acec26
MB
743 codec->write = io_types[i].write;
744 codec->read = io_types[i].read;
17a52fd6 745
7084a42b
MB
746 switch (control) {
747 case SND_SOC_CUSTOM:
748 break;
749
750 case SND_SOC_I2C:
17244c24 751#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
7084a42b
MB
752 codec->hw_write = (hw_write_t)i2c_master_send;
753#endif
afa2f106
MB
754 if (io_types[i].i2c_read)
755 codec->hw_read = io_types[i].i2c_read;
a6d14342
MB
756
757 codec->control_data = container_of(codec->dev,
758 struct i2c_client,
759 dev);
7084a42b
MB
760 break;
761
762 case SND_SOC_SPI:
27ded041
MB
763 if (io_types[i].spi_write)
764 codec->hw_write = io_types[i].spi_write;
a6d14342
MB
765
766 codec->control_data = container_of(codec->dev,
767 struct spi_device,
768 dev);
7084a42b
MB
769 break;
770 }
771
17a52fd6
MB
772 return 0;
773}
774EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
7a30a3db 775
1321e883
DP
776static bool snd_soc_set_cache_val(void *base, unsigned int idx,
777 unsigned int val, unsigned int word_size)
778{
779 switch (word_size) {
780 case 1: {
781 u8 *cache = base;
782 if (cache[idx] == val)
783 return true;
784 cache[idx] = val;
785 break;
786 }
787 case 2: {
788 u16 *cache = base;
789 if (cache[idx] == val)
790 return true;
791 cache[idx] = val;
792 break;
793 }
794 default:
795 BUG();
796 }
797 return false;
798}
799
800static unsigned int snd_soc_get_cache_val(const void *base, unsigned int idx,
801 unsigned int word_size)
802{
803 switch (word_size) {
804 case 1: {
805 const u8 *cache = base;
806 return cache[idx];
807 }
808 case 2: {
809 const u16 *cache = base;
810 return cache[idx];
811 }
812 default:
813 BUG();
814 }
815 /* unreachable */
816 return -1;
817}
818
a7f387d5
DP
819struct snd_soc_rbtree_node {
820 struct rb_node node;
821 unsigned int reg;
822 unsigned int value;
823 unsigned int defval;
824} __attribute__ ((packed));
825
826struct snd_soc_rbtree_ctx {
827 struct rb_root root;
828};
829
830static struct snd_soc_rbtree_node *snd_soc_rbtree_lookup(
831 struct rb_root *root, unsigned int reg)
832{
833 struct rb_node *node;
834 struct snd_soc_rbtree_node *rbnode;
835
836 node = root->rb_node;
837 while (node) {
838 rbnode = container_of(node, struct snd_soc_rbtree_node, node);
839 if (rbnode->reg < reg)
840 node = node->rb_left;
841 else if (rbnode->reg > reg)
842 node = node->rb_right;
843 else
844 return rbnode;
845 }
846
847 return NULL;
848}
849
a7f387d5
DP
850static int snd_soc_rbtree_insert(struct rb_root *root,
851 struct snd_soc_rbtree_node *rbnode)
852{
853 struct rb_node **new, *parent;
854 struct snd_soc_rbtree_node *rbnode_tmp;
855
856 parent = NULL;
857 new = &root->rb_node;
858 while (*new) {
859 rbnode_tmp = container_of(*new, struct snd_soc_rbtree_node,
860 node);
861 parent = *new;
862 if (rbnode_tmp->reg < rbnode->reg)
863 new = &((*new)->rb_left);
864 else if (rbnode_tmp->reg > rbnode->reg)
865 new = &((*new)->rb_right);
866 else
867 return 0;
868 }
869
870 /* insert the node into the rbtree */
871 rb_link_node(&rbnode->node, parent, new);
872 rb_insert_color(&rbnode->node, root);
873
874 return 1;
875}
876
877static int snd_soc_rbtree_cache_sync(struct snd_soc_codec *codec)
878{
879 struct snd_soc_rbtree_ctx *rbtree_ctx;
880 struct rb_node *node;
881 struct snd_soc_rbtree_node *rbnode;
882 unsigned int val;
7a33d4ce 883 int ret;
a7f387d5
DP
884
885 rbtree_ctx = codec->reg_cache;
886 for (node = rb_first(&rbtree_ctx->root); node; node = rb_next(node)) {
887 rbnode = rb_entry(node, struct snd_soc_rbtree_node, node);
888 if (rbnode->value == rbnode->defval)
889 continue;
7a33d4ce
DP
890 ret = snd_soc_cache_read(codec, rbnode->reg, &val);
891 if (ret)
892 return ret;
893 ret = snd_soc_write(codec, rbnode->reg, val);
894 if (ret)
895 return ret;
a7f387d5
DP
896 dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
897 rbnode->reg, val);
898 }
899
900 return 0;
901}
902
903static int snd_soc_rbtree_cache_write(struct snd_soc_codec *codec,
904 unsigned int reg, unsigned int value)
905{
906 struct snd_soc_rbtree_ctx *rbtree_ctx;
907 struct snd_soc_rbtree_node *rbnode;
908
909 rbtree_ctx = codec->reg_cache;
910 rbnode = snd_soc_rbtree_lookup(&rbtree_ctx->root, reg);
911 if (rbnode) {
912 if (rbnode->value == value)
913 return 0;
914 rbnode->value = value;
915 } else {
916 /* bail out early, no need to create the rbnode yet */
917 if (!value)
918 return 0;
919 /*
920 * for uninitialized registers whose value is changed
921 * from the default zero, create an rbnode and insert
922 * it into the tree.
923 */
924 rbnode = kzalloc(sizeof *rbnode, GFP_KERNEL);
925 if (!rbnode)
926 return -ENOMEM;
927 rbnode->reg = reg;
928 rbnode->value = value;
929 snd_soc_rbtree_insert(&rbtree_ctx->root, rbnode);
930 }
931
932 return 0;
933}
934
935static int snd_soc_rbtree_cache_read(struct snd_soc_codec *codec,
936 unsigned int reg, unsigned int *value)
937{
938 struct snd_soc_rbtree_ctx *rbtree_ctx;
939 struct snd_soc_rbtree_node *rbnode;
940
941 rbtree_ctx = codec->reg_cache;
942 rbnode = snd_soc_rbtree_lookup(&rbtree_ctx->root, reg);
943 if (rbnode) {
944 *value = rbnode->value;
945 } else {
946 /* uninitialized registers default to 0 */
947 *value = 0;
948 }
949
950 return 0;
951}
952
953static int snd_soc_rbtree_cache_exit(struct snd_soc_codec *codec)
954{
955 struct rb_node *next;
956 struct snd_soc_rbtree_ctx *rbtree_ctx;
957 struct snd_soc_rbtree_node *rbtree_node;
958
959 /* if we've already been called then just return */
960 rbtree_ctx = codec->reg_cache;
961 if (!rbtree_ctx)
962 return 0;
963
964 /* free up the rbtree */
965 next = rb_first(&rbtree_ctx->root);
966 while (next) {
967 rbtree_node = rb_entry(next, struct snd_soc_rbtree_node, node);
968 next = rb_next(&rbtree_node->node);
969 rb_erase(&rbtree_node->node, &rbtree_ctx->root);
970 kfree(rbtree_node);
971 }
972
973 /* release the resources */
974 kfree(codec->reg_cache);
975 codec->reg_cache = NULL;
976
977 return 0;
978}
979
980static int snd_soc_rbtree_cache_init(struct snd_soc_codec *codec)
981{
1321e883 982 struct snd_soc_rbtree_node *rbtree_node;
a7f387d5 983 struct snd_soc_rbtree_ctx *rbtree_ctx;
1321e883
DP
984 unsigned int val;
985 unsigned int word_size;
986 int i;
987 int ret;
a7f387d5
DP
988
989 codec->reg_cache = kmalloc(sizeof *rbtree_ctx, GFP_KERNEL);
990 if (!codec->reg_cache)
991 return -ENOMEM;
992
993 rbtree_ctx = codec->reg_cache;
994 rbtree_ctx->root = RB_ROOT;
995
3335ddca 996 if (!codec->reg_def_copy)
a7f387d5
DP
997 return 0;
998
1321e883
DP
999 /*
1000 * populate the rbtree with the initialized registers. All other
1001 * registers will be inserted when they are first modified.
1002 */
1003 word_size = codec->driver->reg_word_size;
1004 for (i = 0; i < codec->driver->reg_cache_size; ++i) {
1005 val = snd_soc_get_cache_val(codec->reg_def_copy, i, word_size);
1006 if (!val)
1007 continue;
1008 rbtree_node = kzalloc(sizeof *rbtree_node, GFP_KERNEL);
1009 if (!rbtree_node) {
1010 ret = -ENOMEM;
1011 snd_soc_cache_exit(codec);
1012 break;
1013 }
1014 rbtree_node->reg = i;
1015 rbtree_node->value = val;
1016 rbtree_node->defval = val;
1017 snd_soc_rbtree_insert(&rbtree_ctx->root, rbtree_node);
a7f387d5
DP
1018 }
1019
1020 return 0;
1021}
1022
68d44ee0 1023#ifdef CONFIG_SND_SOC_CACHE_LZO
cc28fb8e
DP
1024struct snd_soc_lzo_ctx {
1025 void *wmem;
1026 void *dst;
1027 const void *src;
1028 size_t src_len;
1029 size_t dst_len;
1030 size_t decompressed_size;
1031 unsigned long *sync_bmp;
1032 int sync_bmp_nbits;
1033};
1034
1035#define LZO_BLOCK_NUM 8
1036static int snd_soc_lzo_block_count(void)
1037{
1038 return LZO_BLOCK_NUM;
1039}
1040
1041static int snd_soc_lzo_prepare(struct snd_soc_lzo_ctx *lzo_ctx)
1042{
1043 lzo_ctx->wmem = kmalloc(LZO1X_MEM_COMPRESS, GFP_KERNEL);
1044 if (!lzo_ctx->wmem)
1045 return -ENOMEM;
1046 return 0;
1047}
1048
1049static int snd_soc_lzo_compress(struct snd_soc_lzo_ctx *lzo_ctx)
1050{
1051 size_t compress_size;
1052 int ret;
1053
1054 ret = lzo1x_1_compress(lzo_ctx->src, lzo_ctx->src_len,
1055 lzo_ctx->dst, &compress_size, lzo_ctx->wmem);
1056 if (ret != LZO_E_OK || compress_size > lzo_ctx->dst_len)
1057 return -EINVAL;
1058 lzo_ctx->dst_len = compress_size;
1059 return 0;
1060}
1061
1062static int snd_soc_lzo_decompress(struct snd_soc_lzo_ctx *lzo_ctx)
1063{
1064 size_t dst_len;
1065 int ret;
1066
1067 dst_len = lzo_ctx->dst_len;
1068 ret = lzo1x_decompress_safe(lzo_ctx->src, lzo_ctx->src_len,
1069 lzo_ctx->dst, &dst_len);
1070 if (ret != LZO_E_OK || dst_len != lzo_ctx->dst_len)
1071 return -EINVAL;
1072 return 0;
1073}
1074
1075static int snd_soc_lzo_compress_cache_block(struct snd_soc_codec *codec,
1076 struct snd_soc_lzo_ctx *lzo_ctx)
1077{
1078 int ret;
1079
1080 lzo_ctx->dst_len = lzo1x_worst_compress(PAGE_SIZE);
1081 lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL);
1082 if (!lzo_ctx->dst) {
1083 lzo_ctx->dst_len = 0;
1084 return -ENOMEM;
1085 }
1086
1087 ret = snd_soc_lzo_compress(lzo_ctx);
1088 if (ret < 0)
1089 return ret;
1090 return 0;
1091}
1092
1093static int snd_soc_lzo_decompress_cache_block(struct snd_soc_codec *codec,
1094 struct snd_soc_lzo_ctx *lzo_ctx)
1095{
1096 int ret;
1097
1098 lzo_ctx->dst_len = lzo_ctx->decompressed_size;
1099 lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL);
1100 if (!lzo_ctx->dst) {
1101 lzo_ctx->dst_len = 0;
1102 return -ENOMEM;
1103 }
1104
1105 ret = snd_soc_lzo_decompress(lzo_ctx);
1106 if (ret < 0)
1107 return ret;
1108 return 0;
1109}
1110
1111static inline int snd_soc_lzo_get_blkindex(struct snd_soc_codec *codec,
1112 unsigned int reg)
1113{
001ae4c0 1114 const struct snd_soc_codec_driver *codec_drv;
cc28fb8e
DP
1115
1116 codec_drv = codec->driver;
cc28fb8e 1117 return (reg * codec_drv->reg_word_size) /
aea170a0 1118 DIV_ROUND_UP(codec->reg_size, snd_soc_lzo_block_count());
cc28fb8e
DP
1119}
1120
1121static inline int snd_soc_lzo_get_blkpos(struct snd_soc_codec *codec,
1122 unsigned int reg)
1123{
001ae4c0 1124 const struct snd_soc_codec_driver *codec_drv;
cc28fb8e
DP
1125
1126 codec_drv = codec->driver;
aea170a0 1127 return reg % (DIV_ROUND_UP(codec->reg_size, snd_soc_lzo_block_count()) /
cc28fb8e
DP
1128 codec_drv->reg_word_size);
1129}
1130
1131static inline int snd_soc_lzo_get_blksize(struct snd_soc_codec *codec)
1132{
001ae4c0 1133 const struct snd_soc_codec_driver *codec_drv;
cc28fb8e
DP
1134
1135 codec_drv = codec->driver;
aea170a0 1136 return DIV_ROUND_UP(codec->reg_size, snd_soc_lzo_block_count());
cc28fb8e
DP
1137}
1138
1139static int snd_soc_lzo_cache_sync(struct snd_soc_codec *codec)
1140{
1141 struct snd_soc_lzo_ctx **lzo_blocks;
1142 unsigned int val;
1143 int i;
7a33d4ce 1144 int ret;
cc28fb8e
DP
1145
1146 lzo_blocks = codec->reg_cache;
1147 for_each_set_bit(i, lzo_blocks[0]->sync_bmp, lzo_blocks[0]->sync_bmp_nbits) {
7a33d4ce
DP
1148 ret = snd_soc_cache_read(codec, i, &val);
1149 if (ret)
1150 return ret;
1151 ret = snd_soc_write(codec, i, val);
1152 if (ret)
1153 return ret;
cc28fb8e
DP
1154 dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
1155 i, val);
1156 }
1157
1158 return 0;
1159}
1160
1161static int snd_soc_lzo_cache_write(struct snd_soc_codec *codec,
1162 unsigned int reg, unsigned int value)
1163{
1164 struct snd_soc_lzo_ctx *lzo_block, **lzo_blocks;
1165 int ret, blkindex, blkpos;
1166 size_t blksize, tmp_dst_len;
1167 void *tmp_dst;
1168
1169 /* index of the compressed lzo block */
1170 blkindex = snd_soc_lzo_get_blkindex(codec, reg);
1171 /* register index within the decompressed block */
1172 blkpos = snd_soc_lzo_get_blkpos(codec, reg);
1173 /* size of the compressed block */
1174 blksize = snd_soc_lzo_get_blksize(codec);
1175 lzo_blocks = codec->reg_cache;
1176 lzo_block = lzo_blocks[blkindex];
1177
1178 /* save the pointer and length of the compressed block */
1179 tmp_dst = lzo_block->dst;
1180 tmp_dst_len = lzo_block->dst_len;
1181
1182 /* prepare the source to be the compressed block */
1183 lzo_block->src = lzo_block->dst;
1184 lzo_block->src_len = lzo_block->dst_len;
1185
1186 /* decompress the block */
1187 ret = snd_soc_lzo_decompress_cache_block(codec, lzo_block);
1188 if (ret < 0) {
1189 kfree(lzo_block->dst);
1190 goto out;
1191 }
1192
1193 /* write the new value to the cache */
1321e883
DP
1194 if (snd_soc_set_cache_val(lzo_block->dst, blkpos, value,
1195 codec->driver->reg_word_size)) {
1196 kfree(lzo_block->dst);
1197 goto out;
cc28fb8e
DP
1198 }
1199
1200 /* prepare the source to be the decompressed block */
1201 lzo_block->src = lzo_block->dst;
1202 lzo_block->src_len = lzo_block->dst_len;
1203
1204 /* compress the block */
1205 ret = snd_soc_lzo_compress_cache_block(codec, lzo_block);
1206 if (ret < 0) {
1207 kfree(lzo_block->dst);
1208 kfree(lzo_block->src);
1209 goto out;
1210 }
1211
1212 /* set the bit so we know we have to sync this register */
1213 set_bit(reg, lzo_block->sync_bmp);
1214 kfree(tmp_dst);
1215 kfree(lzo_block->src);
1216 return 0;
1217out:
1218 lzo_block->dst = tmp_dst;
1219 lzo_block->dst_len = tmp_dst_len;
1220 return ret;
1221}
1222
1223static int snd_soc_lzo_cache_read(struct snd_soc_codec *codec,
1224 unsigned int reg, unsigned int *value)
1225{
1226 struct snd_soc_lzo_ctx *lzo_block, **lzo_blocks;
1227 int ret, blkindex, blkpos;
1228 size_t blksize, tmp_dst_len;
1229 void *tmp_dst;
1230
1231 *value = 0;
1232 /* index of the compressed lzo block */
1233 blkindex = snd_soc_lzo_get_blkindex(codec, reg);
1234 /* register index within the decompressed block */
1235 blkpos = snd_soc_lzo_get_blkpos(codec, reg);
1236 /* size of the compressed block */
1237 blksize = snd_soc_lzo_get_blksize(codec);
1238 lzo_blocks = codec->reg_cache;
1239 lzo_block = lzo_blocks[blkindex];
1240
1241 /* save the pointer and length of the compressed block */
1242 tmp_dst = lzo_block->dst;
1243 tmp_dst_len = lzo_block->dst_len;
1244
1245 /* prepare the source to be the compressed block */
1246 lzo_block->src = lzo_block->dst;
1247 lzo_block->src_len = lzo_block->dst_len;
1248
1249 /* decompress the block */
1250 ret = snd_soc_lzo_decompress_cache_block(codec, lzo_block);
1321e883 1251 if (ret >= 0)
cc28fb8e 1252 /* fetch the value from the cache */
1321e883
DP
1253 *value = snd_soc_get_cache_val(lzo_block->dst, blkpos,
1254 codec->driver->reg_word_size);
cc28fb8e
DP
1255
1256 kfree(lzo_block->dst);
1257 /* restore the pointer and length of the compressed block */
1258 lzo_block->dst = tmp_dst;
1259 lzo_block->dst_len = tmp_dst_len;
1260 return 0;
1261}
1262
1263static int snd_soc_lzo_cache_exit(struct snd_soc_codec *codec)
1264{
1265 struct snd_soc_lzo_ctx **lzo_blocks;
1266 int i, blkcount;
1267
1268 lzo_blocks = codec->reg_cache;
1269 if (!lzo_blocks)
1270 return 0;
1271
1272 blkcount = snd_soc_lzo_block_count();
1273 /*
1274 * the pointer to the bitmap used for syncing the cache
1275 * is shared amongst all lzo_blocks. Ensure it is freed
1276 * only once.
1277 */
1278 if (lzo_blocks[0])
1279 kfree(lzo_blocks[0]->sync_bmp);
1280 for (i = 0; i < blkcount; ++i) {
1281 if (lzo_blocks[i]) {
1282 kfree(lzo_blocks[i]->wmem);
1283 kfree(lzo_blocks[i]->dst);
1284 }
1285 /* each lzo_block is a pointer returned by kmalloc or NULL */
1286 kfree(lzo_blocks[i]);
1287 }
1288 kfree(lzo_blocks);
1289 codec->reg_cache = NULL;
1290 return 0;
1291}
1292
1293static int snd_soc_lzo_cache_init(struct snd_soc_codec *codec)
1294{
1295 struct snd_soc_lzo_ctx **lzo_blocks;
aea170a0 1296 size_t bmp_size;
001ae4c0 1297 const struct snd_soc_codec_driver *codec_drv;
cc28fb8e
DP
1298 int ret, tofree, i, blksize, blkcount;
1299 const char *p, *end;
1300 unsigned long *sync_bmp;
1301
1302 ret = 0;
1303 codec_drv = codec->driver;
cc28fb8e
DP
1304
1305 /*
1306 * If we have not been given a default register cache
1307 * then allocate a dummy zero-ed out region, compress it
1308 * and remember to free it afterwards.
1309 */
1310 tofree = 0;
3335ddca 1311 if (!codec->reg_def_copy)
cc28fb8e
DP
1312 tofree = 1;
1313
3335ddca 1314 if (!codec->reg_def_copy) {
aea170a0 1315 codec->reg_def_copy = kzalloc(codec->reg_size, GFP_KERNEL);
3335ddca 1316 if (!codec->reg_def_copy)
cc28fb8e
DP
1317 return -ENOMEM;
1318 }
1319
1320 blkcount = snd_soc_lzo_block_count();
1321 codec->reg_cache = kzalloc(blkcount * sizeof *lzo_blocks,
1322 GFP_KERNEL);
1323 if (!codec->reg_cache) {
1324 ret = -ENOMEM;
1325 goto err_tofree;
1326 }
1327 lzo_blocks = codec->reg_cache;
1328
1329 /*
1330 * allocate a bitmap to be used when syncing the cache with
1331 * the hardware. Each time a register is modified, the corresponding
1332 * bit is set in the bitmap, so we know that we have to sync
1333 * that register.
1334 */
1335 bmp_size = codec_drv->reg_cache_size;
465d7fcc 1336 sync_bmp = kmalloc(BITS_TO_LONGS(bmp_size) * sizeof(long),
cc28fb8e
DP
1337 GFP_KERNEL);
1338 if (!sync_bmp) {
1339 ret = -ENOMEM;
1340 goto err;
1341 }
09c74a9d 1342 bitmap_zero(sync_bmp, bmp_size);
cc28fb8e
DP
1343
1344 /* allocate the lzo blocks and initialize them */
1345 for (i = 0; i < blkcount; ++i) {
1346 lzo_blocks[i] = kzalloc(sizeof **lzo_blocks,
1347 GFP_KERNEL);
1348 if (!lzo_blocks[i]) {
1349 kfree(sync_bmp);
1350 ret = -ENOMEM;
1351 goto err;
1352 }
1353 lzo_blocks[i]->sync_bmp = sync_bmp;
04f8fd17 1354 lzo_blocks[i]->sync_bmp_nbits = bmp_size;
cc28fb8e
DP
1355 /* alloc the working space for the compressed block */
1356 ret = snd_soc_lzo_prepare(lzo_blocks[i]);
1357 if (ret < 0)
1358 goto err;
1359 }
1360
1361 blksize = snd_soc_lzo_get_blksize(codec);
3335ddca 1362 p = codec->reg_def_copy;
aea170a0 1363 end = codec->reg_def_copy + codec->reg_size;
cc28fb8e
DP
1364 /* compress the register map and fill the lzo blocks */
1365 for (i = 0; i < blkcount; ++i, p += blksize) {
1366 lzo_blocks[i]->src = p;
1367 if (p + blksize > end)
1368 lzo_blocks[i]->src_len = end - p;
1369 else
1370 lzo_blocks[i]->src_len = blksize;
1371 ret = snd_soc_lzo_compress_cache_block(codec,
1372 lzo_blocks[i]);
1373 if (ret < 0)
1374 goto err;
1375 lzo_blocks[i]->decompressed_size =
1376 lzo_blocks[i]->src_len;
1377 }
1378
3335ddca
DP
1379 if (tofree) {
1380 kfree(codec->reg_def_copy);
1381 codec->reg_def_copy = NULL;
1382 }
cc28fb8e
DP
1383 return 0;
1384err:
1385 snd_soc_cache_exit(codec);
1386err_tofree:
3335ddca
DP
1387 if (tofree) {
1388 kfree(codec->reg_def_copy);
1389 codec->reg_def_copy = NULL;
1390 }
cc28fb8e
DP
1391 return ret;
1392}
68d44ee0 1393#endif
cc28fb8e 1394
7a30a3db
DP
1395static int snd_soc_flat_cache_sync(struct snd_soc_codec *codec)
1396{
1397 int i;
7a33d4ce 1398 int ret;
001ae4c0 1399 const struct snd_soc_codec_driver *codec_drv;
7a30a3db
DP
1400 unsigned int val;
1401
1402 codec_drv = codec->driver;
1403 for (i = 0; i < codec_drv->reg_cache_size; ++i) {
7a33d4ce
DP
1404 ret = snd_soc_cache_read(codec, i, &val);
1405 if (ret)
1406 return ret;
d779fce5
DP
1407 if (codec->reg_def_copy)
1408 if (snd_soc_get_cache_val(codec->reg_def_copy,
1321e883
DP
1409 i, codec_drv->reg_word_size) == val)
1410 continue;
7a33d4ce
DP
1411 ret = snd_soc_write(codec, i, val);
1412 if (ret)
1413 return ret;
7a30a3db
DP
1414 dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
1415 i, val);
1416 }
1417 return 0;
1418}
1419
1420static int snd_soc_flat_cache_write(struct snd_soc_codec *codec,
1421 unsigned int reg, unsigned int value)
1422{
1321e883
DP
1423 snd_soc_set_cache_val(codec->reg_cache, reg, value,
1424 codec->driver->reg_word_size);
7a30a3db
DP
1425 return 0;
1426}
1427
1428static int snd_soc_flat_cache_read(struct snd_soc_codec *codec,
1429 unsigned int reg, unsigned int *value)
1430{
1321e883
DP
1431 *value = snd_soc_get_cache_val(codec->reg_cache, reg,
1432 codec->driver->reg_word_size);
7a30a3db
DP
1433 return 0;
1434}
1435
1436static int snd_soc_flat_cache_exit(struct snd_soc_codec *codec)
1437{
1438 if (!codec->reg_cache)
1439 return 0;
1440 kfree(codec->reg_cache);
1441 codec->reg_cache = NULL;
1442 return 0;
1443}
1444
1445static int snd_soc_flat_cache_init(struct snd_soc_codec *codec)
1446{
001ae4c0 1447 const struct snd_soc_codec_driver *codec_drv;
7a30a3db
DP
1448
1449 codec_drv = codec->driver;
7a30a3db 1450
d779fce5
DP
1451 if (codec->reg_def_copy)
1452 codec->reg_cache = kmemdup(codec->reg_def_copy,
aea170a0 1453 codec->reg_size, GFP_KERNEL);
7a30a3db 1454 else
aea170a0 1455 codec->reg_cache = kzalloc(codec->reg_size, GFP_KERNEL);
7a30a3db
DP
1456 if (!codec->reg_cache)
1457 return -ENOMEM;
1458
1459 return 0;
1460}
1461
1462/* an array of all supported compression types */
1463static const struct snd_soc_cache_ops cache_types[] = {
be4fcddd 1464 /* Flat *must* be the first entry for fallback */
7a30a3db 1465 {
df0701bb 1466 .id = SND_SOC_FLAT_COMPRESSION,
0d735eaa 1467 .name = "flat",
7a30a3db
DP
1468 .init = snd_soc_flat_cache_init,
1469 .exit = snd_soc_flat_cache_exit,
1470 .read = snd_soc_flat_cache_read,
1471 .write = snd_soc_flat_cache_write,
1472 .sync = snd_soc_flat_cache_sync
cc28fb8e 1473 },
68d44ee0 1474#ifdef CONFIG_SND_SOC_CACHE_LZO
cc28fb8e
DP
1475 {
1476 .id = SND_SOC_LZO_COMPRESSION,
0d735eaa 1477 .name = "LZO",
cc28fb8e
DP
1478 .init = snd_soc_lzo_cache_init,
1479 .exit = snd_soc_lzo_cache_exit,
1480 .read = snd_soc_lzo_cache_read,
1481 .write = snd_soc_lzo_cache_write,
1482 .sync = snd_soc_lzo_cache_sync
a7f387d5 1483 },
68d44ee0 1484#endif
a7f387d5
DP
1485 {
1486 .id = SND_SOC_RBTREE_COMPRESSION,
0d735eaa 1487 .name = "rbtree",
a7f387d5
DP
1488 .init = snd_soc_rbtree_cache_init,
1489 .exit = snd_soc_rbtree_cache_exit,
1490 .read = snd_soc_rbtree_cache_read,
1491 .write = snd_soc_rbtree_cache_write,
1492 .sync = snd_soc_rbtree_cache_sync
7a30a3db
DP
1493 }
1494};
1495
1496int snd_soc_cache_init(struct snd_soc_codec *codec)
1497{
1498 int i;
1499
1500 for (i = 0; i < ARRAY_SIZE(cache_types); ++i)
23bbce34 1501 if (cache_types[i].id == codec->compress_type)
7a30a3db 1502 break;
be4fcddd
MB
1503
1504 /* Fall back to flat compression */
7a30a3db 1505 if (i == ARRAY_SIZE(cache_types)) {
be4fcddd
MB
1506 dev_warn(codec->dev, "Could not match compress type: %d\n",
1507 codec->compress_type);
1508 i = 0;
7a30a3db
DP
1509 }
1510
1511 mutex_init(&codec->cache_rw_mutex);
1512 codec->cache_ops = &cache_types[i];
1513
0d735eaa
DP
1514 if (codec->cache_ops->init) {
1515 if (codec->cache_ops->name)
1516 dev_dbg(codec->dev, "Initializing %s cache for %s codec\n",
1517 codec->cache_ops->name, codec->name);
7a30a3db 1518 return codec->cache_ops->init(codec);
0d735eaa 1519 }
7a30a3db
DP
1520 return -EINVAL;
1521}
1522
1523/*
1524 * NOTE: keep in mind that this function might be called
1525 * multiple times.
1526 */
1527int snd_soc_cache_exit(struct snd_soc_codec *codec)
1528{
0d735eaa
DP
1529 if (codec->cache_ops && codec->cache_ops->exit) {
1530 if (codec->cache_ops->name)
1531 dev_dbg(codec->dev, "Destroying %s cache for %s codec\n",
1532 codec->cache_ops->name, codec->name);
7a30a3db 1533 return codec->cache_ops->exit(codec);
0d735eaa 1534 }
7a30a3db
DP
1535 return -EINVAL;
1536}
1537
1538/**
1539 * snd_soc_cache_read: Fetch the value of a given register from the cache.
1540 *
1541 * @codec: CODEC to configure.
1542 * @reg: The register index.
1543 * @value: The value to be returned.
1544 */
1545int snd_soc_cache_read(struct snd_soc_codec *codec,
1546 unsigned int reg, unsigned int *value)
1547{
1548 int ret;
1549
1550 mutex_lock(&codec->cache_rw_mutex);
1551
1552 if (value && codec->cache_ops && codec->cache_ops->read) {
1553 ret = codec->cache_ops->read(codec, reg, value);
1554 mutex_unlock(&codec->cache_rw_mutex);
1555 return ret;
1556 }
1557
1558 mutex_unlock(&codec->cache_rw_mutex);
1559 return -EINVAL;
1560}
1561EXPORT_SYMBOL_GPL(snd_soc_cache_read);
1562
1563/**
1564 * snd_soc_cache_write: Set the value of a given register in the cache.
1565 *
1566 * @codec: CODEC to configure.
1567 * @reg: The register index.
1568 * @value: The new register value.
1569 */
1570int snd_soc_cache_write(struct snd_soc_codec *codec,
1571 unsigned int reg, unsigned int value)
1572{
1573 int ret;
1574
1575 mutex_lock(&codec->cache_rw_mutex);
1576
1577 if (codec->cache_ops && codec->cache_ops->write) {
1578 ret = codec->cache_ops->write(codec, reg, value);
1579 mutex_unlock(&codec->cache_rw_mutex);
1580 return ret;
1581 }
1582
1583 mutex_unlock(&codec->cache_rw_mutex);
1584 return -EINVAL;
1585}
1586EXPORT_SYMBOL_GPL(snd_soc_cache_write);
1587
1588/**
1589 * snd_soc_cache_sync: Sync the register cache with the hardware.
1590 *
1591 * @codec: CODEC to configure.
1592 *
1593 * Any registers that should not be synced should be marked as
1594 * volatile. In general drivers can choose not to use the provided
1595 * syncing functionality if they so require.
1596 */
1597int snd_soc_cache_sync(struct snd_soc_codec *codec)
1598{
1599 int ret;
1600
1601 if (!codec->cache_sync) {
1602 return 0;
1603 }
1604
1605 if (codec->cache_ops && codec->cache_ops->sync) {
0d735eaa
DP
1606 if (codec->cache_ops->name)
1607 dev_dbg(codec->dev, "Syncing %s cache for %s codec\n",
1608 codec->cache_ops->name, codec->name);
7a30a3db
DP
1609 ret = codec->cache_ops->sync(codec);
1610 if (!ret)
1611 codec->cache_sync = 0;
1612 return ret;
1613 }
1614
1615 return -EINVAL;
1616}
1617EXPORT_SYMBOL_GPL(snd_soc_cache_sync);
066d16c3
DP
1618
1619static int snd_soc_get_reg_access_index(struct snd_soc_codec *codec,
1620 unsigned int reg)
1621{
1622 const struct snd_soc_codec_driver *codec_drv;
1623 unsigned int min, max, index;
1624
1625 codec_drv = codec->driver;
1626 min = 0;
1627 max = codec_drv->reg_access_size - 1;
1628 do {
1629 index = (min + max) / 2;
1630 if (codec_drv->reg_access_default[index].reg == reg)
1631 return index;
1632 if (codec_drv->reg_access_default[index].reg < reg)
1633 min = index + 1;
1634 else
1635 max = index;
1636 } while (min <= max);
1637 return -1;
1638}
1639
1640int snd_soc_default_volatile_register(struct snd_soc_codec *codec,
1641 unsigned int reg)
1642{
1643 int index;
1644
1645 if (reg >= codec->driver->reg_cache_size)
1646 return 1;
1647 index = snd_soc_get_reg_access_index(codec, reg);
1648 if (index < 0)
1649 return 0;
1650 return codec->driver->reg_access_default[index].vol;
1651}
1652EXPORT_SYMBOL_GPL(snd_soc_default_volatile_register);
1653
1654int snd_soc_default_readable_register(struct snd_soc_codec *codec,
1655 unsigned int reg)
1656{
1657 int index;
1658
1659 if (reg >= codec->driver->reg_cache_size)
1660 return 1;
1661 index = snd_soc_get_reg_access_index(codec, reg);
1662 if (index < 0)
1663 return 0;
1664 return codec->driver->reg_access_default[index].read;
1665}
1666EXPORT_SYMBOL_GPL(snd_soc_default_readable_register);
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