[deliverable/linux.git] / sound / soc / tegra / tegra20_ac97.c

/*
 * tegra20_ac97.c - Tegra20 AC97 platform driver
 *
 * Copyright (c) 2012 Lucas Stach <dev@lynxeye.de>
 *
 * Partly based on code copyright/by:
 *
 * Copyright (c) 2011,2012 Toradex Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>

#include "tegra20_ac97.h"

#define DRV_NAME "tegra20-ac97"

static struct tegra20_ac97 *workdata;

static void tegra20_ac97_codec_reset(struct snd_ac97 *ac97)
{
	u32 readback;
	unsigned long timeout;

	/* reset line is not driven by DAC pad group, have to toggle GPIO */
	gpio_set_value(workdata->reset_gpio, 0);
	udelay(2);

	gpio_set_value(workdata->reset_gpio, 1);
	udelay(2);

	timeout = jiffies + msecs_to_jiffies(100);

	do {
		regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
		if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
			break;
		usleep_range(1000, 2000);
	} while (!time_after(jiffies, timeout));
}

static void tegra20_ac97_codec_warm_reset(struct snd_ac97 *ac97)
{
	u32 readback;
	unsigned long timeout;

	/*
	 * although sync line is driven by the DAC pad group warm reset using
	 * the controller cmd is not working, have to toggle sync line
	 * manually.
	 */
	gpio_request(workdata->sync_gpio, "codec-sync");

	gpio_direction_output(workdata->sync_gpio, 1);

	udelay(2);
	gpio_set_value(workdata->sync_gpio, 0);
	udelay(2);
	gpio_free(workdata->sync_gpio);

	timeout = jiffies + msecs_to_jiffies(100);

	do {
		regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
		if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
			break;
		usleep_range(1000, 2000);
	} while (!time_after(jiffies, timeout));
}

static unsigned short tegra20_ac97_codec_read(struct snd_ac97 *ac97_snd,
					      unsigned short reg)
{
	u32 readback;
	unsigned long timeout;

	regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
		     (((reg | 0x80) << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
		      TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
		     TEGRA20_AC97_CMD_BUSY);

	timeout = jiffies + msecs_to_jiffies(100);

	do {
		regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
		if (readback & TEGRA20_AC97_STATUS1_STA_VALID1)
			break;
		usleep_range(1000, 2000);
	} while (!time_after(jiffies, timeout));

	return ((readback & TEGRA20_AC97_STATUS1_STA_DATA1_MASK) >>
		TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT);
}

static void tegra20_ac97_codec_write(struct snd_ac97 *ac97_snd,
				     unsigned short reg, unsigned short val)
{
	u32 readback;
	unsigned long timeout;

	regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
		     ((reg << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
		      TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
		     ((val << TEGRA20_AC97_CMD_CMD_DATA_SHIFT) &
		      TEGRA20_AC97_CMD_CMD_DATA_MASK) |
		     TEGRA20_AC97_CMD_BUSY);

	timeout = jiffies + msecs_to_jiffies(100);

	do {
		regmap_read(workdata->regmap, TEGRA20_AC97_CMD, &readback);
		if (!(readback & TEGRA20_AC97_CMD_BUSY))
			break;
		usleep_range(1000, 2000);
	} while (!time_after(jiffies, timeout));
}

static struct snd_ac97_bus_ops tegra20_ac97_ops = {
	.read		= tegra20_ac97_codec_read,
	.write		= tegra20_ac97_codec_write,
	.reset		= tegra20_ac97_codec_reset,
	.warm_reset	= tegra20_ac97_codec_warm_reset,
};

static inline void tegra20_ac97_start_playback(struct tegra20_ac97 *ac97)
{
	regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
			   TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN,
			   TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN);

	regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
			   TEGRA20_AC97_CTRL_PCM_DAC_EN |
			   TEGRA20_AC97_CTRL_STM_EN,
			   TEGRA20_AC97_CTRL_PCM_DAC_EN |
			   TEGRA20_AC97_CTRL_STM_EN);
}

static inline void tegra20_ac97_stop_playback(struct tegra20_ac97 *ac97)
{
	regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
			   TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN, 0);

	regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
			   TEGRA20_AC97_CTRL_PCM_DAC_EN, 0);
}

static inline void tegra20_ac97_start_capture(struct tegra20_ac97 *ac97)
{
	regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
			   TEGRA20_AC97_FIFO_SCR_REC_FULL_EN,
			   TEGRA20_AC97_FIFO_SCR_REC_FULL_EN);
}

static inline void tegra20_ac97_stop_capture(struct tegra20_ac97 *ac97)
{
	regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
			   TEGRA20_AC97_FIFO_SCR_REC_FULL_EN, 0);
}

static int tegra20_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
				struct snd_soc_dai *dai)
{
	struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_RESUME:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra20_ac97_start_playback(ac97);
		else
			tegra20_ac97_start_capture(ac97);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	case SNDRV_PCM_TRIGGER_SUSPEND:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra20_ac97_stop_playback(ac97);
		else
			tegra20_ac97_stop_capture(ac97);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static const struct snd_soc_dai_ops tegra20_ac97_dai_ops = {
	.trigger	= tegra20_ac97_trigger,
};

static int tegra20_ac97_probe(struct snd_soc_dai *dai)
{
	struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);

	dai->capture_dma_data = &ac97->capture_dma_data;
	dai->playback_dma_data = &ac97->playback_dma_data;

	return 0;
}

static struct snd_soc_dai_driver tegra20_ac97_dai = {
	.name = "tegra-ac97-pcm",
	.bus_control = true,
	.probe = tegra20_ac97_probe,
	.playback = {
		.stream_name = "PCM Playback",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.capture = {
		.stream_name = "PCM Capture",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops = &tegra20_ac97_dai_ops,
};

static const struct snd_soc_component_driver tegra20_ac97_component = {
	.name		= DRV_NAME,
};

static bool tegra20_ac97_wr_rd_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA20_AC97_CTRL:
	case TEGRA20_AC97_CMD:
	case TEGRA20_AC97_STATUS1:
	case TEGRA20_AC97_FIFO1_SCR:
	case TEGRA20_AC97_FIFO_TX1:
	case TEGRA20_AC97_FIFO_RX1:
		return true;
	default:
		break;
	}

	return false;
}

static bool tegra20_ac97_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA20_AC97_STATUS1:
	case TEGRA20_AC97_FIFO1_SCR:
	case TEGRA20_AC97_FIFO_TX1:
	case TEGRA20_AC97_FIFO_RX1:
		return true;
	default:
		break;
	}

	return false;
}

static bool tegra20_ac97_precious_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA20_AC97_FIFO_TX1:
	case TEGRA20_AC97_FIFO_RX1:
		return true;
	default:
		break;
	}

	return false;
}

static const struct regmap_config tegra20_ac97_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = TEGRA20_AC97_FIFO_RX1,
	.writeable_reg = tegra20_ac97_wr_rd_reg,
	.readable_reg = tegra20_ac97_wr_rd_reg,
	.volatile_reg = tegra20_ac97_volatile_reg,
	.precious_reg = tegra20_ac97_precious_reg,
	.cache_type = REGCACHE_FLAT,
};

static int tegra20_ac97_platform_probe(struct platform_device *pdev)
{
	struct tegra20_ac97 *ac97;
	struct resource *mem;
	void __iomem *regs;
	int ret = 0;

	ac97 = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_ac97),
			    GFP_KERNEL);
	if (!ac97) {
		dev_err(&pdev->dev, "Can't allocate tegra20_ac97\n");
		ret = -ENOMEM;
		goto err;
	}
	dev_set_drvdata(&pdev->dev, ac97);

	ac97->clk_ac97 = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(ac97->clk_ac97)) {
		dev_err(&pdev->dev, "Can't retrieve ac97 clock\n");
		ret = PTR_ERR(ac97->clk_ac97);
		goto err;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	regs = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(regs)) {
		ret = PTR_ERR(regs);
		goto err_clk_put;
	}

	ac97->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
					    &tegra20_ac97_regmap_config);
	if (IS_ERR(ac97->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		ret = PTR_ERR(ac97->regmap);
		goto err_clk_put;
	}

	ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node,
					     "nvidia,codec-reset-gpio", 0);
	if (gpio_is_valid(ac97->reset_gpio)) {
		ret = devm_gpio_request_one(&pdev->dev, ac97->reset_gpio,
					    GPIOF_OUT_INIT_HIGH, "codec-reset");
		if (ret) {
			dev_err(&pdev->dev, "could not get codec-reset GPIO\n");
			goto err_clk_put;
		}
	} else {
		dev_err(&pdev->dev, "no codec-reset GPIO supplied\n");
		goto err_clk_put;
	}

	ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node,
					    "nvidia,codec-sync-gpio", 0);
	if (!gpio_is_valid(ac97->sync_gpio)) {
		dev_err(&pdev->dev, "no codec-sync GPIO supplied\n");
		goto err_clk_put;
	}

	ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
	ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	ac97->capture_dma_data.maxburst = 4;

	ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
	ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	ac97->playback_dma_data.maxburst = 4;

	ret = clk_prepare_enable(ac97->clk_ac97);
	if (ret) {
		dev_err(&pdev->dev, "clk_enable failed: %d\n", ret);
		goto err;
	}

	ret = snd_soc_set_ac97_ops(&tegra20_ac97_ops);
	if (ret) {
		dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
		goto err_clk_disable_unprepare;
	}

	ret = snd_soc_register_component(&pdev->dev, &tegra20_ac97_component,
					 &tegra20_ac97_dai, 1);
	if (ret) {
		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
		ret = -ENOMEM;
		goto err_clk_disable_unprepare;
	}

	ret = tegra_pcm_platform_register(&pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
		goto err_unregister_component;
	}

	/* XXX: crufty ASoC AC97 API - only one AC97 codec allowed */
	workdata = ac97;

	return 0;

err_unregister_component:
	snd_soc_unregister_component(&pdev->dev);
err_clk_disable_unprepare:
	clk_disable_unprepare(ac97->clk_ac97);
err_clk_put:
err:
	snd_soc_set_ac97_ops(NULL);
	return ret;
}

static int tegra20_ac97_platform_remove(struct platform_device *pdev)
{
	struct tegra20_ac97 *ac97 = dev_get_drvdata(&pdev->dev);

	tegra_pcm_platform_unregister(&pdev->dev);
	snd_soc_unregister_component(&pdev->dev);

	clk_disable_unprepare(ac97->clk_ac97);

	snd_soc_set_ac97_ops(NULL);

	return 0;
}

static const struct of_device_id tegra20_ac97_of_match[] = {
	{ .compatible = "nvidia,tegra20-ac97", },
	{},
};

static struct platform_driver tegra20_ac97_driver = {
	.driver = {
		.name = DRV_NAME,
		.of_match_table = tegra20_ac97_of_match,
	},
	.probe = tegra20_ac97_platform_probe,
	.remove = tegra20_ac97_platform_remove,
};
module_platform_driver(tegra20_ac97_driver);

MODULE_AUTHOR("Lucas Stach");
MODULE_DESCRIPTION("Tegra20 AC97 ASoC driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra20_ac97_of_match);
Commit	Line	Data
609dad9b LS	1	/*
	2	* tegra20_ac97.c - Tegra20 AC97 platform driver
	3	*
	4	* Copyright (c) 2012 Lucas Stach <dev@lynxeye.de>
	5	*
	6	* Partly based on code copyright/by:
	7	*
	8	* Copyright (c) 2011,2012 Toradex Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License
	12	* version 2 as published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but
	15	* WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	17	* General Public License for more details.
	18	*
	19	*/
	20
	21	#include <linux/clk.h>
	22	#include <linux/delay.h>
	23	#include <linux/device.h>
	24	#include <linux/gpio.h>
	25	#include <linux/io.h>
	26	#include <linux/jiffies.h>
	27	#include <linux/module.h>
	28	#include <linux/of.h>
	29	#include <linux/of_gpio.h>
	30	#include <linux/platform_device.h>
	31	#include <linux/pm_runtime.h>
	32	#include <linux/regmap.h>
	33	#include <linux/slab.h>
	34	#include <sound/core.h>
	35	#include <sound/pcm.h>
	36	#include <sound/pcm_params.h>
	37	#include <sound/soc.h>
3489d506	38	#include <sound/dmaengine_pcm.h>
609dad9b	39
609dad9b LS	40	#include "tegra20_ac97.h"
	41
	42	#define DRV_NAME "tegra20-ac97"
	43
	44	static struct tegra20_ac97 *workdata;
	45
	46	static void tegra20_ac97_codec_reset(struct snd_ac97 *ac97)
	47	{
	48	u32 readback;
	49	unsigned long timeout;
	50
	51	/* reset line is not driven by DAC pad group, have to toggle GPIO */
	52	gpio_set_value(workdata->reset_gpio, 0);
	53	udelay(2);
	54
	55	gpio_set_value(workdata->reset_gpio, 1);
	56	udelay(2);
	57
	58	timeout = jiffies + msecs_to_jiffies(100);
	59
	60	do {
	61	regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
	62	if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
	63	break;
	64	usleep_range(1000, 2000);
	65	} while (!time_after(jiffies, timeout));
	66	}
	67
	68	static void tegra20_ac97_codec_warm_reset(struct snd_ac97 *ac97)
	69	{
	70	u32 readback;
	71	unsigned long timeout;
	72
	73	/*
	74	* although sync line is driven by the DAC pad group warm reset using
	75	* the controller cmd is not working, have to toggle sync line
	76	* manually.
	77	*/
	78	gpio_request(workdata->sync_gpio, "codec-sync");
	79
	80	gpio_direction_output(workdata->sync_gpio, 1);
	81
	82	udelay(2);
	83	gpio_set_value(workdata->sync_gpio, 0);
	84	udelay(2);
	85	gpio_free(workdata->sync_gpio);
	86
	87	timeout = jiffies + msecs_to_jiffies(100);
	88
	89	do {
	90	regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
	91	if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
	92	break;
	93	usleep_range(1000, 2000);
	94	} while (!time_after(jiffies, timeout));
	95	}
	96
	97	static unsigned short tegra20_ac97_codec_read(struct snd_ac97 *ac97_snd,
	98	unsigned short reg)
	99	{
	100	u32 readback;
	101	unsigned long timeout;
	102
	103	regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
104	(((reg \| 0x80) << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
105	TEGRA20_AC97_CMD_CMD_ADDR_MASK) \|
106	TEGRA20_AC97_CMD_BUSY);
107
108	timeout = jiffies + msecs_to_jiffies(100);
109
110	do {
111	regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
112	if (readback & TEGRA20_AC97_STATUS1_STA_VALID1)
113	break;
114	usleep_range(1000, 2000);
115	} while (!time_after(jiffies, timeout));
116
117	return ((readback & TEGRA20_AC97_STATUS1_STA_DATA1_MASK) >>
118	TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT);
119	}
120
121	static void tegra20_ac97_codec_write(struct snd_ac97 *ac97_snd,
122	unsigned short reg, unsigned short val)
123	{
124	u32 readback;
125	unsigned long timeout;
126
127	regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
128	((reg << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
129	TEGRA20_AC97_CMD_CMD_ADDR_MASK) \|
130	((val << TEGRA20_AC97_CMD_CMD_DATA_SHIFT) &
131	TEGRA20_AC97_CMD_CMD_DATA_MASK) \|
132	TEGRA20_AC97_CMD_BUSY);
133
134	timeout = jiffies + msecs_to_jiffies(100);
135
136	do {
137	regmap_read(workdata->regmap, TEGRA20_AC97_CMD, &readback);
138	if (!(readback & TEGRA20_AC97_CMD_BUSY))
139	break;
140	usleep_range(1000, 2000);
141	} while (!time_after(jiffies, timeout));
142	}
143
b047e1cc	144	static struct snd_ac97_bus_ops tegra20_ac97_ops = {
609dad9b LS	145	.read = tegra20_ac97_codec_read,
	146	.write = tegra20_ac97_codec_write,
	147	.reset = tegra20_ac97_codec_reset,
	148	.warm_reset = tegra20_ac97_codec_warm_reset,
	149	};
609dad9b LS	150
	151	static inline void tegra20_ac97_start_playback(struct tegra20_ac97 *ac97)
	152	{
	153	regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
	154	TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN,
	155	TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN);
	156
	157	regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
	158	TEGRA20_AC97_CTRL_PCM_DAC_EN \|
	159	TEGRA20_AC97_CTRL_STM_EN,
	160	TEGRA20_AC97_CTRL_PCM_DAC_EN \|
	161	TEGRA20_AC97_CTRL_STM_EN);
	162	}
	163
	164	static inline void tegra20_ac97_stop_playback(struct tegra20_ac97 *ac97)
	165	{
	166	regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
	167	TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN, 0);
	168
	169	regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
	170	TEGRA20_AC97_CTRL_PCM_DAC_EN, 0);
	171	}
	172
	173	static inline void tegra20_ac97_start_capture(struct tegra20_ac97 *ac97)
	174	{
	175	regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
	176	TEGRA20_AC97_FIFO_SCR_REC_FULL_EN,
	177	TEGRA20_AC97_FIFO_SCR_REC_FULL_EN);
	178	}
	179
	180	static inline void tegra20_ac97_stop_capture(struct tegra20_ac97 *ac97)
	181	{
	182	regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
	183	TEGRA20_AC97_FIFO_SCR_REC_FULL_EN, 0);
	184	}
	185
	186	static int tegra20_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
	187	struct snd_soc_dai *dai)
	188	{
	189	struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
	190
	191	switch (cmd) {
	192	case SNDRV_PCM_TRIGGER_START:
	193	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	194	case SNDRV_PCM_TRIGGER_RESUME:
	195	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	196	tegra20_ac97_start_playback(ac97);
	197	else
	198	tegra20_ac97_start_capture(ac97);
	199	break;
	200	case SNDRV_PCM_TRIGGER_STOP:
	201	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	202	case SNDRV_PCM_TRIGGER_SUSPEND:
	203	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	204	tegra20_ac97_stop_playback(ac97);
	205	else
	206	tegra20_ac97_stop_capture(ac97);
	207	break;
	208	default:
	209	return -EINVAL;
	210	}
	211
	212	return 0;
	213	}
214
215	static const struct snd_soc_dai_ops tegra20_ac97_dai_ops = {
216	.trigger = tegra20_ac97_trigger,
217	};
218
219	static int tegra20_ac97_probe(struct snd_soc_dai *dai)
220	{
221	struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
222
223	dai->capture_dma_data = &ac97->capture_dma_data;
224	dai->playback_dma_data = &ac97->playback_dma_data;
225
226	return 0;
227	}
228
229	static struct snd_soc_dai_driver tegra20_ac97_dai = {
230	.name = "tegra-ac97-pcm",
bc263214	231	.bus_control = true,
609dad9b LS	232	.probe = tegra20_ac97_probe,
	233	.playback = {
	234	.stream_name = "PCM Playback",
	235	.channels_min = 2,
	236	.channels_max = 2,
	237	.rates = SNDRV_PCM_RATE_8000_48000,
	238	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	239	},
	240	.capture = {
	241	.stream_name = "PCM Capture",
	242	.channels_min = 2,
	243	.channels_max = 2,
	244	.rates = SNDRV_PCM_RATE_8000_48000,
	245	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	246	},
	247	.ops = &tegra20_ac97_dai_ops,
	248	};
	249
359e2cb7 KM	250	static const struct snd_soc_component_driver tegra20_ac97_component = {
	251	.name = DRV_NAME,
	252	};
	253
609dad9b LS	254	static bool tegra20_ac97_wr_rd_reg(struct device *dev, unsigned int reg)
	255	{
	256	switch (reg) {
	257	case TEGRA20_AC97_CTRL:
	258	case TEGRA20_AC97_CMD:
	259	case TEGRA20_AC97_STATUS1:
	260	case TEGRA20_AC97_FIFO1_SCR:
	261	case TEGRA20_AC97_FIFO_TX1:
	262	case TEGRA20_AC97_FIFO_RX1:
	263	return true;
	264	default:
	265	break;
	266	}
	267
	268	return false;
	269	}
	270
	271	static bool tegra20_ac97_volatile_reg(struct device *dev, unsigned int reg)
	272	{
	273	switch (reg) {
	274	case TEGRA20_AC97_STATUS1:
	275	case TEGRA20_AC97_FIFO1_SCR:
	276	case TEGRA20_AC97_FIFO_TX1:
	277	case TEGRA20_AC97_FIFO_RX1:
	278	return true;
	279	default:
	280	break;
	281	}
	282
	283	return false;
	284	}
	285
	286	static bool tegra20_ac97_precious_reg(struct device *dev, unsigned int reg)
	287	{
	288	switch (reg) {
	289	case TEGRA20_AC97_FIFO_TX1:
	290	case TEGRA20_AC97_FIFO_RX1:
	291	return true;
	292	default:
	293	break;
	294	}
	295
	296	return false;
	297	}
	298
	299	static const struct regmap_config tegra20_ac97_regmap_config = {
	300	.reg_bits = 32,
	301	.reg_stride = 4,
	302	.val_bits = 32,
	303	.max_register = TEGRA20_AC97_FIFO_RX1,
	304	.writeable_reg = tegra20_ac97_wr_rd_reg,
	305	.readable_reg = tegra20_ac97_wr_rd_reg,
	306	.volatile_reg = tegra20_ac97_volatile_reg,
	307	.precious_reg = tegra20_ac97_precious_reg,
591d14f0	308	.cache_type = REGCACHE_FLAT,
609dad9b LS	309	};
	310
	311	static int tegra20_ac97_platform_probe(struct platform_device *pdev)
	312	{
	313	struct tegra20_ac97 *ac97;
8a08f4c4	314	struct resource *mem;
609dad9b LS	315	void __iomem *regs;
	316	int ret = 0;
	317
	318	ac97 = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_ac97),
	319	GFP_KERNEL);
	320	if (!ac97) {
	321	dev_err(&pdev->dev, "Can't allocate tegra20_ac97\n");
	322	ret = -ENOMEM;
	323	goto err;
	324	}
	325	dev_set_drvdata(&pdev->dev, ac97);
	326
cfe68642	327	ac97->clk_ac97 = devm_clk_get(&pdev->dev, NULL);
609dad9b LS	328	if (IS_ERR(ac97->clk_ac97)) {
	329	dev_err(&pdev->dev, "Can't retrieve ac97 clock\n");
	330	ret = PTR_ERR(ac97->clk_ac97);
	331	goto err;
	332	}
	333
	334	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2def2516 MB	335	regs = devm_ioremap_resource(&pdev->dev, mem);
	336	if (IS_ERR(regs)) {
	337	ret = PTR_ERR(regs);
609dad9b LS	338	goto err_clk_put;
	339	}
	340
	341	ac97->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
	342	&tegra20_ac97_regmap_config);
	343	if (IS_ERR(ac97->regmap)) {
	344	dev_err(&pdev->dev, "regmap init failed\n");
	345	ret = PTR_ERR(ac97->regmap);
	346	goto err_clk_put;
	347	}
	348
609dad9b LS	349	ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node,
	350	"nvidia,codec-reset-gpio", 0);
	351	if (gpio_is_valid(ac97->reset_gpio)) {
	352	ret = devm_gpio_request_one(&pdev->dev, ac97->reset_gpio,
	353	GPIOF_OUT_INIT_HIGH, "codec-reset");
	354	if (ret) {
	355	dev_err(&pdev->dev, "could not get codec-reset GPIO\n");
	356	goto err_clk_put;
	357	}
	358	} else {
	359	dev_err(&pdev->dev, "no codec-reset GPIO supplied\n");
	360	goto err_clk_put;
	361	}
	362
	363	ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node,
	364	"nvidia,codec-sync-gpio", 0);
	365	if (!gpio_is_valid(ac97->sync_gpio)) {
	366	dev_err(&pdev->dev, "no codec-sync GPIO supplied\n");
	367	goto err_clk_put;
	368	}
	369
	370	ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
3489d506 LPC	371	ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
3489d506 LPC	372	ac97->capture_dma_data.maxburst = 4;
609dad9b LS	373
609dad9b LS	374	ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
647ab784 RZ	375	ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
647ab784 RZ	376	ac97->playback_dma_data.maxburst = 4;
609dad9b	377
609dad9b LS	378	ret = clk_prepare_enable(ac97->clk_ac97);
	379	if (ret) {
	380	dev_err(&pdev->dev, "clk_enable failed: %d\n", ret);
1ca2e847	381	goto err;
609dad9b LS	382	}
609dad9b LS	383
b047e1cc MB	384	ret = snd_soc_set_ac97_ops(&tegra20_ac97_ops);
	385	if (ret) {
	386	dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
753834cb	387	goto err_clk_disable_unprepare;
b047e1cc MB	388	}
b047e1cc MB	389
65fb3e72 MB	390	ret = snd_soc_register_component(&pdev->dev, &tegra20_ac97_component,
	391	&tegra20_ac97_dai, 1);
	392	if (ret) {
	393	dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
	394	ret = -ENOMEM;
753834cb	395	goto err_clk_disable_unprepare;
65fb3e72 MB	396	}
	397
	398	ret = tegra_pcm_platform_register(&pdev->dev);
	399	if (ret) {
	400	dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
	401	goto err_unregister_component;
	402	}
	403
609dad9b LS	404	/* XXX: crufty ASoC AC97 API - only one AC97 codec allowed */
	405	workdata = ac97;
	406
	407	return 0;
	408
359e2cb7 KM	409	err_unregister_component:
359e2cb7 KM	410	snd_soc_unregister_component(&pdev->dev);
753834cb WY	411	err_clk_disable_unprepare:
753834cb WY	412	clk_disable_unprepare(ac97->clk_ac97);
609dad9b	413	err_clk_put:
609dad9b	414	err:
b047e1cc	415	snd_soc_set_ac97_ops(NULL);
609dad9b LS	416	return ret;
	417	}
	418
	419	static int tegra20_ac97_platform_remove(struct platform_device *pdev)
	420	{
	421	struct tegra20_ac97 *ac97 = dev_get_drvdata(&pdev->dev);
	422
	423	tegra_pcm_platform_unregister(&pdev->dev);
359e2cb7	424	snd_soc_unregister_component(&pdev->dev);
609dad9b	425
609dad9b	426	clk_disable_unprepare(ac97->clk_ac97);
609dad9b	427
b047e1cc MB	428	snd_soc_set_ac97_ops(NULL);
b047e1cc MB	429
609dad9b LS	430	return 0;
	431	}
	432
d58579e3	433	static const struct of_device_id tegra20_ac97_of_match[] = {
609dad9b LS	434	{ .compatible = "nvidia,tegra20-ac97", },
	435	{},
	436	};
	437
	438	static struct platform_driver tegra20_ac97_driver = {
	439	.driver = {
	440	.name = DRV_NAME,
609dad9b LS	441	.of_match_table = tegra20_ac97_of_match,
	442	},
	443	.probe = tegra20_ac97_platform_probe,
	444	.remove = tegra20_ac97_platform_remove,
	445	};
	446	module_platform_driver(tegra20_ac97_driver);
	447
	448	MODULE_AUTHOR("Lucas Stach");
	449	MODULE_DESCRIPTION("Tegra20 AC97 ASoC driver");
	450	MODULE_LICENSE("GPL v2");
	451	MODULE_ALIAS("platform:" DRV_NAME);
	452	MODULE_DEVICE_TABLE(of, tegra20_ac97_of_match);