[deliverable/linux.git] / sound / soc / tegra / tegra20_i2s.c

/*
 * tegra20_i2s.c - Tegra20 I2S driver
 *
 * Author: Stephen Warren <swarren@nvidia.com>
 * Copyright (C) 2010,2012 - NVIDIA, Inc.
 *
 * Based on code copyright/by:
 *
 * Copyright (c) 2009-2010, NVIDIA Corporation.
 * Scott Peterson <speterson@nvidia.com>
 *
 * Copyright (C) 2010 Google, Inc.
 * Iliyan Malchev <malchev@google.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>

#include "tegra20_i2s.h"

#define DRV_NAME "tegra20-i2s"

static int tegra20_i2s_runtime_suspend(struct device *dev)
{
	struct tegra20_i2s *i2s = dev_get_drvdata(dev);

	clk_disable_unprepare(i2s->clk_i2s);

	return 0;
}

static int tegra20_i2s_runtime_resume(struct device *dev)
{
	struct tegra20_i2s *i2s = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(i2s->clk_i2s);
	if (ret) {
		dev_err(dev, "clk_enable failed: %d\n", ret);
		return ret;
	}

	return 0;
}

static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai,
				unsigned int fmt)
{
	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	unsigned int mask = 0, val = 0;

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		break;
	default:
		return -EINVAL;
	}

	mask |= TEGRA20_I2S_CTRL_MASTER_ENABLE;
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		val |= TEGRA20_I2S_CTRL_MASTER_ENABLE;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		break;
	default:
		return -EINVAL;
	}

	mask |= TEGRA20_I2S_CTRL_BIT_FORMAT_MASK |
		TEGRA20_I2S_CTRL_LRCK_MASK;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_DSP_A:
		val |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
		val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_DSP_B:
		val |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
		val |= TEGRA20_I2S_CTRL_LRCK_R_LOW;
		break;
	case SND_SOC_DAIFMT_I2S:
		val |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S;
		val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		val |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM;
		val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		val |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM;
		val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val);

	return 0;
}

static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct device *dev = dai->dev;
	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	unsigned int mask, val;
	int ret, sample_size, srate, i2sclock, bitcnt;

	mask = TEGRA20_I2S_CTRL_BIT_SIZE_MASK;
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		val = TEGRA20_I2S_CTRL_BIT_SIZE_16;
		sample_size = 16;
		break;
	case SNDRV_PCM_FORMAT_S24_LE:
		val = TEGRA20_I2S_CTRL_BIT_SIZE_24;
		sample_size = 24;
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		val = TEGRA20_I2S_CTRL_BIT_SIZE_32;
		sample_size = 32;
		break;
	default:
		return -EINVAL;
	}

	mask |= TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK;
	val |= TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED;

	regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val);

	srate = params_rate(params);

	/* Final "* 2" required by Tegra hardware */
	i2sclock = srate * params_channels(params) * sample_size * 2;

	ret = clk_set_rate(i2s->clk_i2s, i2sclock);
	if (ret) {
		dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
		return ret;
	}

	bitcnt = (i2sclock / (2 * srate)) - 1;
	if (bitcnt < 0 || bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
		return -EINVAL;
	val = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;

	if (i2sclock % (2 * srate))
		val |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE;

	regmap_write(i2s->regmap, TEGRA20_I2S_TIMING, val);

	regmap_write(i2s->regmap, TEGRA20_I2S_FIFO_SCR,
		     TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
		     TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);

	return 0;
}

static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s)
{
	regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
			   TEGRA20_I2S_CTRL_FIFO1_ENABLE,
			   TEGRA20_I2S_CTRL_FIFO1_ENABLE);
}

static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s)
{
	regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
			   TEGRA20_I2S_CTRL_FIFO1_ENABLE, 0);
}

static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s)
{
	regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
			   TEGRA20_I2S_CTRL_FIFO2_ENABLE,
			   TEGRA20_I2S_CTRL_FIFO2_ENABLE);
}

static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s)
{
	regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
			   TEGRA20_I2S_CTRL_FIFO2_ENABLE, 0);
}

static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_RESUME:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra20_i2s_start_playback(i2s);
		else
			tegra20_i2s_start_capture(i2s);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	case SNDRV_PCM_TRIGGER_SUSPEND:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra20_i2s_stop_playback(i2s);
		else
			tegra20_i2s_stop_capture(i2s);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int tegra20_i2s_probe(struct snd_soc_dai *dai)
{
	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	dai->capture_dma_data = &i2s->capture_dma_data;
	dai->playback_dma_data = &i2s->playback_dma_data;

	return 0;
}

static const struct snd_soc_dai_ops tegra20_i2s_dai_ops = {
	.set_fmt	= tegra20_i2s_set_fmt,
	.hw_params	= tegra20_i2s_hw_params,
	.trigger	= tegra20_i2s_trigger,
};

static const struct snd_soc_dai_driver tegra20_i2s_dai_template = {
	.probe = tegra20_i2s_probe,
	.playback = {
		.stream_name = "Playback",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.capture = {
		.stream_name = "Capture",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops = &tegra20_i2s_dai_ops,
	.symmetric_rates = 1,
};

static const struct snd_soc_component_driver tegra20_i2s_component = {
	.name		= DRV_NAME,
};

static bool tegra20_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA20_I2S_CTRL:
	case TEGRA20_I2S_STATUS:
	case TEGRA20_I2S_TIMING:
	case TEGRA20_I2S_FIFO_SCR:
	case TEGRA20_I2S_PCM_CTRL:
	case TEGRA20_I2S_NW_CTRL:
	case TEGRA20_I2S_TDM_CTRL:
	case TEGRA20_I2S_TDM_TX_RX_CTRL:
	case TEGRA20_I2S_FIFO1:
	case TEGRA20_I2S_FIFO2:
		return true;
	default:
		return false;
	}
}

static bool tegra20_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA20_I2S_STATUS:
	case TEGRA20_I2S_FIFO_SCR:
	case TEGRA20_I2S_FIFO1:
	case TEGRA20_I2S_FIFO2:
		return true;
	default:
		return false;
	}
}

static bool tegra20_i2s_precious_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA20_I2S_FIFO1:
	case TEGRA20_I2S_FIFO2:
		return true;
	default:
		return false;
	}
}

static const struct regmap_config tegra20_i2s_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = TEGRA20_I2S_FIFO2,
	.writeable_reg = tegra20_i2s_wr_rd_reg,
	.readable_reg = tegra20_i2s_wr_rd_reg,
	.volatile_reg = tegra20_i2s_volatile_reg,
	.precious_reg = tegra20_i2s_precious_reg,
	.cache_type = REGCACHE_FLAT,
};

static int tegra20_i2s_platform_probe(struct platform_device *pdev)
{
	struct tegra20_i2s *i2s;
	struct resource *mem;
	void __iomem *regs;
	int ret;

	i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL);
	if (!i2s) {
		dev_err(&pdev->dev, "Can't allocate tegra20_i2s\n");
		ret = -ENOMEM;
		goto err;
	}
	dev_set_drvdata(&pdev->dev, i2s);

	i2s->dai = tegra20_i2s_dai_template;
	i2s->dai.name = dev_name(&pdev->dev);

	i2s->clk_i2s = clk_get(&pdev->dev, NULL);
	if (IS_ERR(i2s->clk_i2s)) {
		dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
		ret = PTR_ERR(i2s->clk_i2s);
		goto err;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	regs = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(regs)) {
		ret = PTR_ERR(regs);
		goto err_clk_put;
	}

	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
					    &tegra20_i2s_regmap_config);
	if (IS_ERR(i2s->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		ret = PTR_ERR(i2s->regmap);
		goto err_clk_put;
	}

	i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	i2s->capture_dma_data.maxburst = 4;

	i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	i2s->playback_dma_data.maxburst = 4;

	pm_runtime_enable(&pdev->dev);
	if (!pm_runtime_enabled(&pdev->dev)) {
		ret = tegra20_i2s_runtime_resume(&pdev->dev);
		if (ret)
			goto err_pm_disable;
	}

	ret = snd_soc_register_component(&pdev->dev, &tegra20_i2s_component,
					 &i2s->dai, 1);
	if (ret) {
		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
		ret = -ENOMEM;
		goto err_suspend;
	}

	ret = tegra_pcm_platform_register(&pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
		goto err_unregister_component;
	}

	return 0;

err_unregister_component:
	snd_soc_unregister_component(&pdev->dev);
err_suspend:
	if (!pm_runtime_status_suspended(&pdev->dev))
		tegra20_i2s_runtime_suspend(&pdev->dev);
err_pm_disable:
	pm_runtime_disable(&pdev->dev);
err_clk_put:
	clk_put(i2s->clk_i2s);
err:
	return ret;
}

static int tegra20_i2s_platform_remove(struct platform_device *pdev)
{
	struct tegra20_i2s *i2s = dev_get_drvdata(&pdev->dev);

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		tegra20_i2s_runtime_suspend(&pdev->dev);

	tegra_pcm_platform_unregister(&pdev->dev);
	snd_soc_unregister_component(&pdev->dev);

	clk_put(i2s->clk_i2s);

	return 0;
}

static const struct of_device_id tegra20_i2s_of_match[] = {
	{ .compatible = "nvidia,tegra20-i2s", },
	{},
};

static const struct dev_pm_ops tegra20_i2s_pm_ops = {
	SET_RUNTIME_PM_OPS(tegra20_i2s_runtime_suspend,
			   tegra20_i2s_runtime_resume, NULL)
};

static struct platform_driver tegra20_i2s_driver = {
	.driver = {
		.name = DRV_NAME,
		.of_match_table = tegra20_i2s_of_match,
		.pm = &tegra20_i2s_pm_ops,
	},
	.probe = tegra20_i2s_platform_probe,
	.remove = tegra20_i2s_platform_remove,
};
module_platform_driver(tegra20_i2s_driver);

MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
MODULE_DESCRIPTION("Tegra20 I2S ASoC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra20_i2s_of_match);
Commit	Line	Data
71f78e22	1	/*
ef280d39	2	* tegra20_i2s.c - Tegra20 I2S driver
71f78e22 SW	3	*
71f78e22 SW	4	* Author: Stephen Warren <swarren@nvidia.com>
518de86b	5	* Copyright (C) 2010,2012 - NVIDIA, Inc.
71f78e22 SW	6	*
	7	* Based on code copyright/by:
	8	*
	9	* Copyright (c) 2009-2010, NVIDIA Corporation.
	10	* Scott Peterson <speterson@nvidia.com>
	11	*
	12	* Copyright (C) 2010 Google, Inc.
	13	* Iliyan Malchev <malchev@google.com>
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* version 2 as published by the Free Software Foundation.
	18	*
	19	* This program is distributed in the hope that it will be useful, but
	20	* WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	22	* General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	27	* 02110-1301 USA
	28	*
	29	*/
	30
	31	#include <linux/clk.h>
71f78e22	32	#include <linux/device.h>
7613c508 SW	33	#include <linux/io.h>
	34	#include <linux/module.h>
	35	#include <linux/of.h>
71f78e22	36	#include <linux/platform_device.h>
82ef0ae4	37	#include <linux/pm_runtime.h>
c1607416	38	#include <linux/regmap.h>
71f78e22	39	#include <linux/slab.h>
71f78e22 SW	40	#include <sound/core.h>
	41	#include <sound/pcm.h>
	42	#include <sound/pcm_params.h>
	43	#include <sound/soc.h>
3489d506	44	#include <sound/dmaengine_pcm.h>
71f78e22	45
ef280d39	46	#include "tegra20_i2s.h"
71f78e22	47
896637ac	48	#define DRV_NAME "tegra20-i2s"
71f78e22	49
82ef0ae4 SW	50	static int tegra20_i2s_runtime_suspend(struct device *dev)
	51	{
	52	struct tegra20_i2s *i2s = dev_get_drvdata(dev);
	53
65d2bdd3	54	clk_disable_unprepare(i2s->clk_i2s);
82ef0ae4 SW	55
	56	return 0;
	57	}
	58
	59	static int tegra20_i2s_runtime_resume(struct device *dev)
	60	{
	61	struct tegra20_i2s *i2s = dev_get_drvdata(dev);
	62	int ret;
	63
65d2bdd3	64	ret = clk_prepare_enable(i2s->clk_i2s);
82ef0ae4 SW	65	if (ret) {
	66	dev_err(dev, "clk_enable failed: %d\n", ret);
	67	return ret;
	68	}
	69
	70	return 0;
	71	}
	72
896637ac	73	static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai,
71f78e22 SW	74	unsigned int fmt)
71f78e22 SW	75	{
896637ac	76	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
241bf433	77	unsigned int mask = 0, val = 0;
71f78e22 SW	78
	79	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	80	case SND_SOC_DAIFMT_NB_NF:
	81	break;
	82	default:
	83	return -EINVAL;
	84	}
	85
241bf433	86	mask \|= TEGRA20_I2S_CTRL_MASTER_ENABLE;
71f78e22 SW	87	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
71f78e22 SW	88	case SND_SOC_DAIFMT_CBS_CFS:
241bf433	89	val \|= TEGRA20_I2S_CTRL_MASTER_ENABLE;
71f78e22 SW	90	break;
	91	case SND_SOC_DAIFMT_CBM_CFM:
	92	break;
	93	default:
	94	return -EINVAL;
	95	}
	96
0f163546 SW	97	mask \|= TEGRA20_I2S_CTRL_BIT_FORMAT_MASK \|
0f163546 SW	98	TEGRA20_I2S_CTRL_LRCK_MASK;
71f78e22 SW	99	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
71f78e22 SW	100	case SND_SOC_DAIFMT_DSP_A:
0f163546 SW	101	val \|= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
0f163546 SW	102	val \|= TEGRA20_I2S_CTRL_LRCK_L_LOW;
71f78e22 SW	103	break;
71f78e22 SW	104	case SND_SOC_DAIFMT_DSP_B:
0f163546 SW	105	val \|= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
0f163546 SW	106	val \|= TEGRA20_I2S_CTRL_LRCK_R_LOW;
71f78e22 SW	107	break;
71f78e22 SW	108	case SND_SOC_DAIFMT_I2S:
0f163546 SW	109	val \|= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S;
0f163546 SW	110	val \|= TEGRA20_I2S_CTRL_LRCK_L_LOW;
71f78e22 SW	111	break;
71f78e22 SW	112	case SND_SOC_DAIFMT_RIGHT_J:
0f163546 SW	113	val \|= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM;
0f163546 SW	114	val \|= TEGRA20_I2S_CTRL_LRCK_L_LOW;
71f78e22 SW	115	break;
71f78e22 SW	116	case SND_SOC_DAIFMT_LEFT_J:
0f163546 SW	117	val \|= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM;
0f163546 SW	118	val \|= TEGRA20_I2S_CTRL_LRCK_L_LOW;
71f78e22 SW	119	break;
	120	default:
	121	return -EINVAL;
	122	}
	123
0f163546 SW	124	regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val);
0f163546 SW	125
71f78e22 SW	126	return 0;
	127	}
	128
896637ac SW	129	static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream,
	130	struct snd_pcm_hw_params *params,
	131	struct snd_soc_dai *dai)
71f78e22	132	{
c92a40e3	133	struct device *dev = dai->dev;
896637ac	134	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
0f163546	135	unsigned int mask, val;
71f78e22 SW	136	int ret, sample_size, srate, i2sclock, bitcnt;
71f78e22 SW	137
0f163546	138	mask = TEGRA20_I2S_CTRL_BIT_SIZE_MASK;
71f78e22 SW	139	switch (params_format(params)) {
71f78e22 SW	140	case SNDRV_PCM_FORMAT_S16_LE:
0f163546	141	val = TEGRA20_I2S_CTRL_BIT_SIZE_16;
71f78e22 SW	142	sample_size = 16;
	143	break;
	144	case SNDRV_PCM_FORMAT_S24_LE:
0f163546	145	val = TEGRA20_I2S_CTRL_BIT_SIZE_24;
71f78e22 SW	146	sample_size = 24;
	147	break;
	148	case SNDRV_PCM_FORMAT_S32_LE:
0f163546	149	val = TEGRA20_I2S_CTRL_BIT_SIZE_32;
71f78e22 SW	150	sample_size = 32;
	151	break;
	152	default:
	153	return -EINVAL;
	154	}
	155
0f163546 SW	156	mask \|= TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK;
	157	val \|= TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED;
	158
	159	regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val);
	160
71f78e22 SW	161	srate = params_rate(params);
	162
	163	/* Final "* 2" required by Tegra hardware */
	164	i2sclock = srate * params_channels(params) * sample_size * 2;
	165
	166	ret = clk_set_rate(i2s->clk_i2s, i2sclock);
	167	if (ret) {
	168	dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
	169	return ret;
	170	}
	171
	172	bitcnt = (i2sclock / (2 * srate)) - 1;
896637ac	173	if (bitcnt < 0 \|\| bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
71f78e22	174	return -EINVAL;
0f163546	175	val = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
71f78e22 SW	176
71f78e22 SW	177	if (i2sclock % (2 * srate))
0f163546	178	val \|= TEGRA20_I2S_TIMING_NON_SYM_ENABLE;
71f78e22	179
0f163546	180	regmap_write(i2s->regmap, TEGRA20_I2S_TIMING, val);
71f78e22	181
0f163546 SW	182	regmap_write(i2s->regmap, TEGRA20_I2S_FIFO_SCR,
	183	TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS \|
	184	TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
71f78e22 SW	185
	186	return 0;
	187	}
	188
896637ac	189	static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s)
71f78e22	190	{
0f163546 SW	191	regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
	192	TEGRA20_I2S_CTRL_FIFO1_ENABLE,
	193	TEGRA20_I2S_CTRL_FIFO1_ENABLE);
71f78e22 SW	194	}
71f78e22 SW	195
896637ac	196	static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s)
71f78e22	197	{
0f163546 SW	198	regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
0f163546 SW	199	TEGRA20_I2S_CTRL_FIFO1_ENABLE, 0);
71f78e22 SW	200	}
71f78e22 SW	201
896637ac	202	static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s)
71f78e22	203	{
0f163546 SW	204	regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
	205	TEGRA20_I2S_CTRL_FIFO2_ENABLE,
	206	TEGRA20_I2S_CTRL_FIFO2_ENABLE);
71f78e22 SW	207	}
71f78e22 SW	208
896637ac	209	static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s)
71f78e22	210	{
0f163546 SW	211	regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
0f163546 SW	212	TEGRA20_I2S_CTRL_FIFO2_ENABLE, 0);
71f78e22 SW	213	}
71f78e22 SW	214
896637ac SW	215	static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
896637ac SW	216	struct snd_soc_dai *dai)
71f78e22	217	{
896637ac	218	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
71f78e22 SW	219
	220	switch (cmd) {
	221	case SNDRV_PCM_TRIGGER_START:
	222	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	223	case SNDRV_PCM_TRIGGER_RESUME:
71f78e22	224	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
896637ac	225	tegra20_i2s_start_playback(i2s);
71f78e22	226	else
896637ac	227	tegra20_i2s_start_capture(i2s);
71f78e22 SW	228	break;
	229	case SNDRV_PCM_TRIGGER_STOP:
	230	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	231	case SNDRV_PCM_TRIGGER_SUSPEND:
	232	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
896637ac	233	tegra20_i2s_stop_playback(i2s);
71f78e22	234	else
896637ac	235	tegra20_i2s_stop_capture(i2s);
71f78e22 SW	236	break;
	237	default:
	238	return -EINVAL;
	239	}
	240
	241	return 0;
	242	}
	243
896637ac	244	static int tegra20_i2s_probe(struct snd_soc_dai *dai)
71f78e22	245	{
896637ac	246	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
71f78e22 SW	247
	248	dai->capture_dma_data = &i2s->capture_dma_data;
	249	dai->playback_dma_data = &i2s->playback_dma_data;
	250
	251	return 0;
	252	}
	253
896637ac SW	254	static const struct snd_soc_dai_ops tegra20_i2s_dai_ops = {
	255	.set_fmt = tegra20_i2s_set_fmt,
	256	.hw_params = tegra20_i2s_hw_params,
	257	.trigger = tegra20_i2s_trigger,
71f78e22 SW	258	};
71f78e22 SW	259
896637ac SW	260	static const struct snd_soc_dai_driver tegra20_i2s_dai_template = {
896637ac SW	261	.probe = tegra20_i2s_probe,
d4a2eca7	262	.playback = {
9515c101	263	.stream_name = "Playback",
d4a2eca7 SW	264	.channels_min = 2,
	265	.channels_max = 2,
	266	.rates = SNDRV_PCM_RATE_8000_96000,
	267	.formats = SNDRV_PCM_FMTBIT_S16_LE,
71f78e22	268	},
d4a2eca7	269	.capture = {
9515c101	270	.stream_name = "Capture",
d4a2eca7 SW	271	.channels_min = 2,
	272	.channels_max = 2,
	273	.rates = SNDRV_PCM_RATE_8000_96000,
	274	.formats = SNDRV_PCM_FMTBIT_S16_LE,
71f78e22	275	},
896637ac	276	.ops = &tegra20_i2s_dai_ops,
d4a2eca7	277	.symmetric_rates = 1,
71f78e22 SW	278	};
71f78e22 SW	279
a413a3c2 KM	280	static const struct snd_soc_component_driver tegra20_i2s_component = {
	281	.name = DRV_NAME,
	282	};
	283
c1607416 SW	284	static bool tegra20_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
	285	{
	286	switch (reg) {
	287	case TEGRA20_I2S_CTRL:
	288	case TEGRA20_I2S_STATUS:
	289	case TEGRA20_I2S_TIMING:
	290	case TEGRA20_I2S_FIFO_SCR:
	291	case TEGRA20_I2S_PCM_CTRL:
	292	case TEGRA20_I2S_NW_CTRL:
	293	case TEGRA20_I2S_TDM_CTRL:
	294	case TEGRA20_I2S_TDM_TX_RX_CTRL:
	295	case TEGRA20_I2S_FIFO1:
	296	case TEGRA20_I2S_FIFO2:
	297	return true;
	298	default:
	299	return false;
1d198f26	300	}
c1607416 SW	301	}
	302
	303	static bool tegra20_i2s_volatile_reg(struct device *dev, unsigned int reg)
	304	{
	305	switch (reg) {
	306	case TEGRA20_I2S_STATUS:
	307	case TEGRA20_I2S_FIFO_SCR:
	308	case TEGRA20_I2S_FIFO1:
	309	case TEGRA20_I2S_FIFO2:
	310	return true;
	311	default:
	312	return false;
1d198f26	313	}
c1607416 SW	314	}
	315
	316	static bool tegra20_i2s_precious_reg(struct device *dev, unsigned int reg)
	317	{
	318	switch (reg) {
	319	case TEGRA20_I2S_FIFO1:
	320	case TEGRA20_I2S_FIFO2:
	321	return true;
	322	default:
	323	return false;
1d198f26	324	}
c1607416 SW	325	}
	326
	327	static const struct regmap_config tegra20_i2s_regmap_config = {
	328	.reg_bits = 32,
	329	.reg_stride = 4,
	330	.val_bits = 32,
	331	.max_register = TEGRA20_I2S_FIFO2,
	332	.writeable_reg = tegra20_i2s_wr_rd_reg,
	333	.readable_reg = tegra20_i2s_wr_rd_reg,
	334	.volatile_reg = tegra20_i2s_volatile_reg,
	335	.precious_reg = tegra20_i2s_precious_reg,
591d14f0	336	.cache_type = REGCACHE_FLAT,
c1607416 SW	337	};
c1607416 SW	338
4652a0d0	339	static int tegra20_i2s_platform_probe(struct platform_device *pdev)
71f78e22	340	{
896637ac	341	struct tegra20_i2s *i2s;
f57ddcdf	342	struct resource *mem;
c1607416	343	void __iomem *regs;
71f78e22 SW	344	int ret;
71f78e22 SW	345
896637ac	346	i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL);
71f78e22	347	if (!i2s) {
896637ac	348	dev_err(&pdev->dev, "Can't allocate tegra20_i2s\n");
71f78e22	349	ret = -ENOMEM;
bea0ed08	350	goto err;
71f78e22 SW	351	}
	352	dev_set_drvdata(&pdev->dev, i2s);
	353
896637ac	354	i2s->dai = tegra20_i2s_dai_template;
d4a2eca7 SW	355	i2s->dai.name = dev_name(&pdev->dev);
d4a2eca7 SW	356
b5f9cfed	357	i2s->clk_i2s = clk_get(&pdev->dev, NULL);
422650e6	358	if (IS_ERR(i2s->clk_i2s)) {
713dce4e	359	dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
71f78e22	360	ret = PTR_ERR(i2s->clk_i2s);
bea0ed08	361	goto err;
71f78e22 SW	362	}
	363
	364	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
f57ddcdf AL	365	regs = devm_ioremap_resource(&pdev->dev, mem);
	366	if (IS_ERR(regs)) {
	367	ret = PTR_ERR(regs);
bea0ed08	368	goto err_clk_put;
71f78e22 SW	369	}
71f78e22 SW	370
c1607416 SW	371	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
	372	&tegra20_i2s_regmap_config);
	373	if (IS_ERR(i2s->regmap)) {
	374	dev_err(&pdev->dev, "regmap init failed\n");
	375	ret = PTR_ERR(i2s->regmap);
	376	goto err_clk_put;
	377	}
	378
896637ac	379	i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
3489d506 LPC	380	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
3489d506 LPC	381	i2s->capture_dma_data.maxburst = 4;
71f78e22	382
896637ac	383	i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
3489d506 LPC	384	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
3489d506 LPC	385	i2s->playback_dma_data.maxburst = 4;
71f78e22	386
82ef0ae4 SW	387	pm_runtime_enable(&pdev->dev);
	388	if (!pm_runtime_enabled(&pdev->dev)) {
	389	ret = tegra20_i2s_runtime_resume(&pdev->dev);
	390	if (ret)
	391	goto err_pm_disable;
	392	}
	393
a413a3c2 KM	394	ret = snd_soc_register_component(&pdev->dev, &tegra20_i2s_component,
a413a3c2 KM	395	&i2s->dai, 1);
71f78e22 SW	396	if (ret) {
	397	dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
	398	ret = -ENOMEM;
82ef0ae4	399	goto err_suspend;
71f78e22 SW	400	}
71f78e22 SW	401
518de86b SW	402	ret = tegra_pcm_platform_register(&pdev->dev);
	403	if (ret) {
	404	dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
a413a3c2	405	goto err_unregister_component;
518de86b SW	406	}
518de86b SW	407
71f78e22 SW	408	return 0;
71f78e22 SW	409
a413a3c2 KM	410	err_unregister_component:
a413a3c2 KM	411	snd_soc_unregister_component(&pdev->dev);
82ef0ae4 SW	412	err_suspend:
	413	if (!pm_runtime_status_suspended(&pdev->dev))
	414	tegra20_i2s_runtime_suspend(&pdev->dev);
	415	err_pm_disable:
	416	pm_runtime_disable(&pdev->dev);
71f78e22 SW	417	err_clk_put:
71f78e22 SW	418	clk_put(i2s->clk_i2s);
bea0ed08	419	err:
71f78e22 SW	420	return ret;
	421	}
	422
4652a0d0	423	static int tegra20_i2s_platform_remove(struct platform_device *pdev)
71f78e22	424	{
896637ac	425	struct tegra20_i2s *i2s = dev_get_drvdata(&pdev->dev);
71f78e22	426
82ef0ae4 SW	427	pm_runtime_disable(&pdev->dev);
	428	if (!pm_runtime_status_suspended(&pdev->dev))
	429	tegra20_i2s_runtime_suspend(&pdev->dev);
	430
518de86b	431	tegra_pcm_platform_unregister(&pdev->dev);
a413a3c2	432	snd_soc_unregister_component(&pdev->dev);
71f78e22	433
71f78e22 SW	434	clk_put(i2s->clk_i2s);
71f78e22 SW	435
71f78e22 SW	436	return 0;
	437	}
	438
f6e65744	439	static const struct of_device_id tegra20_i2s_of_match[] = {
bf55499e SW	440	{ .compatible = "nvidia,tegra20-i2s", },
	441	{},
	442	};
	443
f6e65744	444	static const struct dev_pm_ops tegra20_i2s_pm_ops = {
82ef0ae4 SW	445	SET_RUNTIME_PM_OPS(tegra20_i2s_runtime_suspend,
	446	tegra20_i2s_runtime_resume, NULL)
	447	};
	448
896637ac	449	static struct platform_driver tegra20_i2s_driver = {
71f78e22 SW	450	.driver = {
71f78e22 SW	451	.name = DRV_NAME,
896637ac	452	.of_match_table = tegra20_i2s_of_match,
82ef0ae4	453	.pm = &tegra20_i2s_pm_ops,
71f78e22	454	},
896637ac	455	.probe = tegra20_i2s_platform_probe,
4652a0d0	456	.remove = tegra20_i2s_platform_remove,
71f78e22	457	};
896637ac	458	module_platform_driver(tegra20_i2s_driver);
71f78e22 SW	459
71f78e22 SW	460	MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
896637ac	461	MODULE_DESCRIPTION("Tegra20 I2S ASoC driver");
71f78e22	462	MODULE_LICENSE("GPL");
8eb34207	463	MODULE_ALIAS("platform:" DRV_NAME);
896637ac	464	MODULE_DEVICE_TABLE(of, tegra20_i2s_of_match);