Commit | Line | Data |
---|---|---|
71f78e22 | 1 | /* |
ef280d39 | 2 | * tegra20_i2s.c - Tegra20 I2S driver |
71f78e22 SW |
3 | * |
4 | * Author: Stephen Warren <swarren@nvidia.com> | |
518de86b | 5 | * Copyright (C) 2010,2012 - NVIDIA, Inc. |
71f78e22 SW |
6 | * |
7 | * Based on code copyright/by: | |
8 | * | |
9 | * Copyright (c) 2009-2010, NVIDIA Corporation. | |
10 | * Scott Peterson <speterson@nvidia.com> | |
11 | * | |
12 | * Copyright (C) 2010 Google, Inc. | |
13 | * Iliyan Malchev <malchev@google.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * version 2 as published by the Free Software Foundation. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
27 | * 02110-1301 USA | |
28 | * | |
29 | */ | |
30 | ||
31 | #include <linux/clk.h> | |
71f78e22 SW |
32 | #include <linux/debugfs.h> |
33 | #include <linux/device.h> | |
7613c508 SW |
34 | #include <linux/io.h> |
35 | #include <linux/module.h> | |
36 | #include <linux/of.h> | |
71f78e22 SW |
37 | #include <linux/platform_device.h> |
38 | #include <linux/seq_file.h> | |
39 | #include <linux/slab.h> | |
71f78e22 SW |
40 | #include <sound/core.h> |
41 | #include <sound/pcm.h> | |
42 | #include <sound/pcm_params.h> | |
43 | #include <sound/soc.h> | |
44 | ||
ef280d39 | 45 | #include "tegra20_i2s.h" |
71f78e22 | 46 | |
896637ac | 47 | #define DRV_NAME "tegra20-i2s" |
71f78e22 | 48 | |
896637ac | 49 | static inline void tegra20_i2s_write(struct tegra20_i2s *i2s, u32 reg, u32 val) |
71f78e22 SW |
50 | { |
51 | __raw_writel(val, i2s->regs + reg); | |
52 | } | |
53 | ||
896637ac | 54 | static inline u32 tegra20_i2s_read(struct tegra20_i2s *i2s, u32 reg) |
71f78e22 SW |
55 | { |
56 | return __raw_readl(i2s->regs + reg); | |
57 | } | |
58 | ||
59 | #ifdef CONFIG_DEBUG_FS | |
896637ac | 60 | static int tegra20_i2s_show(struct seq_file *s, void *unused) |
71f78e22 SW |
61 | { |
62 | #define REG(r) { r, #r } | |
63 | static const struct { | |
64 | int offset; | |
65 | const char *name; | |
66 | } regs[] = { | |
896637ac SW |
67 | REG(TEGRA20_I2S_CTRL), |
68 | REG(TEGRA20_I2S_STATUS), | |
69 | REG(TEGRA20_I2S_TIMING), | |
70 | REG(TEGRA20_I2S_FIFO_SCR), | |
71 | REG(TEGRA20_I2S_PCM_CTRL), | |
72 | REG(TEGRA20_I2S_NW_CTRL), | |
73 | REG(TEGRA20_I2S_TDM_CTRL), | |
74 | REG(TEGRA20_I2S_TDM_TX_RX_CTRL), | |
71f78e22 SW |
75 | }; |
76 | #undef REG | |
77 | ||
896637ac | 78 | struct tegra20_i2s *i2s = s->private; |
71f78e22 SW |
79 | int i; |
80 | ||
81 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
896637ac | 82 | u32 val = tegra20_i2s_read(i2s, regs[i].offset); |
71f78e22 SW |
83 | seq_printf(s, "%s = %08x\n", regs[i].name, val); |
84 | } | |
85 | ||
86 | return 0; | |
87 | } | |
88 | ||
896637ac | 89 | static int tegra20_i2s_debug_open(struct inode *inode, struct file *file) |
71f78e22 | 90 | { |
896637ac | 91 | return single_open(file, tegra20_i2s_show, inode->i_private); |
71f78e22 SW |
92 | } |
93 | ||
896637ac SW |
94 | static const struct file_operations tegra20_i2s_debug_fops = { |
95 | .open = tegra20_i2s_debug_open, | |
71f78e22 SW |
96 | .read = seq_read, |
97 | .llseek = seq_lseek, | |
98 | .release = single_release, | |
99 | }; | |
100 | ||
896637ac | 101 | static void tegra20_i2s_debug_add(struct tegra20_i2s *i2s) |
71f78e22 | 102 | { |
d4a2eca7 SW |
103 | i2s->debug = debugfs_create_file(i2s->dai.name, S_IRUGO, |
104 | snd_soc_debugfs_root, i2s, | |
896637ac | 105 | &tegra20_i2s_debug_fops); |
71f78e22 SW |
106 | } |
107 | ||
896637ac | 108 | static void tegra20_i2s_debug_remove(struct tegra20_i2s *i2s) |
71f78e22 SW |
109 | { |
110 | if (i2s->debug) | |
111 | debugfs_remove(i2s->debug); | |
112 | } | |
113 | #else | |
896637ac | 114 | static inline void tegra20_i2s_debug_add(struct tegra20_i2s *i2s, int id) |
71f78e22 SW |
115 | { |
116 | } | |
117 | ||
896637ac | 118 | static inline void tegra20_i2s_debug_remove(struct tegra20_i2s *i2s) |
71f78e22 SW |
119 | { |
120 | } | |
121 | #endif | |
122 | ||
896637ac | 123 | static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai, |
71f78e22 SW |
124 | unsigned int fmt) |
125 | { | |
896637ac | 126 | struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
71f78e22 SW |
127 | |
128 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
129 | case SND_SOC_DAIFMT_NB_NF: | |
130 | break; | |
131 | default: | |
132 | return -EINVAL; | |
133 | } | |
134 | ||
896637ac | 135 | i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_MASTER_ENABLE; |
71f78e22 SW |
136 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
137 | case SND_SOC_DAIFMT_CBS_CFS: | |
896637ac | 138 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_MASTER_ENABLE; |
71f78e22 SW |
139 | break; |
140 | case SND_SOC_DAIFMT_CBM_CFM: | |
141 | break; | |
142 | default: | |
143 | return -EINVAL; | |
144 | } | |
145 | ||
896637ac SW |
146 | i2s->reg_ctrl &= ~(TEGRA20_I2S_CTRL_BIT_FORMAT_MASK | |
147 | TEGRA20_I2S_CTRL_LRCK_MASK); | |
71f78e22 SW |
148 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
149 | case SND_SOC_DAIFMT_DSP_A: | |
896637ac SW |
150 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP; |
151 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW; | |
71f78e22 SW |
152 | break; |
153 | case SND_SOC_DAIFMT_DSP_B: | |
896637ac SW |
154 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP; |
155 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_R_LOW; | |
71f78e22 SW |
156 | break; |
157 | case SND_SOC_DAIFMT_I2S: | |
896637ac SW |
158 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S; |
159 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW; | |
71f78e22 SW |
160 | break; |
161 | case SND_SOC_DAIFMT_RIGHT_J: | |
896637ac SW |
162 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM; |
163 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW; | |
71f78e22 SW |
164 | break; |
165 | case SND_SOC_DAIFMT_LEFT_J: | |
896637ac SW |
166 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM; |
167 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW; | |
71f78e22 SW |
168 | break; |
169 | default: | |
170 | return -EINVAL; | |
171 | } | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
896637ac SW |
176 | static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream, |
177 | struct snd_pcm_hw_params *params, | |
178 | struct snd_soc_dai *dai) | |
71f78e22 | 179 | { |
7deb2b45 | 180 | struct device *dev = substream->pcm->card->dev; |
896637ac | 181 | struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
71f78e22 SW |
182 | u32 reg; |
183 | int ret, sample_size, srate, i2sclock, bitcnt; | |
184 | ||
896637ac | 185 | i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_BIT_SIZE_MASK; |
71f78e22 SW |
186 | switch (params_format(params)) { |
187 | case SNDRV_PCM_FORMAT_S16_LE: | |
896637ac | 188 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_16; |
71f78e22 SW |
189 | sample_size = 16; |
190 | break; | |
191 | case SNDRV_PCM_FORMAT_S24_LE: | |
896637ac | 192 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_24; |
71f78e22 SW |
193 | sample_size = 24; |
194 | break; | |
195 | case SNDRV_PCM_FORMAT_S32_LE: | |
896637ac | 196 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_32; |
71f78e22 SW |
197 | sample_size = 32; |
198 | break; | |
199 | default: | |
200 | return -EINVAL; | |
201 | } | |
202 | ||
203 | srate = params_rate(params); | |
204 | ||
205 | /* Final "* 2" required by Tegra hardware */ | |
206 | i2sclock = srate * params_channels(params) * sample_size * 2; | |
207 | ||
208 | ret = clk_set_rate(i2s->clk_i2s, i2sclock); | |
209 | if (ret) { | |
210 | dev_err(dev, "Can't set I2S clock rate: %d\n", ret); | |
211 | return ret; | |
212 | } | |
213 | ||
214 | bitcnt = (i2sclock / (2 * srate)) - 1; | |
896637ac | 215 | if (bitcnt < 0 || bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US) |
71f78e22 | 216 | return -EINVAL; |
896637ac | 217 | reg = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT; |
71f78e22 SW |
218 | |
219 | if (i2sclock % (2 * srate)) | |
896637ac | 220 | reg |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE; |
71f78e22 | 221 | |
30d436a6 | 222 | clk_enable(i2s->clk_i2s); |
713d1369 | 223 | |
896637ac | 224 | tegra20_i2s_write(i2s, TEGRA20_I2S_TIMING, reg); |
71f78e22 | 225 | |
896637ac SW |
226 | tegra20_i2s_write(i2s, TEGRA20_I2S_FIFO_SCR, |
227 | TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS | | |
228 | TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS); | |
71f78e22 | 229 | |
30d436a6 | 230 | clk_disable(i2s->clk_i2s); |
713d1369 | 231 | |
71f78e22 SW |
232 | return 0; |
233 | } | |
234 | ||
896637ac | 235 | static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s) |
71f78e22 | 236 | { |
896637ac SW |
237 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO1_ENABLE; |
238 | tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl); | |
71f78e22 SW |
239 | } |
240 | ||
896637ac | 241 | static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s) |
71f78e22 | 242 | { |
896637ac SW |
243 | i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO1_ENABLE; |
244 | tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl); | |
71f78e22 SW |
245 | } |
246 | ||
896637ac | 247 | static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s) |
71f78e22 | 248 | { |
896637ac SW |
249 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO2_ENABLE; |
250 | tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl); | |
71f78e22 SW |
251 | } |
252 | ||
896637ac | 253 | static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s) |
71f78e22 | 254 | { |
896637ac SW |
255 | i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO2_ENABLE; |
256 | tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl); | |
71f78e22 SW |
257 | } |
258 | ||
896637ac SW |
259 | static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
260 | struct snd_soc_dai *dai) | |
71f78e22 | 261 | { |
896637ac | 262 | struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
71f78e22 SW |
263 | |
264 | switch (cmd) { | |
265 | case SNDRV_PCM_TRIGGER_START: | |
266 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
267 | case SNDRV_PCM_TRIGGER_RESUME: | |
30d436a6 | 268 | clk_enable(i2s->clk_i2s); |
71f78e22 | 269 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
896637ac | 270 | tegra20_i2s_start_playback(i2s); |
71f78e22 | 271 | else |
896637ac | 272 | tegra20_i2s_start_capture(i2s); |
71f78e22 SW |
273 | break; |
274 | case SNDRV_PCM_TRIGGER_STOP: | |
275 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
276 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
277 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
896637ac | 278 | tegra20_i2s_stop_playback(i2s); |
71f78e22 | 279 | else |
896637ac | 280 | tegra20_i2s_stop_capture(i2s); |
30d436a6 | 281 | clk_disable(i2s->clk_i2s); |
71f78e22 SW |
282 | break; |
283 | default: | |
284 | return -EINVAL; | |
285 | } | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
896637ac | 290 | static int tegra20_i2s_probe(struct snd_soc_dai *dai) |
71f78e22 | 291 | { |
896637ac | 292 | struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
71f78e22 SW |
293 | |
294 | dai->capture_dma_data = &i2s->capture_dma_data; | |
295 | dai->playback_dma_data = &i2s->playback_dma_data; | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
896637ac SW |
300 | static const struct snd_soc_dai_ops tegra20_i2s_dai_ops = { |
301 | .set_fmt = tegra20_i2s_set_fmt, | |
302 | .hw_params = tegra20_i2s_hw_params, | |
303 | .trigger = tegra20_i2s_trigger, | |
71f78e22 SW |
304 | }; |
305 | ||
896637ac SW |
306 | static const struct snd_soc_dai_driver tegra20_i2s_dai_template = { |
307 | .probe = tegra20_i2s_probe, | |
d4a2eca7 SW |
308 | .playback = { |
309 | .channels_min = 2, | |
310 | .channels_max = 2, | |
311 | .rates = SNDRV_PCM_RATE_8000_96000, | |
312 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
71f78e22 | 313 | }, |
d4a2eca7 SW |
314 | .capture = { |
315 | .channels_min = 2, | |
316 | .channels_max = 2, | |
317 | .rates = SNDRV_PCM_RATE_8000_96000, | |
318 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
71f78e22 | 319 | }, |
896637ac | 320 | .ops = &tegra20_i2s_dai_ops, |
d4a2eca7 | 321 | .symmetric_rates = 1, |
71f78e22 SW |
322 | }; |
323 | ||
896637ac | 324 | static __devinit int tegra20_i2s_platform_probe(struct platform_device *pdev) |
71f78e22 | 325 | { |
896637ac | 326 | struct tegra20_i2s *i2s; |
71f78e22 | 327 | struct resource *mem, *memregion, *dmareq; |
bf55499e SW |
328 | u32 of_dma[2]; |
329 | u32 dma_ch; | |
71f78e22 SW |
330 | int ret; |
331 | ||
896637ac | 332 | i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL); |
71f78e22 | 333 | if (!i2s) { |
896637ac | 334 | dev_err(&pdev->dev, "Can't allocate tegra20_i2s\n"); |
71f78e22 | 335 | ret = -ENOMEM; |
bea0ed08 | 336 | goto err; |
71f78e22 SW |
337 | } |
338 | dev_set_drvdata(&pdev->dev, i2s); | |
339 | ||
896637ac | 340 | i2s->dai = tegra20_i2s_dai_template; |
d4a2eca7 SW |
341 | i2s->dai.name = dev_name(&pdev->dev); |
342 | ||
b5f9cfed | 343 | i2s->clk_i2s = clk_get(&pdev->dev, NULL); |
422650e6 | 344 | if (IS_ERR(i2s->clk_i2s)) { |
713dce4e | 345 | dev_err(&pdev->dev, "Can't retrieve i2s clock\n"); |
71f78e22 | 346 | ret = PTR_ERR(i2s->clk_i2s); |
bea0ed08 | 347 | goto err; |
71f78e22 SW |
348 | } |
349 | ||
350 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
351 | if (!mem) { | |
352 | dev_err(&pdev->dev, "No memory resource\n"); | |
353 | ret = -ENODEV; | |
354 | goto err_clk_put; | |
355 | } | |
356 | ||
357 | dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
358 | if (!dmareq) { | |
bf55499e SW |
359 | if (of_property_read_u32_array(pdev->dev.of_node, |
360 | "nvidia,dma-request-selector", | |
361 | of_dma, 2) < 0) { | |
362 | dev_err(&pdev->dev, "No DMA resource\n"); | |
363 | ret = -ENODEV; | |
364 | goto err_clk_put; | |
365 | } | |
366 | dma_ch = of_dma[1]; | |
367 | } else { | |
368 | dma_ch = dmareq->start; | |
71f78e22 SW |
369 | } |
370 | ||
bea0ed08 SW |
371 | memregion = devm_request_mem_region(&pdev->dev, mem->start, |
372 | resource_size(mem), DRV_NAME); | |
71f78e22 SW |
373 | if (!memregion) { |
374 | dev_err(&pdev->dev, "Memory region already claimed\n"); | |
375 | ret = -EBUSY; | |
376 | goto err_clk_put; | |
377 | } | |
378 | ||
bea0ed08 | 379 | i2s->regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
71f78e22 SW |
380 | if (!i2s->regs) { |
381 | dev_err(&pdev->dev, "ioremap failed\n"); | |
382 | ret = -ENOMEM; | |
bea0ed08 | 383 | goto err_clk_put; |
71f78e22 SW |
384 | } |
385 | ||
896637ac | 386 | i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2; |
71f78e22 SW |
387 | i2s->capture_dma_data.wrap = 4; |
388 | i2s->capture_dma_data.width = 32; | |
bf55499e | 389 | i2s->capture_dma_data.req_sel = dma_ch; |
71f78e22 | 390 | |
896637ac | 391 | i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1; |
71f78e22 SW |
392 | i2s->playback_dma_data.wrap = 4; |
393 | i2s->playback_dma_data.width = 32; | |
bf55499e | 394 | i2s->playback_dma_data.req_sel = dma_ch; |
71f78e22 | 395 | |
896637ac | 396 | i2s->reg_ctrl = TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED; |
71f78e22 | 397 | |
d4a2eca7 | 398 | ret = snd_soc_register_dai(&pdev->dev, &i2s->dai); |
71f78e22 SW |
399 | if (ret) { |
400 | dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); | |
401 | ret = -ENOMEM; | |
bea0ed08 | 402 | goto err_clk_put; |
71f78e22 SW |
403 | } |
404 | ||
518de86b SW |
405 | ret = tegra_pcm_platform_register(&pdev->dev); |
406 | if (ret) { | |
407 | dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); | |
408 | goto err_unregister_dai; | |
409 | } | |
410 | ||
896637ac | 411 | tegra20_i2s_debug_add(i2s); |
71f78e22 SW |
412 | |
413 | return 0; | |
414 | ||
518de86b SW |
415 | err_unregister_dai: |
416 | snd_soc_unregister_dai(&pdev->dev); | |
71f78e22 SW |
417 | err_clk_put: |
418 | clk_put(i2s->clk_i2s); | |
bea0ed08 | 419 | err: |
71f78e22 SW |
420 | return ret; |
421 | } | |
422 | ||
896637ac | 423 | static int __devexit tegra20_i2s_platform_remove(struct platform_device *pdev) |
71f78e22 | 424 | { |
896637ac | 425 | struct tegra20_i2s *i2s = dev_get_drvdata(&pdev->dev); |
71f78e22 | 426 | |
518de86b | 427 | tegra_pcm_platform_unregister(&pdev->dev); |
71f78e22 SW |
428 | snd_soc_unregister_dai(&pdev->dev); |
429 | ||
896637ac | 430 | tegra20_i2s_debug_remove(i2s); |
71f78e22 | 431 | |
71f78e22 SW |
432 | clk_put(i2s->clk_i2s); |
433 | ||
71f78e22 SW |
434 | return 0; |
435 | } | |
436 | ||
896637ac | 437 | static const struct of_device_id tegra20_i2s_of_match[] __devinitconst = { |
bf55499e SW |
438 | { .compatible = "nvidia,tegra20-i2s", }, |
439 | {}, | |
440 | }; | |
441 | ||
896637ac | 442 | static struct platform_driver tegra20_i2s_driver = { |
71f78e22 SW |
443 | .driver = { |
444 | .name = DRV_NAME, | |
445 | .owner = THIS_MODULE, | |
896637ac | 446 | .of_match_table = tegra20_i2s_of_match, |
71f78e22 | 447 | }, |
896637ac SW |
448 | .probe = tegra20_i2s_platform_probe, |
449 | .remove = __devexit_p(tegra20_i2s_platform_remove), | |
71f78e22 | 450 | }; |
896637ac | 451 | module_platform_driver(tegra20_i2s_driver); |
71f78e22 SW |
452 | |
453 | MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); | |
896637ac | 454 | MODULE_DESCRIPTION("Tegra20 I2S ASoC driver"); |
71f78e22 | 455 | MODULE_LICENSE("GPL"); |
8eb34207 | 456 | MODULE_ALIAS("platform:" DRV_NAME); |
896637ac | 457 | MODULE_DEVICE_TABLE(of, tegra20_i2s_of_match); |