[deliverable/linux.git] / sound / soc / tegra / tegra20_i2s.c

/*
 * tegra20_i2s.c - Tegra20 I2S driver
 *
 * Author: Stephen Warren <swarren@nvidia.com>
 * Copyright (C) 2010,2012 - NVIDIA, Inc.
 *
 * Based on code copyright/by:
 *
 * Copyright (c) 2009-2010, NVIDIA Corporation.
 * Scott Peterson <speterson@nvidia.com>
 *
 * Copyright (C) 2010 Google, Inc.
 * Iliyan Malchev <malchev@google.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include "tegra20_i2s.h"

#define DRV_NAME "tegra20-i2s"

static inline void tegra20_i2s_write(struct tegra20_i2s *i2s, u32 reg, u32 val)
{
	regmap_write(i2s->regmap, reg, val);
}

static inline u32 tegra20_i2s_read(struct tegra20_i2s *i2s, u32 reg)
{
	u32 val;
	regmap_read(i2s->regmap, reg, &val);
	return val;
}

static int tegra20_i2s_runtime_suspend(struct device *dev)
{
	struct tegra20_i2s *i2s = dev_get_drvdata(dev);

	clk_disable_unprepare(i2s->clk_i2s);

	return 0;
}

static int tegra20_i2s_runtime_resume(struct device *dev)
{
	struct tegra20_i2s *i2s = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(i2s->clk_i2s);
	if (ret) {
		dev_err(dev, "clk_enable failed: %d\n", ret);
		return ret;
	}

	return 0;
}

static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai,
				unsigned int fmt)
{
	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		break;
	default:
		return -EINVAL;
	}

	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_MASTER_ENABLE;
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_MASTER_ENABLE;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		break;
	default:
		return -EINVAL;
	}

	i2s->reg_ctrl &= ~(TEGRA20_I2S_CTRL_BIT_FORMAT_MASK |
			   TEGRA20_I2S_CTRL_LRCK_MASK);
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_DSP_A:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_DSP_B:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_R_LOW;
		break;
	case SND_SOC_DAIFMT_I2S:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S;
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM;
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM;
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct device *dev = substream->pcm->card->dev;
	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	u32 reg;
	int ret, sample_size, srate, i2sclock, bitcnt;

	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_BIT_SIZE_MASK;
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_16;
		sample_size = 16;
		break;
	case SNDRV_PCM_FORMAT_S24_LE:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_24;
		sample_size = 24;
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_32;
		sample_size = 32;
		break;
	default:
		return -EINVAL;
	}

	srate = params_rate(params);

	/* Final "* 2" required by Tegra hardware */
	i2sclock = srate * params_channels(params) * sample_size * 2;

	ret = clk_set_rate(i2s->clk_i2s, i2sclock);
	if (ret) {
		dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
		return ret;
	}

	bitcnt = (i2sclock / (2 * srate)) - 1;
	if (bitcnt < 0 || bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
		return -EINVAL;
	reg = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;

	if (i2sclock % (2 * srate))
		reg |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE;

	tegra20_i2s_write(i2s, TEGRA20_I2S_TIMING, reg);

	tegra20_i2s_write(i2s, TEGRA20_I2S_FIFO_SCR,
		TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
		TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);

	return 0;
}

static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s)
{
	i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO1_ENABLE;
	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
}

static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s)
{
	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO1_ENABLE;
	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
}

static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s)
{
	i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO2_ENABLE;
	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
}

static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s)
{
	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO2_ENABLE;
	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
}

static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_RESUME:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra20_i2s_start_playback(i2s);
		else
			tegra20_i2s_start_capture(i2s);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	case SNDRV_PCM_TRIGGER_SUSPEND:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra20_i2s_stop_playback(i2s);
		else
			tegra20_i2s_stop_capture(i2s);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int tegra20_i2s_probe(struct snd_soc_dai *dai)
{
	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	dai->capture_dma_data = &i2s->capture_dma_data;
	dai->playback_dma_data = &i2s->playback_dma_data;

	return 0;
}

static const struct snd_soc_dai_ops tegra20_i2s_dai_ops = {
	.set_fmt	= tegra20_i2s_set_fmt,
	.hw_params	= tegra20_i2s_hw_params,
	.trigger	= tegra20_i2s_trigger,
};

static const struct snd_soc_dai_driver tegra20_i2s_dai_template = {
	.probe = tegra20_i2s_probe,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops = &tegra20_i2s_dai_ops,
	.symmetric_rates = 1,
};

static bool tegra20_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA20_I2S_CTRL:
	case TEGRA20_I2S_STATUS:
	case TEGRA20_I2S_TIMING:
	case TEGRA20_I2S_FIFO_SCR:
	case TEGRA20_I2S_PCM_CTRL:
	case TEGRA20_I2S_NW_CTRL:
	case TEGRA20_I2S_TDM_CTRL:
	case TEGRA20_I2S_TDM_TX_RX_CTRL:
	case TEGRA20_I2S_FIFO1:
	case TEGRA20_I2S_FIFO2:
		return true;
	default:
		return false;
	};
}

static bool tegra20_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA20_I2S_STATUS:
	case TEGRA20_I2S_FIFO_SCR:
	case TEGRA20_I2S_FIFO1:
	case TEGRA20_I2S_FIFO2:
		return true;
	default:
		return false;
	};
}

static bool tegra20_i2s_precious_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA20_I2S_FIFO1:
	case TEGRA20_I2S_FIFO2:
		return true;
	default:
		return false;
	};
}

static const struct regmap_config tegra20_i2s_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = TEGRA20_I2S_FIFO2,
	.writeable_reg = tegra20_i2s_wr_rd_reg,
	.readable_reg = tegra20_i2s_wr_rd_reg,
	.volatile_reg = tegra20_i2s_volatile_reg,
	.precious_reg = tegra20_i2s_precious_reg,
	.cache_type = REGCACHE_RBTREE,
};

static __devinit int tegra20_i2s_platform_probe(struct platform_device *pdev)
{
	struct tegra20_i2s *i2s;
	struct resource *mem, *memregion, *dmareq;
	u32 of_dma[2];
	u32 dma_ch;
	void __iomem *regs;
	int ret;

	i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL);
	if (!i2s) {
		dev_err(&pdev->dev, "Can't allocate tegra20_i2s\n");
		ret = -ENOMEM;
		goto err;
	}
	dev_set_drvdata(&pdev->dev, i2s);

	i2s->dai = tegra20_i2s_dai_template;
	i2s->dai.name = dev_name(&pdev->dev);

	i2s->clk_i2s = clk_get(&pdev->dev, NULL);
	if (IS_ERR(i2s->clk_i2s)) {
		dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
		ret = PTR_ERR(i2s->clk_i2s);
		goto err;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "No memory resource\n");
		ret = -ENODEV;
		goto err_clk_put;
	}

	dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	if (!dmareq) {
		if (of_property_read_u32_array(pdev->dev.of_node,
					"nvidia,dma-request-selector",
					of_dma, 2) < 0) {
			dev_err(&pdev->dev, "No DMA resource\n");
			ret = -ENODEV;
			goto err_clk_put;
		}
		dma_ch = of_dma[1];
	} else {
		dma_ch = dmareq->start;
	}

	memregion = devm_request_mem_region(&pdev->dev, mem->start,
					    resource_size(mem), DRV_NAME);
	if (!memregion) {
		dev_err(&pdev->dev, "Memory region already claimed\n");
		ret = -EBUSY;
		goto err_clk_put;
	}

	regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
	if (!regs) {
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -ENOMEM;
		goto err_clk_put;
	}

	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
					    &tegra20_i2s_regmap_config);
	if (IS_ERR(i2s->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		ret = PTR_ERR(i2s->regmap);
		goto err_clk_put;
	}

	i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
	i2s->capture_dma_data.wrap = 4;
	i2s->capture_dma_data.width = 32;
	i2s->capture_dma_data.req_sel = dma_ch;

	i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
	i2s->playback_dma_data.wrap = 4;
	i2s->playback_dma_data.width = 32;
	i2s->playback_dma_data.req_sel = dma_ch;

	i2s->reg_ctrl = TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED;

	pm_runtime_enable(&pdev->dev);
	if (!pm_runtime_enabled(&pdev->dev)) {
		ret = tegra20_i2s_runtime_resume(&pdev->dev);
		if (ret)
			goto err_pm_disable;
	}

	ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
	if (ret) {
		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
		ret = -ENOMEM;
		goto err_suspend;
	}

	ret = tegra_pcm_platform_register(&pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
		goto err_unregister_dai;
	}

	return 0;

err_unregister_dai:
	snd_soc_unregister_dai(&pdev->dev);
err_suspend:
	if (!pm_runtime_status_suspended(&pdev->dev))
		tegra20_i2s_runtime_suspend(&pdev->dev);
err_pm_disable:
	pm_runtime_disable(&pdev->dev);
err_clk_put:
	clk_put(i2s->clk_i2s);
err:
	return ret;
}

static int __devexit tegra20_i2s_platform_remove(struct platform_device *pdev)
{
	struct tegra20_i2s *i2s = dev_get_drvdata(&pdev->dev);

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		tegra20_i2s_runtime_suspend(&pdev->dev);

	tegra_pcm_platform_unregister(&pdev->dev);
	snd_soc_unregister_dai(&pdev->dev);

	clk_put(i2s->clk_i2s);

	return 0;
}

static const struct of_device_id tegra20_i2s_of_match[] __devinitconst = {
	{ .compatible = "nvidia,tegra20-i2s", },
	{},
};

static const struct dev_pm_ops tegra20_i2s_pm_ops __devinitconst = {
	SET_RUNTIME_PM_OPS(tegra20_i2s_runtime_suspend,
			   tegra20_i2s_runtime_resume, NULL)
};

static struct platform_driver tegra20_i2s_driver = {
	.driver = {
		.name = DRV_NAME,
		.owner = THIS_MODULE,
		.of_match_table = tegra20_i2s_of_match,
		.pm = &tegra20_i2s_pm_ops,
	},
	.probe = tegra20_i2s_platform_probe,
	.remove = __devexit_p(tegra20_i2s_platform_remove),
};
module_platform_driver(tegra20_i2s_driver);

MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
MODULE_DESCRIPTION("Tegra20 I2S ASoC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra20_i2s_of_match);
Commit	Line	Data
71f78e22	1	/*
ef280d39	2	* tegra20_i2s.c - Tegra20 I2S driver
71f78e22 SW	3	*
71f78e22 SW	4	* Author: Stephen Warren <swarren@nvidia.com>
518de86b	5	* Copyright (C) 2010,2012 - NVIDIA, Inc.
71f78e22 SW	6	*
	7	* Based on code copyright/by:
	8	*
	9	* Copyright (c) 2009-2010, NVIDIA Corporation.
	10	* Scott Peterson <speterson@nvidia.com>
	11	*
	12	* Copyright (C) 2010 Google, Inc.
	13	* Iliyan Malchev <malchev@google.com>
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* version 2 as published by the Free Software Foundation.
	18	*
	19	* This program is distributed in the hope that it will be useful, but
	20	* WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	22	* General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	27	* 02110-1301 USA
	28	*
	29	*/
	30
	31	#include <linux/clk.h>
71f78e22	32	#include <linux/device.h>
7613c508 SW	33	#include <linux/io.h>
	34	#include <linux/module.h>
	35	#include <linux/of.h>
71f78e22	36	#include <linux/platform_device.h>
82ef0ae4	37	#include <linux/pm_runtime.h>
c1607416	38	#include <linux/regmap.h>
71f78e22	39	#include <linux/slab.h>
71f78e22 SW	40	#include <sound/core.h>
	41	#include <sound/pcm.h>
	42	#include <sound/pcm_params.h>
	43	#include <sound/soc.h>
	44
ef280d39	45	#include "tegra20_i2s.h"
71f78e22	46
896637ac	47	#define DRV_NAME "tegra20-i2s"
71f78e22	48
896637ac	49	static inline void tegra20_i2s_write(struct tegra20_i2s *i2s, u32 reg, u32 val)
71f78e22	50	{
c1607416	51	regmap_write(i2s->regmap, reg, val);
71f78e22 SW	52	}
71f78e22 SW	53
896637ac	54	static inline u32 tegra20_i2s_read(struct tegra20_i2s *i2s, u32 reg)
71f78e22	55	{
c1607416 SW	56	u32 val;
	57	regmap_read(i2s->regmap, reg, &val);
	58	return val;
71f78e22 SW	59	}
71f78e22 SW	60
82ef0ae4 SW	61	static int tegra20_i2s_runtime_suspend(struct device *dev)
	62	{
	63	struct tegra20_i2s *i2s = dev_get_drvdata(dev);
	64
65d2bdd3	65	clk_disable_unprepare(i2s->clk_i2s);
82ef0ae4 SW	66
	67	return 0;
	68	}
	69
	70	static int tegra20_i2s_runtime_resume(struct device *dev)
	71	{
	72	struct tegra20_i2s *i2s = dev_get_drvdata(dev);
	73	int ret;
	74
65d2bdd3	75	ret = clk_prepare_enable(i2s->clk_i2s);
82ef0ae4 SW	76	if (ret) {
	77	dev_err(dev, "clk_enable failed: %d\n", ret);
	78	return ret;
	79	}
	80
	81	return 0;
	82	}
	83
896637ac	84	static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai,
71f78e22 SW	85	unsigned int fmt)
71f78e22 SW	86	{
896637ac	87	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
71f78e22 SW	88
	89	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	90	case SND_SOC_DAIFMT_NB_NF:
	91	break;
	92	default:
	93	return -EINVAL;
	94	}
	95
896637ac	96	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_MASTER_ENABLE;
71f78e22 SW	97	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
71f78e22 SW	98	case SND_SOC_DAIFMT_CBS_CFS:
896637ac	99	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_MASTER_ENABLE;
71f78e22 SW	100	break;
	101	case SND_SOC_DAIFMT_CBM_CFM:
	102	break;
	103	default:
	104	return -EINVAL;
	105	}
	106
896637ac SW	107	i2s->reg_ctrl &= ~(TEGRA20_I2S_CTRL_BIT_FORMAT_MASK \|
896637ac SW	108	TEGRA20_I2S_CTRL_LRCK_MASK);
71f78e22 SW	109	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
71f78e22 SW	110	case SND_SOC_DAIFMT_DSP_A:
896637ac SW	111	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
896637ac SW	112	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_LRCK_L_LOW;
71f78e22 SW	113	break;
71f78e22 SW	114	case SND_SOC_DAIFMT_DSP_B:
896637ac SW	115	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
896637ac SW	116	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_LRCK_R_LOW;
71f78e22 SW	117	break;
71f78e22 SW	118	case SND_SOC_DAIFMT_I2S:
896637ac SW	119	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S;
896637ac SW	120	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_LRCK_L_LOW;
71f78e22 SW	121	break;
71f78e22 SW	122	case SND_SOC_DAIFMT_RIGHT_J:
896637ac SW	123	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM;
896637ac SW	124	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_LRCK_L_LOW;
71f78e22 SW	125	break;
71f78e22 SW	126	case SND_SOC_DAIFMT_LEFT_J:
896637ac SW	127	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM;
896637ac SW	128	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_LRCK_L_LOW;
71f78e22 SW	129	break;
	130	default:
	131	return -EINVAL;
	132	}
	133
	134	return 0;
	135	}
	136
896637ac SW	137	static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream,
	138	struct snd_pcm_hw_params *params,
	139	struct snd_soc_dai *dai)
71f78e22	140	{
7deb2b45	141	struct device *dev = substream->pcm->card->dev;
896637ac	142	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
71f78e22 SW	143	u32 reg;
	144	int ret, sample_size, srate, i2sclock, bitcnt;
	145
896637ac	146	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_BIT_SIZE_MASK;
71f78e22 SW	147	switch (params_format(params)) {
71f78e22 SW	148	case SNDRV_PCM_FORMAT_S16_LE:
896637ac	149	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_SIZE_16;
71f78e22 SW	150	sample_size = 16;
	151	break;
	152	case SNDRV_PCM_FORMAT_S24_LE:
896637ac	153	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_SIZE_24;
71f78e22 SW	154	sample_size = 24;
	155	break;
	156	case SNDRV_PCM_FORMAT_S32_LE:
896637ac	157	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_SIZE_32;
71f78e22 SW	158	sample_size = 32;
	159	break;
	160	default:
	161	return -EINVAL;
	162	}
	163
	164	srate = params_rate(params);
	165
	166	/* Final "* 2" required by Tegra hardware */
	167	i2sclock = srate * params_channels(params) * sample_size * 2;
	168
	169	ret = clk_set_rate(i2s->clk_i2s, i2sclock);
	170	if (ret) {
	171	dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
	172	return ret;
	173	}
	174
	175	bitcnt = (i2sclock / (2 * srate)) - 1;
896637ac	176	if (bitcnt < 0 \|\| bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
71f78e22	177	return -EINVAL;
896637ac	178	reg = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
71f78e22 SW	179
71f78e22 SW	180	if (i2sclock % (2 * srate))
896637ac	181	reg \|= TEGRA20_I2S_TIMING_NON_SYM_ENABLE;
71f78e22	182
896637ac	183	tegra20_i2s_write(i2s, TEGRA20_I2S_TIMING, reg);
71f78e22	184
896637ac SW	185	tegra20_i2s_write(i2s, TEGRA20_I2S_FIFO_SCR,
	186	TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS \|
	187	TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
71f78e22 SW	188
	189	return 0;
	190	}
	191
896637ac	192	static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s)
71f78e22	193	{
896637ac SW	194	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_FIFO1_ENABLE;
896637ac SW	195	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
71f78e22 SW	196	}
71f78e22 SW	197
896637ac	198	static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s)
71f78e22	199	{
896637ac SW	200	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO1_ENABLE;
896637ac SW	201	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
71f78e22 SW	202	}
71f78e22 SW	203
896637ac	204	static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s)
71f78e22	205	{
896637ac SW	206	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_FIFO2_ENABLE;
896637ac SW	207	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
71f78e22 SW	208	}
71f78e22 SW	209
896637ac	210	static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s)
71f78e22	211	{
896637ac SW	212	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO2_ENABLE;
896637ac SW	213	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
71f78e22 SW	214	}
71f78e22 SW	215
896637ac SW	216	static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
896637ac SW	217	struct snd_soc_dai *dai)
71f78e22	218	{
896637ac	219	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
71f78e22 SW	220
	221	switch (cmd) {
	222	case SNDRV_PCM_TRIGGER_START:
	223	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	224	case SNDRV_PCM_TRIGGER_RESUME:
71f78e22	225	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
896637ac	226	tegra20_i2s_start_playback(i2s);
71f78e22	227	else
896637ac	228	tegra20_i2s_start_capture(i2s);
71f78e22 SW	229	break;
	230	case SNDRV_PCM_TRIGGER_STOP:
	231	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	232	case SNDRV_PCM_TRIGGER_SUSPEND:
	233	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
896637ac	234	tegra20_i2s_stop_playback(i2s);
71f78e22	235	else
896637ac	236	tegra20_i2s_stop_capture(i2s);
71f78e22 SW	237	break;
	238	default:
	239	return -EINVAL;
	240	}
	241
	242	return 0;
	243	}
	244
896637ac	245	static int tegra20_i2s_probe(struct snd_soc_dai *dai)
71f78e22	246	{
896637ac	247	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
71f78e22 SW	248
	249	dai->capture_dma_data = &i2s->capture_dma_data;
	250	dai->playback_dma_data = &i2s->playback_dma_data;
	251
	252	return 0;
	253	}
	254
896637ac SW	255	static const struct snd_soc_dai_ops tegra20_i2s_dai_ops = {
	256	.set_fmt = tegra20_i2s_set_fmt,
	257	.hw_params = tegra20_i2s_hw_params,
	258	.trigger = tegra20_i2s_trigger,
71f78e22 SW	259	};
71f78e22 SW	260
896637ac SW	261	static const struct snd_soc_dai_driver tegra20_i2s_dai_template = {
896637ac SW	262	.probe = tegra20_i2s_probe,
d4a2eca7 SW	263	.playback = {
	264	.channels_min = 2,
	265	.channels_max = 2,
	266	.rates = SNDRV_PCM_RATE_8000_96000,
	267	.formats = SNDRV_PCM_FMTBIT_S16_LE,
71f78e22	268	},
d4a2eca7 SW	269	.capture = {
	270	.channels_min = 2,
	271	.channels_max = 2,
	272	.rates = SNDRV_PCM_RATE_8000_96000,
	273	.formats = SNDRV_PCM_FMTBIT_S16_LE,
71f78e22	274	},
896637ac	275	.ops = &tegra20_i2s_dai_ops,
d4a2eca7	276	.symmetric_rates = 1,
71f78e22 SW	277	};
71f78e22 SW	278
c1607416 SW	279	static bool tegra20_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
	280	{
	281	switch (reg) {
	282	case TEGRA20_I2S_CTRL:
	283	case TEGRA20_I2S_STATUS:
	284	case TEGRA20_I2S_TIMING:
	285	case TEGRA20_I2S_FIFO_SCR:
	286	case TEGRA20_I2S_PCM_CTRL:
	287	case TEGRA20_I2S_NW_CTRL:
	288	case TEGRA20_I2S_TDM_CTRL:
	289	case TEGRA20_I2S_TDM_TX_RX_CTRL:
	290	case TEGRA20_I2S_FIFO1:
	291	case TEGRA20_I2S_FIFO2:
	292	return true;
	293	default:
	294	return false;
	295	};
	296	}
	297
	298	static bool tegra20_i2s_volatile_reg(struct device *dev, unsigned int reg)
	299	{
	300	switch (reg) {
	301	case TEGRA20_I2S_STATUS:
	302	case TEGRA20_I2S_FIFO_SCR:
	303	case TEGRA20_I2S_FIFO1:
	304	case TEGRA20_I2S_FIFO2:
	305	return true;
	306	default:
	307	return false;
	308	};
	309	}
	310
	311	static bool tegra20_i2s_precious_reg(struct device *dev, unsigned int reg)
	312	{
	313	switch (reg) {
	314	case TEGRA20_I2S_FIFO1:
	315	case TEGRA20_I2S_FIFO2:
	316	return true;
	317	default:
	318	return false;
	319	};
	320	}
	321
	322	static const struct regmap_config tegra20_i2s_regmap_config = {
	323	.reg_bits = 32,
	324	.reg_stride = 4,
	325	.val_bits = 32,
	326	.max_register = TEGRA20_I2S_FIFO2,
	327	.writeable_reg = tegra20_i2s_wr_rd_reg,
	328	.readable_reg = tegra20_i2s_wr_rd_reg,
	329	.volatile_reg = tegra20_i2s_volatile_reg,
	330	.precious_reg = tegra20_i2s_precious_reg,
	331	.cache_type = REGCACHE_RBTREE,
	332	};
	333
896637ac	334	static __devinit int tegra20_i2s_platform_probe(struct platform_device *pdev)
71f78e22	335	{
896637ac	336	struct tegra20_i2s *i2s;
71f78e22	337	struct resource mem, memregion, *dmareq;
bf55499e SW	338	u32 of_dma[2];
bf55499e SW	339	u32 dma_ch;
c1607416	340	void __iomem *regs;
71f78e22 SW	341	int ret;
71f78e22 SW	342
896637ac	343	i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL);
71f78e22	344	if (!i2s) {
896637ac	345	dev_err(&pdev->dev, "Can't allocate tegra20_i2s\n");
71f78e22	346	ret = -ENOMEM;
bea0ed08	347	goto err;
71f78e22 SW	348	}
	349	dev_set_drvdata(&pdev->dev, i2s);
	350
896637ac	351	i2s->dai = tegra20_i2s_dai_template;
d4a2eca7 SW	352	i2s->dai.name = dev_name(&pdev->dev);
d4a2eca7 SW	353
b5f9cfed	354	i2s->clk_i2s = clk_get(&pdev->dev, NULL);
422650e6	355	if (IS_ERR(i2s->clk_i2s)) {
713dce4e	356	dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
71f78e22	357	ret = PTR_ERR(i2s->clk_i2s);
bea0ed08	358	goto err;
71f78e22 SW	359	}
	360
	361	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	362	if (!mem) {
	363	dev_err(&pdev->dev, "No memory resource\n");
	364	ret = -ENODEV;
	365	goto err_clk_put;
	366	}
	367
	368	dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	369	if (!dmareq) {
bf55499e SW	370	if (of_property_read_u32_array(pdev->dev.of_node,
	371	"nvidia,dma-request-selector",
	372	of_dma, 2) < 0) {
	373	dev_err(&pdev->dev, "No DMA resource\n");
	374	ret = -ENODEV;
	375	goto err_clk_put;
	376	}
	377	dma_ch = of_dma[1];
	378	} else {
	379	dma_ch = dmareq->start;
71f78e22 SW	380	}
71f78e22 SW	381
bea0ed08 SW	382	memregion = devm_request_mem_region(&pdev->dev, mem->start,
bea0ed08 SW	383	resource_size(mem), DRV_NAME);
71f78e22 SW	384	if (!memregion) {
	385	dev_err(&pdev->dev, "Memory region already claimed\n");
	386	ret = -EBUSY;
	387	goto err_clk_put;
	388	}
	389
c1607416 SW	390	regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
c1607416 SW	391	if (!regs) {
71f78e22 SW	392	dev_err(&pdev->dev, "ioremap failed\n");
71f78e22 SW	393	ret = -ENOMEM;
bea0ed08	394	goto err_clk_put;
71f78e22 SW	395	}
71f78e22 SW	396
c1607416 SW	397	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
	398	&tegra20_i2s_regmap_config);
	399	if (IS_ERR(i2s->regmap)) {
	400	dev_err(&pdev->dev, "regmap init failed\n");
	401	ret = PTR_ERR(i2s->regmap);
	402	goto err_clk_put;
	403	}
	404
896637ac	405	i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
71f78e22 SW	406	i2s->capture_dma_data.wrap = 4;
71f78e22 SW	407	i2s->capture_dma_data.width = 32;
bf55499e	408	i2s->capture_dma_data.req_sel = dma_ch;
71f78e22	409
896637ac	410	i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
71f78e22 SW	411	i2s->playback_dma_data.wrap = 4;
71f78e22 SW	412	i2s->playback_dma_data.width = 32;
bf55499e	413	i2s->playback_dma_data.req_sel = dma_ch;
71f78e22	414
896637ac	415	i2s->reg_ctrl = TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED;
71f78e22	416
82ef0ae4 SW	417	pm_runtime_enable(&pdev->dev);
	418	if (!pm_runtime_enabled(&pdev->dev)) {
	419	ret = tegra20_i2s_runtime_resume(&pdev->dev);
	420	if (ret)
	421	goto err_pm_disable;
	422	}
	423
d4a2eca7	424	ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
71f78e22 SW	425	if (ret) {
	426	dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
	427	ret = -ENOMEM;
82ef0ae4	428	goto err_suspend;
71f78e22 SW	429	}
71f78e22 SW	430
518de86b SW	431	ret = tegra_pcm_platform_register(&pdev->dev);
	432	if (ret) {
	433	dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
	434	goto err_unregister_dai;
	435	}
	436
71f78e22 SW	437	return 0;
71f78e22 SW	438
518de86b SW	439	err_unregister_dai:
518de86b SW	440	snd_soc_unregister_dai(&pdev->dev);
82ef0ae4 SW	441	err_suspend:
	442	if (!pm_runtime_status_suspended(&pdev->dev))
	443	tegra20_i2s_runtime_suspend(&pdev->dev);
	444	err_pm_disable:
	445	pm_runtime_disable(&pdev->dev);
71f78e22 SW	446	err_clk_put:
71f78e22 SW	447	clk_put(i2s->clk_i2s);
bea0ed08	448	err:
71f78e22 SW	449	return ret;
	450	}
	451
896637ac	452	static int __devexit tegra20_i2s_platform_remove(struct platform_device *pdev)
71f78e22	453	{
896637ac	454	struct tegra20_i2s *i2s = dev_get_drvdata(&pdev->dev);
71f78e22	455
82ef0ae4 SW	456	pm_runtime_disable(&pdev->dev);
	457	if (!pm_runtime_status_suspended(&pdev->dev))
	458	tegra20_i2s_runtime_suspend(&pdev->dev);
	459
518de86b	460	tegra_pcm_platform_unregister(&pdev->dev);
71f78e22 SW	461	snd_soc_unregister_dai(&pdev->dev);
71f78e22 SW	462
71f78e22 SW	463	clk_put(i2s->clk_i2s);
71f78e22 SW	464
71f78e22 SW	465	return 0;
	466	}
	467
896637ac	468	static const struct of_device_id tegra20_i2s_of_match[] __devinitconst = {
bf55499e SW	469	{ .compatible = "nvidia,tegra20-i2s", },
	470	{},
	471	};
	472
82ef0ae4 SW	473	static const struct dev_pm_ops tegra20_i2s_pm_ops __devinitconst = {
	474	SET_RUNTIME_PM_OPS(tegra20_i2s_runtime_suspend,
	475	tegra20_i2s_runtime_resume, NULL)
	476	};
	477
896637ac	478	static struct platform_driver tegra20_i2s_driver = {
71f78e22 SW	479	.driver = {
	480	.name = DRV_NAME,
	481	.owner = THIS_MODULE,
896637ac	482	.of_match_table = tegra20_i2s_of_match,
82ef0ae4	483	.pm = &tegra20_i2s_pm_ops,
71f78e22	484	},
896637ac SW	485	.probe = tegra20_i2s_platform_probe,
896637ac SW	486	.remove = __devexit_p(tegra20_i2s_platform_remove),
71f78e22	487	};
896637ac	488	module_platform_driver(tegra20_i2s_driver);
71f78e22 SW	489
71f78e22 SW	490	MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
896637ac	491	MODULE_DESCRIPTION("Tegra20 I2S ASoC driver");
71f78e22	492	MODULE_LICENSE("GPL");
8eb34207	493	MODULE_ALIAS("platform:" DRV_NAME);
896637ac	494	MODULE_DEVICE_TABLE(of, tegra20_i2s_of_match);