Commit | Line | Data |
---|---|---|
71f78e22 | 1 | /* |
ef280d39 | 2 | * tegra20_i2s.c - Tegra20 I2S driver |
71f78e22 SW |
3 | * |
4 | * Author: Stephen Warren <swarren@nvidia.com> | |
518de86b | 5 | * Copyright (C) 2010,2012 - NVIDIA, Inc. |
71f78e22 SW |
6 | * |
7 | * Based on code copyright/by: | |
8 | * | |
9 | * Copyright (c) 2009-2010, NVIDIA Corporation. | |
10 | * Scott Peterson <speterson@nvidia.com> | |
11 | * | |
12 | * Copyright (C) 2010 Google, Inc. | |
13 | * Iliyan Malchev <malchev@google.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * version 2 as published by the Free Software Foundation. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
27 | * 02110-1301 USA | |
28 | * | |
29 | */ | |
30 | ||
31 | #include <linux/clk.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/debugfs.h> | |
34 | #include <linux/device.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/seq_file.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/io.h> | |
bf55499e | 39 | #include <linux/of.h> |
71f78e22 SW |
40 | #include <mach/iomap.h> |
41 | #include <sound/core.h> | |
42 | #include <sound/pcm.h> | |
43 | #include <sound/pcm_params.h> | |
44 | #include <sound/soc.h> | |
45 | ||
ef280d39 | 46 | #include "tegra20_i2s.h" |
71f78e22 | 47 | |
896637ac | 48 | #define DRV_NAME "tegra20-i2s" |
71f78e22 | 49 | |
896637ac | 50 | static inline void tegra20_i2s_write(struct tegra20_i2s *i2s, u32 reg, u32 val) |
71f78e22 SW |
51 | { |
52 | __raw_writel(val, i2s->regs + reg); | |
53 | } | |
54 | ||
896637ac | 55 | static inline u32 tegra20_i2s_read(struct tegra20_i2s *i2s, u32 reg) |
71f78e22 SW |
56 | { |
57 | return __raw_readl(i2s->regs + reg); | |
58 | } | |
59 | ||
60 | #ifdef CONFIG_DEBUG_FS | |
896637ac | 61 | static int tegra20_i2s_show(struct seq_file *s, void *unused) |
71f78e22 SW |
62 | { |
63 | #define REG(r) { r, #r } | |
64 | static const struct { | |
65 | int offset; | |
66 | const char *name; | |
67 | } regs[] = { | |
896637ac SW |
68 | REG(TEGRA20_I2S_CTRL), |
69 | REG(TEGRA20_I2S_STATUS), | |
70 | REG(TEGRA20_I2S_TIMING), | |
71 | REG(TEGRA20_I2S_FIFO_SCR), | |
72 | REG(TEGRA20_I2S_PCM_CTRL), | |
73 | REG(TEGRA20_I2S_NW_CTRL), | |
74 | REG(TEGRA20_I2S_TDM_CTRL), | |
75 | REG(TEGRA20_I2S_TDM_TX_RX_CTRL), | |
71f78e22 SW |
76 | }; |
77 | #undef REG | |
78 | ||
896637ac | 79 | struct tegra20_i2s *i2s = s->private; |
71f78e22 SW |
80 | int i; |
81 | ||
82 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
896637ac | 83 | u32 val = tegra20_i2s_read(i2s, regs[i].offset); |
71f78e22 SW |
84 | seq_printf(s, "%s = %08x\n", regs[i].name, val); |
85 | } | |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
896637ac | 90 | static int tegra20_i2s_debug_open(struct inode *inode, struct file *file) |
71f78e22 | 91 | { |
896637ac | 92 | return single_open(file, tegra20_i2s_show, inode->i_private); |
71f78e22 SW |
93 | } |
94 | ||
896637ac SW |
95 | static const struct file_operations tegra20_i2s_debug_fops = { |
96 | .open = tegra20_i2s_debug_open, | |
71f78e22 SW |
97 | .read = seq_read, |
98 | .llseek = seq_lseek, | |
99 | .release = single_release, | |
100 | }; | |
101 | ||
896637ac | 102 | static void tegra20_i2s_debug_add(struct tegra20_i2s *i2s) |
71f78e22 | 103 | { |
d4a2eca7 SW |
104 | i2s->debug = debugfs_create_file(i2s->dai.name, S_IRUGO, |
105 | snd_soc_debugfs_root, i2s, | |
896637ac | 106 | &tegra20_i2s_debug_fops); |
71f78e22 SW |
107 | } |
108 | ||
896637ac | 109 | static void tegra20_i2s_debug_remove(struct tegra20_i2s *i2s) |
71f78e22 SW |
110 | { |
111 | if (i2s->debug) | |
112 | debugfs_remove(i2s->debug); | |
113 | } | |
114 | #else | |
896637ac | 115 | static inline void tegra20_i2s_debug_add(struct tegra20_i2s *i2s, int id) |
71f78e22 SW |
116 | { |
117 | } | |
118 | ||
896637ac | 119 | static inline void tegra20_i2s_debug_remove(struct tegra20_i2s *i2s) |
71f78e22 SW |
120 | { |
121 | } | |
122 | #endif | |
123 | ||
896637ac | 124 | static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai, |
71f78e22 SW |
125 | unsigned int fmt) |
126 | { | |
896637ac | 127 | struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
71f78e22 SW |
128 | |
129 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
130 | case SND_SOC_DAIFMT_NB_NF: | |
131 | break; | |
132 | default: | |
133 | return -EINVAL; | |
134 | } | |
135 | ||
896637ac | 136 | i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_MASTER_ENABLE; |
71f78e22 SW |
137 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
138 | case SND_SOC_DAIFMT_CBS_CFS: | |
896637ac | 139 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_MASTER_ENABLE; |
71f78e22 SW |
140 | break; |
141 | case SND_SOC_DAIFMT_CBM_CFM: | |
142 | break; | |
143 | default: | |
144 | return -EINVAL; | |
145 | } | |
146 | ||
896637ac SW |
147 | i2s->reg_ctrl &= ~(TEGRA20_I2S_CTRL_BIT_FORMAT_MASK | |
148 | TEGRA20_I2S_CTRL_LRCK_MASK); | |
71f78e22 SW |
149 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
150 | case SND_SOC_DAIFMT_DSP_A: | |
896637ac SW |
151 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP; |
152 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW; | |
71f78e22 SW |
153 | break; |
154 | case SND_SOC_DAIFMT_DSP_B: | |
896637ac SW |
155 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP; |
156 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_R_LOW; | |
71f78e22 SW |
157 | break; |
158 | case SND_SOC_DAIFMT_I2S: | |
896637ac SW |
159 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S; |
160 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW; | |
71f78e22 SW |
161 | break; |
162 | case SND_SOC_DAIFMT_RIGHT_J: | |
896637ac SW |
163 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM; |
164 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW; | |
71f78e22 SW |
165 | break; |
166 | case SND_SOC_DAIFMT_LEFT_J: | |
896637ac SW |
167 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM; |
168 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW; | |
71f78e22 SW |
169 | break; |
170 | default: | |
171 | return -EINVAL; | |
172 | } | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
896637ac SW |
177 | static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream, |
178 | struct snd_pcm_hw_params *params, | |
179 | struct snd_soc_dai *dai) | |
71f78e22 | 180 | { |
7deb2b45 | 181 | struct device *dev = substream->pcm->card->dev; |
896637ac | 182 | struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
71f78e22 SW |
183 | u32 reg; |
184 | int ret, sample_size, srate, i2sclock, bitcnt; | |
185 | ||
896637ac | 186 | i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_BIT_SIZE_MASK; |
71f78e22 SW |
187 | switch (params_format(params)) { |
188 | case SNDRV_PCM_FORMAT_S16_LE: | |
896637ac | 189 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_16; |
71f78e22 SW |
190 | sample_size = 16; |
191 | break; | |
192 | case SNDRV_PCM_FORMAT_S24_LE: | |
896637ac | 193 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_24; |
71f78e22 SW |
194 | sample_size = 24; |
195 | break; | |
196 | case SNDRV_PCM_FORMAT_S32_LE: | |
896637ac | 197 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_32; |
71f78e22 SW |
198 | sample_size = 32; |
199 | break; | |
200 | default: | |
201 | return -EINVAL; | |
202 | } | |
203 | ||
204 | srate = params_rate(params); | |
205 | ||
206 | /* Final "* 2" required by Tegra hardware */ | |
207 | i2sclock = srate * params_channels(params) * sample_size * 2; | |
208 | ||
209 | ret = clk_set_rate(i2s->clk_i2s, i2sclock); | |
210 | if (ret) { | |
211 | dev_err(dev, "Can't set I2S clock rate: %d\n", ret); | |
212 | return ret; | |
213 | } | |
214 | ||
215 | bitcnt = (i2sclock / (2 * srate)) - 1; | |
896637ac | 216 | if (bitcnt < 0 || bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US) |
71f78e22 | 217 | return -EINVAL; |
896637ac | 218 | reg = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT; |
71f78e22 SW |
219 | |
220 | if (i2sclock % (2 * srate)) | |
896637ac | 221 | reg |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE; |
71f78e22 | 222 | |
30d436a6 | 223 | clk_enable(i2s->clk_i2s); |
713d1369 | 224 | |
896637ac | 225 | tegra20_i2s_write(i2s, TEGRA20_I2S_TIMING, reg); |
71f78e22 | 226 | |
896637ac SW |
227 | tegra20_i2s_write(i2s, TEGRA20_I2S_FIFO_SCR, |
228 | TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS | | |
229 | TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS); | |
71f78e22 | 230 | |
30d436a6 | 231 | clk_disable(i2s->clk_i2s); |
713d1369 | 232 | |
71f78e22 SW |
233 | return 0; |
234 | } | |
235 | ||
896637ac | 236 | static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s) |
71f78e22 | 237 | { |
896637ac SW |
238 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO1_ENABLE; |
239 | tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl); | |
71f78e22 SW |
240 | } |
241 | ||
896637ac | 242 | static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s) |
71f78e22 | 243 | { |
896637ac SW |
244 | i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO1_ENABLE; |
245 | tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl); | |
71f78e22 SW |
246 | } |
247 | ||
896637ac | 248 | static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s) |
71f78e22 | 249 | { |
896637ac SW |
250 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO2_ENABLE; |
251 | tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl); | |
71f78e22 SW |
252 | } |
253 | ||
896637ac | 254 | static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s) |
71f78e22 | 255 | { |
896637ac SW |
256 | i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO2_ENABLE; |
257 | tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl); | |
71f78e22 SW |
258 | } |
259 | ||
896637ac SW |
260 | static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
261 | struct snd_soc_dai *dai) | |
71f78e22 | 262 | { |
896637ac | 263 | struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
71f78e22 SW |
264 | |
265 | switch (cmd) { | |
266 | case SNDRV_PCM_TRIGGER_START: | |
267 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
268 | case SNDRV_PCM_TRIGGER_RESUME: | |
30d436a6 | 269 | clk_enable(i2s->clk_i2s); |
71f78e22 | 270 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
896637ac | 271 | tegra20_i2s_start_playback(i2s); |
71f78e22 | 272 | else |
896637ac | 273 | tegra20_i2s_start_capture(i2s); |
71f78e22 SW |
274 | break; |
275 | case SNDRV_PCM_TRIGGER_STOP: | |
276 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
277 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
278 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
896637ac | 279 | tegra20_i2s_stop_playback(i2s); |
71f78e22 | 280 | else |
896637ac | 281 | tegra20_i2s_stop_capture(i2s); |
30d436a6 | 282 | clk_disable(i2s->clk_i2s); |
71f78e22 SW |
283 | break; |
284 | default: | |
285 | return -EINVAL; | |
286 | } | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
896637ac | 291 | static int tegra20_i2s_probe(struct snd_soc_dai *dai) |
71f78e22 | 292 | { |
896637ac | 293 | struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
71f78e22 SW |
294 | |
295 | dai->capture_dma_data = &i2s->capture_dma_data; | |
296 | dai->playback_dma_data = &i2s->playback_dma_data; | |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
896637ac SW |
301 | static const struct snd_soc_dai_ops tegra20_i2s_dai_ops = { |
302 | .set_fmt = tegra20_i2s_set_fmt, | |
303 | .hw_params = tegra20_i2s_hw_params, | |
304 | .trigger = tegra20_i2s_trigger, | |
71f78e22 SW |
305 | }; |
306 | ||
896637ac SW |
307 | static const struct snd_soc_dai_driver tegra20_i2s_dai_template = { |
308 | .probe = tegra20_i2s_probe, | |
d4a2eca7 SW |
309 | .playback = { |
310 | .channels_min = 2, | |
311 | .channels_max = 2, | |
312 | .rates = SNDRV_PCM_RATE_8000_96000, | |
313 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
71f78e22 | 314 | }, |
d4a2eca7 SW |
315 | .capture = { |
316 | .channels_min = 2, | |
317 | .channels_max = 2, | |
318 | .rates = SNDRV_PCM_RATE_8000_96000, | |
319 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
71f78e22 | 320 | }, |
896637ac | 321 | .ops = &tegra20_i2s_dai_ops, |
d4a2eca7 | 322 | .symmetric_rates = 1, |
71f78e22 SW |
323 | }; |
324 | ||
896637ac | 325 | static __devinit int tegra20_i2s_platform_probe(struct platform_device *pdev) |
71f78e22 | 326 | { |
896637ac | 327 | struct tegra20_i2s *i2s; |
71f78e22 | 328 | struct resource *mem, *memregion, *dmareq; |
bf55499e SW |
329 | u32 of_dma[2]; |
330 | u32 dma_ch; | |
71f78e22 SW |
331 | int ret; |
332 | ||
896637ac | 333 | i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL); |
71f78e22 | 334 | if (!i2s) { |
896637ac | 335 | dev_err(&pdev->dev, "Can't allocate tegra20_i2s\n"); |
71f78e22 | 336 | ret = -ENOMEM; |
bea0ed08 | 337 | goto err; |
71f78e22 SW |
338 | } |
339 | dev_set_drvdata(&pdev->dev, i2s); | |
340 | ||
896637ac | 341 | i2s->dai = tegra20_i2s_dai_template; |
d4a2eca7 SW |
342 | i2s->dai.name = dev_name(&pdev->dev); |
343 | ||
b5f9cfed | 344 | i2s->clk_i2s = clk_get(&pdev->dev, NULL); |
422650e6 | 345 | if (IS_ERR(i2s->clk_i2s)) { |
713dce4e | 346 | dev_err(&pdev->dev, "Can't retrieve i2s clock\n"); |
71f78e22 | 347 | ret = PTR_ERR(i2s->clk_i2s); |
bea0ed08 | 348 | goto err; |
71f78e22 SW |
349 | } |
350 | ||
351 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
352 | if (!mem) { | |
353 | dev_err(&pdev->dev, "No memory resource\n"); | |
354 | ret = -ENODEV; | |
355 | goto err_clk_put; | |
356 | } | |
357 | ||
358 | dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
359 | if (!dmareq) { | |
bf55499e SW |
360 | if (of_property_read_u32_array(pdev->dev.of_node, |
361 | "nvidia,dma-request-selector", | |
362 | of_dma, 2) < 0) { | |
363 | dev_err(&pdev->dev, "No DMA resource\n"); | |
364 | ret = -ENODEV; | |
365 | goto err_clk_put; | |
366 | } | |
367 | dma_ch = of_dma[1]; | |
368 | } else { | |
369 | dma_ch = dmareq->start; | |
71f78e22 SW |
370 | } |
371 | ||
bea0ed08 SW |
372 | memregion = devm_request_mem_region(&pdev->dev, mem->start, |
373 | resource_size(mem), DRV_NAME); | |
71f78e22 SW |
374 | if (!memregion) { |
375 | dev_err(&pdev->dev, "Memory region already claimed\n"); | |
376 | ret = -EBUSY; | |
377 | goto err_clk_put; | |
378 | } | |
379 | ||
bea0ed08 | 380 | i2s->regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
71f78e22 SW |
381 | if (!i2s->regs) { |
382 | dev_err(&pdev->dev, "ioremap failed\n"); | |
383 | ret = -ENOMEM; | |
bea0ed08 | 384 | goto err_clk_put; |
71f78e22 SW |
385 | } |
386 | ||
896637ac | 387 | i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2; |
71f78e22 SW |
388 | i2s->capture_dma_data.wrap = 4; |
389 | i2s->capture_dma_data.width = 32; | |
bf55499e | 390 | i2s->capture_dma_data.req_sel = dma_ch; |
71f78e22 | 391 | |
896637ac | 392 | i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1; |
71f78e22 SW |
393 | i2s->playback_dma_data.wrap = 4; |
394 | i2s->playback_dma_data.width = 32; | |
bf55499e | 395 | i2s->playback_dma_data.req_sel = dma_ch; |
71f78e22 | 396 | |
896637ac | 397 | i2s->reg_ctrl = TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED; |
71f78e22 | 398 | |
d4a2eca7 | 399 | ret = snd_soc_register_dai(&pdev->dev, &i2s->dai); |
71f78e22 SW |
400 | if (ret) { |
401 | dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); | |
402 | ret = -ENOMEM; | |
bea0ed08 | 403 | goto err_clk_put; |
71f78e22 SW |
404 | } |
405 | ||
518de86b SW |
406 | ret = tegra_pcm_platform_register(&pdev->dev); |
407 | if (ret) { | |
408 | dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); | |
409 | goto err_unregister_dai; | |
410 | } | |
411 | ||
896637ac | 412 | tegra20_i2s_debug_add(i2s); |
71f78e22 SW |
413 | |
414 | return 0; | |
415 | ||
518de86b SW |
416 | err_unregister_dai: |
417 | snd_soc_unregister_dai(&pdev->dev); | |
71f78e22 SW |
418 | err_clk_put: |
419 | clk_put(i2s->clk_i2s); | |
bea0ed08 | 420 | err: |
71f78e22 SW |
421 | return ret; |
422 | } | |
423 | ||
896637ac | 424 | static int __devexit tegra20_i2s_platform_remove(struct platform_device *pdev) |
71f78e22 | 425 | { |
896637ac | 426 | struct tegra20_i2s *i2s = dev_get_drvdata(&pdev->dev); |
71f78e22 | 427 | |
518de86b | 428 | tegra_pcm_platform_unregister(&pdev->dev); |
71f78e22 SW |
429 | snd_soc_unregister_dai(&pdev->dev); |
430 | ||
896637ac | 431 | tegra20_i2s_debug_remove(i2s); |
71f78e22 | 432 | |
71f78e22 SW |
433 | clk_put(i2s->clk_i2s); |
434 | ||
71f78e22 SW |
435 | return 0; |
436 | } | |
437 | ||
896637ac | 438 | static const struct of_device_id tegra20_i2s_of_match[] __devinitconst = { |
bf55499e SW |
439 | { .compatible = "nvidia,tegra20-i2s", }, |
440 | {}, | |
441 | }; | |
442 | ||
896637ac | 443 | static struct platform_driver tegra20_i2s_driver = { |
71f78e22 SW |
444 | .driver = { |
445 | .name = DRV_NAME, | |
446 | .owner = THIS_MODULE, | |
896637ac | 447 | .of_match_table = tegra20_i2s_of_match, |
71f78e22 | 448 | }, |
896637ac SW |
449 | .probe = tegra20_i2s_platform_probe, |
450 | .remove = __devexit_p(tegra20_i2s_platform_remove), | |
71f78e22 | 451 | }; |
896637ac | 452 | module_platform_driver(tegra20_i2s_driver); |
71f78e22 SW |
453 | |
454 | MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); | |
896637ac | 455 | MODULE_DESCRIPTION("Tegra20 I2S ASoC driver"); |
71f78e22 | 456 | MODULE_LICENSE("GPL"); |
8eb34207 | 457 | MODULE_ALIAS("platform:" DRV_NAME); |
896637ac | 458 | MODULE_DEVICE_TABLE(of, tegra20_i2s_of_match); |