[deliverable/linux.git] / sound / soc / tegra / tegra20_i2s.c

/*
 * tegra20_i2s.c - Tegra20 I2S driver
 *
 * Author: Stephen Warren <swarren@nvidia.com>
 * Copyright (C) 2010,2012 - NVIDIA, Inc.
 *
 * Based on code copyright/by:
 *
 * Copyright (c) 2009-2010, NVIDIA Corporation.
 * Scott Peterson <speterson@nvidia.com>
 *
 * Copyright (C) 2010 Google, Inc.
 * Iliyan Malchev <malchev@google.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include "tegra20_i2s.h"

#define DRV_NAME "tegra20-i2s"

static inline void tegra20_i2s_write(struct tegra20_i2s *i2s, u32 reg, u32 val)
{
	__raw_writel(val, i2s->regs + reg);
}

static inline u32 tegra20_i2s_read(struct tegra20_i2s *i2s, u32 reg)
{
	return __raw_readl(i2s->regs + reg);
}

static int tegra20_i2s_runtime_suspend(struct device *dev)
{
	struct tegra20_i2s *i2s = dev_get_drvdata(dev);

	clk_disable(i2s->clk_i2s);

	return 0;
}

static int tegra20_i2s_runtime_resume(struct device *dev)
{
	struct tegra20_i2s *i2s = dev_get_drvdata(dev);
	int ret;

	ret = clk_enable(i2s->clk_i2s);
	if (ret) {
		dev_err(dev, "clk_enable failed: %d\n", ret);
		return ret;
	}

	return 0;
}

#ifdef CONFIG_DEBUG_FS
static int tegra20_i2s_show(struct seq_file *s, void *unused)
{
#define REG(r) { r, #r }
	static const struct {
		int offset;
		const char *name;
	} regs[] = {
		REG(TEGRA20_I2S_CTRL),
		REG(TEGRA20_I2S_STATUS),
		REG(TEGRA20_I2S_TIMING),
		REG(TEGRA20_I2S_FIFO_SCR),
		REG(TEGRA20_I2S_PCM_CTRL),
		REG(TEGRA20_I2S_NW_CTRL),
		REG(TEGRA20_I2S_TDM_CTRL),
		REG(TEGRA20_I2S_TDM_TX_RX_CTRL),
	};
#undef REG

	struct tegra20_i2s *i2s = s->private;
	int i;

	for (i = 0; i < ARRAY_SIZE(regs); i++) {
		u32 val = tegra20_i2s_read(i2s, regs[i].offset);
		seq_printf(s, "%s = %08x\n", regs[i].name, val);
	}

	return 0;
}

static int tegra20_i2s_debug_open(struct inode *inode, struct file *file)
{
	return single_open(file, tegra20_i2s_show, inode->i_private);
}

static const struct file_operations tegra20_i2s_debug_fops = {
	.open    = tegra20_i2s_debug_open,
	.read    = seq_read,
	.llseek  = seq_lseek,
	.release = single_release,
};

static void tegra20_i2s_debug_add(struct tegra20_i2s *i2s)
{
	i2s->debug = debugfs_create_file(i2s->dai.name, S_IRUGO,
					 snd_soc_debugfs_root, i2s,
					 &tegra20_i2s_debug_fops);
}

static void tegra20_i2s_debug_remove(struct tegra20_i2s *i2s)
{
	if (i2s->debug)
		debugfs_remove(i2s->debug);
}
#else
static inline void tegra20_i2s_debug_add(struct tegra20_i2s *i2s, int id)
{
}

static inline void tegra20_i2s_debug_remove(struct tegra20_i2s *i2s)
{
}
#endif

static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai,
				unsigned int fmt)
{
	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		break;
	default:
		return -EINVAL;
	}

	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_MASTER_ENABLE;
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_MASTER_ENABLE;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		break;
	default:
		return -EINVAL;
	}

	i2s->reg_ctrl &= ~(TEGRA20_I2S_CTRL_BIT_FORMAT_MASK |
			   TEGRA20_I2S_CTRL_LRCK_MASK);
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_DSP_A:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_DSP_B:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_R_LOW;
		break;
	case SND_SOC_DAIFMT_I2S:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S;
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM;
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM;
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct device *dev = substream->pcm->card->dev;
	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	u32 reg;
	int ret, sample_size, srate, i2sclock, bitcnt;

	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_BIT_SIZE_MASK;
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_16;
		sample_size = 16;
		break;
	case SNDRV_PCM_FORMAT_S24_LE:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_24;
		sample_size = 24;
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_32;
		sample_size = 32;
		break;
	default:
		return -EINVAL;
	}

	srate = params_rate(params);

	/* Final "* 2" required by Tegra hardware */
	i2sclock = srate * params_channels(params) * sample_size * 2;

	ret = clk_set_rate(i2s->clk_i2s, i2sclock);
	if (ret) {
		dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
		return ret;
	}

	bitcnt = (i2sclock / (2 * srate)) - 1;
	if (bitcnt < 0 || bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
		return -EINVAL;
	reg = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;

	if (i2sclock % (2 * srate))
		reg |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE;

	tegra20_i2s_write(i2s, TEGRA20_I2S_TIMING, reg);

	tegra20_i2s_write(i2s, TEGRA20_I2S_FIFO_SCR,
		TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
		TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);

	return 0;
}

static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s)
{
	i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO1_ENABLE;
	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
}

static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s)
{
	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO1_ENABLE;
	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
}

static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s)
{
	i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO2_ENABLE;
	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
}

static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s)
{
	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO2_ENABLE;
	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
}

static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_RESUME:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra20_i2s_start_playback(i2s);
		else
			tegra20_i2s_start_capture(i2s);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	case SNDRV_PCM_TRIGGER_SUSPEND:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra20_i2s_stop_playback(i2s);
		else
			tegra20_i2s_stop_capture(i2s);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int tegra20_i2s_probe(struct snd_soc_dai *dai)
{
	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	dai->capture_dma_data = &i2s->capture_dma_data;
	dai->playback_dma_data = &i2s->playback_dma_data;

	return 0;
}

static const struct snd_soc_dai_ops tegra20_i2s_dai_ops = {
	.set_fmt	= tegra20_i2s_set_fmt,
	.hw_params	= tegra20_i2s_hw_params,
	.trigger	= tegra20_i2s_trigger,
};

static const struct snd_soc_dai_driver tegra20_i2s_dai_template = {
	.probe = tegra20_i2s_probe,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops = &tegra20_i2s_dai_ops,
	.symmetric_rates = 1,
};

static __devinit int tegra20_i2s_platform_probe(struct platform_device *pdev)
{
	struct tegra20_i2s *i2s;
	struct resource *mem, *memregion, *dmareq;
	u32 of_dma[2];
	u32 dma_ch;
	int ret;

	i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL);
	if (!i2s) {
		dev_err(&pdev->dev, "Can't allocate tegra20_i2s\n");
		ret = -ENOMEM;
		goto err;
	}
	dev_set_drvdata(&pdev->dev, i2s);

	i2s->dai = tegra20_i2s_dai_template;
	i2s->dai.name = dev_name(&pdev->dev);

	i2s->clk_i2s = clk_get(&pdev->dev, NULL);
	if (IS_ERR(i2s->clk_i2s)) {
		dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
		ret = PTR_ERR(i2s->clk_i2s);
		goto err;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "No memory resource\n");
		ret = -ENODEV;
		goto err_clk_put;
	}

	dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	if (!dmareq) {
		if (of_property_read_u32_array(pdev->dev.of_node,
					"nvidia,dma-request-selector",
					of_dma, 2) < 0) {
			dev_err(&pdev->dev, "No DMA resource\n");
			ret = -ENODEV;
			goto err_clk_put;
		}
		dma_ch = of_dma[1];
	} else {
		dma_ch = dmareq->start;
	}

	memregion = devm_request_mem_region(&pdev->dev, mem->start,
					    resource_size(mem), DRV_NAME);
	if (!memregion) {
		dev_err(&pdev->dev, "Memory region already claimed\n");
		ret = -EBUSY;
		goto err_clk_put;
	}

	i2s->regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
	if (!i2s->regs) {
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -ENOMEM;
		goto err_clk_put;
	}

	i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
	i2s->capture_dma_data.wrap = 4;
	i2s->capture_dma_data.width = 32;
	i2s->capture_dma_data.req_sel = dma_ch;

	i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
	i2s->playback_dma_data.wrap = 4;
	i2s->playback_dma_data.width = 32;
	i2s->playback_dma_data.req_sel = dma_ch;

	i2s->reg_ctrl = TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED;

	pm_runtime_enable(&pdev->dev);
	if (!pm_runtime_enabled(&pdev->dev)) {
		ret = tegra20_i2s_runtime_resume(&pdev->dev);
		if (ret)
			goto err_pm_disable;
	}

	ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
	if (ret) {
		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
		ret = -ENOMEM;
		goto err_suspend;
	}

	ret = tegra_pcm_platform_register(&pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
		goto err_unregister_dai;
	}

	tegra20_i2s_debug_add(i2s);

	return 0;

err_unregister_dai:
	snd_soc_unregister_dai(&pdev->dev);
err_suspend:
	if (!pm_runtime_status_suspended(&pdev->dev))
		tegra20_i2s_runtime_suspend(&pdev->dev);
err_pm_disable:
	pm_runtime_disable(&pdev->dev);
err_clk_put:
	clk_put(i2s->clk_i2s);
err:
	return ret;
}

static int __devexit tegra20_i2s_platform_remove(struct platform_device *pdev)
{
	struct tegra20_i2s *i2s = dev_get_drvdata(&pdev->dev);

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		tegra20_i2s_runtime_suspend(&pdev->dev);

	tegra_pcm_platform_unregister(&pdev->dev);
	snd_soc_unregister_dai(&pdev->dev);

	tegra20_i2s_debug_remove(i2s);

	clk_put(i2s->clk_i2s);

	return 0;
}

static const struct of_device_id tegra20_i2s_of_match[] __devinitconst = {
	{ .compatible = "nvidia,tegra20-i2s", },
	{},
};

static const struct dev_pm_ops tegra20_i2s_pm_ops __devinitconst = {
	SET_RUNTIME_PM_OPS(tegra20_i2s_runtime_suspend,
			   tegra20_i2s_runtime_resume, NULL)
};

static struct platform_driver tegra20_i2s_driver = {
	.driver = {
		.name = DRV_NAME,
		.owner = THIS_MODULE,
		.of_match_table = tegra20_i2s_of_match,
		.pm = &tegra20_i2s_pm_ops,
	},
	.probe = tegra20_i2s_platform_probe,
	.remove = __devexit_p(tegra20_i2s_platform_remove),
};
module_platform_driver(tegra20_i2s_driver);

MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
MODULE_DESCRIPTION("Tegra20 I2S ASoC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra20_i2s_of_match);
Commit	Line	Data
71f78e22	1	/*
ef280d39	2	* tegra20_i2s.c - Tegra20 I2S driver
71f78e22 SW	3	*
71f78e22 SW	4	* Author: Stephen Warren <swarren@nvidia.com>
518de86b	5	* Copyright (C) 2010,2012 - NVIDIA, Inc.
71f78e22 SW	6	*
	7	* Based on code copyright/by:
	8	*
	9	* Copyright (c) 2009-2010, NVIDIA Corporation.
	10	* Scott Peterson <speterson@nvidia.com>
	11	*
	12	* Copyright (C) 2010 Google, Inc.
	13	* Iliyan Malchev <malchev@google.com>
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* version 2 as published by the Free Software Foundation.
	18	*
	19	* This program is distributed in the hope that it will be useful, but
	20	* WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	22	* General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	27	* 02110-1301 USA
	28	*
	29	*/
	30
	31	#include <linux/clk.h>
71f78e22 SW	32	#include <linux/debugfs.h>
71f78e22 SW	33	#include <linux/device.h>
7613c508 SW	34	#include <linux/io.h>
	35	#include <linux/module.h>
	36	#include <linux/of.h>
71f78e22	37	#include <linux/platform_device.h>
82ef0ae4	38	#include <linux/pm_runtime.h>
71f78e22 SW	39	#include <linux/seq_file.h>
71f78e22 SW	40	#include <linux/slab.h>
71f78e22 SW	41	#include <sound/core.h>
	42	#include <sound/pcm.h>
	43	#include <sound/pcm_params.h>
	44	#include <sound/soc.h>
	45
ef280d39	46	#include "tegra20_i2s.h"
71f78e22	47
896637ac	48	#define DRV_NAME "tegra20-i2s"
71f78e22	49
896637ac	50	static inline void tegra20_i2s_write(struct tegra20_i2s *i2s, u32 reg, u32 val)
71f78e22 SW	51	{
	52	__raw_writel(val, i2s->regs + reg);
	53	}
	54
896637ac	55	static inline u32 tegra20_i2s_read(struct tegra20_i2s *i2s, u32 reg)
71f78e22 SW	56	{
	57	return __raw_readl(i2s->regs + reg);
	58	}
	59
82ef0ae4 SW	60	static int tegra20_i2s_runtime_suspend(struct device *dev)
	61	{
	62	struct tegra20_i2s *i2s = dev_get_drvdata(dev);
	63
	64	clk_disable(i2s->clk_i2s);
	65
	66	return 0;
	67	}
	68
	69	static int tegra20_i2s_runtime_resume(struct device *dev)
	70	{
	71	struct tegra20_i2s *i2s = dev_get_drvdata(dev);
	72	int ret;
	73
	74	ret = clk_enable(i2s->clk_i2s);
	75	if (ret) {
	76	dev_err(dev, "clk_enable failed: %d\n", ret);
	77	return ret;
	78	}
	79
	80	return 0;
	81	}
	82
71f78e22	83	#ifdef CONFIG_DEBUG_FS
896637ac	84	static int tegra20_i2s_show(struct seq_file s, void unused)
71f78e22 SW	85	{
	86	#define REG(r) { r, #r }
	87	static const struct {
	88	int offset;
	89	const char *name;
	90	} regs[] = {
896637ac SW	91	REG(TEGRA20_I2S_CTRL),
	92	REG(TEGRA20_I2S_STATUS),
	93	REG(TEGRA20_I2S_TIMING),
	94	REG(TEGRA20_I2S_FIFO_SCR),
	95	REG(TEGRA20_I2S_PCM_CTRL),
	96	REG(TEGRA20_I2S_NW_CTRL),
	97	REG(TEGRA20_I2S_TDM_CTRL),
	98	REG(TEGRA20_I2S_TDM_TX_RX_CTRL),
71f78e22 SW	99	};
	100	#undef REG
	101
896637ac	102	struct tegra20_i2s *i2s = s->private;
71f78e22 SW	103	int i;
	104
	105	for (i = 0; i < ARRAY_SIZE(regs); i++) {
896637ac	106	u32 val = tegra20_i2s_read(i2s, regs[i].offset);
71f78e22 SW	107	seq_printf(s, "%s = %08x\n", regs[i].name, val);
	108	}
	109
	110	return 0;
	111	}
	112
896637ac	113	static int tegra20_i2s_debug_open(struct inode inode, struct file file)
71f78e22	114	{
896637ac	115	return single_open(file, tegra20_i2s_show, inode->i_private);
71f78e22 SW	116	}
71f78e22 SW	117
896637ac SW	118	static const struct file_operations tegra20_i2s_debug_fops = {
896637ac SW	119	.open = tegra20_i2s_debug_open,
71f78e22 SW	120	.read = seq_read,
	121	.llseek = seq_lseek,
	122	.release = single_release,
	123	};
	124
896637ac	125	static void tegra20_i2s_debug_add(struct tegra20_i2s *i2s)
71f78e22	126	{
d4a2eca7 SW	127	i2s->debug = debugfs_create_file(i2s->dai.name, S_IRUGO,
d4a2eca7 SW	128	snd_soc_debugfs_root, i2s,
896637ac	129	&tegra20_i2s_debug_fops);
71f78e22 SW	130	}
71f78e22 SW	131
896637ac	132	static void tegra20_i2s_debug_remove(struct tegra20_i2s *i2s)
71f78e22 SW	133	{
	134	if (i2s->debug)
	135	debugfs_remove(i2s->debug);
	136	}
	137	#else
896637ac	138	static inline void tegra20_i2s_debug_add(struct tegra20_i2s *i2s, int id)
71f78e22 SW	139	{
	140	}
	141
896637ac	142	static inline void tegra20_i2s_debug_remove(struct tegra20_i2s *i2s)
71f78e22 SW	143	{
	144	}
	145	#endif
	146
896637ac	147	static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai,
71f78e22 SW	148	unsigned int fmt)
71f78e22 SW	149	{
896637ac	150	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
71f78e22 SW	151
	152	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	153	case SND_SOC_DAIFMT_NB_NF:
	154	break;
	155	default:
	156	return -EINVAL;
	157	}
	158
896637ac	159	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_MASTER_ENABLE;
71f78e22 SW	160	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
71f78e22 SW	161	case SND_SOC_DAIFMT_CBS_CFS:
896637ac	162	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_MASTER_ENABLE;
71f78e22 SW	163	break;
	164	case SND_SOC_DAIFMT_CBM_CFM:
	165	break;
	166	default:
	167	return -EINVAL;
	168	}
	169
896637ac SW	170	i2s->reg_ctrl &= ~(TEGRA20_I2S_CTRL_BIT_FORMAT_MASK \|
896637ac SW	171	TEGRA20_I2S_CTRL_LRCK_MASK);
71f78e22 SW	172	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
71f78e22 SW	173	case SND_SOC_DAIFMT_DSP_A:
896637ac SW	174	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
896637ac SW	175	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_LRCK_L_LOW;
71f78e22 SW	176	break;
71f78e22 SW	177	case SND_SOC_DAIFMT_DSP_B:
896637ac SW	178	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
896637ac SW	179	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_LRCK_R_LOW;
71f78e22 SW	180	break;
71f78e22 SW	181	case SND_SOC_DAIFMT_I2S:
896637ac SW	182	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S;
896637ac SW	183	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_LRCK_L_LOW;
71f78e22 SW	184	break;
71f78e22 SW	185	case SND_SOC_DAIFMT_RIGHT_J:
896637ac SW	186	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM;
896637ac SW	187	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_LRCK_L_LOW;
71f78e22 SW	188	break;
71f78e22 SW	189	case SND_SOC_DAIFMT_LEFT_J:
896637ac SW	190	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM;
896637ac SW	191	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_LRCK_L_LOW;
71f78e22 SW	192	break;
	193	default:
	194	return -EINVAL;
	195	}
	196
	197	return 0;
	198	}
	199
896637ac SW	200	static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream,
	201	struct snd_pcm_hw_params *params,
	202	struct snd_soc_dai *dai)
71f78e22	203	{
7deb2b45	204	struct device *dev = substream->pcm->card->dev;
896637ac	205	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
71f78e22 SW	206	u32 reg;
	207	int ret, sample_size, srate, i2sclock, bitcnt;
	208
896637ac	209	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_BIT_SIZE_MASK;
71f78e22 SW	210	switch (params_format(params)) {
71f78e22 SW	211	case SNDRV_PCM_FORMAT_S16_LE:
896637ac	212	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_SIZE_16;
71f78e22 SW	213	sample_size = 16;
	214	break;
	215	case SNDRV_PCM_FORMAT_S24_LE:
896637ac	216	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_SIZE_24;
71f78e22 SW	217	sample_size = 24;
	218	break;
	219	case SNDRV_PCM_FORMAT_S32_LE:
896637ac	220	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_BIT_SIZE_32;
71f78e22 SW	221	sample_size = 32;
	222	break;
	223	default:
	224	return -EINVAL;
	225	}
	226
	227	srate = params_rate(params);
	228
	229	/* Final "* 2" required by Tegra hardware */
	230	i2sclock = srate * params_channels(params) * sample_size * 2;
	231
	232	ret = clk_set_rate(i2s->clk_i2s, i2sclock);
	233	if (ret) {
	234	dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
	235	return ret;
	236	}
	237
	238	bitcnt = (i2sclock / (2 * srate)) - 1;
896637ac	239	if (bitcnt < 0 \|\| bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
71f78e22	240	return -EINVAL;
896637ac	241	reg = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
71f78e22 SW	242
71f78e22 SW	243	if (i2sclock % (2 * srate))
896637ac	244	reg \|= TEGRA20_I2S_TIMING_NON_SYM_ENABLE;
71f78e22	245
896637ac	246	tegra20_i2s_write(i2s, TEGRA20_I2S_TIMING, reg);
71f78e22	247
896637ac SW	248	tegra20_i2s_write(i2s, TEGRA20_I2S_FIFO_SCR,
	249	TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS \|
	250	TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
71f78e22 SW	251
	252	return 0;
	253	}
	254
896637ac	255	static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s)
71f78e22	256	{
896637ac SW	257	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_FIFO1_ENABLE;
896637ac SW	258	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
71f78e22 SW	259	}
71f78e22 SW	260
896637ac	261	static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s)
71f78e22	262	{
896637ac SW	263	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO1_ENABLE;
896637ac SW	264	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
71f78e22 SW	265	}
71f78e22 SW	266
896637ac	267	static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s)
71f78e22	268	{
896637ac SW	269	i2s->reg_ctrl \|= TEGRA20_I2S_CTRL_FIFO2_ENABLE;
896637ac SW	270	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
71f78e22 SW	271	}
71f78e22 SW	272
896637ac	273	static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s)
71f78e22	274	{
896637ac SW	275	i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO2_ENABLE;
896637ac SW	276	tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
71f78e22 SW	277	}
71f78e22 SW	278
896637ac SW	279	static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
896637ac SW	280	struct snd_soc_dai *dai)
71f78e22	281	{
896637ac	282	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
71f78e22 SW	283
	284	switch (cmd) {
	285	case SNDRV_PCM_TRIGGER_START:
	286	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	287	case SNDRV_PCM_TRIGGER_RESUME:
71f78e22	288	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
896637ac	289	tegra20_i2s_start_playback(i2s);
71f78e22	290	else
896637ac	291	tegra20_i2s_start_capture(i2s);
71f78e22 SW	292	break;
	293	case SNDRV_PCM_TRIGGER_STOP:
	294	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	295	case SNDRV_PCM_TRIGGER_SUSPEND:
	296	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
896637ac	297	tegra20_i2s_stop_playback(i2s);
71f78e22	298	else
896637ac	299	tegra20_i2s_stop_capture(i2s);
71f78e22 SW	300	break;
	301	default:
	302	return -EINVAL;
	303	}
	304
	305	return 0;
	306	}
	307
896637ac	308	static int tegra20_i2s_probe(struct snd_soc_dai *dai)
71f78e22	309	{
896637ac	310	struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
71f78e22 SW	311
	312	dai->capture_dma_data = &i2s->capture_dma_data;
	313	dai->playback_dma_data = &i2s->playback_dma_data;
	314
	315	return 0;
	316	}
	317
896637ac SW	318	static const struct snd_soc_dai_ops tegra20_i2s_dai_ops = {
	319	.set_fmt = tegra20_i2s_set_fmt,
	320	.hw_params = tegra20_i2s_hw_params,
	321	.trigger = tegra20_i2s_trigger,
71f78e22 SW	322	};
71f78e22 SW	323
896637ac SW	324	static const struct snd_soc_dai_driver tegra20_i2s_dai_template = {
896637ac SW	325	.probe = tegra20_i2s_probe,
d4a2eca7 SW	326	.playback = {
	327	.channels_min = 2,
	328	.channels_max = 2,
	329	.rates = SNDRV_PCM_RATE_8000_96000,
	330	.formats = SNDRV_PCM_FMTBIT_S16_LE,
71f78e22	331	},
d4a2eca7 SW	332	.capture = {
	333	.channels_min = 2,
	334	.channels_max = 2,
	335	.rates = SNDRV_PCM_RATE_8000_96000,
	336	.formats = SNDRV_PCM_FMTBIT_S16_LE,
71f78e22	337	},
896637ac	338	.ops = &tegra20_i2s_dai_ops,
d4a2eca7	339	.symmetric_rates = 1,
71f78e22 SW	340	};
71f78e22 SW	341
896637ac	342	static __devinit int tegra20_i2s_platform_probe(struct platform_device *pdev)
71f78e22	343	{
896637ac	344	struct tegra20_i2s *i2s;
71f78e22	345	struct resource mem, memregion, *dmareq;
bf55499e SW	346	u32 of_dma[2];
bf55499e SW	347	u32 dma_ch;
71f78e22 SW	348	int ret;
71f78e22 SW	349
896637ac	350	i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL);
71f78e22	351	if (!i2s) {
896637ac	352	dev_err(&pdev->dev, "Can't allocate tegra20_i2s\n");
71f78e22	353	ret = -ENOMEM;
bea0ed08	354	goto err;
71f78e22 SW	355	}
	356	dev_set_drvdata(&pdev->dev, i2s);
	357
896637ac	358	i2s->dai = tegra20_i2s_dai_template;
d4a2eca7 SW	359	i2s->dai.name = dev_name(&pdev->dev);
d4a2eca7 SW	360
b5f9cfed	361	i2s->clk_i2s = clk_get(&pdev->dev, NULL);
422650e6	362	if (IS_ERR(i2s->clk_i2s)) {
713dce4e	363	dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
71f78e22	364	ret = PTR_ERR(i2s->clk_i2s);
bea0ed08	365	goto err;
71f78e22 SW	366	}
	367
	368	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	369	if (!mem) {
	370	dev_err(&pdev->dev, "No memory resource\n");
	371	ret = -ENODEV;
	372	goto err_clk_put;
	373	}
	374
	375	dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	376	if (!dmareq) {
bf55499e SW	377	if (of_property_read_u32_array(pdev->dev.of_node,
	378	"nvidia,dma-request-selector",
	379	of_dma, 2) < 0) {
	380	dev_err(&pdev->dev, "No DMA resource\n");
	381	ret = -ENODEV;
	382	goto err_clk_put;
	383	}
	384	dma_ch = of_dma[1];
	385	} else {
	386	dma_ch = dmareq->start;
71f78e22 SW	387	}
71f78e22 SW	388
bea0ed08 SW	389	memregion = devm_request_mem_region(&pdev->dev, mem->start,
bea0ed08 SW	390	resource_size(mem), DRV_NAME);
71f78e22 SW	391	if (!memregion) {
	392	dev_err(&pdev->dev, "Memory region already claimed\n");
	393	ret = -EBUSY;
	394	goto err_clk_put;
	395	}
	396
bea0ed08	397	i2s->regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
71f78e22 SW	398	if (!i2s->regs) {
	399	dev_err(&pdev->dev, "ioremap failed\n");
	400	ret = -ENOMEM;
bea0ed08	401	goto err_clk_put;
71f78e22 SW	402	}
71f78e22 SW	403
896637ac	404	i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
71f78e22 SW	405	i2s->capture_dma_data.wrap = 4;
71f78e22 SW	406	i2s->capture_dma_data.width = 32;
bf55499e	407	i2s->capture_dma_data.req_sel = dma_ch;
71f78e22	408
896637ac	409	i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
71f78e22 SW	410	i2s->playback_dma_data.wrap = 4;
71f78e22 SW	411	i2s->playback_dma_data.width = 32;
bf55499e	412	i2s->playback_dma_data.req_sel = dma_ch;
71f78e22	413
896637ac	414	i2s->reg_ctrl = TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED;
71f78e22	415
82ef0ae4 SW	416	pm_runtime_enable(&pdev->dev);
	417	if (!pm_runtime_enabled(&pdev->dev)) {
	418	ret = tegra20_i2s_runtime_resume(&pdev->dev);
	419	if (ret)
	420	goto err_pm_disable;
	421	}
	422
d4a2eca7	423	ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
71f78e22 SW	424	if (ret) {
	425	dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
	426	ret = -ENOMEM;
82ef0ae4	427	goto err_suspend;
71f78e22 SW	428	}
71f78e22 SW	429
518de86b SW	430	ret = tegra_pcm_platform_register(&pdev->dev);
	431	if (ret) {
	432	dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
	433	goto err_unregister_dai;
	434	}
	435
896637ac	436	tegra20_i2s_debug_add(i2s);
71f78e22 SW	437
	438	return 0;
	439
518de86b SW	440	err_unregister_dai:
518de86b SW	441	snd_soc_unregister_dai(&pdev->dev);
82ef0ae4 SW	442	err_suspend:
	443	if (!pm_runtime_status_suspended(&pdev->dev))
	444	tegra20_i2s_runtime_suspend(&pdev->dev);
	445	err_pm_disable:
	446	pm_runtime_disable(&pdev->dev);
71f78e22 SW	447	err_clk_put:
71f78e22 SW	448	clk_put(i2s->clk_i2s);
bea0ed08	449	err:
71f78e22 SW	450	return ret;
	451	}
	452
896637ac	453	static int __devexit tegra20_i2s_platform_remove(struct platform_device *pdev)
71f78e22	454	{
896637ac	455	struct tegra20_i2s *i2s = dev_get_drvdata(&pdev->dev);
71f78e22	456
82ef0ae4 SW	457	pm_runtime_disable(&pdev->dev);
	458	if (!pm_runtime_status_suspended(&pdev->dev))
	459	tegra20_i2s_runtime_suspend(&pdev->dev);
	460
518de86b	461	tegra_pcm_platform_unregister(&pdev->dev);
71f78e22 SW	462	snd_soc_unregister_dai(&pdev->dev);
71f78e22 SW	463
896637ac	464	tegra20_i2s_debug_remove(i2s);
71f78e22	465
71f78e22 SW	466	clk_put(i2s->clk_i2s);
71f78e22 SW	467
71f78e22 SW	468	return 0;
	469	}
	470
896637ac	471	static const struct of_device_id tegra20_i2s_of_match[] __devinitconst = {
bf55499e SW	472	{ .compatible = "nvidia,tegra20-i2s", },
	473	{},
	474	};
	475
82ef0ae4 SW	476	static const struct dev_pm_ops tegra20_i2s_pm_ops __devinitconst = {
	477	SET_RUNTIME_PM_OPS(tegra20_i2s_runtime_suspend,
	478	tegra20_i2s_runtime_resume, NULL)
	479	};
	480
896637ac	481	static struct platform_driver tegra20_i2s_driver = {
71f78e22 SW	482	.driver = {
	483	.name = DRV_NAME,
	484	.owner = THIS_MODULE,
896637ac	485	.of_match_table = tegra20_i2s_of_match,
82ef0ae4	486	.pm = &tegra20_i2s_pm_ops,
71f78e22	487	},
896637ac SW	488	.probe = tegra20_i2s_platform_probe,
896637ac SW	489	.remove = __devexit_p(tegra20_i2s_platform_remove),
71f78e22	490	};
896637ac	491	module_platform_driver(tegra20_i2s_driver);
71f78e22 SW	492
71f78e22 SW	493	MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
896637ac	494	MODULE_DESCRIPTION("Tegra20 I2S ASoC driver");
71f78e22	495	MODULE_LICENSE("GPL");
8eb34207	496	MODULE_ALIAS("platform:" DRV_NAME);
896637ac	497	MODULE_DEVICE_TABLE(of, tegra20_i2s_of_match);