[deliverable/linux.git] / sound / soc / tegra / tegra20_i2s.c

/*
 * tegra20_i2s.c - Tegra20 I2S driver
 *
 * Author: Stephen Warren <swarren@nvidia.com>
 * Copyright (C) 2010,2012 - NVIDIA, Inc.
 *
 * Based on code copyright/by:
 *
 * Copyright (c) 2009-2010, NVIDIA Corporation.
 * Scott Peterson <speterson@nvidia.com>
 *
 * Copyright (C) 2010 Google, Inc.
 * Iliyan Malchev <malchev@google.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/clk.h>
#include <linux/module.h>
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <mach/iomap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include "tegra20_i2s.h"

#define DRV_NAME "tegra-i2s"

static inline void tegra_i2s_write(struct tegra_i2s *i2s, u32 reg, u32 val)
{
	__raw_writel(val, i2s->regs + reg);
}

static inline u32 tegra_i2s_read(struct tegra_i2s *i2s, u32 reg)
{
	return __raw_readl(i2s->regs + reg);
}

#ifdef CONFIG_DEBUG_FS
static int tegra_i2s_show(struct seq_file *s, void *unused)
{
#define REG(r) { r, #r }
	static const struct {
		int offset;
		const char *name;
	} regs[] = {
		REG(TEGRA_I2S_CTRL),
		REG(TEGRA_I2S_STATUS),
		REG(TEGRA_I2S_TIMING),
		REG(TEGRA_I2S_FIFO_SCR),
		REG(TEGRA_I2S_PCM_CTRL),
		REG(TEGRA_I2S_NW_CTRL),
		REG(TEGRA_I2S_TDM_CTRL),
		REG(TEGRA_I2S_TDM_TX_RX_CTRL),
	};
#undef REG

	struct tegra_i2s *i2s = s->private;
	int i;

	for (i = 0; i < ARRAY_SIZE(regs); i++) {
		u32 val = tegra_i2s_read(i2s, regs[i].offset);
		seq_printf(s, "%s = %08x\n", regs[i].name, val);
	}

	return 0;
}

static int tegra_i2s_debug_open(struct inode *inode, struct file *file)
{
	return single_open(file, tegra_i2s_show, inode->i_private);
}

static const struct file_operations tegra_i2s_debug_fops = {
	.open    = tegra_i2s_debug_open,
	.read    = seq_read,
	.llseek  = seq_lseek,
	.release = single_release,
};

static void tegra_i2s_debug_add(struct tegra_i2s *i2s)
{
	i2s->debug = debugfs_create_file(i2s->dai.name, S_IRUGO,
					 snd_soc_debugfs_root, i2s,
					 &tegra_i2s_debug_fops);
}

static void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
{
	if (i2s->debug)
		debugfs_remove(i2s->debug);
}
#else
static inline void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id)
{
}

static inline void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
{
}
#endif

static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
				unsigned int fmt)
{
	struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		break;
	default:
		return -EINVAL;
	}

	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_MASTER_ENABLE;
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_MASTER_ENABLE;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		break;
	default:
		return -EINVAL;
	}

	i2s->reg_ctrl &= ~(TEGRA_I2S_CTRL_BIT_FORMAT_MASK |
				TEGRA_I2S_CTRL_LRCK_MASK);
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_DSP_A:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_DSP_B:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_R_LOW;
		break;
	case SND_SOC_DAIFMT_I2S:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_I2S;
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_RJM;
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_LJM;
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int tegra_i2s_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params,
				struct snd_soc_dai *dai)
{
	struct device *dev = substream->pcm->card->dev;
	struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	u32 reg;
	int ret, sample_size, srate, i2sclock, bitcnt;

	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_BIT_SIZE_MASK;
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_16;
		sample_size = 16;
		break;
	case SNDRV_PCM_FORMAT_S24_LE:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_24;
		sample_size = 24;
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_32;
		sample_size = 32;
		break;
	default:
		return -EINVAL;
	}

	srate = params_rate(params);

	/* Final "* 2" required by Tegra hardware */
	i2sclock = srate * params_channels(params) * sample_size * 2;

	ret = clk_set_rate(i2s->clk_i2s, i2sclock);
	if (ret) {
		dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
		return ret;
	}

	bitcnt = (i2sclock / (2 * srate)) - 1;
	if (bitcnt < 0 || bitcnt > TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
		return -EINVAL;
	reg = bitcnt << TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;

	if (i2sclock % (2 * srate))
		reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE;

	clk_enable(i2s->clk_i2s);

	tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg);

	tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR,
		TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
		TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);

	clk_disable(i2s->clk_i2s);

	return 0;
}

static void tegra_i2s_start_playback(struct tegra_i2s *i2s)
{
	i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO1_ENABLE;
	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
}

static void tegra_i2s_stop_playback(struct tegra_i2s *i2s)
{
	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO1_ENABLE;
	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
}

static void tegra_i2s_start_capture(struct tegra_i2s *i2s)
{
	i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO2_ENABLE;
	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
}

static void tegra_i2s_stop_capture(struct tegra_i2s *i2s)
{
	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO2_ENABLE;
	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
}

static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
				struct snd_soc_dai *dai)
{
	struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_RESUME:
		clk_enable(i2s->clk_i2s);
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra_i2s_start_playback(i2s);
		else
			tegra_i2s_start_capture(i2s);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	case SNDRV_PCM_TRIGGER_SUSPEND:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra_i2s_stop_playback(i2s);
		else
			tegra_i2s_stop_capture(i2s);
		clk_disable(i2s->clk_i2s);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int tegra_i2s_probe(struct snd_soc_dai *dai)
{
	struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	dai->capture_dma_data = &i2s->capture_dma_data;
	dai->playback_dma_data = &i2s->playback_dma_data;

	return 0;
}

static const struct snd_soc_dai_ops tegra_i2s_dai_ops = {
	.set_fmt	= tegra_i2s_set_fmt,
	.hw_params	= tegra_i2s_hw_params,
	.trigger	= tegra_i2s_trigger,
};

static const struct snd_soc_dai_driver tegra_i2s_dai_template = {
	.probe = tegra_i2s_probe,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops = &tegra_i2s_dai_ops,
	.symmetric_rates = 1,
};

static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev)
{
	struct tegra_i2s *i2s;
	struct resource *mem, *memregion, *dmareq;
	u32 of_dma[2];
	u32 dma_ch;
	int ret;

	i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra_i2s), GFP_KERNEL);
	if (!i2s) {
		dev_err(&pdev->dev, "Can't allocate tegra_i2s\n");
		ret = -ENOMEM;
		goto err;
	}
	dev_set_drvdata(&pdev->dev, i2s);

	i2s->dai = tegra_i2s_dai_template;
	i2s->dai.name = dev_name(&pdev->dev);

	i2s->clk_i2s = clk_get(&pdev->dev, NULL);
	if (IS_ERR(i2s->clk_i2s)) {
		dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
		ret = PTR_ERR(i2s->clk_i2s);
		goto err;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "No memory resource\n");
		ret = -ENODEV;
		goto err_clk_put;
	}

	dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	if (!dmareq) {
		if (of_property_read_u32_array(pdev->dev.of_node,
					"nvidia,dma-request-selector",
					of_dma, 2) < 0) {
			dev_err(&pdev->dev, "No DMA resource\n");
			ret = -ENODEV;
			goto err_clk_put;
		}
		dma_ch = of_dma[1];
	} else {
		dma_ch = dmareq->start;
	}

	memregion = devm_request_mem_region(&pdev->dev, mem->start,
					    resource_size(mem), DRV_NAME);
	if (!memregion) {
		dev_err(&pdev->dev, "Memory region already claimed\n");
		ret = -EBUSY;
		goto err_clk_put;
	}

	i2s->regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
	if (!i2s->regs) {
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -ENOMEM;
		goto err_clk_put;
	}

	i2s->capture_dma_data.addr = mem->start + TEGRA_I2S_FIFO2;
	i2s->capture_dma_data.wrap = 4;
	i2s->capture_dma_data.width = 32;
	i2s->capture_dma_data.req_sel = dma_ch;

	i2s->playback_dma_data.addr = mem->start + TEGRA_I2S_FIFO1;
	i2s->playback_dma_data.wrap = 4;
	i2s->playback_dma_data.width = 32;
	i2s->playback_dma_data.req_sel = dma_ch;

	i2s->reg_ctrl = TEGRA_I2S_CTRL_FIFO_FORMAT_PACKED;

	ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
	if (ret) {
		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
		ret = -ENOMEM;
		goto err_clk_put;
	}

	ret = tegra_pcm_platform_register(&pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
		goto err_unregister_dai;
	}

	tegra_i2s_debug_add(i2s);

	return 0;

err_unregister_dai:
	snd_soc_unregister_dai(&pdev->dev);
err_clk_put:
	clk_put(i2s->clk_i2s);
err:
	return ret;
}

static int __devexit tegra_i2s_platform_remove(struct platform_device *pdev)
{
	struct tegra_i2s *i2s = dev_get_drvdata(&pdev->dev);

	tegra_pcm_platform_unregister(&pdev->dev);
	snd_soc_unregister_dai(&pdev->dev);

	tegra_i2s_debug_remove(i2s);

	clk_put(i2s->clk_i2s);

	return 0;
}

static const struct of_device_id tegra_i2s_of_match[] __devinitconst = {
	{ .compatible = "nvidia,tegra20-i2s", },
	{},
};

static struct platform_driver tegra_i2s_driver = {
	.driver = {
		.name = DRV_NAME,
		.owner = THIS_MODULE,
		.of_match_table = tegra_i2s_of_match,
	},
	.probe = tegra_i2s_platform_probe,
	.remove = __devexit_p(tegra_i2s_platform_remove),
};
module_platform_driver(tegra_i2s_driver);

MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
MODULE_DESCRIPTION("Tegra I2S ASoC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra_i2s_of_match);
Commit	Line	Data
71f78e22	1	/*
ef280d39	2	* tegra20_i2s.c - Tegra20 I2S driver
71f78e22 SW	3	*
71f78e22 SW	4	* Author: Stephen Warren <swarren@nvidia.com>
518de86b	5	* Copyright (C) 2010,2012 - NVIDIA, Inc.
71f78e22 SW	6	*
	7	* Based on code copyright/by:
	8	*
	9	* Copyright (c) 2009-2010, NVIDIA Corporation.
	10	* Scott Peterson <speterson@nvidia.com>
	11	*
	12	* Copyright (C) 2010 Google, Inc.
	13	* Iliyan Malchev <malchev@google.com>
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* version 2 as published by the Free Software Foundation.
	18	*
	19	* This program is distributed in the hope that it will be useful, but
	20	* WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	22	* General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	27	* 02110-1301 USA
	28	*
	29	*/
	30
	31	#include <linux/clk.h>
	32	#include <linux/module.h>
	33	#include <linux/debugfs.h>
	34	#include <linux/device.h>
	35	#include <linux/platform_device.h>
	36	#include <linux/seq_file.h>
	37	#include <linux/slab.h>
	38	#include <linux/io.h>
bf55499e	39	#include <linux/of.h>
71f78e22 SW	40	#include <mach/iomap.h>
	41	#include <sound/core.h>
	42	#include <sound/pcm.h>
	43	#include <sound/pcm_params.h>
	44	#include <sound/soc.h>
	45
ef280d39	46	#include "tegra20_i2s.h"
71f78e22 SW	47
	48	#define DRV_NAME "tegra-i2s"
	49
	50	static inline void tegra_i2s_write(struct tegra_i2s *i2s, u32 reg, u32 val)
	51	{
	52	__raw_writel(val, i2s->regs + reg);
	53	}
	54
	55	static inline u32 tegra_i2s_read(struct tegra_i2s *i2s, u32 reg)
	56	{
	57	return __raw_readl(i2s->regs + reg);
	58	}
	59
	60	#ifdef CONFIG_DEBUG_FS
	61	static int tegra_i2s_show(struct seq_file s, void unused)
	62	{
	63	#define REG(r) { r, #r }
	64	static const struct {
	65	int offset;
	66	const char *name;
	67	} regs[] = {
	68	REG(TEGRA_I2S_CTRL),
	69	REG(TEGRA_I2S_STATUS),
	70	REG(TEGRA_I2S_TIMING),
	71	REG(TEGRA_I2S_FIFO_SCR),
	72	REG(TEGRA_I2S_PCM_CTRL),
	73	REG(TEGRA_I2S_NW_CTRL),
	74	REG(TEGRA_I2S_TDM_CTRL),
	75	REG(TEGRA_I2S_TDM_TX_RX_CTRL),
	76	};
	77	#undef REG
	78
	79	struct tegra_i2s *i2s = s->private;
	80	int i;
	81
	82	for (i = 0; i < ARRAY_SIZE(regs); i++) {
	83	u32 val = tegra_i2s_read(i2s, regs[i].offset);
	84	seq_printf(s, "%s = %08x\n", regs[i].name, val);
	85	}
	86
	87	return 0;
	88	}
	89
	90	static int tegra_i2s_debug_open(struct inode inode, struct file file)
	91	{
	92	return single_open(file, tegra_i2s_show, inode->i_private);
	93	}
	94
	95	static const struct file_operations tegra_i2s_debug_fops = {
	96	.open = tegra_i2s_debug_open,
	97	.read = seq_read,
	98	.llseek = seq_lseek,
	99	.release = single_release,
	100	};
	101
d4a2eca7	102	static void tegra_i2s_debug_add(struct tegra_i2s *i2s)
71f78e22	103	{
d4a2eca7 SW	104	i2s->debug = debugfs_create_file(i2s->dai.name, S_IRUGO,
	105	snd_soc_debugfs_root, i2s,
	106	&tegra_i2s_debug_fops);
71f78e22 SW	107	}
	108
	109	static void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
	110	{
	111	if (i2s->debug)
	112	debugfs_remove(i2s->debug);
	113	}
	114	#else
0dfe8da4	115	static inline void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id)
71f78e22 SW	116	{
	117	}
	118
	119	static inline void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
	120	{
	121	}
	122	#endif
	123
	124	static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
	125	unsigned int fmt)
	126	{
	127	struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	128
	129	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	130	case SND_SOC_DAIFMT_NB_NF:
	131	break;
	132	default:
	133	return -EINVAL;
	134	}
	135
	136	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_MASTER_ENABLE;
	137	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	138	case SND_SOC_DAIFMT_CBS_CFS:
	139	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_MASTER_ENABLE;
	140	break;
	141	case SND_SOC_DAIFMT_CBM_CFM:
	142	break;
	143	default:
	144	return -EINVAL;
	145	}
	146
7deb2b45	147	i2s->reg_ctrl &= ~(TEGRA_I2S_CTRL_BIT_FORMAT_MASK \|
71f78e22 SW	148	TEGRA_I2S_CTRL_LRCK_MASK);
	149	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	150	case SND_SOC_DAIFMT_DSP_A:
	151	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
	152	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_LRCK_L_LOW;
	153	break;
	154	case SND_SOC_DAIFMT_DSP_B:
	155	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
	156	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_LRCK_R_LOW;
	157	break;
	158	case SND_SOC_DAIFMT_I2S:
	159	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_FORMAT_I2S;
	160	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_LRCK_L_LOW;
	161	break;
	162	case SND_SOC_DAIFMT_RIGHT_J:
	163	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_FORMAT_RJM;
	164	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_LRCK_L_LOW;
	165	break;
	166	case SND_SOC_DAIFMT_LEFT_J:
	167	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_FORMAT_LJM;
	168	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_LRCK_L_LOW;
	169	break;
	170	default:
	171	return -EINVAL;
	172	}
	173
	174	return 0;
	175	}
	176
	177	static int tegra_i2s_hw_params(struct snd_pcm_substream *substream,
	178	struct snd_pcm_hw_params *params,
	179	struct snd_soc_dai *dai)
	180	{
7deb2b45	181	struct device *dev = substream->pcm->card->dev;
71f78e22 SW	182	struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	183	u32 reg;
	184	int ret, sample_size, srate, i2sclock, bitcnt;
	185
	186	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_BIT_SIZE_MASK;
	187	switch (params_format(params)) {
	188	case SNDRV_PCM_FORMAT_S16_LE:
	189	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_SIZE_16;
	190	sample_size = 16;
	191	break;
	192	case SNDRV_PCM_FORMAT_S24_LE:
	193	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_SIZE_24;
	194	sample_size = 24;
	195	break;
	196	case SNDRV_PCM_FORMAT_S32_LE:
	197	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_SIZE_32;
	198	sample_size = 32;
	199	break;
	200	default:
	201	return -EINVAL;
	202	}
	203
	204	srate = params_rate(params);
	205
	206	/* Final "* 2" required by Tegra hardware */
	207	i2sclock = srate * params_channels(params) * sample_size * 2;
	208
	209	ret = clk_set_rate(i2s->clk_i2s, i2sclock);
	210	if (ret) {
	211	dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
	212	return ret;
	213	}
	214
	215	bitcnt = (i2sclock / (2 * srate)) - 1;
	216	if (bitcnt < 0 \|\| bitcnt > TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
	217	return -EINVAL;
	218	reg = bitcnt << TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
	219
	220	if (i2sclock % (2 * srate))
	221	reg \|= TEGRA_I2S_TIMING_NON_SYM_ENABLE;
	222
30d436a6	223	clk_enable(i2s->clk_i2s);
713d1369	224
71f78e22 SW	225	tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg);
	226
	227	tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR,
	228	TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS \|
	229	TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
	230
30d436a6	231	clk_disable(i2s->clk_i2s);
713d1369	232
71f78e22 SW	233	return 0;
	234	}
	235
	236	static void tegra_i2s_start_playback(struct tegra_i2s *i2s)
	237	{
	238	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_FIFO1_ENABLE;
	239	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
	240	}
	241
	242	static void tegra_i2s_stop_playback(struct tegra_i2s *i2s)
	243	{
	244	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO1_ENABLE;
	245	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
	246	}
	247
	248	static void tegra_i2s_start_capture(struct tegra_i2s *i2s)
	249	{
	250	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_FIFO2_ENABLE;
	251	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
	252	}
	253
	254	static void tegra_i2s_stop_capture(struct tegra_i2s *i2s)
	255	{
	256	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO2_ENABLE;
	257	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
	258	}
	259
	260	static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
	261	struct snd_soc_dai *dai)
	262	{
	263	struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	264
	265	switch (cmd) {
	266	case SNDRV_PCM_TRIGGER_START:
	267	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	268	case SNDRV_PCM_TRIGGER_RESUME:
30d436a6	269	clk_enable(i2s->clk_i2s);
71f78e22 SW	270	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	271	tegra_i2s_start_playback(i2s);
	272	else
	273	tegra_i2s_start_capture(i2s);
	274	break;
	275	case SNDRV_PCM_TRIGGER_STOP:
	276	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	277	case SNDRV_PCM_TRIGGER_SUSPEND:
	278	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	279	tegra_i2s_stop_playback(i2s);
	280	else
	281	tegra_i2s_stop_capture(i2s);
30d436a6	282	clk_disable(i2s->clk_i2s);
71f78e22 SW	283	break;
	284	default:
	285	return -EINVAL;
	286	}
	287
	288	return 0;
	289	}
	290
	291	static int tegra_i2s_probe(struct snd_soc_dai *dai)
	292	{
7deb2b45	293	struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
71f78e22 SW	294
	295	dai->capture_dma_data = &i2s->capture_dma_data;
	296	dai->playback_dma_data = &i2s->playback_dma_data;
	297
	298	return 0;
	299	}
	300
85e7652d	301	static const struct snd_soc_dai_ops tegra_i2s_dai_ops = {
71f78e22 SW	302	.set_fmt = tegra_i2s_set_fmt,
	303	.hw_params = tegra_i2s_hw_params,
	304	.trigger = tegra_i2s_trigger,
	305	};
	306
d4a2eca7 SW	307	static const struct snd_soc_dai_driver tegra_i2s_dai_template = {
	308	.probe = tegra_i2s_probe,
	309	.playback = {
	310	.channels_min = 2,
	311	.channels_max = 2,
	312	.rates = SNDRV_PCM_RATE_8000_96000,
	313	.formats = SNDRV_PCM_FMTBIT_S16_LE,
71f78e22	314	},
d4a2eca7 SW	315	.capture = {
	316	.channels_min = 2,
	317	.channels_max = 2,
	318	.rates = SNDRV_PCM_RATE_8000_96000,
	319	.formats = SNDRV_PCM_FMTBIT_S16_LE,
71f78e22	320	},
d4a2eca7 SW	321	.ops = &tegra_i2s_dai_ops,
d4a2eca7 SW	322	.symmetric_rates = 1,
71f78e22 SW	323	};
	324
	325	static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev)
	326	{
7deb2b45	327	struct tegra_i2s *i2s;
71f78e22	328	struct resource mem, memregion, *dmareq;
bf55499e SW	329	u32 of_dma[2];
bf55499e SW	330	u32 dma_ch;
71f78e22 SW	331	int ret;
71f78e22 SW	332
bea0ed08	333	i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra_i2s), GFP_KERNEL);
71f78e22 SW	334	if (!i2s) {
	335	dev_err(&pdev->dev, "Can't allocate tegra_i2s\n");
	336	ret = -ENOMEM;
bea0ed08	337	goto err;
71f78e22 SW	338	}
	339	dev_set_drvdata(&pdev->dev, i2s);
	340
d4a2eca7 SW	341	i2s->dai = tegra_i2s_dai_template;
	342	i2s->dai.name = dev_name(&pdev->dev);
	343
b5f9cfed	344	i2s->clk_i2s = clk_get(&pdev->dev, NULL);
422650e6	345	if (IS_ERR(i2s->clk_i2s)) {
713dce4e	346	dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
71f78e22	347	ret = PTR_ERR(i2s->clk_i2s);
bea0ed08	348	goto err;
71f78e22 SW	349	}
	350
	351	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	352	if (!mem) {
	353	dev_err(&pdev->dev, "No memory resource\n");
	354	ret = -ENODEV;
	355	goto err_clk_put;
	356	}
	357
	358	dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	359	if (!dmareq) {
bf55499e SW	360	if (of_property_read_u32_array(pdev->dev.of_node,
	361	"nvidia,dma-request-selector",
	362	of_dma, 2) < 0) {
	363	dev_err(&pdev->dev, "No DMA resource\n");
	364	ret = -ENODEV;
	365	goto err_clk_put;
	366	}
	367	dma_ch = of_dma[1];
	368	} else {
	369	dma_ch = dmareq->start;
71f78e22 SW	370	}
71f78e22 SW	371
bea0ed08 SW	372	memregion = devm_request_mem_region(&pdev->dev, mem->start,
bea0ed08 SW	373	resource_size(mem), DRV_NAME);
71f78e22 SW	374	if (!memregion) {
	375	dev_err(&pdev->dev, "Memory region already claimed\n");
	376	ret = -EBUSY;
	377	goto err_clk_put;
	378	}
	379
bea0ed08	380	i2s->regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
71f78e22 SW	381	if (!i2s->regs) {
	382	dev_err(&pdev->dev, "ioremap failed\n");
	383	ret = -ENOMEM;
bea0ed08	384	goto err_clk_put;
71f78e22 SW	385	}
	386
	387	i2s->capture_dma_data.addr = mem->start + TEGRA_I2S_FIFO2;
	388	i2s->capture_dma_data.wrap = 4;
	389	i2s->capture_dma_data.width = 32;
bf55499e	390	i2s->capture_dma_data.req_sel = dma_ch;
71f78e22 SW	391
	392	i2s->playback_dma_data.addr = mem->start + TEGRA_I2S_FIFO1;
	393	i2s->playback_dma_data.wrap = 4;
	394	i2s->playback_dma_data.width = 32;
bf55499e	395	i2s->playback_dma_data.req_sel = dma_ch;
71f78e22 SW	396
	397	i2s->reg_ctrl = TEGRA_I2S_CTRL_FIFO_FORMAT_PACKED;
	398
d4a2eca7	399	ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
71f78e22 SW	400	if (ret) {
	401	dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
	402	ret = -ENOMEM;
bea0ed08	403	goto err_clk_put;
71f78e22 SW	404	}
71f78e22 SW	405
518de86b SW	406	ret = tegra_pcm_platform_register(&pdev->dev);
	407	if (ret) {
	408	dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
	409	goto err_unregister_dai;
	410	}
	411
d4a2eca7	412	tegra_i2s_debug_add(i2s);
71f78e22 SW	413
	414	return 0;
	415
518de86b SW	416	err_unregister_dai:
518de86b SW	417	snd_soc_unregister_dai(&pdev->dev);
71f78e22 SW	418	err_clk_put:
71f78e22 SW	419	clk_put(i2s->clk_i2s);
bea0ed08	420	err:
71f78e22 SW	421	return ret;
	422	}
	423
	424	static int __devexit tegra_i2s_platform_remove(struct platform_device *pdev)
	425	{
	426	struct tegra_i2s *i2s = dev_get_drvdata(&pdev->dev);
71f78e22	427
518de86b	428	tegra_pcm_platform_unregister(&pdev->dev);
71f78e22 SW	429	snd_soc_unregister_dai(&pdev->dev);
	430
	431	tegra_i2s_debug_remove(i2s);
	432
71f78e22 SW	433	clk_put(i2s->clk_i2s);
71f78e22 SW	434
71f78e22 SW	435	return 0;
	436	}
	437
bf55499e SW	438	static const struct of_device_id tegra_i2s_of_match[] __devinitconst = {
	439	{ .compatible = "nvidia,tegra20-i2s", },
	440	{},
	441	};
	442
71f78e22 SW	443	static struct platform_driver tegra_i2s_driver = {
	444	.driver = {
	445	.name = DRV_NAME,
	446	.owner = THIS_MODULE,
bf55499e	447	.of_match_table = tegra_i2s_of_match,
71f78e22 SW	448	},
	449	.probe = tegra_i2s_platform_probe,
	450	.remove = __devexit_p(tegra_i2s_platform_remove),
	451	};
bea0ed08	452	module_platform_driver(tegra_i2s_driver);
71f78e22 SW	453
	454	MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
	455	MODULE_DESCRIPTION("Tegra I2S ASoC driver");
	456	MODULE_LICENSE("GPL");
8eb34207	457	MODULE_ALIAS("platform:" DRV_NAME);
bf55499e	458	MODULE_DEVICE_TABLE(of, tegra_i2s_of_match);