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clk: tegra: remove bogus PCIE_XCLK
[deliverable/linux.git] / sound / soc / tegra / tegra30_ahub.c
CommitLineData
be944d42
SW		 1/*
2 * tegra30_ahub.c - Tegra30 AHUB driver
3 *
4 * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/clk.h>
20#include <linux/device.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/of_platform.h>
24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/regmap.h>
5185e0ac 27#include <linux/reset.h>
be944d42 28#include <linux/slab.h>
be944d42
SW		 29#include <sound/soc.h>
30#include "tegra30_ahub.h"
31
32#define DRV_NAME "tegra30-ahub"
33
34static struct tegra30_ahub *ahub;
35
36static inline void tegra30_apbif_write(u32 reg, u32 val)
37{
38 regmap_write(ahub->regmap_apbif, reg, val);
39}
40
41static inline u32 tegra30_apbif_read(u32 reg)
42{
43 u32 val;
44 regmap_read(ahub->regmap_apbif, reg, &val);
45 return val;
46}
47
48static inline void tegra30_audio_write(u32 reg, u32 val)
49{
50 regmap_write(ahub->regmap_ahub, reg, val);
51}
52
53static int tegra30_ahub_runtime_suspend(struct device *dev)
54{
55 regcache_cache_only(ahub->regmap_apbif, true);
56 regcache_cache_only(ahub->regmap_ahub, true);
57
65d2bdd3
PG		 58 clk_disable_unprepare(ahub->clk_apbif);
59 clk_disable_unprepare(ahub->clk_d_audio);
be944d42
SW		 60
61 return 0;
62}
63
64/*
65 * clk_apbif isn't required for an I2S<->I2S configuration where no PCM data
66 * is read from or sent to memory. However, that's not something the rest of
67 * the driver supports right now, so we'll just treat the two clocks as one
68 * for now.
69 *
70 * These functions should not be a plain ref-count. Instead, each active stream
71 * contributes some requirement to the minimum clock rate, so starting or
72 * stopping streams should dynamically adjust the clock as required. However,
73 * this is not yet implemented.
74 */
75static int tegra30_ahub_runtime_resume(struct device *dev)
76{
77 int ret;
78
65d2bdd3 79 ret = clk_prepare_enable(ahub->clk_d_audio);
be944d42
SW		 80 if (ret) {
81 dev_err(dev, "clk_enable d_audio failed: %d\n", ret);
82 return ret;
83 }
65d2bdd3 84 ret = clk_prepare_enable(ahub->clk_apbif);
be944d42
SW		 85 if (ret) {
86 dev_err(dev, "clk_enable apbif failed: %d\n", ret);
87 clk_disable(ahub->clk_d_audio);
88 return ret;
89 }
90
91 regcache_cache_only(ahub->regmap_apbif, false);
92 regcache_cache_only(ahub->regmap_ahub, false);
93
94 return 0;
95}
96
97int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
5608bd3e
SW		 98 char *dmachan, int dmachan_len,
99 dma_addr_t *fiforeg)
be944d42
SW		 100{
101 int channel;
102 u32 reg, val;
5e049fce 103 struct tegra30_ahub_cif_conf cif_conf;
be944d42
SW		 104
105 channel = find_first_zero_bit(ahub->rx_usage,
106 TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
107 if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT)
108 return -EBUSY;
109
110 __set_bit(channel, ahub->rx_usage);
111
112 *rxcif = TEGRA30_AHUB_RXCIF_APBIF_RX0 + channel;
5608bd3e 113 snprintf(dmachan, dmachan_len, "rx%d", channel);
be944d42
SW		 114 *fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_RXFIFO +
115 (channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE);
be944d42 116
768db0b9
SW		 117 pm_runtime_get_sync(ahub->dev);
118
be944d42
SW		 119 reg = TEGRA30_AHUB_CHANNEL_CTRL +
120 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
121 val = tegra30_apbif_read(reg);
122 val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK |
123 TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK);
124 val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) |
125 TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN |
126 TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16;
127 tegra30_apbif_write(reg, val);
128
5e049fce
SW		 129 cif_conf.threshold = 0;
130 cif_conf.audio_channels = 2;
131 cif_conf.client_channels = 2;
132 cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16;
133 cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16;
134 cif_conf.expand = 0;
135 cif_conf.stereo_conv = 0;
136 cif_conf.replicate = 0;
137 cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX;
138 cif_conf.truncate = 0;
139 cif_conf.mono_conv = 0;
140
be944d42
SW		 141 reg = TEGRA30_AHUB_CIF_RX_CTRL +
142 (channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE);
5e049fce 143 ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);
be944d42 144
768db0b9
SW		 145 pm_runtime_put(ahub->dev);
146
be944d42
SW		 147 return 0;
148}
149EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_rx_fifo);
150
151int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
152{
153 int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
154 int reg, val;
155
768db0b9
SW		 156 pm_runtime_get_sync(ahub->dev);
157
be944d42
SW		 158 reg = TEGRA30_AHUB_CHANNEL_CTRL +
159 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
160 val = tegra30_apbif_read(reg);
161 val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
162 tegra30_apbif_write(reg, val);
163
768db0b9
SW		 164 pm_runtime_put(ahub->dev);
165
be944d42
SW		 166 return 0;
167}
168EXPORT_SYMBOL_GPL(tegra30_ahub_enable_rx_fifo);
169
170int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
171{
172 int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
173 int reg, val;
174
768db0b9
SW		 175 pm_runtime_get_sync(ahub->dev);
176
be944d42
SW		 177 reg = TEGRA30_AHUB_CHANNEL_CTRL +
178 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
179 val = tegra30_apbif_read(reg);
180 val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
181 tegra30_apbif_write(reg, val);
182
768db0b9
SW		 183 pm_runtime_put(ahub->dev);
184
be944d42
SW		 185 return 0;
186}
187EXPORT_SYMBOL_GPL(tegra30_ahub_disable_rx_fifo);
188
189int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif)
190{
191 int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
192
193 __clear_bit(channel, ahub->rx_usage);
194
195 return 0;
196}
197EXPORT_SYMBOL_GPL(tegra30_ahub_free_rx_fifo);
198
199int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
5608bd3e
SW		 200 char *dmachan, int dmachan_len,
201 dma_addr_t *fiforeg)
be944d42
SW		 202{
203 int channel;
204 u32 reg, val;
5e049fce 205 struct tegra30_ahub_cif_conf cif_conf;
be944d42
SW		 206
207 channel = find_first_zero_bit(ahub->tx_usage,
208 TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
209 if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT)
210 return -EBUSY;
211
212 __set_bit(channel, ahub->tx_usage);
213
214 *txcif = TEGRA30_AHUB_TXCIF_APBIF_TX0 + channel;
5608bd3e 215 snprintf(dmachan, dmachan_len, "tx%d", channel);
be944d42
SW		 216 *fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_TXFIFO +
217 (channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE);
be944d42 218
768db0b9
SW		 219 pm_runtime_get_sync(ahub->dev);
220
be944d42
SW		 221 reg = TEGRA30_AHUB_CHANNEL_CTRL +
222 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
223 val = tegra30_apbif_read(reg);
224 val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK |
225 TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK);
226 val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) |
227 TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN |
228 TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16;
229 tegra30_apbif_write(reg, val);
230
5e049fce
SW		 231 cif_conf.threshold = 0;
232 cif_conf.audio_channels = 2;
233 cif_conf.client_channels = 2;
234 cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16;
235 cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16;
236 cif_conf.expand = 0;
237 cif_conf.stereo_conv = 0;
238 cif_conf.replicate = 0;
239 cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX;
240 cif_conf.truncate = 0;
241 cif_conf.mono_conv = 0;
242
be944d42
SW		 243 reg = TEGRA30_AHUB_CIF_TX_CTRL +
244 (channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE);
5e049fce 245 ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);
be944d42 246
768db0b9
SW		 247 pm_runtime_put(ahub->dev);
248
be944d42
SW		 249 return 0;
250}
251EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_tx_fifo);
252
253int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif)
254{
255 int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
256 int reg, val;
257
768db0b9
SW		 258 pm_runtime_get_sync(ahub->dev);
259
be944d42
SW		 260 reg = TEGRA30_AHUB_CHANNEL_CTRL +
261 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
262 val = tegra30_apbif_read(reg);
263 val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
264 tegra30_apbif_write(reg, val);
265
768db0b9
SW		 266 pm_runtime_put(ahub->dev);
267
be944d42
SW		 268 return 0;
269}
270EXPORT_SYMBOL_GPL(tegra30_ahub_enable_tx_fifo);
271
272int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif)
273{
274 int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
275 int reg, val;
276
768db0b9
SW		 277 pm_runtime_get_sync(ahub->dev);
278
be944d42
SW		 279 reg = TEGRA30_AHUB_CHANNEL_CTRL +
280 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
281 val = tegra30_apbif_read(reg);
282 val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
283 tegra30_apbif_write(reg, val);
284
768db0b9
SW		 285 pm_runtime_put(ahub->dev);
286
be944d42
SW		 287 return 0;
288}
289EXPORT_SYMBOL_GPL(tegra30_ahub_disable_tx_fifo);
290
291int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif)
292{
293 int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
294
295 __clear_bit(channel, ahub->tx_usage);
296
297 return 0;
298}
299EXPORT_SYMBOL_GPL(tegra30_ahub_free_tx_fifo);
300
301int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif,
302 enum tegra30_ahub_txcif txcif)
303{
304 int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
305 int reg;
306
768db0b9
SW		 307 pm_runtime_get_sync(ahub->dev);
308
be944d42
SW		 309 reg = TEGRA30_AHUB_AUDIO_RX +
310 (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
311 tegra30_audio_write(reg, 1 << txcif);
312
768db0b9
SW		 313 pm_runtime_put(ahub->dev);
314
be944d42
SW		 315 return 0;
316}
317EXPORT_SYMBOL_GPL(tegra30_ahub_set_rx_cif_source);
318
319int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif)
320{
321 int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
322 int reg;
323
768db0b9
SW		 324 pm_runtime_get_sync(ahub->dev);
325
be944d42
SW		 326 reg = TEGRA30_AHUB_AUDIO_RX +
327 (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
328 tegra30_audio_write(reg, 0);
329
768db0b9
SW		 330 pm_runtime_put(ahub->dev);
331
be944d42
SW		 332 return 0;
333}
334EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source);
335
5185e0ac
SW		 336#define MOD_LIST_MASK_TEGRA30 BIT(0)
337#define MOD_LIST_MASK_TEGRA114 BIT(1)
95d36075 338
5185e0ac
SW		 339#define MOD_LIST_MASK_TEGRA30_OR_LATER \
340 (MOD_LIST_MASK_TEGRA30 | MOD_LIST_MASK_TEGRA114)
95d36075
SW		 341
342static const struct {
5185e0ac
SW		 343 const char *rst_name;
344 u32 mod_list_mask;
345} configlink_mods[] = {
346 { "i2s0", MOD_LIST_MASK_TEGRA30_OR_LATER },
347 { "i2s1", MOD_LIST_MASK_TEGRA30_OR_LATER },
348 { "i2s2", MOD_LIST_MASK_TEGRA30_OR_LATER },
349 { "i2s3", MOD_LIST_MASK_TEGRA30_OR_LATER },
350 { "i2s4", MOD_LIST_MASK_TEGRA30_OR_LATER },
351 { "dam0", MOD_LIST_MASK_TEGRA30_OR_LATER },
352 { "dam1", MOD_LIST_MASK_TEGRA30_OR_LATER },
353 { "dam2", MOD_LIST_MASK_TEGRA30_OR_LATER },
354 { "spdif", MOD_LIST_MASK_TEGRA30_OR_LATER },
355 { "amx", MOD_LIST_MASK_TEGRA114 },
356 { "adx", MOD_LIST_MASK_TEGRA114 },
be944d42
SW		 357};
358
be944d42
SW		 359#define LAST_REG(name) \
360 (TEGRA30_AHUB_##name + \
361 (TEGRA30_AHUB_##name##_STRIDE * TEGRA30_AHUB_##name##_COUNT) - 4)
362
363#define REG_IN_ARRAY(reg, name) \
364 ((reg >= TEGRA30_AHUB_##name) && \
365 (reg <= LAST_REG(name) && \
366 (!((reg - TEGRA30_AHUB_##name) % TEGRA30_AHUB_##name##_STRIDE))))
367
368static bool tegra30_ahub_apbif_wr_rd_reg(struct device *dev, unsigned int reg)
369{
370 switch (reg) {
371 case TEGRA30_AHUB_CONFIG_LINK_CTRL:
372 case TEGRA30_AHUB_MISC_CTRL:
373 case TEGRA30_AHUB_APBDMA_LIVE_STATUS:
374 case TEGRA30_AHUB_I2S_LIVE_STATUS:
375 case TEGRA30_AHUB_SPDIF_LIVE_STATUS:
376 case TEGRA30_AHUB_I2S_INT_MASK:
377 case TEGRA30_AHUB_DAM_INT_MASK:
378 case TEGRA30_AHUB_SPDIF_INT_MASK:
379 case TEGRA30_AHUB_APBIF_INT_MASK:
380 case TEGRA30_AHUB_I2S_INT_STATUS:
381 case TEGRA30_AHUB_DAM_INT_STATUS:
382 case TEGRA30_AHUB_SPDIF_INT_STATUS:
383 case TEGRA30_AHUB_APBIF_INT_STATUS:
384 case TEGRA30_AHUB_I2S_INT_SOURCE:
385 case TEGRA30_AHUB_DAM_INT_SOURCE:
386 case TEGRA30_AHUB_SPDIF_INT_SOURCE:
387 case TEGRA30_AHUB_APBIF_INT_SOURCE:
388 case TEGRA30_AHUB_I2S_INT_SET:
389 case TEGRA30_AHUB_DAM_INT_SET:
390 case TEGRA30_AHUB_SPDIF_INT_SET:
391 case TEGRA30_AHUB_APBIF_INT_SET:
392 return true;
393 default:
394 break;
1d198f26 395 }
be944d42
SW		 396
397 if (REG_IN_ARRAY(reg, CHANNEL_CTRL) ||
398 REG_IN_ARRAY(reg, CHANNEL_CLEAR) ||
399 REG_IN_ARRAY(reg, CHANNEL_STATUS) ||
400 REG_IN_ARRAY(reg, CHANNEL_TXFIFO) ||
401 REG_IN_ARRAY(reg, CHANNEL_RXFIFO) ||
402 REG_IN_ARRAY(reg, CIF_TX_CTRL) ||
403 REG_IN_ARRAY(reg, CIF_RX_CTRL) ||
404 REG_IN_ARRAY(reg, DAM_LIVE_STATUS))
405 return true;
406
407 return false;
408}
409
410static bool tegra30_ahub_apbif_volatile_reg(struct device *dev,
411 unsigned int reg)
412{
413 switch (reg) {
414 case TEGRA30_AHUB_CONFIG_LINK_CTRL:
415 case TEGRA30_AHUB_MISC_CTRL:
416 case TEGRA30_AHUB_APBDMA_LIVE_STATUS:
417 case TEGRA30_AHUB_I2S_LIVE_STATUS:
418 case TEGRA30_AHUB_SPDIF_LIVE_STATUS:
419 case TEGRA30_AHUB_I2S_INT_STATUS:
420 case TEGRA30_AHUB_DAM_INT_STATUS:
421 case TEGRA30_AHUB_SPDIF_INT_STATUS:
422 case TEGRA30_AHUB_APBIF_INT_STATUS:
423 case TEGRA30_AHUB_I2S_INT_SET:
424 case TEGRA30_AHUB_DAM_INT_SET:
425 case TEGRA30_AHUB_SPDIF_INT_SET:
426 case TEGRA30_AHUB_APBIF_INT_SET:
427 return true;
428 default:
429 break;
1d198f26 430 }
be944d42
SW		 431
432 if (REG_IN_ARRAY(reg, CHANNEL_CLEAR) ||
433 REG_IN_ARRAY(reg, CHANNEL_STATUS) ||
434 REG_IN_ARRAY(reg, CHANNEL_TXFIFO) ||
435 REG_IN_ARRAY(reg, CHANNEL_RXFIFO) ||
436 REG_IN_ARRAY(reg, DAM_LIVE_STATUS))
437 return true;
438
439 return false;
440}
441
442static bool tegra30_ahub_apbif_precious_reg(struct device *dev,
443 unsigned int reg)
444{
445 if (REG_IN_ARRAY(reg, CHANNEL_TXFIFO) ||
446 REG_IN_ARRAY(reg, CHANNEL_RXFIFO))
447 return true;
448
449 return false;
450}
451
452static const struct regmap_config tegra30_ahub_apbif_regmap_config = {
453 .name = "apbif",
454 .reg_bits = 32,
455 .val_bits = 32,
456 .reg_stride = 4,
457 .max_register = TEGRA30_AHUB_APBIF_INT_SET,
458 .writeable_reg = tegra30_ahub_apbif_wr_rd_reg,
459 .readable_reg = tegra30_ahub_apbif_wr_rd_reg,
460 .volatile_reg = tegra30_ahub_apbif_volatile_reg,
461 .precious_reg = tegra30_ahub_apbif_precious_reg,
462 .cache_type = REGCACHE_RBTREE,
463};
464
465static bool tegra30_ahub_ahub_wr_rd_reg(struct device *dev, unsigned int reg)
466{
467 if (REG_IN_ARRAY(reg, AUDIO_RX))
468 return true;
469
470 return false;
471}
472
473static const struct regmap_config tegra30_ahub_ahub_regmap_config = {
474 .name = "ahub",
475 .reg_bits = 32,
476 .val_bits = 32,
477 .reg_stride = 4,
478 .max_register = LAST_REG(AUDIO_RX),
479 .writeable_reg = tegra30_ahub_ahub_wr_rd_reg,
480 .readable_reg = tegra30_ahub_ahub_wr_rd_reg,
481 .cache_type = REGCACHE_RBTREE,
482};
483
95d36075 484static struct tegra30_ahub_soc_data soc_data_tegra30 = {
5185e0ac 485 .mod_list_mask = MOD_LIST_MASK_TEGRA30,
5e049fce 486 .set_audio_cif = tegra30_ahub_set_cif,
95d36075
SW		 487};
488
489static struct tegra30_ahub_soc_data soc_data_tegra114 = {
5185e0ac 490 .mod_list_mask = MOD_LIST_MASK_TEGRA114,
5e049fce
SW		 491 .set_audio_cif = tegra30_ahub_set_cif,
492};
493
494static struct tegra30_ahub_soc_data soc_data_tegra124 = {
5185e0ac 495 .mod_list_mask = MOD_LIST_MASK_TEGRA114,
5e049fce 496 .set_audio_cif = tegra124_ahub_set_cif,
95d36075
SW		 497};
498
499static const struct of_device_id tegra30_ahub_of_match[] = {
5e049fce 500 { .compatible = "nvidia,tegra124-ahub", .data = &soc_data_tegra124 },
95d36075
SW		 501 { .compatible = "nvidia,tegra114-ahub", .data = &soc_data_tegra114 },
502 { .compatible = "nvidia,tegra30-ahub", .data = &soc_data_tegra30 },
503 {},
504};
505
4652a0d0 506static int tegra30_ahub_probe(struct platform_device *pdev)
be944d42 507{
95d36075
SW		 508 const struct of_device_id *match;
509 const struct tegra30_ahub_soc_data *soc_data;
5185e0ac 510 struct reset_control *rst;
be944d42
SW		 511 int i;
512 struct resource *res0, *res1, *region;
be944d42
SW		 513 void __iomem *regs_apbif, *regs_ahub;
514 int ret = 0;
515
516 if (ahub)
517 return -ENODEV;
518
95d36075
SW		 519 match = of_match_device(tegra30_ahub_of_match, &pdev->dev);
520 if (!match)
521 return -EINVAL;
522 soc_data = match->data;
523
be944d42
SW		 524 /*
525 * The AHUB hosts a register bus: the "configlink". For this to
526 * operate correctly, all devices on this bus must be out of reset.
527 * Ensure that here.
528 */
5185e0ac
SW		 529 for (i = 0; i < ARRAY_SIZE(configlink_mods); i++) {
530 if (!(configlink_mods[i].mod_list_mask &
531 soc_data->mod_list_mask))
95d36075 532 continue;
5185e0ac
SW		 533
534 rst = reset_control_get(&pdev->dev,
535 configlink_mods[i].rst_name);
536 if (IS_ERR(rst)) {
537 dev_err(&pdev->dev, "Can't get reset %s\n",
538 configlink_mods[i].rst_name);
539 ret = PTR_ERR(rst);
be944d42
SW		 540 goto err;
541 }
5185e0ac
SW		 542
543 ret = reset_control_deassert(rst);
544 reset_control_put(rst);
545 if (ret)
546 goto err;
be944d42
SW		 547 }
548
549 ahub = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_ahub),
550 GFP_KERNEL);
551 if (!ahub) {
552 dev_err(&pdev->dev, "Can't allocate tegra30_ahub\n");
553 ret = -ENOMEM;
554 goto err;
555 }
556 dev_set_drvdata(&pdev->dev, ahub);
557
5e049fce 558 ahub->soc_data = soc_data;
be944d42
SW		 559 ahub->dev = &pdev->dev;
560
561 ahub->clk_d_audio = clk_get(&pdev->dev, "d_audio");
562 if (IS_ERR(ahub->clk_d_audio)) {
563 dev_err(&pdev->dev, "Can't retrieve ahub d_audio clock\n");
564 ret = PTR_ERR(ahub->clk_d_audio);
565 goto err;
566 }
567
568 ahub->clk_apbif = clk_get(&pdev->dev, "apbif");
569 if (IS_ERR(ahub->clk_apbif)) {
570 dev_err(&pdev->dev, "Can't retrieve ahub apbif clock\n");
571 ret = PTR_ERR(ahub->clk_apbif);
572 goto err_clk_put_d_audio;
573 }
574
be944d42
SW		 575 res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
576 if (!res0) {
577 dev_err(&pdev->dev, "No apbif memory resource\n");
578 ret = -ENODEV;
579 goto err_clk_put_apbif;
580 }
581
582 region = devm_request_mem_region(&pdev->dev, res0->start,
583 resource_size(res0), DRV_NAME);
584 if (!region) {
585 dev_err(&pdev->dev, "request region apbif failed\n");
586 ret = -EBUSY;
587 goto err_clk_put_apbif;
588 }
589 ahub->apbif_addr = res0->start;
590
591 regs_apbif = devm_ioremap(&pdev->dev, res0->start,
592 resource_size(res0));
593 if (!regs_apbif) {
594 dev_err(&pdev->dev, "ioremap apbif failed\n");
595 ret = -ENOMEM;
596 goto err_clk_put_apbif;
597 }
598
599 ahub->regmap_apbif = devm_regmap_init_mmio(&pdev->dev, regs_apbif,
600 &tegra30_ahub_apbif_regmap_config);
601 if (IS_ERR(ahub->regmap_apbif)) {
602 dev_err(&pdev->dev, "apbif regmap init failed\n");
603 ret = PTR_ERR(ahub->regmap_apbif);
604 goto err_clk_put_apbif;
605 }
606 regcache_cache_only(ahub->regmap_apbif, true);
607
608 res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
609 if (!res1) {
610 dev_err(&pdev->dev, "No ahub memory resource\n");
611 ret = -ENODEV;
612 goto err_clk_put_apbif;
613 }
614
615 region = devm_request_mem_region(&pdev->dev, res1->start,
616 resource_size(res1), DRV_NAME);
617 if (!region) {
618 dev_err(&pdev->dev, "request region ahub failed\n");
619 ret = -EBUSY;
620 goto err_clk_put_apbif;
621 }
622
623 regs_ahub = devm_ioremap(&pdev->dev, res1->start,
624 resource_size(res1));
625 if (!regs_ahub) {
626 dev_err(&pdev->dev, "ioremap ahub failed\n");
627 ret = -ENOMEM;
628 goto err_clk_put_apbif;
629 }
630
631 ahub->regmap_ahub = devm_regmap_init_mmio(&pdev->dev, regs_ahub,
632 &tegra30_ahub_ahub_regmap_config);
633 if (IS_ERR(ahub->regmap_ahub)) {
634 dev_err(&pdev->dev, "ahub regmap init failed\n");
635 ret = PTR_ERR(ahub->regmap_ahub);
636 goto err_clk_put_apbif;
637 }
638 regcache_cache_only(ahub->regmap_ahub, true);
639
640 pm_runtime_enable(&pdev->dev);
641 if (!pm_runtime_enabled(&pdev->dev)) {
642 ret = tegra30_ahub_runtime_resume(&pdev->dev);
643 if (ret)
644 goto err_pm_disable;
645 }
646
79cf5918 647 of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
be944d42
SW		 648
649 return 0;
650
651err_pm_disable:
652 pm_runtime_disable(&pdev->dev);
653err_clk_put_apbif:
654 clk_put(ahub->clk_apbif);
655err_clk_put_d_audio:
656 clk_put(ahub->clk_d_audio);
ecb2c174 657 ahub = NULL;
be944d42
SW		 658err:
659 return ret;
660}
661
4652a0d0 662static int tegra30_ahub_remove(struct platform_device *pdev)
be944d42
SW		 663{
664 if (!ahub)
665 return -ENODEV;
666
667 pm_runtime_disable(&pdev->dev);
668 if (!pm_runtime_status_suspended(&pdev->dev))
669 tegra30_ahub_runtime_suspend(&pdev->dev);
670
671 clk_put(ahub->clk_apbif);
672 clk_put(ahub->clk_d_audio);
673
ecb2c174 674 ahub = NULL;
be944d42
SW		 675
676 return 0;
677}
678
2f41a3f4
SW		 679#ifdef CONFIG_PM_SLEEP
680static int tegra30_ahub_suspend(struct device *dev)
681{
682 regcache_mark_dirty(ahub->regmap_ahub);
683 regcache_mark_dirty(ahub->regmap_apbif);
684
685 return 0;
686}
687
688static int tegra30_ahub_resume(struct device *dev)
689{
690 int ret;
691
249e66c3
SW		 692 ret = pm_runtime_get_sync(dev);
693 if (ret < 0)
694 return ret;
2f41a3f4
SW		 695 ret = regcache_sync(ahub->regmap_ahub);
696 ret |= regcache_sync(ahub->regmap_apbif);
249e66c3 697 pm_runtime_put(dev);
2f41a3f4
SW		 698
699 return ret;
700}
701#endif
702
f6e65744 703static const struct dev_pm_ops tegra30_ahub_pm_ops = {
be944d42
SW		 704 SET_RUNTIME_PM_OPS(tegra30_ahub_runtime_suspend,
705 tegra30_ahub_runtime_resume, NULL)
2f41a3f4 706 SET_SYSTEM_SLEEP_PM_OPS(tegra30_ahub_suspend, tegra30_ahub_resume)
be944d42
SW		 707};
708
709static struct platform_driver tegra30_ahub_driver = {
710 .probe = tegra30_ahub_probe,
4652a0d0 711 .remove = tegra30_ahub_remove,
be944d42
SW		 712 .driver = {
713 .name = DRV_NAME,
714 .owner = THIS_MODULE,
715 .of_match_table = tegra30_ahub_of_match,
716 .pm = &tegra30_ahub_pm_ops,
717 },
718};
719module_platform_driver(tegra30_ahub_driver);
720
5e049fce
SW		 721void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg,
722 struct tegra30_ahub_cif_conf *conf)
723{
724 unsigned int value;
725
726 value = (conf->threshold <<
727 TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
728 ((conf->audio_channels - 1) <<
729 TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
730 ((conf->client_channels - 1) <<
731 TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
732 (conf->audio_bits <<
733 TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
734 (conf->client_bits <<
735 TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
736 (conf->expand <<
737 TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) |
738 (conf->stereo_conv <<
739 TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) |
740 (conf->replicate <<
741 TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT) |
742 (conf->direction <<
743 TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) |
744 (conf->truncate <<
745 TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) |
746 (conf->mono_conv <<
747 TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT);
748
749 regmap_write(regmap, reg, value);
750}
751EXPORT_SYMBOL_GPL(tegra30_ahub_set_cif);
752
753void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg,
754 struct tegra30_ahub_cif_conf *conf)
755{
756 unsigned int value;
757
758 value = (conf->threshold <<
759 TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
760 ((conf->audio_channels - 1) <<
761 TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
762 ((conf->client_channels - 1) <<
763 TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
764 (conf->audio_bits <<
765 TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
766 (conf->client_bits <<
767 TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
768 (conf->expand <<
769 TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) |
770 (conf->stereo_conv <<
771 TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) |
772 (conf->replicate <<
773 TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT) |
774 (conf->direction <<
775 TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) |
776 (conf->truncate <<
777 TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) |
778 (conf->mono_conv <<
779 TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT);
780
781 regmap_write(regmap, reg, value);
782}
783EXPORT_SYMBOL_GPL(tegra124_ahub_set_cif);
784
be944d42
SW		 785MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
786MODULE_DESCRIPTION("Tegra30 AHUB driver");
787MODULE_LICENSE("GPL v2");
788MODULE_ALIAS("platform:" DRV_NAME);
69c5b753 789MODULE_DEVICE_TABLE(of, tegra30_ahub_of_match);
Linux kernel - Deliverables
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