[deliverable/linux.git] / sound / soc / tegra / tegra30_i2s.c

/*
 * tegra30_i2s.c - Tegra30 I2S driver
 *
 * Author: Stephen Warren <swarren@nvidia.com>
 * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
 *
 * Based on code copyright/by:
 *
 * Copyright (c) 2009-2010, NVIDIA Corporation.
 * Scott Peterson <speterson@nvidia.com>
 *
 * Copyright (C) 2010 Google, Inc.
 * Iliyan Malchev <malchev@google.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include "tegra30_ahub.h"
#include "tegra30_i2s.h"

#define DRV_NAME "tegra30-i2s"

static inline void tegra30_i2s_write(struct tegra30_i2s *i2s, u32 reg, u32 val)
{
	regmap_write(i2s->regmap, reg, val);
}

static inline u32 tegra30_i2s_read(struct tegra30_i2s *i2s, u32 reg)
{
	u32 val;
	regmap_read(i2s->regmap, reg, &val);
	return val;
}

static int tegra30_i2s_runtime_suspend(struct device *dev)
{
	struct tegra30_i2s *i2s = dev_get_drvdata(dev);

	regcache_cache_only(i2s->regmap, true);

	clk_disable_unprepare(i2s->clk_i2s);

	return 0;
}

static int tegra30_i2s_runtime_resume(struct device *dev)
{
	struct tegra30_i2s *i2s = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(i2s->clk_i2s);
	if (ret) {
		dev_err(dev, "clk_enable failed: %d\n", ret);
		return ret;
	}

	regcache_cache_only(i2s->regmap, false);

	return 0;
}

int tegra30_i2s_startup(struct snd_pcm_substream *substream,
			struct snd_soc_dai *dai)
{
	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	int ret;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
					&i2s->playback_dma_data.addr,
					&i2s->playback_dma_data.req_sel);
		i2s->playback_dma_data.wrap = 4;
		i2s->playback_dma_data.width = 32;
		tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
					       i2s->playback_fifo_cif);
	} else {
		ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
					&i2s->capture_dma_data.addr,
					&i2s->capture_dma_data.req_sel);
		i2s->capture_dma_data.wrap = 4;
		i2s->capture_dma_data.width = 32;
		tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
					       i2s->capture_i2s_cif);
	}

	return ret;
}

void tegra30_i2s_shutdown(struct snd_pcm_substream *substream,
			struct snd_soc_dai *dai)
{
	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
		tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
	} else {
		tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
		tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
	}
}

static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
				unsigned int fmt)
{
	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		break;
	default:
		return -EINVAL;
	}

	i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_MASTER_ENABLE;
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		i2s->reg_ctrl |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		break;
	default:
		return -EINVAL;
	}

	i2s->reg_ctrl &= ~(TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
			   TEGRA30_I2S_CTRL_LRCK_MASK);
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_DSP_A:
		i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
		i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_DSP_B:
		i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
		i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
		break;
	case SND_SOC_DAIFMT_I2S:
		i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
		i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
		i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
		i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct device *dev = substream->pcm->card->dev;
	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	u32 val;
	int ret, sample_size, srate, i2sclock, bitcnt;

	if (params_channels(params) != 2)
		return -EINVAL;

	i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_16;
		sample_size = 16;
		break;
	default:
		return -EINVAL;
	}

	srate = params_rate(params);

	/* Final "* 2" required by Tegra hardware */
	i2sclock = srate * params_channels(params) * sample_size * 2;

	bitcnt = (i2sclock / (2 * srate)) - 1;
	if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
		return -EINVAL;

	ret = clk_set_rate(i2s->clk_i2s, i2sclock);
	if (ret) {
		dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
		return ret;
	}

	val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;

	if (i2sclock % (2 * srate))
		val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;

	tegra30_i2s_write(i2s, TEGRA30_I2S_TIMING, val);

	val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
	      (1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
	      (1 << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
	      TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
	      TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
		tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
	} else {
		val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
		tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_TX_CTRL, val);
	}

	val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
	      (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
	tegra30_i2s_write(i2s, TEGRA30_I2S_OFFSET, val);

	return 0;
}

static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
{
	tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
	i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
	tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
}

static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
{
	tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
	i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
	tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
}

static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
{
	tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
	i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
	tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
}

static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
{
	tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
	i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
	tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
}

static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
				struct snd_soc_dai *dai)
{
	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_RESUME:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra30_i2s_start_playback(i2s);
		else
			tegra30_i2s_start_capture(i2s);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	case SNDRV_PCM_TRIGGER_SUSPEND:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra30_i2s_stop_playback(i2s);
		else
			tegra30_i2s_stop_capture(i2s);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int tegra30_i2s_probe(struct snd_soc_dai *dai)
{
	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	dai->capture_dma_data = &i2s->capture_dma_data;
	dai->playback_dma_data = &i2s->playback_dma_data;

	return 0;
}

static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
	.startup	= tegra30_i2s_startup,
	.shutdown	= tegra30_i2s_shutdown,
	.set_fmt	= tegra30_i2s_set_fmt,
	.hw_params	= tegra30_i2s_hw_params,
	.trigger	= tegra30_i2s_trigger,
};

static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
	.probe = tegra30_i2s_probe,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops = &tegra30_i2s_dai_ops,
	.symmetric_rates = 1,
};

static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA30_I2S_CTRL:
	case TEGRA30_I2S_TIMING:
	case TEGRA30_I2S_OFFSET:
	case TEGRA30_I2S_CH_CTRL:
	case TEGRA30_I2S_SLOT_CTRL:
	case TEGRA30_I2S_CIF_RX_CTRL:
	case TEGRA30_I2S_CIF_TX_CTRL:
	case TEGRA30_I2S_FLOWCTL:
	case TEGRA30_I2S_TX_STEP:
	case TEGRA30_I2S_FLOW_STATUS:
	case TEGRA30_I2S_FLOW_TOTAL:
	case TEGRA30_I2S_FLOW_OVER:
	case TEGRA30_I2S_FLOW_UNDER:
	case TEGRA30_I2S_LCOEF_1_4_0:
	case TEGRA30_I2S_LCOEF_1_4_1:
	case TEGRA30_I2S_LCOEF_1_4_2:
	case TEGRA30_I2S_LCOEF_1_4_3:
	case TEGRA30_I2S_LCOEF_1_4_4:
	case TEGRA30_I2S_LCOEF_1_4_5:
	case TEGRA30_I2S_LCOEF_2_4_0:
	case TEGRA30_I2S_LCOEF_2_4_1:
	case TEGRA30_I2S_LCOEF_2_4_2:
		return true;
	default:
		return false;
	};
}

static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA30_I2S_FLOW_STATUS:
	case TEGRA30_I2S_FLOW_TOTAL:
	case TEGRA30_I2S_FLOW_OVER:
	case TEGRA30_I2S_FLOW_UNDER:
		return true;
	default:
		return false;
	};
}

static const struct regmap_config tegra30_i2s_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = TEGRA30_I2S_LCOEF_2_4_2,
	.writeable_reg = tegra30_i2s_wr_rd_reg,
	.readable_reg = tegra30_i2s_wr_rd_reg,
	.volatile_reg = tegra30_i2s_volatile_reg,
	.cache_type = REGCACHE_RBTREE,
};

static __devinit int tegra30_i2s_platform_probe(struct platform_device *pdev)
{
	struct tegra30_i2s *i2s;
	u32 cif_ids[2];
	struct resource *mem, *memregion;
	void __iomem *regs;
	int ret;

	i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
	if (!i2s) {
		dev_err(&pdev->dev, "Can't allocate tegra30_i2s\n");
		ret = -ENOMEM;
		goto err;
	}
	dev_set_drvdata(&pdev->dev, i2s);

	i2s->dai = tegra30_i2s_dai_template;
	i2s->dai.name = dev_name(&pdev->dev);

	ret = of_property_read_u32_array(pdev->dev.of_node,
					 "nvidia,ahub-cif-ids", cif_ids,
					 ARRAY_SIZE(cif_ids));
	if (ret < 0)
		goto err;

	i2s->playback_i2s_cif = cif_ids[0];
	i2s->capture_i2s_cif = cif_ids[1];

	i2s->clk_i2s = clk_get(&pdev->dev, NULL);
	if (IS_ERR(i2s->clk_i2s)) {
		dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
		ret = PTR_ERR(i2s->clk_i2s);
		goto err;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "No memory resource\n");
		ret = -ENODEV;
		goto err_clk_put;
	}

	memregion = devm_request_mem_region(&pdev->dev, mem->start,
					    resource_size(mem), DRV_NAME);
	if (!memregion) {
		dev_err(&pdev->dev, "Memory region already claimed\n");
		ret = -EBUSY;
		goto err_clk_put;
	}

	regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
	if (!regs) {
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -ENOMEM;
		goto err_clk_put;
	}

	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
					    &tegra30_i2s_regmap_config);
	if (IS_ERR(i2s->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		ret = PTR_ERR(i2s->regmap);
		goto err_clk_put;
	}
	regcache_cache_only(i2s->regmap, true);

	pm_runtime_enable(&pdev->dev);
	if (!pm_runtime_enabled(&pdev->dev)) {
		ret = tegra30_i2s_runtime_resume(&pdev->dev);
		if (ret)
			goto err_pm_disable;
	}

	ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
	if (ret) {
		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
		ret = -ENOMEM;
		goto err_suspend;
	}

	ret = tegra_pcm_platform_register(&pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
		goto err_unregister_dai;
	}

	return 0;

err_unregister_dai:
	snd_soc_unregister_dai(&pdev->dev);
err_suspend:
	if (!pm_runtime_status_suspended(&pdev->dev))
		tegra30_i2s_runtime_suspend(&pdev->dev);
err_pm_disable:
	pm_runtime_disable(&pdev->dev);
err_clk_put:
	clk_put(i2s->clk_i2s);
err:
	return ret;
}

static int __devexit tegra30_i2s_platform_remove(struct platform_device *pdev)
{
	struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		tegra30_i2s_runtime_suspend(&pdev->dev);

	tegra_pcm_platform_unregister(&pdev->dev);
	snd_soc_unregister_dai(&pdev->dev);

	clk_put(i2s->clk_i2s);

	return 0;
}

static const struct of_device_id tegra30_i2s_of_match[] __devinitconst = {
	{ .compatible = "nvidia,tegra30-i2s", },
	{},
};

static const struct dev_pm_ops tegra30_i2s_pm_ops __devinitconst = {
	SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
			   tegra30_i2s_runtime_resume, NULL)
};

static struct platform_driver tegra30_i2s_driver = {
	.driver = {
		.name = DRV_NAME,
		.owner = THIS_MODULE,
		.of_match_table = tegra30_i2s_of_match,
		.pm = &tegra30_i2s_pm_ops,
	},
	.probe = tegra30_i2s_platform_probe,
	.remove = __devexit_p(tegra30_i2s_platform_remove),
};
module_platform_driver(tegra30_i2s_driver);

MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);
Commit	Line	Data
4fb0384f SW	1	/*
	2	* tegra30_i2s.c - Tegra30 I2S driver
	3	*
	4	* Author: Stephen Warren <swarren@nvidia.com>
	5	* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
	6	*
	7	* Based on code copyright/by:
	8	*
	9	* Copyright (c) 2009-2010, NVIDIA Corporation.
	10	* Scott Peterson <speterson@nvidia.com>
	11	*
	12	* Copyright (C) 2010 Google, Inc.
	13	* Iliyan Malchev <malchev@google.com>
	14	*
	15	* This program is free software; you can redistribute it and/or modify it
	16	* under the terms and conditions of the GNU General Public License,
	17	* version 2, as published by the Free Software Foundation.
	18	*
	19	* This program is distributed in the hope it will be useful, but WITHOUT
	20	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	21	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	22	* more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	26	*/
	27
	28	#include <linux/clk.h>
	29	#include <linux/device.h>
	30	#include <linux/io.h>
	31	#include <linux/module.h>
	32	#include <linux/of.h>
	33	#include <linux/platform_device.h>
	34	#include <linux/pm_runtime.h>
	35	#include <linux/regmap.h>
	36	#include <linux/slab.h>
	37	#include <sound/core.h>
	38	#include <sound/pcm.h>
	39	#include <sound/pcm_params.h>
	40	#include <sound/soc.h>
	41
	42	#include "tegra30_ahub.h"
	43	#include "tegra30_i2s.h"
	44
	45	#define DRV_NAME "tegra30-i2s"
	46
	47	static inline void tegra30_i2s_write(struct tegra30_i2s *i2s, u32 reg, u32 val)
	48	{
	49	regmap_write(i2s->regmap, reg, val);
	50	}
	51
	52	static inline u32 tegra30_i2s_read(struct tegra30_i2s *i2s, u32 reg)
	53	{
	54	u32 val;
	55	regmap_read(i2s->regmap, reg, &val);
	56	return val;
	57	}
	58
	59	static int tegra30_i2s_runtime_suspend(struct device *dev)
	60	{
	61	struct tegra30_i2s *i2s = dev_get_drvdata(dev);
	62
	63	regcache_cache_only(i2s->regmap, true);
	64
65d2bdd3	65	clk_disable_unprepare(i2s->clk_i2s);
4fb0384f SW	66
	67	return 0;
	68	}
	69
	70	static int tegra30_i2s_runtime_resume(struct device *dev)
	71	{
	72	struct tegra30_i2s *i2s = dev_get_drvdata(dev);
	73	int ret;
	74
65d2bdd3	75	ret = clk_prepare_enable(i2s->clk_i2s);
4fb0384f SW	76	if (ret) {
	77	dev_err(dev, "clk_enable failed: %d\n", ret);
	78	return ret;
	79	}
	80
	81	regcache_cache_only(i2s->regmap, false);
	82
	83	return 0;
	84	}
	85
	86	int tegra30_i2s_startup(struct snd_pcm_substream *substream,
	87	struct snd_soc_dai *dai)
	88	{
	89	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	90	int ret;
	91
	92	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	93	ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
	94	&i2s->playback_dma_data.addr,
	95	&i2s->playback_dma_data.req_sel);
	96	i2s->playback_dma_data.wrap = 4;
	97	i2s->playback_dma_data.width = 32;
	98	tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
	99	i2s->playback_fifo_cif);
	100	} else {
	101	ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
	102	&i2s->capture_dma_data.addr,
	103	&i2s->capture_dma_data.req_sel);
	104	i2s->capture_dma_data.wrap = 4;
	105	i2s->capture_dma_data.width = 32;
	106	tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
	107	i2s->capture_i2s_cif);
	108	}
	109
	110	return ret;
	111	}
	112
	113	void tegra30_i2s_shutdown(struct snd_pcm_substream *substream,
	114	struct snd_soc_dai *dai)
	115	{
	116	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	117
	118	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	119	tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
	120	tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
	121	} else {
	122	tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
	123	tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
	124	}
	125	}
	126
	127	static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
	128	unsigned int fmt)
	129	{
	130	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	131
	132	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	133	case SND_SOC_DAIFMT_NB_NF:
	134	break;
	135	default:
	136	return -EINVAL;
	137	}
	138
	139	i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_MASTER_ENABLE;
140	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
141	case SND_SOC_DAIFMT_CBS_CFS:
142	i2s->reg_ctrl \|= TEGRA30_I2S_CTRL_MASTER_ENABLE;
143	break;
144	case SND_SOC_DAIFMT_CBM_CFM:
145	break;
146	default:
147	return -EINVAL;
148	}
149
150	i2s->reg_ctrl &= ~(TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK \|
151	TEGRA30_I2S_CTRL_LRCK_MASK);
152	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
153	case SND_SOC_DAIFMT_DSP_A:
154	i2s->reg_ctrl \|= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
155	i2s->reg_ctrl \|= TEGRA30_I2S_CTRL_LRCK_L_LOW;
156	break;
157	case SND_SOC_DAIFMT_DSP_B:
158	i2s->reg_ctrl \|= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
159	i2s->reg_ctrl \|= TEGRA30_I2S_CTRL_LRCK_R_LOW;
160	break;
161	case SND_SOC_DAIFMT_I2S:
162	i2s->reg_ctrl \|= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
163	i2s->reg_ctrl \|= TEGRA30_I2S_CTRL_LRCK_L_LOW;
164	break;
165	case SND_SOC_DAIFMT_RIGHT_J:
166	i2s->reg_ctrl \|= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
167	i2s->reg_ctrl \|= TEGRA30_I2S_CTRL_LRCK_L_LOW;
168	break;
169	case SND_SOC_DAIFMT_LEFT_J:
170	i2s->reg_ctrl \|= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
171	i2s->reg_ctrl \|= TEGRA30_I2S_CTRL_LRCK_L_LOW;
172	break;
173	default:
174	return -EINVAL;
175	}
176
177	return 0;
178	}
179
180	static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
181	struct snd_pcm_hw_params *params,
182	struct snd_soc_dai *dai)
183	{
184	struct device *dev = substream->pcm->card->dev;
185	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
186	u32 val;
187	int ret, sample_size, srate, i2sclock, bitcnt;
188
189	if (params_channels(params) != 2)
190	return -EINVAL;
191
192	i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
193	switch (params_format(params)) {
194	case SNDRV_PCM_FORMAT_S16_LE:
195	i2s->reg_ctrl \|= TEGRA30_I2S_CTRL_BIT_SIZE_16;
196	sample_size = 16;
197	break;
198	default:
199	return -EINVAL;
200	}
201
202	srate = params_rate(params);
203
204	/* Final "* 2" required by Tegra hardware */
205	i2sclock = srate * params_channels(params) * sample_size * 2;
206
207	bitcnt = (i2sclock / (2 * srate)) - 1;
208	if (bitcnt < 0 \|\| bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
209	return -EINVAL;
210
211	ret = clk_set_rate(i2s->clk_i2s, i2sclock);
212	if (ret) {
213	dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
214	return ret;
215	}
216
217	val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
218
219	if (i2sclock % (2 * srate))
220	val \|= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
221
222	tegra30_i2s_write(i2s, TEGRA30_I2S_TIMING, val);
223
224	val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) \|
225	(1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) \|
226	(1 << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) \|
227	TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 \|
228	TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16;
229
230	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
231	val \|= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
232	tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
233	} else {
234	val \|= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
235	tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_TX_CTRL, val);
236	}
237
238	val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) \|
239	(1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
240	tegra30_i2s_write(i2s, TEGRA30_I2S_OFFSET, val);
241
242	return 0;
243	}
244
245	static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
246	{
247	tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
248	i2s->reg_ctrl \|= TEGRA30_I2S_CTRL_XFER_EN_TX;
249	tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
250	}
251
252	static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
253	{
254	tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
255	i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
256	tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
257	}
258
259	static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
260	{
261	tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
262	i2s->reg_ctrl \|= TEGRA30_I2S_CTRL_XFER_EN_RX;
263	tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
264	}
265
266	static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
267	{
268	tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
269	i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
270	tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
271	}
272
273	static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
274	struct snd_soc_dai *dai)
275	{
276	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
277
278	switch (cmd) {
279	case SNDRV_PCM_TRIGGER_START:
280	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
281	case SNDRV_PCM_TRIGGER_RESUME:
282	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
283	tegra30_i2s_start_playback(i2s);
284	else
285	tegra30_i2s_start_capture(i2s);
286	break;
287	case SNDRV_PCM_TRIGGER_STOP:
288	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
289	case SNDRV_PCM_TRIGGER_SUSPEND:
290	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
291	tegra30_i2s_stop_playback(i2s);
292	else
293	tegra30_i2s_stop_capture(i2s);
294	break;
295	default:
296	return -EINVAL;
297	}
298
299	return 0;
300	}
301
302	static int tegra30_i2s_probe(struct snd_soc_dai *dai)
303	{
304	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
305
306	dai->capture_dma_data = &i2s->capture_dma_data;
307	dai->playback_dma_data = &i2s->playback_dma_data;
308
309	return 0;
310	}
311
312	static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
313	.startup = tegra30_i2s_startup,
314	.shutdown = tegra30_i2s_shutdown,
315	.set_fmt = tegra30_i2s_set_fmt,
316	.hw_params = tegra30_i2s_hw_params,
317	.trigger = tegra30_i2s_trigger,
318	};
319
320	static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
321	.probe = tegra30_i2s_probe,
322	.playback = {
323	.channels_min = 2,
324	.channels_max = 2,
325	.rates = SNDRV_PCM_RATE_8000_96000,
326	.formats = SNDRV_PCM_FMTBIT_S16_LE,
327	},
328	.capture = {
329	.channels_min = 2,
330	.channels_max = 2,
331	.rates = SNDRV_PCM_RATE_8000_96000,
332	.formats = SNDRV_PCM_FMTBIT_S16_LE,
333	},
334	.ops = &tegra30_i2s_dai_ops,
335	.symmetric_rates = 1,
336	};
337
338	static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
339	{
340	switch (reg) {
341	case TEGRA30_I2S_CTRL:
342	case TEGRA30_I2S_TIMING:
343	case TEGRA30_I2S_OFFSET:
344	case TEGRA30_I2S_CH_CTRL:
345	case TEGRA30_I2S_SLOT_CTRL:
346	case TEGRA30_I2S_CIF_RX_CTRL:
347	case TEGRA30_I2S_CIF_TX_CTRL:
348	case TEGRA30_I2S_FLOWCTL:
349	case TEGRA30_I2S_TX_STEP:
350	case TEGRA30_I2S_FLOW_STATUS:
351	case TEGRA30_I2S_FLOW_TOTAL:
352	case TEGRA30_I2S_FLOW_OVER:
353	case TEGRA30_I2S_FLOW_UNDER:
354	case TEGRA30_I2S_LCOEF_1_4_0:
355	case TEGRA30_I2S_LCOEF_1_4_1:
356	case TEGRA30_I2S_LCOEF_1_4_2:
357	case TEGRA30_I2S_LCOEF_1_4_3:
358	case TEGRA30_I2S_LCOEF_1_4_4:
359	case TEGRA30_I2S_LCOEF_1_4_5:
360	case TEGRA30_I2S_LCOEF_2_4_0:
361	case TEGRA30_I2S_LCOEF_2_4_1:
362	case TEGRA30_I2S_LCOEF_2_4_2:
363	return true;
364	default:
365	return false;
366	};
367	}
368
369	static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
370	{
371	switch (reg) {
372	case TEGRA30_I2S_FLOW_STATUS:
373	case TEGRA30_I2S_FLOW_TOTAL:
374	case TEGRA30_I2S_FLOW_OVER:
375	case TEGRA30_I2S_FLOW_UNDER:
376	return true;
377	default:
378	return false;
379	};
380	}
381
382	static const struct regmap_config tegra30_i2s_regmap_config = {
383	.reg_bits = 32,
384	.reg_stride = 4,
385	.val_bits = 32,
386	.max_register = TEGRA30_I2S_LCOEF_2_4_2,
387	.writeable_reg = tegra30_i2s_wr_rd_reg,
388	.readable_reg = tegra30_i2s_wr_rd_reg,
389	.volatile_reg = tegra30_i2s_volatile_reg,
390	.cache_type = REGCACHE_RBTREE,
391	};
392
393	static __devinit int tegra30_i2s_platform_probe(struct platform_device *pdev)
394	{
395	struct tegra30_i2s *i2s;
396	u32 cif_ids[2];
397	struct resource mem, memregion;
398	void __iomem *regs;
399	int ret;
400
401	i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
402	if (!i2s) {
403	dev_err(&pdev->dev, "Can't allocate tegra30_i2s\n");
404	ret = -ENOMEM;
405	goto err;
406	}
407	dev_set_drvdata(&pdev->dev, i2s);
408
409	i2s->dai = tegra30_i2s_dai_template;
410	i2s->dai.name = dev_name(&pdev->dev);
411
412	ret = of_property_read_u32_array(pdev->dev.of_node,
413	"nvidia,ahub-cif-ids", cif_ids,
414	ARRAY_SIZE(cif_ids));
415	if (ret < 0)
416	goto err;
417
418	i2s->playback_i2s_cif = cif_ids[0];
419	i2s->capture_i2s_cif = cif_ids[1];
420
421	i2s->clk_i2s = clk_get(&pdev->dev, NULL);
422	if (IS_ERR(i2s->clk_i2s)) {
423	dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
424	ret = PTR_ERR(i2s->clk_i2s);
425	goto err;
426	}
427
428	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
429	if (!mem) {
430	dev_err(&pdev->dev, "No memory resource\n");
431	ret = -ENODEV;
432	goto err_clk_put;
433	}
434
435	memregion = devm_request_mem_region(&pdev->dev, mem->start,
436	resource_size(mem), DRV_NAME);
437	if (!memregion) {
438	dev_err(&pdev->dev, "Memory region already claimed\n");
439	ret = -EBUSY;
440	goto err_clk_put;
441	}
442
443	regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
444	if (!regs) {
445	dev_err(&pdev->dev, "ioremap failed\n");
446	ret = -ENOMEM;
447	goto err_clk_put;
448	}
449
450	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
451	&tegra30_i2s_regmap_config);
452	if (IS_ERR(i2s->regmap)) {
453	dev_err(&pdev->dev, "regmap init failed\n");
454	ret = PTR_ERR(i2s->regmap);
455	goto err_clk_put;
456	}
457	regcache_cache_only(i2s->regmap, true);
458
459	pm_runtime_enable(&pdev->dev);
460	if (!pm_runtime_enabled(&pdev->dev)) {
461	ret = tegra30_i2s_runtime_resume(&pdev->dev);
462	if (ret)
463	goto err_pm_disable;
464	}
465
466	ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
467	if (ret) {
468	dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
469	ret = -ENOMEM;
470	goto err_suspend;
471	}
472
473	ret = tegra_pcm_platform_register(&pdev->dev);
474	if (ret) {
475	dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
476	goto err_unregister_dai;
477	}
478
479	return 0;
480
481	err_unregister_dai:
482	snd_soc_unregister_dai(&pdev->dev);
483	err_suspend:
484	if (!pm_runtime_status_suspended(&pdev->dev))
485	tegra30_i2s_runtime_suspend(&pdev->dev);
486	err_pm_disable:
487	pm_runtime_disable(&pdev->dev);
488	err_clk_put:
489	clk_put(i2s->clk_i2s);
490	err:
491	return ret;
492	}
493
494	static int __devexit tegra30_i2s_platform_remove(struct platform_device *pdev)
495	{
496	struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
497
498	pm_runtime_disable(&pdev->dev);
499	if (!pm_runtime_status_suspended(&pdev->dev))
500	tegra30_i2s_runtime_suspend(&pdev->dev);
501
502	tegra_pcm_platform_unregister(&pdev->dev);
503	snd_soc_unregister_dai(&pdev->dev);
504
505	clk_put(i2s->clk_i2s);
506
507	return 0;
508	}
509
510	static const struct of_device_id tegra30_i2s_of_match[] __devinitconst = {
511	{ .compatible = "nvidia,tegra30-i2s", },
512	{},
513	};
514
515	static const struct dev_pm_ops tegra30_i2s_pm_ops __devinitconst = {
516	SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
517	tegra30_i2s_runtime_resume, NULL)
518	};
519
520	static struct platform_driver tegra30_i2s_driver = {
521	.driver = {
522	.name = DRV_NAME,
523	.owner = THIS_MODULE,
524	.of_match_table = tegra30_i2s_of_match,
525	.pm = &tegra30_i2s_pm_ops,
526	},
527	.probe = tegra30_i2s_platform_probe,
528	.remove = __devexit_p(tegra30_i2s_platform_remove),
529	};
530	module_platform_driver(tegra30_i2s_driver);
531
532	MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
533	MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
534	MODULE_LICENSE("GPL");
535	MODULE_ALIAS("platform:" DRV_NAME);
536	MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);