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a50a399b SW |
1 | /* |
2 | * tegra_asoc_utils.c - Harmony machine ASoC driver | |
3 | * | |
4 | * Author: Stephen Warren <swarren@nvidia.com> | |
c2f6702d | 5 | * Copyright (C) 2010,2012 - NVIDIA, Inc. |
a50a399b SW |
6 | * |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * version 2 as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
19 | * 02110-1301 USA | |
20 | * | |
21 | */ | |
22 | ||
23 | #include <linux/clk.h> | |
d64e57ce | 24 | #include <linux/device.h> |
a50a399b SW |
25 | #include <linux/err.h> |
26 | #include <linux/kernel.h> | |
da155d5b | 27 | #include <linux/module.h> |
c2f6702d | 28 | #include <linux/of.h> |
a50a399b SW |
29 | |
30 | #include "tegra_asoc_utils.h" | |
31 | ||
d64e57ce | 32 | int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate, |
07541396 | 33 | int mclk) |
a50a399b SW |
34 | { |
35 | int new_baseclock; | |
07541396 | 36 | bool clk_change; |
a50a399b SW |
37 | int err; |
38 | ||
39 | switch (srate) { | |
40 | case 11025: | |
41 | case 22050: | |
42 | case 44100: | |
43 | case 88200: | |
c2f6702d SW |
44 | if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20) |
45 | new_baseclock = 56448000; | |
a7fc5d25 | 46 | else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30) |
c2f6702d | 47 | new_baseclock = 564480000; |
a7fc5d25 SW |
48 | else |
49 | new_baseclock = 282240000; | |
a50a399b SW |
50 | break; |
51 | case 8000: | |
52 | case 16000: | |
53 | case 32000: | |
54 | case 48000: | |
55 | case 64000: | |
56 | case 96000: | |
c2f6702d SW |
57 | if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20) |
58 | new_baseclock = 73728000; | |
a7fc5d25 | 59 | else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30) |
c2f6702d | 60 | new_baseclock = 552960000; |
a7fc5d25 SW |
61 | else |
62 | new_baseclock = 368640000; | |
a50a399b SW |
63 | break; |
64 | default: | |
65 | return -EINVAL; | |
66 | } | |
67 | ||
07541396 | 68 | clk_change = ((new_baseclock != data->set_baseclock) || |
d64e57ce | 69 | (mclk != data->set_mclk)); |
07541396 SW |
70 | if (!clk_change) |
71 | return 0; | |
a50a399b | 72 | |
d64e57ce SW |
73 | data->set_baseclock = 0; |
74 | data->set_mclk = 0; | |
a50a399b | 75 | |
65d2bdd3 PG |
76 | clk_disable_unprepare(data->clk_cdev1); |
77 | clk_disable_unprepare(data->clk_pll_a_out0); | |
78 | clk_disable_unprepare(data->clk_pll_a); | |
a50a399b | 79 | |
d64e57ce | 80 | err = clk_set_rate(data->clk_pll_a, new_baseclock); |
a50a399b | 81 | if (err) { |
d64e57ce | 82 | dev_err(data->dev, "Can't set pll_a rate: %d\n", err); |
a50a399b SW |
83 | return err; |
84 | } | |
85 | ||
d64e57ce | 86 | err = clk_set_rate(data->clk_pll_a_out0, mclk); |
a50a399b | 87 | if (err) { |
d64e57ce | 88 | dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err); |
a50a399b SW |
89 | return err; |
90 | } | |
91 | ||
c2f6702d | 92 | /* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */ |
a50a399b | 93 | |
65d2bdd3 | 94 | err = clk_prepare_enable(data->clk_pll_a); |
a50a399b | 95 | if (err) { |
d64e57ce | 96 | dev_err(data->dev, "Can't enable pll_a: %d\n", err); |
a50a399b SW |
97 | return err; |
98 | } | |
99 | ||
65d2bdd3 | 100 | err = clk_prepare_enable(data->clk_pll_a_out0); |
a50a399b | 101 | if (err) { |
d64e57ce | 102 | dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err); |
a50a399b SW |
103 | return err; |
104 | } | |
105 | ||
65d2bdd3 | 106 | err = clk_prepare_enable(data->clk_cdev1); |
a50a399b | 107 | if (err) { |
d64e57ce | 108 | dev_err(data->dev, "Can't enable cdev1: %d\n", err); |
a50a399b SW |
109 | return err; |
110 | } | |
111 | ||
d64e57ce SW |
112 | data->set_baseclock = new_baseclock; |
113 | data->set_mclk = mclk; | |
a50a399b SW |
114 | |
115 | return 0; | |
116 | } | |
a3cd50de | 117 | EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_rate); |
a50a399b | 118 | |
919ad49c LS |
119 | int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data) |
120 | { | |
121 | const int pll_rate = 73728000; | |
122 | const int ac97_rate = 24576000; | |
123 | int err; | |
124 | ||
125 | clk_disable_unprepare(data->clk_cdev1); | |
126 | clk_disable_unprepare(data->clk_pll_a_out0); | |
127 | clk_disable_unprepare(data->clk_pll_a); | |
128 | ||
129 | /* | |
130 | * AC97 rate is fixed at 24.576MHz and is used for both the host | |
131 | * controller and the external codec | |
132 | */ | |
133 | err = clk_set_rate(data->clk_pll_a, pll_rate); | |
134 | if (err) { | |
135 | dev_err(data->dev, "Can't set pll_a rate: %d\n", err); | |
136 | return err; | |
137 | } | |
138 | ||
139 | err = clk_set_rate(data->clk_pll_a_out0, ac97_rate); | |
140 | if (err) { | |
141 | dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err); | |
142 | return err; | |
143 | } | |
144 | ||
145 | /* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */ | |
146 | ||
147 | err = clk_prepare_enable(data->clk_pll_a); | |
148 | if (err) { | |
149 | dev_err(data->dev, "Can't enable pll_a: %d\n", err); | |
150 | return err; | |
151 | } | |
152 | ||
153 | err = clk_prepare_enable(data->clk_pll_a_out0); | |
154 | if (err) { | |
155 | dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err); | |
156 | return err; | |
157 | } | |
158 | ||
159 | err = clk_prepare_enable(data->clk_cdev1); | |
160 | if (err) { | |
161 | dev_err(data->dev, "Can't enable cdev1: %d\n", err); | |
162 | return err; | |
163 | } | |
164 | ||
165 | data->set_baseclock = pll_rate; | |
166 | data->set_mclk = ac97_rate; | |
167 | ||
168 | return 0; | |
169 | } | |
170 | EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_ac97_rate); | |
171 | ||
d64e57ce SW |
172 | int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data, |
173 | struct device *dev) | |
a50a399b SW |
174 | { |
175 | int ret; | |
176 | ||
d64e57ce SW |
177 | data->dev = dev; |
178 | ||
8127bf55 | 179 | if (of_machine_is_compatible("nvidia,tegra20")) |
c2f6702d SW |
180 | data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA20; |
181 | else if (of_machine_is_compatible("nvidia,tegra30")) | |
182 | data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA30; | |
110147c8 | 183 | else if (of_machine_is_compatible("nvidia,tegra114")) |
a7fc5d25 | 184 | data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA114; |
5e049fce SW |
185 | else if (of_machine_is_compatible("nvidia,tegra124")) |
186 | data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA124; | |
110147c8 | 187 | else { |
a7fc5d25 | 188 | dev_err(data->dev, "SoC unknown to Tegra ASoC utils\n"); |
c2f6702d | 189 | return -EINVAL; |
a7fc5d25 | 190 | } |
c2f6702d | 191 | |
110147c8 | 192 | data->clk_pll_a = clk_get(dev, "pll_a"); |
d64e57ce SW |
193 | if (IS_ERR(data->clk_pll_a)) { |
194 | dev_err(data->dev, "Can't retrieve clk pll_a\n"); | |
195 | ret = PTR_ERR(data->clk_pll_a); | |
a50a399b SW |
196 | goto err; |
197 | } | |
198 | ||
110147c8 | 199 | data->clk_pll_a_out0 = clk_get(dev, "pll_a_out0"); |
d64e57ce SW |
200 | if (IS_ERR(data->clk_pll_a_out0)) { |
201 | dev_err(data->dev, "Can't retrieve clk pll_a_out0\n"); | |
202 | ret = PTR_ERR(data->clk_pll_a_out0); | |
422650e6 | 203 | goto err_put_pll_a; |
a50a399b SW |
204 | } |
205 | ||
110147c8 | 206 | data->clk_cdev1 = clk_get(dev, "mclk"); |
d64e57ce SW |
207 | if (IS_ERR(data->clk_cdev1)) { |
208 | dev_err(data->dev, "Can't retrieve clk cdev1\n"); | |
209 | ret = PTR_ERR(data->clk_cdev1); | |
422650e6 | 210 | goto err_put_pll_a_out0; |
a50a399b SW |
211 | } |
212 | ||
a9005b67 SW |
213 | ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100); |
214 | if (ret) | |
215 | goto err_put_cdev1; | |
216 | ||
a50a399b SW |
217 | return 0; |
218 | ||
a9005b67 SW |
219 | err_put_cdev1: |
220 | clk_put(data->clk_cdev1); | |
422650e6 | 221 | err_put_pll_a_out0: |
d64e57ce | 222 | clk_put(data->clk_pll_a_out0); |
422650e6 | 223 | err_put_pll_a: |
d64e57ce | 224 | clk_put(data->clk_pll_a); |
a50a399b | 225 | err: |
a50a399b SW |
226 | return ret; |
227 | } | |
a3cd50de | 228 | EXPORT_SYMBOL_GPL(tegra_asoc_utils_init); |
a50a399b | 229 | |
d64e57ce | 230 | void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data) |
a50a399b | 231 | { |
d64e57ce SW |
232 | clk_put(data->clk_cdev1); |
233 | clk_put(data->clk_pll_a_out0); | |
234 | clk_put(data->clk_pll_a); | |
a50a399b | 235 | } |
a3cd50de | 236 | EXPORT_SYMBOL_GPL(tegra_asoc_utils_fini); |
a50a399b | 237 | |
a3cd50de SW |
238 | MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); |
239 | MODULE_DESCRIPTION("Tegra ASoC utility code"); | |
240 | MODULE_LICENSE("GPL"); |