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71f78e22 SW |
1 | /* |
2 | * tegra_i2s.c - Tegra I2S driver | |
3 | * | |
4 | * Author: Stephen Warren <swarren@nvidia.com> | |
518de86b | 5 | * Copyright (C) 2010,2012 - NVIDIA, Inc. |
71f78e22 SW |
6 | * |
7 | * Based on code copyright/by: | |
8 | * | |
9 | * Copyright (c) 2009-2010, NVIDIA Corporation. | |
10 | * Scott Peterson <speterson@nvidia.com> | |
11 | * | |
12 | * Copyright (C) 2010 Google, Inc. | |
13 | * Iliyan Malchev <malchev@google.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * version 2 as published by the Free Software Foundation. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
27 | * 02110-1301 USA | |
28 | * | |
29 | */ | |
30 | ||
31 | #include <linux/clk.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/debugfs.h> | |
34 | #include <linux/device.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/seq_file.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/io.h> | |
bf55499e | 39 | #include <linux/of.h> |
71f78e22 SW |
40 | #include <mach/iomap.h> |
41 | #include <sound/core.h> | |
42 | #include <sound/pcm.h> | |
43 | #include <sound/pcm_params.h> | |
44 | #include <sound/soc.h> | |
45 | ||
71f78e22 SW |
46 | #include "tegra_i2s.h" |
47 | ||
48 | #define DRV_NAME "tegra-i2s" | |
49 | ||
50 | static inline void tegra_i2s_write(struct tegra_i2s *i2s, u32 reg, u32 val) | |
51 | { | |
52 | __raw_writel(val, i2s->regs + reg); | |
53 | } | |
54 | ||
55 | static inline u32 tegra_i2s_read(struct tegra_i2s *i2s, u32 reg) | |
56 | { | |
57 | return __raw_readl(i2s->regs + reg); | |
58 | } | |
59 | ||
60 | #ifdef CONFIG_DEBUG_FS | |
61 | static int tegra_i2s_show(struct seq_file *s, void *unused) | |
62 | { | |
63 | #define REG(r) { r, #r } | |
64 | static const struct { | |
65 | int offset; | |
66 | const char *name; | |
67 | } regs[] = { | |
68 | REG(TEGRA_I2S_CTRL), | |
69 | REG(TEGRA_I2S_STATUS), | |
70 | REG(TEGRA_I2S_TIMING), | |
71 | REG(TEGRA_I2S_FIFO_SCR), | |
72 | REG(TEGRA_I2S_PCM_CTRL), | |
73 | REG(TEGRA_I2S_NW_CTRL), | |
74 | REG(TEGRA_I2S_TDM_CTRL), | |
75 | REG(TEGRA_I2S_TDM_TX_RX_CTRL), | |
76 | }; | |
77 | #undef REG | |
78 | ||
79 | struct tegra_i2s *i2s = s->private; | |
80 | int i; | |
81 | ||
82 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
83 | u32 val = tegra_i2s_read(i2s, regs[i].offset); | |
84 | seq_printf(s, "%s = %08x\n", regs[i].name, val); | |
85 | } | |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
90 | static int tegra_i2s_debug_open(struct inode *inode, struct file *file) | |
91 | { | |
92 | return single_open(file, tegra_i2s_show, inode->i_private); | |
93 | } | |
94 | ||
95 | static const struct file_operations tegra_i2s_debug_fops = { | |
96 | .open = tegra_i2s_debug_open, | |
97 | .read = seq_read, | |
98 | .llseek = seq_lseek, | |
99 | .release = single_release, | |
100 | }; | |
101 | ||
d4a2eca7 | 102 | static void tegra_i2s_debug_add(struct tegra_i2s *i2s) |
71f78e22 | 103 | { |
d4a2eca7 SW |
104 | i2s->debug = debugfs_create_file(i2s->dai.name, S_IRUGO, |
105 | snd_soc_debugfs_root, i2s, | |
106 | &tegra_i2s_debug_fops); | |
71f78e22 SW |
107 | } |
108 | ||
109 | static void tegra_i2s_debug_remove(struct tegra_i2s *i2s) | |
110 | { | |
111 | if (i2s->debug) | |
112 | debugfs_remove(i2s->debug); | |
113 | } | |
114 | #else | |
0dfe8da4 | 115 | static inline void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id) |
71f78e22 SW |
116 | { |
117 | } | |
118 | ||
119 | static inline void tegra_i2s_debug_remove(struct tegra_i2s *i2s) | |
120 | { | |
121 | } | |
122 | #endif | |
123 | ||
124 | static int tegra_i2s_set_fmt(struct snd_soc_dai *dai, | |
125 | unsigned int fmt) | |
126 | { | |
127 | struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai); | |
128 | ||
129 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
130 | case SND_SOC_DAIFMT_NB_NF: | |
131 | break; | |
132 | default: | |
133 | return -EINVAL; | |
134 | } | |
135 | ||
136 | i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_MASTER_ENABLE; | |
137 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
138 | case SND_SOC_DAIFMT_CBS_CFS: | |
139 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_MASTER_ENABLE; | |
140 | break; | |
141 | case SND_SOC_DAIFMT_CBM_CFM: | |
142 | break; | |
143 | default: | |
144 | return -EINVAL; | |
145 | } | |
146 | ||
147 | i2s->reg_ctrl &= ~(TEGRA_I2S_CTRL_BIT_FORMAT_MASK | | |
148 | TEGRA_I2S_CTRL_LRCK_MASK); | |
149 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
150 | case SND_SOC_DAIFMT_DSP_A: | |
151 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP; | |
152 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW; | |
153 | break; | |
154 | case SND_SOC_DAIFMT_DSP_B: | |
155 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP; | |
156 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_R_LOW; | |
157 | break; | |
158 | case SND_SOC_DAIFMT_I2S: | |
159 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_I2S; | |
160 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW; | |
161 | break; | |
162 | case SND_SOC_DAIFMT_RIGHT_J: | |
163 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_RJM; | |
164 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW; | |
165 | break; | |
166 | case SND_SOC_DAIFMT_LEFT_J: | |
167 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_LJM; | |
168 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW; | |
169 | break; | |
170 | default: | |
171 | return -EINVAL; | |
172 | } | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
177 | static int tegra_i2s_hw_params(struct snd_pcm_substream *substream, | |
178 | struct snd_pcm_hw_params *params, | |
179 | struct snd_soc_dai *dai) | |
180 | { | |
181 | struct device *dev = substream->pcm->card->dev; | |
182 | struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai); | |
183 | u32 reg; | |
184 | int ret, sample_size, srate, i2sclock, bitcnt; | |
185 | ||
186 | i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_BIT_SIZE_MASK; | |
187 | switch (params_format(params)) { | |
188 | case SNDRV_PCM_FORMAT_S16_LE: | |
189 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_16; | |
190 | sample_size = 16; | |
191 | break; | |
192 | case SNDRV_PCM_FORMAT_S24_LE: | |
193 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_24; | |
194 | sample_size = 24; | |
195 | break; | |
196 | case SNDRV_PCM_FORMAT_S32_LE: | |
197 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_32; | |
198 | sample_size = 32; | |
199 | break; | |
200 | default: | |
201 | return -EINVAL; | |
202 | } | |
203 | ||
204 | srate = params_rate(params); | |
205 | ||
206 | /* Final "* 2" required by Tegra hardware */ | |
207 | i2sclock = srate * params_channels(params) * sample_size * 2; | |
208 | ||
209 | ret = clk_set_rate(i2s->clk_i2s, i2sclock); | |
210 | if (ret) { | |
211 | dev_err(dev, "Can't set I2S clock rate: %d\n", ret); | |
212 | return ret; | |
213 | } | |
214 | ||
215 | bitcnt = (i2sclock / (2 * srate)) - 1; | |
216 | if (bitcnt < 0 || bitcnt > TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US) | |
217 | return -EINVAL; | |
218 | reg = bitcnt << TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT; | |
219 | ||
220 | if (i2sclock % (2 * srate)) | |
221 | reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE; | |
222 | ||
713d1369 SW |
223 | if (!i2s->clk_refs) |
224 | clk_enable(i2s->clk_i2s); | |
225 | ||
71f78e22 SW |
226 | tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg); |
227 | ||
228 | tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR, | |
229 | TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS | | |
230 | TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS); | |
231 | ||
713d1369 SW |
232 | if (!i2s->clk_refs) |
233 | clk_disable(i2s->clk_i2s); | |
234 | ||
71f78e22 SW |
235 | return 0; |
236 | } | |
237 | ||
238 | static void tegra_i2s_start_playback(struct tegra_i2s *i2s) | |
239 | { | |
240 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO1_ENABLE; | |
241 | tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl); | |
242 | } | |
243 | ||
244 | static void tegra_i2s_stop_playback(struct tegra_i2s *i2s) | |
245 | { | |
246 | i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO1_ENABLE; | |
247 | tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl); | |
248 | } | |
249 | ||
250 | static void tegra_i2s_start_capture(struct tegra_i2s *i2s) | |
251 | { | |
252 | i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO2_ENABLE; | |
253 | tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl); | |
254 | } | |
255 | ||
256 | static void tegra_i2s_stop_capture(struct tegra_i2s *i2s) | |
257 | { | |
258 | i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO2_ENABLE; | |
259 | tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl); | |
260 | } | |
261 | ||
262 | static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd, | |
263 | struct snd_soc_dai *dai) | |
264 | { | |
265 | struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai); | |
266 | ||
267 | switch (cmd) { | |
268 | case SNDRV_PCM_TRIGGER_START: | |
269 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
270 | case SNDRV_PCM_TRIGGER_RESUME: | |
271 | if (!i2s->clk_refs) | |
272 | clk_enable(i2s->clk_i2s); | |
273 | i2s->clk_refs++; | |
274 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
275 | tegra_i2s_start_playback(i2s); | |
276 | else | |
277 | tegra_i2s_start_capture(i2s); | |
278 | break; | |
279 | case SNDRV_PCM_TRIGGER_STOP: | |
280 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
281 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
282 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
283 | tegra_i2s_stop_playback(i2s); | |
284 | else | |
285 | tegra_i2s_stop_capture(i2s); | |
286 | i2s->clk_refs--; | |
287 | if (!i2s->clk_refs) | |
288 | clk_disable(i2s->clk_i2s); | |
289 | break; | |
290 | default: | |
291 | return -EINVAL; | |
292 | } | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
297 | static int tegra_i2s_probe(struct snd_soc_dai *dai) | |
298 | { | |
299 | struct tegra_i2s * i2s = snd_soc_dai_get_drvdata(dai); | |
300 | ||
301 | dai->capture_dma_data = &i2s->capture_dma_data; | |
302 | dai->playback_dma_data = &i2s->playback_dma_data; | |
303 | ||
304 | return 0; | |
305 | } | |
306 | ||
85e7652d | 307 | static const struct snd_soc_dai_ops tegra_i2s_dai_ops = { |
71f78e22 SW |
308 | .set_fmt = tegra_i2s_set_fmt, |
309 | .hw_params = tegra_i2s_hw_params, | |
310 | .trigger = tegra_i2s_trigger, | |
311 | }; | |
312 | ||
d4a2eca7 SW |
313 | static const struct snd_soc_dai_driver tegra_i2s_dai_template = { |
314 | .probe = tegra_i2s_probe, | |
315 | .playback = { | |
316 | .channels_min = 2, | |
317 | .channels_max = 2, | |
318 | .rates = SNDRV_PCM_RATE_8000_96000, | |
319 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
71f78e22 | 320 | }, |
d4a2eca7 SW |
321 | .capture = { |
322 | .channels_min = 2, | |
323 | .channels_max = 2, | |
324 | .rates = SNDRV_PCM_RATE_8000_96000, | |
325 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
71f78e22 | 326 | }, |
d4a2eca7 SW |
327 | .ops = &tegra_i2s_dai_ops, |
328 | .symmetric_rates = 1, | |
71f78e22 SW |
329 | }; |
330 | ||
331 | static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev) | |
332 | { | |
333 | struct tegra_i2s * i2s; | |
71f78e22 | 334 | struct resource *mem, *memregion, *dmareq; |
bf55499e SW |
335 | u32 of_dma[2]; |
336 | u32 dma_ch; | |
71f78e22 SW |
337 | int ret; |
338 | ||
bea0ed08 | 339 | i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra_i2s), GFP_KERNEL); |
71f78e22 SW |
340 | if (!i2s) { |
341 | dev_err(&pdev->dev, "Can't allocate tegra_i2s\n"); | |
342 | ret = -ENOMEM; | |
bea0ed08 | 343 | goto err; |
71f78e22 SW |
344 | } |
345 | dev_set_drvdata(&pdev->dev, i2s); | |
346 | ||
d4a2eca7 SW |
347 | i2s->dai = tegra_i2s_dai_template; |
348 | i2s->dai.name = dev_name(&pdev->dev); | |
349 | ||
b5f9cfed | 350 | i2s->clk_i2s = clk_get(&pdev->dev, NULL); |
422650e6 | 351 | if (IS_ERR(i2s->clk_i2s)) { |
713dce4e | 352 | dev_err(&pdev->dev, "Can't retrieve i2s clock\n"); |
71f78e22 | 353 | ret = PTR_ERR(i2s->clk_i2s); |
bea0ed08 | 354 | goto err; |
71f78e22 SW |
355 | } |
356 | ||
357 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
358 | if (!mem) { | |
359 | dev_err(&pdev->dev, "No memory resource\n"); | |
360 | ret = -ENODEV; | |
361 | goto err_clk_put; | |
362 | } | |
363 | ||
364 | dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
365 | if (!dmareq) { | |
bf55499e SW |
366 | if (of_property_read_u32_array(pdev->dev.of_node, |
367 | "nvidia,dma-request-selector", | |
368 | of_dma, 2) < 0) { | |
369 | dev_err(&pdev->dev, "No DMA resource\n"); | |
370 | ret = -ENODEV; | |
371 | goto err_clk_put; | |
372 | } | |
373 | dma_ch = of_dma[1]; | |
374 | } else { | |
375 | dma_ch = dmareq->start; | |
71f78e22 SW |
376 | } |
377 | ||
bea0ed08 SW |
378 | memregion = devm_request_mem_region(&pdev->dev, mem->start, |
379 | resource_size(mem), DRV_NAME); | |
71f78e22 SW |
380 | if (!memregion) { |
381 | dev_err(&pdev->dev, "Memory region already claimed\n"); | |
382 | ret = -EBUSY; | |
383 | goto err_clk_put; | |
384 | } | |
385 | ||
bea0ed08 | 386 | i2s->regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
71f78e22 SW |
387 | if (!i2s->regs) { |
388 | dev_err(&pdev->dev, "ioremap failed\n"); | |
389 | ret = -ENOMEM; | |
bea0ed08 | 390 | goto err_clk_put; |
71f78e22 SW |
391 | } |
392 | ||
393 | i2s->capture_dma_data.addr = mem->start + TEGRA_I2S_FIFO2; | |
394 | i2s->capture_dma_data.wrap = 4; | |
395 | i2s->capture_dma_data.width = 32; | |
bf55499e | 396 | i2s->capture_dma_data.req_sel = dma_ch; |
71f78e22 SW |
397 | |
398 | i2s->playback_dma_data.addr = mem->start + TEGRA_I2S_FIFO1; | |
399 | i2s->playback_dma_data.wrap = 4; | |
400 | i2s->playback_dma_data.width = 32; | |
bf55499e | 401 | i2s->playback_dma_data.req_sel = dma_ch; |
71f78e22 SW |
402 | |
403 | i2s->reg_ctrl = TEGRA_I2S_CTRL_FIFO_FORMAT_PACKED; | |
404 | ||
d4a2eca7 | 405 | ret = snd_soc_register_dai(&pdev->dev, &i2s->dai); |
71f78e22 SW |
406 | if (ret) { |
407 | dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); | |
408 | ret = -ENOMEM; | |
bea0ed08 | 409 | goto err_clk_put; |
71f78e22 SW |
410 | } |
411 | ||
518de86b SW |
412 | ret = tegra_pcm_platform_register(&pdev->dev); |
413 | if (ret) { | |
414 | dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); | |
415 | goto err_unregister_dai; | |
416 | } | |
417 | ||
d4a2eca7 | 418 | tegra_i2s_debug_add(i2s); |
71f78e22 SW |
419 | |
420 | return 0; | |
421 | ||
518de86b SW |
422 | err_unregister_dai: |
423 | snd_soc_unregister_dai(&pdev->dev); | |
71f78e22 SW |
424 | err_clk_put: |
425 | clk_put(i2s->clk_i2s); | |
bea0ed08 | 426 | err: |
71f78e22 SW |
427 | return ret; |
428 | } | |
429 | ||
430 | static int __devexit tegra_i2s_platform_remove(struct platform_device *pdev) | |
431 | { | |
432 | struct tegra_i2s *i2s = dev_get_drvdata(&pdev->dev); | |
71f78e22 | 433 | |
518de86b | 434 | tegra_pcm_platform_unregister(&pdev->dev); |
71f78e22 SW |
435 | snd_soc_unregister_dai(&pdev->dev); |
436 | ||
437 | tegra_i2s_debug_remove(i2s); | |
438 | ||
71f78e22 SW |
439 | clk_put(i2s->clk_i2s); |
440 | ||
71f78e22 SW |
441 | return 0; |
442 | } | |
443 | ||
bf55499e SW |
444 | static const struct of_device_id tegra_i2s_of_match[] __devinitconst = { |
445 | { .compatible = "nvidia,tegra20-i2s", }, | |
446 | {}, | |
447 | }; | |
448 | ||
71f78e22 SW |
449 | static struct platform_driver tegra_i2s_driver = { |
450 | .driver = { | |
451 | .name = DRV_NAME, | |
452 | .owner = THIS_MODULE, | |
bf55499e | 453 | .of_match_table = tegra_i2s_of_match, |
71f78e22 SW |
454 | }, |
455 | .probe = tegra_i2s_platform_probe, | |
456 | .remove = __devexit_p(tegra_i2s_platform_remove), | |
457 | }; | |
bea0ed08 | 458 | module_platform_driver(tegra_i2s_driver); |
71f78e22 SW |
459 | |
460 | MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); | |
461 | MODULE_DESCRIPTION("Tegra I2S ASoC driver"); | |
462 | MODULE_LICENSE("GPL"); | |
8eb34207 | 463 | MODULE_ALIAS("platform:" DRV_NAME); |
bf55499e | 464 | MODULE_DEVICE_TABLE(of, tegra_i2s_of_match); |