[deliverable/linux.git] / sound / soc / tegra / tegra_i2s.c

/*
 * tegra_i2s.c - Tegra I2S driver
 *
 * Author: Stephen Warren <swarren@nvidia.com>
 * Copyright (C) 2010 - NVIDIA, Inc.
 *
 * Based on code copyright/by:
 *
 * Copyright (c) 2009-2010, NVIDIA Corporation.
 * Scott Peterson <speterson@nvidia.com>
 *
 * Copyright (C) 2010 Google, Inc.
 * Iliyan Malchev <malchev@google.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/clk.h>
#include <linux/module.h>
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <mach/iomap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include "tegra_i2s.h"

#define DRV_NAME "tegra-i2s"

static inline void tegra_i2s_write(struct tegra_i2s *i2s, u32 reg, u32 val)
{
	__raw_writel(val, i2s->regs + reg);
}

static inline u32 tegra_i2s_read(struct tegra_i2s *i2s, u32 reg)
{
	return __raw_readl(i2s->regs + reg);
}

#ifdef CONFIG_DEBUG_FS
static int tegra_i2s_show(struct seq_file *s, void *unused)
{
#define REG(r) { r, #r }
	static const struct {
		int offset;
		const char *name;
	} regs[] = {
		REG(TEGRA_I2S_CTRL),
		REG(TEGRA_I2S_STATUS),
		REG(TEGRA_I2S_TIMING),
		REG(TEGRA_I2S_FIFO_SCR),
		REG(TEGRA_I2S_PCM_CTRL),
		REG(TEGRA_I2S_NW_CTRL),
		REG(TEGRA_I2S_TDM_CTRL),
		REG(TEGRA_I2S_TDM_TX_RX_CTRL),
	};
#undef REG

	struct tegra_i2s *i2s = s->private;
	int i;

	for (i = 0; i < ARRAY_SIZE(regs); i++) {
		u32 val = tegra_i2s_read(i2s, regs[i].offset);
		seq_printf(s, "%s = %08x\n", regs[i].name, val);
	}

	return 0;
}

static int tegra_i2s_debug_open(struct inode *inode, struct file *file)
{
	return single_open(file, tegra_i2s_show, inode->i_private);
}

static const struct file_operations tegra_i2s_debug_fops = {
	.open    = tegra_i2s_debug_open,
	.read    = seq_read,
	.llseek  = seq_lseek,
	.release = single_release,
};

static void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id)
{
	char name[] = DRV_NAME ".0";

	snprintf(name, sizeof(name), DRV_NAME".%1d", id);
	i2s->debug = debugfs_create_file(name, S_IRUGO, snd_soc_debugfs_root,
						i2s, &tegra_i2s_debug_fops);
}

static void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
{
	if (i2s->debug)
		debugfs_remove(i2s->debug);
}
#else
static inline void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id)
{
}

static inline void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
{
}
#endif

static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
				unsigned int fmt)
{
	struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		break;
	default:
		return -EINVAL;
	}

	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_MASTER_ENABLE;
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_MASTER_ENABLE;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		break;
	default:
		return -EINVAL;
	}

	i2s->reg_ctrl &= ~(TEGRA_I2S_CTRL_BIT_FORMAT_MASK | 
				TEGRA_I2S_CTRL_LRCK_MASK);
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_DSP_A:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_DSP_B:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_R_LOW;
		break;
	case SND_SOC_DAIFMT_I2S:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_I2S;
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_RJM;
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_LJM;
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int tegra_i2s_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params,
				struct snd_soc_dai *dai)
{
        struct device *dev = substream->pcm->card->dev;
	struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	u32 reg;
	int ret, sample_size, srate, i2sclock, bitcnt;

	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_BIT_SIZE_MASK;
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_16;
		sample_size = 16;
		break;
	case SNDRV_PCM_FORMAT_S24_LE:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_24;
		sample_size = 24;
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_32;
		sample_size = 32;
		break;
	default:
		return -EINVAL;
	}

	srate = params_rate(params);

	/* Final "* 2" required by Tegra hardware */
	i2sclock = srate * params_channels(params) * sample_size * 2;

	ret = clk_set_rate(i2s->clk_i2s, i2sclock);
	if (ret) {
		dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
		return ret;
	}

	bitcnt = (i2sclock / (2 * srate)) - 1;
	if (bitcnt < 0 || bitcnt > TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
		return -EINVAL;
	reg = bitcnt << TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;

	if (i2sclock % (2 * srate))
		reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE;

	if (!i2s->clk_refs)
		clk_enable(i2s->clk_i2s);

	tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg);

	tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR,
		TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
		TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);

	if (!i2s->clk_refs)
		clk_disable(i2s->clk_i2s);

	return 0;
}

static void tegra_i2s_start_playback(struct tegra_i2s *i2s)
{
	i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO1_ENABLE;
	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
}

static void tegra_i2s_stop_playback(struct tegra_i2s *i2s)
{
	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO1_ENABLE;
	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
}

static void tegra_i2s_start_capture(struct tegra_i2s *i2s)
{
	i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO2_ENABLE;
	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
}

static void tegra_i2s_stop_capture(struct tegra_i2s *i2s)
{
	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO2_ENABLE;
	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
}

static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
				struct snd_soc_dai *dai)
{
	struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_RESUME:
		if (!i2s->clk_refs)
			clk_enable(i2s->clk_i2s);
		i2s->clk_refs++;
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra_i2s_start_playback(i2s);
		else
			tegra_i2s_start_capture(i2s);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	case SNDRV_PCM_TRIGGER_SUSPEND:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra_i2s_stop_playback(i2s);
		else
			tegra_i2s_stop_capture(i2s);
		i2s->clk_refs--;
		if (!i2s->clk_refs)
			clk_disable(i2s->clk_i2s);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int tegra_i2s_probe(struct snd_soc_dai *dai)
{
	struct tegra_i2s * i2s = snd_soc_dai_get_drvdata(dai);

	dai->capture_dma_data = &i2s->capture_dma_data;
	dai->playback_dma_data = &i2s->playback_dma_data;

	return 0;
}

static struct snd_soc_dai_ops tegra_i2s_dai_ops = {
	.set_fmt	= tegra_i2s_set_fmt,
	.hw_params	= tegra_i2s_hw_params,
	.trigger	= tegra_i2s_trigger,
};

static struct snd_soc_dai_driver tegra_i2s_dai[] = {
	{
		.name = DRV_NAME ".0",
		.probe = tegra_i2s_probe,
		.playback = {
			.channels_min = 2,
			.channels_max = 2,
			.rates = SNDRV_PCM_RATE_8000_96000,
			.formats = SNDRV_PCM_FMTBIT_S16_LE,
		},
		.capture = {
			.channels_min = 2,
			.channels_max = 2,
			.rates = SNDRV_PCM_RATE_8000_96000,
			.formats = SNDRV_PCM_FMTBIT_S16_LE,
		},
		.ops = &tegra_i2s_dai_ops,
		.symmetric_rates = 1,
	},
	{
		.name = DRV_NAME ".1",
		.probe = tegra_i2s_probe,
		.playback = {
			.channels_min = 2,
			.channels_max = 2,
			.rates = SNDRV_PCM_RATE_8000_96000,
			.formats = SNDRV_PCM_FMTBIT_S16_LE,
		},
		.capture = {
			.channels_min = 2,
			.channels_max = 2,
			.rates = SNDRV_PCM_RATE_8000_96000,
			.formats = SNDRV_PCM_FMTBIT_S16_LE,
		},
		.ops = &tegra_i2s_dai_ops,
		.symmetric_rates = 1,
	},
};

static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev)
{
	struct tegra_i2s * i2s;
	struct resource *mem, *memregion, *dmareq;
	int ret;

	if ((pdev->id < 0) ||
		(pdev->id >= ARRAY_SIZE(tegra_i2s_dai))) {
		dev_err(&pdev->dev, "ID %d out of range\n", pdev->id);
		return -EINVAL;
	}

	i2s = kzalloc(sizeof(struct tegra_i2s), GFP_KERNEL);
	if (!i2s) {
		dev_err(&pdev->dev, "Can't allocate tegra_i2s\n");
		ret = -ENOMEM;
		goto exit;
	}
	dev_set_drvdata(&pdev->dev, i2s);

	i2s->clk_i2s = clk_get(&pdev->dev, NULL);
	if (IS_ERR(i2s->clk_i2s)) {
		dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
		ret = PTR_ERR(i2s->clk_i2s);
		goto err_free;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "No memory resource\n");
		ret = -ENODEV;
		goto err_clk_put;
	}

	dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	if (!dmareq) {
		dev_err(&pdev->dev, "No DMA resource\n");
		ret = -ENODEV;
		goto err_clk_put;
	}

	memregion = request_mem_region(mem->start, resource_size(mem),
					DRV_NAME);
	if (!memregion) {
		dev_err(&pdev->dev, "Memory region already claimed\n");
		ret = -EBUSY;
		goto err_clk_put;
	}

	i2s->regs = ioremap(mem->start, resource_size(mem));
	if (!i2s->regs) {
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -ENOMEM;
		goto err_release;
	}

	i2s->capture_dma_data.addr = mem->start + TEGRA_I2S_FIFO2;
	i2s->capture_dma_data.wrap = 4;
	i2s->capture_dma_data.width = 32;
	i2s->capture_dma_data.req_sel = dmareq->start;

	i2s->playback_dma_data.addr = mem->start + TEGRA_I2S_FIFO1;
	i2s->playback_dma_data.wrap = 4;
	i2s->playback_dma_data.width = 32;
	i2s->playback_dma_data.req_sel = dmareq->start;

	i2s->reg_ctrl = TEGRA_I2S_CTRL_FIFO_FORMAT_PACKED;

	ret = snd_soc_register_dai(&pdev->dev, &tegra_i2s_dai[pdev->id]);
	if (ret) {
		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
		ret = -ENOMEM;
		goto err_unmap;
	}

	tegra_i2s_debug_add(i2s, pdev->id);

	return 0;

err_unmap:
	iounmap(i2s->regs);
err_release:
	release_mem_region(mem->start, resource_size(mem));
err_clk_put:
	clk_put(i2s->clk_i2s);
err_free:
	kfree(i2s);
exit:
	return ret;
}

static int __devexit tegra_i2s_platform_remove(struct platform_device *pdev)
{
	struct tegra_i2s *i2s = dev_get_drvdata(&pdev->dev);
	struct resource *res;

	snd_soc_unregister_dai(&pdev->dev);

	tegra_i2s_debug_remove(i2s);

	iounmap(i2s->regs);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(res->start, resource_size(res));

	clk_put(i2s->clk_i2s);

	kfree(i2s);

	return 0;
}

static struct platform_driver tegra_i2s_driver = {
	.driver = {
		.name = DRV_NAME,
		.owner = THIS_MODULE,
	},
	.probe = tegra_i2s_platform_probe,
	.remove = __devexit_p(tegra_i2s_platform_remove),
};

static int __init snd_tegra_i2s_init(void)
{
	return platform_driver_register(&tegra_i2s_driver);
}
module_init(snd_tegra_i2s_init);

static void __exit snd_tegra_i2s_exit(void)
{
	platform_driver_unregister(&tegra_i2s_driver);
}
module_exit(snd_tegra_i2s_exit);

MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
MODULE_DESCRIPTION("Tegra I2S ASoC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
71f78e22 SW	1	/*
	2	* tegra_i2s.c - Tegra I2S driver
	3	*
	4	* Author: Stephen Warren <swarren@nvidia.com>
	5	* Copyright (C) 2010 - NVIDIA, Inc.
	6	*
	7	* Based on code copyright/by:
	8	*
	9	* Copyright (c) 2009-2010, NVIDIA Corporation.
	10	* Scott Peterson <speterson@nvidia.com>
	11	*
	12	* Copyright (C) 2010 Google, Inc.
	13	* Iliyan Malchev <malchev@google.com>
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* version 2 as published by the Free Software Foundation.
	18	*
	19	* This program is distributed in the hope that it will be useful, but
	20	* WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	22	* General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	27	* 02110-1301 USA
	28	*
	29	*/
	30
	31	#include <linux/clk.h>
	32	#include <linux/module.h>
	33	#include <linux/debugfs.h>
	34	#include <linux/device.h>
	35	#include <linux/platform_device.h>
	36	#include <linux/seq_file.h>
	37	#include <linux/slab.h>
	38	#include <linux/io.h>
	39	#include <mach/iomap.h>
	40	#include <sound/core.h>
	41	#include <sound/pcm.h>
	42	#include <sound/pcm_params.h>
	43	#include <sound/soc.h>
	44
71f78e22 SW	45	#include "tegra_i2s.h"
	46
	47	#define DRV_NAME "tegra-i2s"
	48
	49	static inline void tegra_i2s_write(struct tegra_i2s *i2s, u32 reg, u32 val)
	50	{
	51	__raw_writel(val, i2s->regs + reg);
	52	}
	53
	54	static inline u32 tegra_i2s_read(struct tegra_i2s *i2s, u32 reg)
	55	{
	56	return __raw_readl(i2s->regs + reg);
	57	}
	58
	59	#ifdef CONFIG_DEBUG_FS
	60	static int tegra_i2s_show(struct seq_file s, void unused)
	61	{
	62	#define REG(r) { r, #r }
	63	static const struct {
	64	int offset;
	65	const char *name;
	66	} regs[] = {
	67	REG(TEGRA_I2S_CTRL),
	68	REG(TEGRA_I2S_STATUS),
	69	REG(TEGRA_I2S_TIMING),
	70	REG(TEGRA_I2S_FIFO_SCR),
	71	REG(TEGRA_I2S_PCM_CTRL),
	72	REG(TEGRA_I2S_NW_CTRL),
	73	REG(TEGRA_I2S_TDM_CTRL),
	74	REG(TEGRA_I2S_TDM_TX_RX_CTRL),
	75	};
	76	#undef REG
	77
	78	struct tegra_i2s *i2s = s->private;
	79	int i;
	80
	81	for (i = 0; i < ARRAY_SIZE(regs); i++) {
	82	u32 val = tegra_i2s_read(i2s, regs[i].offset);
	83	seq_printf(s, "%s = %08x\n", regs[i].name, val);
	84	}
	85
	86	return 0;
	87	}
	88
	89	static int tegra_i2s_debug_open(struct inode inode, struct file file)
	90	{
	91	return single_open(file, tegra_i2s_show, inode->i_private);
	92	}
	93
	94	static const struct file_operations tegra_i2s_debug_fops = {
	95	.open = tegra_i2s_debug_open,
	96	.read = seq_read,
	97	.llseek = seq_lseek,
	98	.release = single_release,
	99	};
	100
	101	static void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id)
	102	{
	103	char name[] = DRV_NAME ".0";
	104
	105	snprintf(name, sizeof(name), DRV_NAME".%1d", id);
8a9dab1a	106	i2s->debug = debugfs_create_file(name, S_IRUGO, snd_soc_debugfs_root,
71f78e22 SW	107	i2s, &tegra_i2s_debug_fops);
	108	}
	109
	110	static void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
	111	{
	112	if (i2s->debug)
	113	debugfs_remove(i2s->debug);
	114	}
	115	#else
0dfe8da4	116	static inline void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id)
71f78e22 SW	117	{
	118	}
	119
	120	static inline void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
	121	{
	122	}
	123	#endif
	124
	125	static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
	126	unsigned int fmt)
	127	{
	128	struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	129
	130	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	131	case SND_SOC_DAIFMT_NB_NF:
	132	break;
	133	default:
	134	return -EINVAL;
	135	}
	136
	137	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_MASTER_ENABLE;
	138	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	139	case SND_SOC_DAIFMT_CBS_CFS:
	140	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_MASTER_ENABLE;
	141	break;
	142	case SND_SOC_DAIFMT_CBM_CFM:
	143	break;
	144	default:
	145	return -EINVAL;
	146	}
	147
	148	i2s->reg_ctrl &= ~(TEGRA_I2S_CTRL_BIT_FORMAT_MASK \|
	149	TEGRA_I2S_CTRL_LRCK_MASK);
	150	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	151	case SND_SOC_DAIFMT_DSP_A:
	152	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
	153	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_LRCK_L_LOW;
	154	break;
	155	case SND_SOC_DAIFMT_DSP_B:
	156	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
	157	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_LRCK_R_LOW;
	158	break;
	159	case SND_SOC_DAIFMT_I2S:
	160	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_FORMAT_I2S;
	161	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_LRCK_L_LOW;
	162	break;
	163	case SND_SOC_DAIFMT_RIGHT_J:
	164	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_FORMAT_RJM;
	165	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_LRCK_L_LOW;
	166	break;
	167	case SND_SOC_DAIFMT_LEFT_J:
	168	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_FORMAT_LJM;
	169	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_LRCK_L_LOW;
	170	break;
	171	default:
	172	return -EINVAL;
	173	}
	174
	175	return 0;
	176	}
	177
	178	static int tegra_i2s_hw_params(struct snd_pcm_substream *substream,
	179	struct snd_pcm_hw_params *params,
	180	struct snd_soc_dai *dai)
181	{
182	struct device *dev = substream->pcm->card->dev;
183	struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
184	u32 reg;
185	int ret, sample_size, srate, i2sclock, bitcnt;
186
187	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_BIT_SIZE_MASK;
188	switch (params_format(params)) {
189	case SNDRV_PCM_FORMAT_S16_LE:
190	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_SIZE_16;
191	sample_size = 16;
192	break;
193	case SNDRV_PCM_FORMAT_S24_LE:
194	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_SIZE_24;
195	sample_size = 24;
196	break;
197	case SNDRV_PCM_FORMAT_S32_LE:
198	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_BIT_SIZE_32;
199	sample_size = 32;
200	break;
201	default:
202	return -EINVAL;
203	}
204
205	srate = params_rate(params);
206
207	/* Final "* 2" required by Tegra hardware */
208	i2sclock = srate * params_channels(params) * sample_size * 2;
209
210	ret = clk_set_rate(i2s->clk_i2s, i2sclock);
211	if (ret) {
212	dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
213	return ret;
214	}
215
216	bitcnt = (i2sclock / (2 * srate)) - 1;
217	if (bitcnt < 0 \|\| bitcnt > TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
218	return -EINVAL;
219	reg = bitcnt << TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
220
221	if (i2sclock % (2 * srate))
222	reg \|= TEGRA_I2S_TIMING_NON_SYM_ENABLE;
223
713d1369 SW	224	if (!i2s->clk_refs)
	225	clk_enable(i2s->clk_i2s);
	226
71f78e22 SW	227	tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg);
	228
	229	tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR,
	230	TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS \|
	231	TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
	232
713d1369 SW	233	if (!i2s->clk_refs)
	234	clk_disable(i2s->clk_i2s);
	235
71f78e22 SW	236	return 0;
	237	}
	238
	239	static void tegra_i2s_start_playback(struct tegra_i2s *i2s)
	240	{
	241	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_FIFO1_ENABLE;
	242	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
	243	}
	244
	245	static void tegra_i2s_stop_playback(struct tegra_i2s *i2s)
	246	{
	247	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO1_ENABLE;
	248	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
	249	}
	250
	251	static void tegra_i2s_start_capture(struct tegra_i2s *i2s)
	252	{
	253	i2s->reg_ctrl \|= TEGRA_I2S_CTRL_FIFO2_ENABLE;
	254	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
	255	}
	256
	257	static void tegra_i2s_stop_capture(struct tegra_i2s *i2s)
	258	{
	259	i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO2_ENABLE;
	260	tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
	261	}
	262
	263	static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
	264	struct snd_soc_dai *dai)
	265	{
	266	struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	267
	268	switch (cmd) {
	269	case SNDRV_PCM_TRIGGER_START:
	270	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	271	case SNDRV_PCM_TRIGGER_RESUME:
	272	if (!i2s->clk_refs)
	273	clk_enable(i2s->clk_i2s);
	274	i2s->clk_refs++;
	275	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	276	tegra_i2s_start_playback(i2s);
	277	else
	278	tegra_i2s_start_capture(i2s);
	279	break;
	280	case SNDRV_PCM_TRIGGER_STOP:
	281	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	282	case SNDRV_PCM_TRIGGER_SUSPEND:
	283	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	284	tegra_i2s_stop_playback(i2s);
	285	else
	286	tegra_i2s_stop_capture(i2s);
	287	i2s->clk_refs--;
	288	if (!i2s->clk_refs)
	289	clk_disable(i2s->clk_i2s);
	290	break;
	291	default:
	292	return -EINVAL;
	293	}
	294
	295	return 0;
	296	}
	297
	298	static int tegra_i2s_probe(struct snd_soc_dai *dai)
	299	{
300	struct tegra_i2s * i2s = snd_soc_dai_get_drvdata(dai);
301
302	dai->capture_dma_data = &i2s->capture_dma_data;
303	dai->playback_dma_data = &i2s->playback_dma_data;
304
305	return 0;
306	}
307
308	static struct snd_soc_dai_ops tegra_i2s_dai_ops = {
309	.set_fmt = tegra_i2s_set_fmt,
310	.hw_params = tegra_i2s_hw_params,
311	.trigger = tegra_i2s_trigger,
312	};
313
019cd3b2	314	static struct snd_soc_dai_driver tegra_i2s_dai[] = {
71f78e22 SW	315	{
	316	.name = DRV_NAME ".0",
	317	.probe = tegra_i2s_probe,
	318	.playback = {
	319	.channels_min = 2,
	320	.channels_max = 2,
	321	.rates = SNDRV_PCM_RATE_8000_96000,
	322	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	323	},
	324	.capture = {
	325	.channels_min = 2,
	326	.channels_max = 2,
	327	.rates = SNDRV_PCM_RATE_8000_96000,
	328	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	329	},
	330	.ops = &tegra_i2s_dai_ops,
	331	.symmetric_rates = 1,
	332	},
	333	{
	334	.name = DRV_NAME ".1",
	335	.probe = tegra_i2s_probe,
	336	.playback = {
	337	.channels_min = 2,
	338	.channels_max = 2,
	339	.rates = SNDRV_PCM_RATE_8000_96000,
	340	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	341	},
	342	.capture = {
	343	.channels_min = 2,
	344	.channels_max = 2,
	345	.rates = SNDRV_PCM_RATE_8000_96000,
	346	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	347	},
	348	.ops = &tegra_i2s_dai_ops,
	349	.symmetric_rates = 1,
	350	},
	351	};
	352
	353	static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev)
	354	{
	355	struct tegra_i2s * i2s;
71f78e22 SW	356	struct resource mem, memregion, *dmareq;
	357	int ret;
	358
	359	if ((pdev->id < 0) \|\|
	360	(pdev->id >= ARRAY_SIZE(tegra_i2s_dai))) {
	361	dev_err(&pdev->dev, "ID %d out of range\n", pdev->id);
	362	return -EINVAL;
	363	}
	364
71f78e22 SW	365	i2s = kzalloc(sizeof(struct tegra_i2s), GFP_KERNEL);
	366	if (!i2s) {
	367	dev_err(&pdev->dev, "Can't allocate tegra_i2s\n");
	368	ret = -ENOMEM;
	369	goto exit;
	370	}
	371	dev_set_drvdata(&pdev->dev, i2s);
	372
b5f9cfed	373	i2s->clk_i2s = clk_get(&pdev->dev, NULL);
422650e6	374	if (IS_ERR(i2s->clk_i2s)) {
713dce4e	375	dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
71f78e22 SW	376	ret = PTR_ERR(i2s->clk_i2s);
	377	goto err_free;
	378	}
	379
	380	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	381	if (!mem) {
	382	dev_err(&pdev->dev, "No memory resource\n");
	383	ret = -ENODEV;
	384	goto err_clk_put;
	385	}
	386
	387	dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	388	if (!dmareq) {
	389	dev_err(&pdev->dev, "No DMA resource\n");
	390	ret = -ENODEV;
	391	goto err_clk_put;
	392	}
	393
	394	memregion = request_mem_region(mem->start, resource_size(mem),
	395	DRV_NAME);
	396	if (!memregion) {
	397	dev_err(&pdev->dev, "Memory region already claimed\n");
	398	ret = -EBUSY;
	399	goto err_clk_put;
	400	}
	401
	402	i2s->regs = ioremap(mem->start, resource_size(mem));
	403	if (!i2s->regs) {
	404	dev_err(&pdev->dev, "ioremap failed\n");
	405	ret = -ENOMEM;
	406	goto err_release;
	407	}
	408
	409	i2s->capture_dma_data.addr = mem->start + TEGRA_I2S_FIFO2;
	410	i2s->capture_dma_data.wrap = 4;
	411	i2s->capture_dma_data.width = 32;
	412	i2s->capture_dma_data.req_sel = dmareq->start;
	413
	414	i2s->playback_dma_data.addr = mem->start + TEGRA_I2S_FIFO1;
	415	i2s->playback_dma_data.wrap = 4;
	416	i2s->playback_dma_data.width = 32;
	417	i2s->playback_dma_data.req_sel = dmareq->start;
	418
	419	i2s->reg_ctrl = TEGRA_I2S_CTRL_FIFO_FORMAT_PACKED;
	420
	421	ret = snd_soc_register_dai(&pdev->dev, &tegra_i2s_dai[pdev->id]);
	422	if (ret) {
	423	dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
	424	ret = -ENOMEM;
	425	goto err_unmap;
	426	}
	427
	428	tegra_i2s_debug_add(i2s, pdev->id);
	429
	430	return 0;
	431
	432	err_unmap:
	433	iounmap(i2s->regs);
	434	err_release:
	435	release_mem_region(mem->start, resource_size(mem));
	436	err_clk_put:
	437	clk_put(i2s->clk_i2s);
	438	err_free:
	439	kfree(i2s);
440	exit:
441	return ret;
442	}
443
444	static int __devexit tegra_i2s_platform_remove(struct platform_device *pdev)
445	{
446	struct tegra_i2s *i2s = dev_get_drvdata(&pdev->dev);
447	struct resource *res;
448
449	snd_soc_unregister_dai(&pdev->dev);
450
451	tegra_i2s_debug_remove(i2s);
452
453	iounmap(i2s->regs);
454
455	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
456	release_mem_region(res->start, resource_size(res));
457
458	clk_put(i2s->clk_i2s);
459
460	kfree(i2s);
461
462	return 0;
463	}
464
465	static struct platform_driver tegra_i2s_driver = {
466	.driver = {
467	.name = DRV_NAME,
468	.owner = THIS_MODULE,
469	},
470	.probe = tegra_i2s_platform_probe,
471	.remove = __devexit_p(tegra_i2s_platform_remove),
472	};
473
474	static int __init snd_tegra_i2s_init(void)
475	{
476	return platform_driver_register(&tegra_i2s_driver);
477	}
478	module_init(snd_tegra_i2s_init);
479
480	static void __exit snd_tegra_i2s_exit(void)
481	{
482	platform_driver_unregister(&tegra_i2s_driver);
483	}
484	module_exit(snd_tegra_i2s_exit);
485
486	MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
487	MODULE_DESCRIPTION("Tegra I2S ASoC driver");
488	MODULE_LICENSE("GPL");
8eb34207	489	MODULE_ALIAS("platform:" DRV_NAME);